阅读说明：本技术 三维nor存储器电路制造中的晶片接合 (Wafer bonding in three-dimensional NOR memory circuit fabrication ) 是由 S.B.赫尔纳 E.哈拉里 于 2019-09-23 设计创作，主要内容包括：存储器阵列和单晶电路在同一集成电路中通过晶片接合(例如,粘合晶片接合或阳极晶片接合)来提供,并且通过互连层的导体互连。附加电路或存储器阵列可由附加晶片接合提供,并在晶片接合界面处通过互连层电连接。存储器阵列可包括具有单晶外延硅沟道材料的存储或存储器晶体管。(The memory array and the single crystal circuit are provided in the same integrated circuit by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) and are interconnected by conductors of an interconnect layer. Additional circuitry or memory arrays may be provided by additional die bonding and electrically connected through interconnect layers at the die bonding interface. The memory array may include memory or memory transistors having a single crystal epitaxial silicon channel material.)

1. An integrated circuit, comprising:

a single crystal semiconductor substrate;

a first circuit set comprising single crystal transistors formed in the semiconductor substrate;

a first interconnect layer comprising a plurality of conductors formed on top of the circuitry; and

a first memory block electrically connected to the first set of circuits through conductors of the first interconnect layer, wherein the conductors of the first interconnect layer and the first memory block are connected by wafer bonding.

2. The integrated circuit of claim 1, wherein the die bond is one of: thermocompression wafer bonding, anode and thermal wafer bonding.

3. The integrated circuit of claim 1, further comprising a second interconnect layer formed over the first memory block, wherein the second interconnect layer comprises a plurality of conductors, and wherein the first interconnect layer and the second interconnect layer are disposed on opposite sides of the first memory block.

4. The integrated circuit of claim 3, further comprising a second set of circuits, wherein the second set of circuits comprises single crystalline transistors, wherein the second set of circuits is electrically connected to the first memory block through conductors of the second interconnect layer, and wherein the second set of circuits and conductors of the second interconnect layer are connected by wafer bonding.

5. The integrated circuit of claim 4, wherein the second set of circuits is formed in a silicon layer disposed on an insulator layer of a silicon-on-insulator wafer.

6. The integrated circuit of claim 5, further comprising a third interconnect layer, wherein the third interconnect layer comprises a plurality of conductors, and the third interconnect layer is disposed on a side of the insulating layer opposite the silicon layer on which the second set of circuits is formed.

7. The integrated circuit of claim 4, wherein the first set of circuits comprises high voltage or analog transistors.

8. The integrated circuit of claim 4, wherein the second set of circuits is formed from low-voltage, short-channel, high-performance logic complementary metal oxide semiconductor transistors.

9. The integrated circuit of claim 3, further comprising a second memory block, wherein the second memory block is electrically connected to the first memory block through a conductor of the second interconnect layer, and wherein the second memory block and the conductor of the second interconnect layer are connected by wafer bonding.

10. The integrated circuit of claim 1, wherein the first memory block comprises memory cells having a single crystalline silicon channel material.

11. The integrated circuit of claim 1, further comprising a second memory block, wherein the second memory block is electrically connected to the first memory block, and wherein the first memory block and the second memory block are connected by die bonding.

12. The integrated circuit of claim 11, further comprising a second interconnect layer formed on top of the second memory block on an opposite side of the first memory block, wherein the second interconnect layer comprises a plurality of conductors.

13. The integrated circuit of claim 1, wherein the first memory block comprises one or more of: non-volatile memory string arrays and quasi-volatile memory string arrays.

14. The integrated circuit of claim 13, wherein the first memory block is organized as a three-dimensional memory array.

15. The integrated circuit of claim 14, wherein the three-dimensional memory array comprises NOR-type memory strings.

1. Field of the invention

The present invention relates to wafer bonding techniques in integrated circuit fabrication. In particular, the present invention relates to wafer bonding techniques for high density three-dimensional memory circuits.

2. Background of the invention

Wafer bonding is a technique used in the manufacture of many semiconductor devices. In die bonding, two dies of the same or nearly the same area are connected, for example, by thermocompression (thermocompression), adhesive (adhesive), anodic (anodic), or thermal (thermal) techniques. Generally, after bonding, all or substantially all of the substrate is removed from one or both wafers.

The aforementioned co-pending application discloses a three-dimensional memory structure formed on top of a single crystalline semiconductor substrate, organized as an array of NOR memory strings (strings). In this context, a "NOR memory string" refers to a group of thin film memory transistors that share source and drain regions. Fig. 1 shows a cross-section of a memory structure 30 comprising an array of NOR memory strings formed over CMOS (complementary metal oxide semiconductor) circuitry and interconnect layers on a semiconductor substrate. As shown in fig. 1, memory structure 30 is formed over a substrate 150. For example, semiconductor wafers known to those of ordinary skill in the art for making electronic circuits may be used as suitable substrates. Non-semiconductor substrates, such as silicon dioxide, may also be used.

Various circuit elements, such as the CMOS circuit 10 represented by the CMOS transistors shown in fig. 1, may be fabricated on or in a semiconductor substrate 150, interconnected by contacts or vias 16 via conductors 22 (e.g., copper) of a conventional interconnect layer. These circuit elements are fabricated on a semiconductor substrate using conventional techniques prior to forming the memory structure 30. The circuitry, referred to herein as interconnect layer 20, is typically embedded in an insulating layer, which may include conductors to support the operation of the memory array in memory structure 30. A memory structure 30 is formed over the interconnect layer 20. For example, interconnect layer 20 provides conductors 24 (global word lines) to connect conductors 32 (e.g., heavily doped polysilicon) in memory structure 30 that serve as word lines for addressing the various memory transistors. The conductor 32 is referred to as a local word line (local word line) in this description.

As shown in fig. 1, the memory structure 30 includes a plurality of stacks (e.g., active stacks 101a, 101b, and 101c) of active strips (active strips). By way of example, fig. 1 shows stacks 101a, 101b and 101c, each comprising four active strips, the active stacks being insulated from each other by an insulating layer 107. Fig. 1 shows a cross-section of an active strip, the strip extending longitudinally into and out of the plane of the cross-section. In this context, the active strip includes a drain layer 104, a source layer 103, a body layer 102, and a channel layer 108. (channel layers 108 are provided on both sides of the body layer 102). In some embodiments, both drain layer 104 and source layer 103 are n + polysilicon, while channel layer 108 is p-polysilicon and body layer 102 is p + polysilicon. In some embodiments, a dielectric layer may be used in place of the body layer 102. The active strip as shown in fig. 1 further comprises conductive layers 105t and 105b adjacent to the source layer 103 and the drain layer 104, respectively, for reducing the resistance along the length direction of the source layer 103 and the drain layer 104. Along each side of each stack of active strips (i.e., along each side of each active strip), a charge-trapping layer 107 and a plurality of local word lines 32 are disposed. In fig. 1, the local word lines 32 are conductive columns along both sides of the stack of active strips. A memory transistor may be formed by a local word line, a portion of the channel layer 108, a portion of the charge trapping layer 107 therebetween, and the source layer 103 and the drain layer 104. A plurality of memory transistors formed along the active stripe share the drain layer 104 and the source layer 103. Adjacent memory transistors sharing source and drain layers along an active stripe form a NOR memory string. (turning on any memory transistor in the NOR memory string will result in a conductive transistor current between the common source and drain layers.)

The order of the fabrication process imposes limitations on the CMOS devices, interconnect layers, and memory devices. For example, because it is desirable to form an ONO (oxide-nitride-oxide) multilayer structure or stack utilizing Low Pressure Chemical Vapor Deposition (LPCVD), memory devices typically require a thermal budget (thermal budget) of at least 750 degrees celsius for several hours during fabrication. In an ONO multilayer structure, the desired oxide and nitride may be a high temperature oxide (HTO; or silicon dioxide) and silicon nitride (SiN), respectively. In addition, a layer of alumina (Al) may be required₂O₃) As a blocking oxide in the ONO stack. However, from the electrical property point of view, crystalline alumina (Al)₂O₃) Which produces the desired Al₂O₃-annealing (anneal) temperatures above nine hundred degrees celsius are required. However, fabrication temperatures in excess of 350 degrees celsius would make copper unusable for the horizontal interconnect layer 20 embedded in the associated low K dielectric film, even when tungsten is used in the vertical interconnect 16 to connect the copper horizontal interconnect. Similarly, manufacturing temperatures in excess of 500 degrees celsius would preclude the use of aluminum interconnect layers. Tungsten may be one of the options for interconnect layer materials when the fabrication temperature exceeds 500 degrees celsius. However, tungsten has a higher resistance, as shown in table 1 below. The resulting increase in interconnect resistance increases signal delay, which adversely affects memory device performance.

The thermal budget process of a memory device limits the underlying CMOS circuitry (e.g., CMOS transistor 10) in at least two ways. First, cobalt silicide or other high temperature contact material, such as tungsten or tungsten silicide, must be selected for the gate, source/drain metallization 12 in the CMOS transistor 10 to allow the maximum fabrication temperature to be raised to 750 degrees celsius. Although cobalt silicide has a relatively low sheet and contact resistance compared to silicon, it is desirable to use deeper doped junctions in the silicon material because more silicon is consumed in the silicidation step and because of the roughness of the interface between cobalt silicide and silicon. Conversely, transistors with short channel lengths require shallower doped junctions in order to reduce leakage current. Although nickel silicide is commonly used in the source and drain contacts of the current generation of small transistors, cobalt silicide is preferred over nickel silicide because nickel silicide cannot withstand temperatures above 450 degrees celsius. When the temperature is higher than 450 ℃, the nickel silicide film may agglomerate on the silicon, destroying the low sheet resistance and low contact resistance characteristics of the nickel silicide film.

Second, for shallow junction and narrow channel devices, temperatures above 600 ℃ should be avoided after junction formation to prevent dopant diffusion out of the source and drain junctions.

Accordingly, a fabrication method is desired that allows for the integration of optimal CMOS devices and interconnect layers with a three-dimensional NOR memory structure (e.g., memory structure 30 of fig. 1), without the thermal budget of the memory structure limiting the design choices of the CMOS devices and interconnect layers.

Disclosure of Invention

According to one embodiment of the invention, the memory array and the single crystalline circuit are provided in the same integrated circuit by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) and are interconnected by conductors of an interconnect layer.

Additional circuitry or memory arrays may be provided by additional die bonding and electrically connected by interconnect layers at the die bonding interface.

According to one embodiment of the invention, a memory array may include memory or memory transistors having single crystal epitaxial silicon channel material.

The invention is better understood upon consideration of the following detailed description in conjunction with the accompanying drawings.

Drawings

Fig. 1 shows a cross-section of a memory structure 30 containing an array of NOR memory strings formed on top of CMOS circuitry and interconnect layers on a semiconductor substrate.

Fig. 2A shows a semiconductor substrate 100 on which interconnect layers and CMOS devices for supporting a three-dimensional NOR memory structure are fabricated.

Fig. 2B shows a three-dimensional NOR memory structure (i.e., memory structure 30) separately fabricated on a semiconductor substrate 110, above an insulating oxide (e.g., silicon dioxide) layer 120.

Fig. 3A shows two devices a 'and B' to be fabricated on wafer substrates a and B being wafer bonded.

Fig. 3B shows that devices a 'and B' have been perfectly aligned and electrically connected after wafer bonding.

Fig. 3C shows devices a 'and B' electrically connected after wafer bonding, with a 250nm wide dislocation.

Fig. 3D shows the use of bonding metal C to facilitate bonding of wafers a and B at devices a 'and B' (i.e., at the mutual contact points).

Fig. 4 shows that, using the wafer of fig. 2A and 2B as an example, the substrate 110 of the memory structure 30 may be removed.

Fig. 5 shows the formation of an interconnect layer 40 over the memory structure 30.

FIGS. 6A, 6B, 6C, 6D, 6E, 6F show a process flow for fabricating CuA and CoA circuits using wafer bonding techniques.

Fig. 7A, 7B, 7C depict connecting memory blocks 310 and 360 using wafer bonding of substrates 300 and 350.

Fig. 8A, 8B, 8C, 8D, 8E depict a process in which a CuA-type CMOS transistor is placed under a memory block with an epitaxial single-crystal silicon channel in the memory cell, according to one embodiment of the invention.

For clarity of presentation and to allow cross-reference between the figures, like elements in the figures are assigned like reference numerals.

Detailed Description

According to one embodiment of the invention, rather than fabricating CMOS devices (e.g., CMOS transistors 10) and interconnect layers (e.g., interconnect layer 20) on the same silicon substrate as memory structure 30, CMOS devices and interconnect layers are fabricated on separate semiconductor substrates. Fig. 2A shows a semiconductor substrate 100 on which an interconnect layer 20 and CMOS device 10 for supporting a three-dimensional NOR memory structure are fabricated. As shown in FIG. 2B, on the substrate 110, an isolation oxide (e.g., SiO)₂) A three-dimensional NOR memory structure (i.e., memory structure 30) is fabricated separately on layer 120. Both substrates 100 and 110 may be provided from silicon wafers, as known to one of ordinary skill in the art.

After the required manufacturing steps are performed on each of the semiconductor substrates 100 and 110, the wafers are bonded together using a "flip chip" technique, wherein the surface of the semiconductor substrate 100 with the interconnect layer 20 is bonded to the surface of the semiconductor substrate 110 with the memory structure 30. In this manner, the fabrication of the interconnect layer 20 and the CMOS device 10 is not limited by the high temperatures that are optimal for fabricating the memory structure 30.

The wafers are bonded such that the contact points in the interconnect layer 20 are electrically connected to corresponding contact points of the memory structure 30. The lithographic alignment marks in each respective substrate allow alignment of the target joint with minimal misalignment. Fig. 3A-3D illustrate exemplary wafer bonding of substrates a and B at designated wafer bonding points. Fig. 3A shows two devices a 'and B' fabricated on wafer substrates a and B being wafer bonded. For example, devices A 'and B' may be 300nm wide conductors in an interconnect system. Fig. 3B shows devices a 'and B' fully aligned and electrically connected after wafer bonding. FIG. 3C shows devices A 'and B' electrically connected after wafer bonding, with a 250nm wide misalignment. (in the most advanced wafer bonding technology, the alignment accuracy can be within 250 nm). Bonding of substrates a and B may be performed using any suitable wafer bonding technique, such as thermocompression, anodic, plasma activated, eutectic or surface activated wafer bonding. Among these techniques, anodic wafer bonding is preferable. By anodic wafer bonding, the two wafer substrates are brought into contact and an electrostatic field is applied, thereby electrically and physically connecting the devices.

According to one embodiment of the present invention, as shown in fig. 3D, bonding metal C may be used to promote bonding between wafers a and B at their mutual contact points (i.e., at devices a 'and B'). For example, the bonding metal C may be chromium, titanium, indium or alloys thereof, or any suitable material. The principles and mechanisms of wafer bonding are understood by those of ordinary skill in the art and therefore a detailed discussion is omitted in this description.

After bonding, one substrate may be removed. Fig. 4 shows that, using the wafer of fig. 2A and 2B as an example, the substrate 110 of the memory structure 30 may be removed. The substrate 110 may be removed by any suitable wafer thinning technique, such as laser lift-off, mechanical polishing, or chemical etching. In one embodiment, mechanical polishing may be combined with chemical etching to remove the substrate 110. By combining mechanical polishing and chemical etching, the substrate 110 can be removed at lower cost and with greater precision (i.e., without damage to the memory structure 30) than if either technique were used alone. For example, assume that the substrate 110 is 500 microns thick. Then, mechanical polishing may first remove about 480 microns from the substrate in an initial step, leaving about 20 microns thick substrate 110 to be removed by chemical etching.

In wafer thinning techniques by mechanical polishing, the wafer is rotated about its center on a grinding surface. Thinning the wafer by mechanical force is sometimes referred to as grinding when the resulting substrate surface is rough, and "polishing" when the resulting substrate surface is smooth. Grinding or polishing methods, or any combination thereof, may be used. After the mechanical grinding or polishing step is completed, the chemical etching may remove the remaining 20 microns of the memory structure 30.

The chemical etching of the substrate 110 may be accomplished using any suitable chemistry. Examples of suitable chemicals for silicon substrate 110 include KOH, TMAH, HF⁺HNO3 or HF⁺And NH₄F. An oxide layer between the silicon substrate 110 and the memory structure 30 can serve as an etch stop layer. As shown in figure 4 of the drawings,the etch stop layer 120 ensures that the memory structure 30 remains intact and is not damaged by the chemical etching of the substrate 110. When an oxide layer (e.g., SiO)₂) When used as an etch stop layer, KOH may be used because it etches silicon at about the rate it etches SiO₂500 times higher than the original value. Thus, SiO₂The layer may serve as an effective etch stop for the silicon etch.

After the substrate 110 is removed, further fabrication may be performed on the bonded wafer. For example, fig. 5 illustrates the formation of an interconnect layer 40 and a memory structure 30. Where the formation of memory structure 30 is separate from the formation of interconnect layer 40, aluminum or copper may be selected for interconnect layer 40. Such interconnects may be formed at lower temperatures (e.g., 450 ℃ or less).

According to another embodiment of the invention, wafer bonding may be used to fabricate single crystal transistors under a memory array, referred to as CMOS under the array ("CuA"), and over the memory array, referred to as CMOS over the array ("CoA"). FIGS. 6A-6F show a series of steps for fabricating CuA and CoA circuits using wafer bonding techniques.

As shown in fig. 6A, CMOS transistors 210 are fabricated on substrate 200, and memory array 140 is fabricated on substrate 130. Next, the substrate 130 is flipped over and bonded to the substrate 200 using wafer bonding techniques such that the memory array 140 is electrically connected to the CMOS transistors 210 above the substrate 200 through the interconnect layer 220, as shown in fig. 6B. The substrate 200 is then removed to expose the memory array 140. Thereafter, as shown in FIG. 6C, an interconnect layer 150 is fabricated from above the exposed side of the memory array 140.

As shown in fig. 6D, a second set of CMOS transistors 290 is fabricated over the substrate 260. The substrate 260 is most preferably a silicon-on-insulator ("SOI") wafer in which oxide (SiO)₂) Two layers of single crystal silicon are provided on opposite sides of the layer. As shown in fig. 6D, CMOS transistor 290 and interconnect layer 300 thereover are formed on and over silicon layer 280, silicon layer 280 being SiO₂Layer 270 is separated from substrate 260. The substrate 260 is then flipped over and wafer bonded to allow the CMOS transistors 290 to be electrically connected to the memory array 140 through the interconnect layer 150, as shown in fig. 6E.

The substrate 260 is then removed to the exposed SiO₂Layer 270 and interconnect layer 310 are fabricated above and electrically connect CMOS transistors 290 as shown in fig. 6F. The resulting combination is CuA-type CMOS transistor 210 built into a single crystalline silicon substrate 200, memory array 140 at least partially covering CMOS transistor 220, CoA-type CMOS transistor 290 at least partially covering memory array 140, and multilayer interconnect layers 150, 200, and 310 covering and underlying memory array 140. By providing CMOS transistors below and above the memory array, as shown in fig. 6A-6F, a high efficiency memory array is achieved. A high efficiency memory array refers to a memory array fabricated on a semiconductor die with almost all of the area occupied by memory cells. For example, in fig. 6A-6F, CMOS transistor 210 under memory array 140 may be a high voltage or analog transistor, while CMOS transistor 290 on memory array 140 may be a low voltage, short channel, high performance logic CMOS transistor, which is desirable in a physical location as close as possible to the input/output pads of the chip.

According to another embodiment of the present invention, a memory block may be bonded to another memory block using wafer bonding. In this manner, high area density memory structures may be realized on a single chip while simplifying fabrication by minimizing the aspect ratio of the fabricated memory structures. Fig. 7A-7C illustrate the use of wafer bonding of substrates 300 and 350 to connect memory blocks 310 and 360. As shown in fig. 7A, CMOS transistor 210 is fabricated on substrate 300 along with interconnect layer 220 and memory block 310, while memory block 360 is fabricated on substrate 350. Substrate 350 is then flipped over and die bonded to substrate 360 such that memory blocks 310 and 350 are electrically connected as shown in fig. 7B. The substrate 350 is then removed and an interconnect layer 370 is fabricated, as shown in fig. 7C.

According to yet another embodiment of the present invention, a single crystalline silicon channel for a memory cell transistor may be formed by depositing an epitaxial silicon layer from a single crystalline substrate. Such processing is difficult for memory blocks having CuA-type CMOS transistors because a "clean" path from the substrate to the source/drain layers of the memory array may not be available. An example of forming single crystal epitaxial silicon in a thin film memory transistor is disclosed, for example, in provisional application II, which is incorporated by reference above. In particular, among other types of thin film memory transistors, provisional application II discloses one type of thin film memory transistor, referred to herein as a quasi-volatile memory (QVM) circuit, having a data retention time (e.g., 100 milliseconds to one year) that is greater than conventional Dynamic Random Access Memory (DRAM) circuits and less than conventional non-volatile memory circuits. QVM circuits may be organized, for example, as a three-dimensional array of NOR memory strings. When the memory block is built on top of a silicon substrate only (i.e., without CuA-type CMOS transistors underneath), a clear path is provided for epitaxial silicon deposition. The substrate wafer with the resulting memory blocks may then be bonded to another substrate on which CMOS transistors have been fabricated. Figures 8A-8E illustrate a process by which CuA-type CMOS transistors are provided beneath a memory block having an epitaxial single-crystal silicon channel in the memory cell, according to one embodiment of the invention.

As shown in fig. 8A, a stack of active strips (each having source and drain layers 420) is first formed on a substrate 400, and trenches separate the stack of adjacent active strips up to the substrate 400, as shown in fig. 8A. Epitaxial silicon 430 is then grown from the silicon substrate 400 from the surface 402 of the substrate 400, as shown in fig. 8B, and the anisotropic etch then removes substantially all of the epitaxial silicon 430 from the trenches, except for epitaxial silicon channels 440 that remain in the recessed regions between the source and drain layers of the active strips, as shown in fig. 8C. Fabrication of memory block 810 then proceeds to completion, as shown in FIG. 8D. (example fabrication processes are disclosed, for example, in the co-pending application incorporated by reference.) the substrate 400 is then flipped over and wafer bonded to a substrate 450, the substrate 450 containing the CMOS transistors 210 and the interconnect layer 220 formed thereon, as shown in fig. 8D-8E. As previously described, the substrate 400 may be removed and an interconnect layer may be fabricated over the memory blocks.

The foregoing detailed description is provided to illustrate specific embodiments of the invention and is not intended to limit the invention. Many variations and modifications are possible within the scope of the invention. The invention is set forth in the appended claims.