阅读说明：本技术 基于sram实现多比特权重存储与计算的电路及存储与模拟计算系统 (Circuit for realizing multi-bit weight storage and calculation based on SRAM (static random Access memory) and storage and analog calculation system ) 是由 朱贤桢 梁龙飞 于 2021-07-02 设计创作，主要内容包括：本发明的基于SRAM实现多比特权重存储与计算的电路及存储与模拟计算系统,本发明充分利用了SRAM的特性,让SRAM不仅有存的能力,同时又具备了算的能力,通过在存储阵列中额外增加不同容值的电容N列对应不同比特,赋予其可以进行权重存储和运算的能力,并提升计算精度。(The circuit for realizing multi-bit weight storage and calculation based on the SRAM and the storage and analog calculation system make full use of the characteristics of the SRAM, so that the SRAM not only has storage capacity, but also has calculation capacity, and the capacity of weight storage and calculation is endowed by additionally adding different capacitance values of the capacitor N columns corresponding to different bits in the storage array, and the calculation precision is improved.)

1. A circuit for realizing multi-bit weight storage and calculation based on SRAM (static random access memory), which is used for carrying out analog calculation and/or storage flow, and comprises: the N columns correspond to 10T SRAM units with different bits, the first input and output ends of each 10T SRAM unit corresponding to the Nth bit are respectively connected with the LBLT-N end of the Nth bit line, and the second input and output ends of the 10T SRAM units corresponding to the Nth bit are respectively connected with the LBLF-N end of the Nth bit line;

wherein N is an integer greater than or equal to 1, and the 10T SRAM cell corresponding to the Nth bit includes:

a 6T SRAM cell having input and output terminals Q1 and Q2 for simultaneously inputting and outputting data;

the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor;

one end of the two ends is grounded and is connected in sequence 2^N-1A first capacitor and 2^N-1A second capacitor, and the first capacitor andthe stored charge quantity of the second capacitor is Cu;

the six CMOS transmission gates are sequentially marked as P1-P6;

and the input and output end Q1 of the 6T SRAM unit is respectively connected with the end of an Nth bit line BL-N1 and the gate of the second NMOS transistor, and the input and output end Q2 of the 6T SRAM unit is respectively connected with the end of an Nth bit line BL-N2 and the gate of the fourth NMOS transistor;

the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the drain electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the first NMOS tube is connected with one end of the first capacitor farthest from the grounding end, and the source electrode of the third NMOS tube is connected with one end of the second capacitor farthest from the grounding end;

one end of the first capacitor farthest from the ground end is also connected with a CMOS transmission gate P1, a CMOS transmission gate P2 and a CMOS transmission gate P3 respectively; one end of the second capacitor farthest from the ground end is respectively connected with the CMOS transmission gate P4, the CMOS transmission gate P5 and the CMOS transmission gate P6;

an output terminal GRBL connected to the CMOS transmission gate P3 and the CMOS transmission gate P6;

the read word line RWL is respectively connected with the grid electrode of the first NMOS transistor, the grid electrode of the third NMOS transistor, one end of the first capacitor farthest from the grounding end, one end of the second capacitor farthest from the grounding end, an Nth bit line BL-N1 end and an Nth bit line BL-N2 end;

the word line control end WL and the enabling control end EN are respectively connected to corresponding levels of the circuit;

the forward average voltage output terminal Pavg and the reverse average voltage output terminal Navg are respectively connected with the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4 and the CMOS transmission gate P5 in the forward direction and in the reverse direction.

2. The circuit for implementing multibit weight storage and computation based on SRAM as claimed in claim 1, wherein said analog computation flow comprises: a charging step and a calculating step within one clock signal.

3. The SRAM-based circuit for implementing multi-bit weight storage and calculation as claimed in claim 2, wherein the charging step comprises:

when the outputs of the read word line RWL, the word line control end WL and the enable control end EN are at a high level, and the outputs of the CMOS transmission gate P3 and the CMOS transmission gate P6 are at a low level, the first capacitor and the second capacitor are sequentially charged to the voltages of the input and output ends Q1 and Q2, which are stored in the 6T SRAM cell in advance, respectively;

when the read word line RWL, the word line control terminal WL and the enable control terminal EN are at a low level, the CMOS transmission gate P3 and the CMOS transmission gate P6 are at a high level, and the first capacitor and the second capacitor are discharged to the same voltage as the GRBL.

4. The SRAM-based circuit for implementing multi-bit weight storage and calculation as claimed in claim 2, wherein the calculating step comprises:

calculating respective charge amounts of an Nth bit line LBLT-N terminal and an Nth bit line LBLF-N terminal corresponding to each bit based on the single bit calculation step;

based on the analog calculation step, the output voltage value of the circuit is obtained according to the respective charge amounts of the Nth bit line LBLT-N end and the Nth bit line LBLF-N end of the 10T SRAM cell corresponding to each bit.

5. The SRAM-based circuit for implementing multi-bit weight storage and computation of claim 4, wherein the single-bit computation step comprises:

if the 6T SRAM unit in the 10T SRAM unit corresponding to the Nth bit has 0 and the second NMOS tube is cut off, the voltage V of the LBLT-N end_LBLT-NFor said output GRBL output voltage value V_GRBLThen the charge amount at the LBLT-N terminal is Q_NT＝2^N-1×Cu×V_GRBLWhen the fourth NMOS tube is electrified, the voltage V at the LBLF-N end is obtained_LBLF-N0, the amount of charge Q at the LBLF-N terminal_NFIs 0;

if the 6T SRAM unit in the 10T SRAM unit corresponding to the Nth bit has 1 and the second NMOS tube is powered on, the voltage V of the LBLT-N end_LBLT-N0, the charge quantity Q of the LBLT-N terminal_NTIs the voltage V at the 0, LBLF-N terminal_LBLF-NFor said output terminal GRBL to output a voltage value V_GRBLThen the amount of charge at the LBLF-N terminal is Q_NF＝2^N-1×Cu×V_GRBL。

6. The SRAM-based circuit for implementing multi-bit weight storage and computation of claim 5, wherein the step of performing analog computation comprises:

the charge quantity Q of each of the Nth bit line LBLT-N terminal and the Nth bit line LBLF-N terminal corresponding to each bit_NTAnd Q_NFObtaining the voltage V output by the forward average voltage value output terminal Pavg_PavgAnd the reverse average voltage value output end Navg outputs a voltage value V_Navg；

According to the voltage VPavg output by the forward average voltage value output end Pavg and the voltage value V output by the reverse average voltage value output end Navg_NavgCalculating an output voltage value V as:

V＝V_Pavg-V_Navg。

7. the SRAM-based multi-bit weight storage and calculation circuit of claim 6, wherein the respective charge amounts Q of the Nth bit line LBLT-N and the Nth bit line LBLF-N corresponding to the respective bits_NTAnd Q_NFObtaining the voltage V output by the forward average voltage value output terminal Pavg_PavgAnd the reverse average voltage value output end Navg outputs a voltage value V_NavgThe method comprises the following steps:

the charge quantity Q of the N bit line LBLT-N end corresponding to each bit_NTAnd the number of the first capacitors corresponding to the 10T SRAM cells corresponding to each bit is 2^N-1And the charge amount Cu of each first capacitor is summed to obtain a charge amount summation value Q_TAnd the total charge amount N of all the first capacitors_CAccording to the sum Q of the charge quantities_TAnd all ofTotal charge N of a capacitor_CObtaining the voltage V output by the forward average voltage value output terminal Pavg_PavgComprises the following steps:

charge quantity Q of N bit line LBLF-N end corresponding to each bit_NFAnd the number of the first capacitors corresponding to the 10T SRAM cells corresponding to each bit is 2^N-1And the charge amount Cu of each first capacitor is summed to obtain a charge amount summation value Q_FAnd the total charge amount N of all the first capacitors_CAccording to the sum Q of the charge quantities_FAnd the total charge amount N of all the first capacitors_CObtaining the output voltage value V of the reverse average voltage value output end Navg_NavgComprises the following steps:

8. the circuit according to claim 1, wherein the storing procedure comprises: a write flow and a read flow;

wherein the writing process comprises: when the word line control terminal WL and the enable control terminal EN are simultaneously outputted as high level, the input and output terminals Q1 and Q2 of the 6T SRAM cell of the 10T SRAM cell corresponding to the nth bit are written with data;

the readout flow includes: when the enable control terminal EN output is high level, the input and output terminals Q1 and Q2 of the 6T SRAM cell of the 10T SRAM cell corresponding to the nth bit read data.

9. A storage and emulation computing system, the system comprising:

an SRAM array comprising a plurality of SRAM-based circuits according to any one of claims 1 to 8 for implementing multi-bit weight storage and computation;

and the calculation module is connected with the SRAM array and used for carrying out analog calculation on the output voltage value of the SRAM array based on an analog calculation formula.

10. The storage and analog computing system of claim 9, wherein the analog computing formula comprises:

wherein k is a circuit of a k-th row in the SRAM array, i is a circuit of an i-th column in the SRAM array, and V_YTo be the output voltage value, V_PavgIs the forward average voltage value output by the forward average voltage value output terminal Pavg of the SRAM array, the V_NavgOutputting a voltage value for a reverse average voltage value output terminal Navg of the SRAM array, the V_Y,kIs the average value of the output voltage values of each circuit in the SRAM array, w_k,iThe output value V of the input/output terminal of the 6T SRAM cell corresponding to the N bit of the 10T SRAM cell corresponding to the circuit of the ith row and ith column_GRBLiThe output voltage value of the output terminal GRBL in the circuit of the kth row and the ith column.

Technical Field

The invention relates to the field of data processing, in particular to a circuit for realizing multi-bit weight storage and calculation based on an SRAM (static random access memory) and a storage and analog calculation system.

Background

In recent years, rapid development of AI-related technologies has made our lives more beautiful, and at the same time, has made increasing demands on computing power in various application scenarios. Analog Computing (Analog Computing) saves the loss in time and power consumption caused by data transfer; and the method is suitable for low-power consumption and high-efficiency scenes. In the prior art, the SRAM is generally only applied to the operation memory cell, but the SRAM cannot be used as the basic analog operation unit, and the calculation accuracy cannot meet the requirement.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a circuit for implementing multi-bit weight storage and calculation based on SRAM and a storage and analog calculation system, which solve the problems that the SRAM is generally only applied to an operation storage unit, the SRAM cannot be used as a basic analog operation unit, and the calculation accuracy cannot meet the requirement in the prior art.

To achieve the above and other related objects, the present invention provides a circuit for implementing multi-bit weight storage and calculation based on SRAM, for performing analog calculation and/or storage process, the circuit comprising: the N columns correspond to different bit 10T SRAM units, the first input and output ends of each 10T SRAM unit corresponding to the Nth bit are respectively connected with the LBLT-N end of the Nth bit line, and the second input and output ends of the 10T SRAM units corresponding to the Nth bit are respectively connected with the LBLF-N end of the Nth bit line; wherein N is an integer greater than or equal to 1, and the 10T SRAM cell corresponding to the Nth bit includes: a 6T SRAM cell having input and output terminals Q1 and Q2 for simultaneously inputting and outputting data; the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; one end of the two ends is grounded and is connected in sequence 2^N-1A first capacitor and 2^N-1The charge quantity stored by the first capacitor and the second capacitor is Cu; the six CMOS transmission gates are sequentially marked as P1-P6; and the input and output end Q1 of the 6T SRAM unit is respectively connected with the end of an Nth bit line BL-N1 and the gate of the second NMOS transistor, and the input and output end Q2 of the 6T SRAM unit is respectively connected with the end of an Nth bit line BL-N2 and the gate of the fourth NMOS transistor; the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the drain electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the first NMOS tube is connected with one end of the first capacitor farthest from the grounding end, and the source electrode of the third NMOS tube is connected with one end of the second capacitor farthest from the grounding end; one end of the first capacitor farthest from the ground end is also connected with a CMOS transmission gate P1, a CMOS transmission gate P2 and a CMOS transmission gate P3 respectively; one end of the second capacitor farthest from the ground end is respectively connected with the CMOS transmission gate P4, the CMOS transmission gate P5 and the CMOS transmission gate P6; an output terminal GRBL connected to the CMOS transmission gate P3 and the CMOS transmission gate P6; the read word line RWL is respectively connected with the grid electrode of the first NMOS tube, the grid electrode of the third NMOS tube and the distanceOne end of the first capacitor farthest from the grounding end, one end of the second capacitor farthest from the grounding end, the end of the Nth bit line BL-N1 and the end of the Nth bit line BL-N2 are connected; the word line control end WL and the enabling control end EN are respectively connected to corresponding levels of the circuit; the forward average voltage output terminal Pavg and the reverse average voltage output terminal Navg are respectively connected with the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4 and the CMOS transmission gate P5 in the forward direction and in the reverse direction.

In an embodiment of the present invention, the simulation calculation process includes: a charging step and a calculating step within one clock signal.

In an embodiment of the present invention, the charging step includes: when the outputs of the read word line RWL, the word line control end WL and the enable control end EN are at a high level, and the outputs of the CMOS transmission gate P3 and the CMOS transmission gate P6 are at a low level, the first capacitor and the second capacitor are sequentially charged to the voltages of the input and output ends Q1 and Q2, which are stored in the 6T SRAM cell in advance, respectively; when the read word line RWL, the word line control terminal WL and the enable control terminal EN are at a low level, the CMOS transmission gate P3 and the CMOS transmission gate P6 are at a high level, and the first capacitor and the second capacitor are discharged to the same voltage as the GRBL.

In an embodiment of the present invention, the calculating step includes: calculating respective charge amounts of an Nth bit line LBLT-N terminal and an Nth bit line LBLF-N terminal corresponding to each bit based on the single bit calculation step; based on the analog calculation step, the output voltage value of the circuit is obtained according to the respective charge amounts of the Nth bit line LBLT-N end and the Nth bit line LBLF-N end of the 10T SRAM cell corresponding to each bit.

In an embodiment of the present invention, the single bit calculating step includes: if the 6T SRAM unit in the 10T SRAM unit corresponding to the Nth bit has 0 and the second NMOS tube is cut off, the voltage V of the LBLT-N end_LBLT-NFor said output GRBL output voltage value V_GRBLThen the charge amount at the LBLT-N terminal is Q_NT＝2^N-1×Cu×V_GRBLWhen the fourth NMOS tube is electrified, the voltage V at the LBLF-N end is obtained_LBLF-N0, the amount of charge at the LBLF-N terminalQ_NFIf the number 0 corresponds to the number 1 of the 6T SRAM cell in the 10T SRAM cell of the Nth bit and the second NMOS transistor is powered on, the voltage V at the LBLT-N end_LBLT-N0, the charge quantity Q of the LBLT-N terminal_NTIs the voltage V at the 0, LBLF-N terminal_LBLF-NFor said output terminal GRBL to output a voltage value V_GRBLThen the amount of charge at the LBLF-N terminal is Q_NF＝2^N-1×Cu×V_GRBL。

In an embodiment of the present invention, the simulation calculating step includes: the charge quantity Q of each of the Nth bit line LBLT-N terminal and the Nth bit line LBLF-N terminal corresponding to each bit_NTAnd Q_NFObtaining the voltage V output by the forward average voltage value output terminal Pavg_PavgAnd the reverse average voltage value output end Navg outputs a voltage value V_Navg(ii) a According to the voltage VPavg output by the forward average voltage value output end Pavg and the voltage value V output by the reverse average voltage value output end Navg_NavgCalculating an output voltage value V as: v is V_Pavg-V_Navg。

In an embodiment of the invention, the charge amount Q of each of the Nth bit line LBLT-N and the Nth bit line LBLF-N corresponding to each bit_NTAnd Q_NFObtaining the voltage V output by the forward average voltage value output terminal Pavg_PavgAnd the reverse average voltage value output end Navg outputs a voltage value V_NavgThe method comprises the following steps: the charge quantity Q of the N bit line LBLT-N end corresponding to each bit_NTAnd the number of first capacitors corresponding to the 10T SRAM cells corresponding to each bit is 2^N-1And the charge amount Cu of each first capacitor is summed to obtain a charge amount summation value Q_TAnd the total charge amount N of all the first capacitors_CAccording to the sum Q of the charge quantities_TAnd the total charge amount N of all the first capacitors_CObtaining the voltage V output by the forward average voltage value output terminal Pavg_PavgComprises the following steps:charge quantity Q of N bit line LBLF-N end corresponding to each bit_NFAnd 10T SRAM cell correspondence for each bit2 of the first capacitor^N-1And the charge amount Cu of each first capacitor is summed to obtain a charge amount summation value Q_FAnd the total charge amount N of all the first capacitors_CAccording to the sum Q of the charge quantities_FAnd the total charge amount N of all the first capacitors_CObtaining the output voltage value V of the reverse average voltage value output end Navg_NavgComprises the following steps:

in an embodiment of the present invention, the storing process includes: a write flow and a read flow; wherein the writing process comprises: when the word line control terminal WL and the enable control terminal EN are simultaneously outputted as high level, the input and output terminals Q1 and Q2 of the 6T SRAM cell of the 10T SRAM cell corresponding to the nth bit are written with data; the readout flow includes: when the enable control terminal EN output is high level, the input and output terminals Q1 and Q2 of the 6T SRAM cell of the 10T SRAM cell corresponding to the nth bit read data.

To achieve the above and other related objects, the present invention provides a storage and emulation computing system, comprising: the SRAM array is formed by a plurality of circuits which realize multi-bit weight storage and calculation based on the SRAM; and the calculation module is connected with the SRAM array and used for carrying out analog calculation on the output voltage value of the SRAM array based on an analog calculation formula.

In an embodiment of the present invention, the simulation calculation formula includes:

wherein k is a circuit of a k-th row in the SRAM array, i is a circuit of an i-th column in the SRAM array, and V_YTo output voltage value, thereforeV is_PavgIs the forward average voltage value output by the forward average voltage value output terminal Pavg of the SRAM array, the V_NavgOutputting a voltage value for a reverse average voltage value output terminal Navg of the SRAM array, the V_Y,kIs the average value of the output voltage values of each circuit in the SRAM array, w_k,iThe output value V of the input/output terminal of the 6T SRAM cell corresponding to the N bit of the 10T SRAM cell corresponding to the circuit of the ith row and ith column_GRBLiThe output voltage value of the output terminal GRBL in the circuit of the kth row and the ith column.

As described above, the circuit for implementing multi-bit weight storage and calculation based on SRAM and the storage and analog calculation system of the present invention have the following advantages: the invention makes full use of the characteristics of the SRAM, enables the SRAM to have storage capacity and calculation capacity, and endows the storage array with capacity of weight storage and calculation by additionally adding the capacitors with different capacitance values in the N columns corresponding to different bits, and improves the calculation precision.

Drawings

Fig. 1 is a schematic structural diagram of a circuit for implementing multi-bit weight storage and calculation based on SRAM according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a storage and emulation computing system according to an embodiment of the present invention.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

It is noted that in the following description, reference is made to the accompanying drawings which illustrate several embodiments of the present invention. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "below," "lower," "over," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as illustrated in the figures.

Throughout the specification, when a part is referred to as being "connected" to another part, this includes not only a case of being "directly connected" but also a case of being "indirectly connected" with another element interposed therebetween. In addition, when a certain part is referred to as "including" a certain component, unless otherwise stated, other components are not excluded, but it means that other components may be included.

The terms first, second, third, etc. are used herein to describe various elements, components, regions, layers and/or sections, but are not limited thereto. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the present invention.

Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," and/or "comprising," when used in this specification, specify the presence of stated features, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, operations, elements, components, items, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions or operations are inherently mutually exclusive in some way.

The circuit for realizing multi-bit weight storage and calculation based on the SRAM provided by the embodiment of the invention fully utilizes the characteristics of the SRAM, so that the SRAM not only has storage capacity, but also has calculation capacity, and the capacity of weight storage and calculation can be given to the SRAM by additionally adding different capacitance values of N columns of capacitors corresponding to different bits in a storage array, and the calculation precision is improved.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that those skilled in the art can easily implement the embodiments of the present invention. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

Fig. 1 is a schematic structural diagram of a circuit for implementing multi-bit weight storage and calculation based on SRAM according to an embodiment of the present invention.

For performing analog computation and/or storage procedures, the circuit comprising:

N10T SRAM units which correspond to different bit weights and are sequentially arranged in a column, wherein the first input and output ends of each 10T SRAM unit corresponding to the Nth bit are respectively connected with the LBLT-N end of the Nth bit line, and the second input and output ends of each 10T SRAM unit corresponding to the Nth bit are respectively connected with the LBLF-N end of the Nth bit line; n is an integer greater than or equal to 1; for example, LBL _ T0_0, LBL _ F0_0, LBL _ T0_1, LBL _ F0_1, LBL _ T0_ N-1, and LBL _ F0_ N-1 in FIG. 1;

wherein the 10T SRAM cell corresponding to the Nth bit includes: a 6T SRAM cell 6T having input and output terminals Q1 and Q2 for simultaneously inputting and outputting data; a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a fourth NMOS transistor NM 4; 2N-1 first capacitors C1 and 2N-1 second capacitors C2, one end of each of which is grounded, are connected in sequence, and the charge amount stored in the first capacitors and the charge amount stored in the second capacitors are Cu; the six CMOS transmission gates are sequentially marked as P1-P6;

and the input and output end Q1 of the 6T SRAM cell 6T is respectively connected to the end of the nth bit line BL-N1 and the gate of the second NMOS transistor NM2, and the input and output end Q2 of the 6T SRAM cell 6T is respectively connected to the end of the nth bit line BL-N2 and the gate of the fourth NMOS transistor NM 4; the drain of the first NMOS transistor NM1 is connected to the drain of the second NMOS transistor NM2, the drain of the third NMOS transistor NM3 is connected to the drain of the fourth NMOS transistor NM4, the source of the first NMOS transistor NM1 is connected to the end of the first capacitor C1 farthest from the ground terminal, and the source of the third NMOS transistor NM3 is connected to the end of the second capacitor C2 farthest from the ground terminal; one end of the first capacitor C1 farthest from the ground end is further connected to the CMOS transmission gate P1, the CMOS transmission gate P2 and the CMOS transmission gate P3 respectively; one end of the second capacitor C2 farthest from the ground end is connected to the CMOS transmission gate P4, the CMOS transmission gate P5 and the CMOS transmission gate P6 respectively; an output terminal GRBL connected to the CMOS transmission gate P3 and the CMOS transmission gate P6; the read word line RWL is respectively connected to the gate of the first NMOS transistor NM1, the gate of the third NMOS transistor NM3, the end of the first capacitor C1 farthest from the ground, the end of the second capacitor C2 farthest from the ground, the end of the nth bit line BL-N1, and the end of the nth bit line BL-N2; the word line control end WL and the enabling control end EN are respectively connected to corresponding levels of the circuit; the forward average voltage output terminal Pavg and the reverse average voltage output terminal Navg are respectively connected with the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4 and the CMOS transmission gate P5 in the forward direction and in the reverse direction.

In fig. 1, three 10T SRAM cells are taken as an example, and the number of 10T SRAM cells in the present application is not limited thereto.

Optionally, the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4, and the CMOS transmission gate P5 are configured to open a switch when a forward average voltage value and/or a reverse average voltage value needs to be calculated in the analog calculation process; and/or the CMOS transmission gate P3 and the CMOS transmission gate P6 are used for opening a switch when multiplication calculation is needed in the analog calculation flow.

Specifically, the CMOS transmission gate P1, the CMOS transmission gate P2, the CMOS transmission gate P4, and the CMOS transmission gate P5 are used for turning on a switch when a forward average voltage value and/or a reverse average voltage value needs to be calculated, or turning off the switch when the forward average voltage value and/or the reverse average voltage value needs to be calculated; the CMOS transmission gate P3 and the CMOS transmission gate P6 are used for opening the switch when multiplication calculation is needed in the analog calculation flow, otherwise, the switch is closed.

Preferably, the CMOS transmission gate P1 is the same as the CMOS transmission gate P4, the CMOS transmission gate P2 is the same as the CMOS transmission gate P5, and the CMOS transmission gate P3 is the same as the CMOS transmission gate P6.

Optionally, the storing process includes: a write flow and a read flow; wherein the writing process comprises: when the word line control terminal WL and the enable control terminal EN are simultaneously outputted as high level, the input and output terminals Q1 and Q2 of the 6T SRAM cell of the 10T SRAM cell corresponding to the nth bit are written with data; the readout flow includes: the readout flow includes: when the enable control terminal EN output is high level, the input and output terminals Q1 and Q2 of the 6T SRAM cell of the 10T SRAM cell corresponding to the nth bit read data.

Optionally, the simulation calculation process includes: a charging step and a calculating step into which one clock signal is divided.

Optionally, the charging step includes: the charging step includes: when the outputs of the read word line RWL, the word line control terminal WL and the enable control terminal EN are at a high level, and the outputs of the CMOS transmission gate P3 and the CMOS transmission gate P6 are at a low level, the first capacitor C1 and the second capacitor C2 are sequentially charged to the voltages of the input and output terminals Q1 and Q2 pre-stored in the 6T SRAM cell 6T, respectively; when the read word line RWL, the word line control terminal WL and the enable control terminal EN are at a low level, the outputs of the CMOS transmission gate P3 and the CMOS transmission gate P6 are at a high level, and the first capacitor C1 and the second capacitor C2 are discharged to the same voltage as the GRBL voltage, so as to complete the calculation step.

Optionally, the calculating step includes: calculating respective charge amounts of an Nth bit line LBLT-N terminal and an Nth bit line LBLF-N terminal corresponding to each bit based on the single bit calculation step; based on the analog calculation step, the output voltage value of the circuit is obtained according to the respective charge amounts of the Nth bit line LBLT-N end and the Nth bit line LBLF-N end of the 10T SRAM cell corresponding to each bit.

Optionally, the single-bit calculating step includes: if the 6T SRAM cell of the 10T SRAM cells corresponding to the Nth bit has 0 and the second NMOS transistor NM2 is turned off, the voltage V at the LBLT-N terminal_LBLT-NFor said output GRBL output voltage value V_GRBLThen the charge amount at the LBLT-N terminal is Q_NT＝2^N-1×Cu×V_GRBLWhen the fourth NMOS tube NM4 is powered on, the voltage V at the LBLF-N end is obtained_LBLF-NIf the charge quantity QF is 0, the charge quantity QF at the LBLF-N end is 0; if the 6T SRAM cell in the 10T SRAM cell corresponding to the Nth bit has 1 and the second NMOS transistor NM2 is powered on, the voltage V at the LBLT-N terminal_LBLT-N0, the charge quantity Q of the LBLT-N terminal_NIs the voltage V at the 0, LBLF-N terminal_LBLF-NFor said output GRBL output voltage value V_GRBLThen the amount of charge at the LBLF-N terminal is Q_NF＝2^N-1×Cu×V_GRBL。

Optionally, the single-bit calculation step is performed based on different weight values, if N is equal to 2, the 1 st bit 10T SRAM cell is set as the LSB weight, and the 2 nd bit 10T SRAM cell is set as the MSB weight; if N is more than 2, setting the 10T SRAM unit of the 1 st bit as LSB weight, setting the 10T SRAM units of the 2 nd to N-1 th bits as MSB-N-1 weight, and setting the 10T SRAM unit of the N th bit as MSB weight;

if N is equal to 2, the weight value has two bits, and has the following conditions:

(1) when the weight value is 00, the number of the 10T SRAM cells corresponding to the 1 st bit of the LSB weight is 0, and the second NMOS transistor NM2 is turned off, the voltage V at the LBL _ T0_0 end is V_{LBL_T0_0}For said output GRBL output voltage value V_GRBLThen the charge amount at the end of LBL _ T0_0 is Q_1T＝Cu×V_GRBLWhen the fourth NMOS transistor NM4 is turned on, the voltage V at the LBL _ F0_0 terminal is increased_{LBL_F0_0}0, the charge amount Q at the end of LBL _ F0_0_1FIs 0; then 0 exists in the 6T SRAM cell of the 10T SRAM cells of the 2 nd bit corresponding to the MSB weight, and the NM of the second NMOS transistor2 is turned off, and the read word line RWL is high, the voltage V at the end of LBL _ T0_1_{LBL_T0_1}For said output GRBL output voltage value V_GRBLThen the charge amount at the end of LBL _ T0_1 is Q_2T＝2Cu×V_GRBLWhen the fourth NMOS transistor NM4 is turned on, the voltage V at the LBL _ F0_1 end is increased_{LBL_F0_1}0, the charge amount Q at the end of LBL _ F0_1_2FIs 0;

(2) if the weight value is 10, the 6T SRAM cell of the 10T SRAM cell corresponding to the 1 st bit of the LSB weight has 0, and the second NMOS transistor NM2 is turned off, the voltage V at the LBL _ T0_0 end is V_{LBL_T0_0}For said output GRBL output voltage value V_GRBLThen the charge amount at the end of LBL _ T0_0 is Q_1T＝Cu×V_GRBLWhen the fourth NMOS transistor NM4 is turned on, the voltage V at the LBL _ F0_0 terminal is increased_{LBL_F0_0}0, the charge amount Q at the end of LBL _ F0_0_1FIs 0; the 6T SRAM cell of the 2 nd bit 10T SRAM cell corresponding to the MSB weight has 1, the second NMOS transistor NM2 is powered on, and the voltage V at the LBL _ T0_1 terminal is_{LBL_T0_1}0, the charge amount Q at the end of LBL _ T0_1_2TVoltage V at LBL _ F0_1 terminal is 0_{LBL_F0_1}For said output GRBL output voltage value V_GRBLThen the charge amount at the end of LBL _ F0_1 is Q_2F＝2Cu×V_GRBL；

(3) If the weighted value is 01, the 6T SRAM cell of the 10T SRAM cell corresponding to the 1 st bit of the LSB weight has 1, and if the second NMOS transistor NM2 is powered on, the voltage V at the LBL _ T0_0 end is applied_{LBL_T0_0}0, the charge amount Q at the end of LBL _ T0_0_1TIs 0, voltage V at LBL _ F0_0 terminal_{LBL_F0_0}For said output GRBL output voltage value V_GRBLThen the charge amount at the end of LBL _ F0_0 is Q_1F＝Cu×V_GRBL(ii) a Then 0 exists in the 6T SRAM cell of the 2 nd bit 10T SRAM cell corresponding to the MSB weight, the second NMOS transistor NM2 is turned off, the read word line RWL is high, and the voltage V at the LBL _ T0_1 end is high_{LBL_T0_1}For said output GRBL output voltage value V_GRBLThen the charge amount at the end of LBL _ T0_1 is Q_2T＝2Cu×V_GRBLWhen the fourth NMOS transistor NM4 is turned on, the voltage V at the LBL _ F0_1 end is increased_{LBL_F0_1}0, the charge amount Q at the end of LBL _ F0_1_2FIs 0;

(4) weighted value of11, if the 6T SRAM cell of the 10T SRAM cell corresponding to the 1 st bit of the LSB weight has 1, the second NMOS transistor NM2 is powered on, and the voltage V at the LBL _ T0_0 terminal is set to be 1_{LBL_T0_0}0, the charge amount Q at the end of LBL _ T0_0_1TIs 0, voltage V at LBL _ F0_0 terminal_{LBL_F0_0}For said output GRBL output voltage value V_GRBLThen the charge amount at the end of LBL _ F0_0 is Q_1F＝Cu×V_GRBL(ii) a The 6T SRAM cell of the 2 nd bit 10T SRAM cell corresponding to the MSB weight has 1, the second NMOS transistor NM2 is powered on, and the voltage V at the LBL _ T0_1 terminal is_{LBL_T0_1}0, the charge amount Q at the end of LBL _ T0_1_2TVoltage V at LBL _ F0_1 terminal is 0_{LBL_F0_1}For said output GRBL output voltage value V_GRBLThen the charge amount at the end of LBL _ F0_1 is Q_2F＝2Cu×V_GRBL；

If N is greater than 2, the weighted value has N binary digits, the Nth bit corresponds to the 10T SRAM unit of the Nth bit, and then the 10T SRAM units corresponding to the Nth bit are respectively calculated at 2^NThe calculation steps of the respective charge amounts of the LBLT-N terminal and the LBLF-N terminal of the 10T SRAM cell corresponding to the nth bit obtained under the condition of the weight value are similar to those when N is equal to 2, and therefore, the description is omitted.

Optionally, the step of analog computation includes: the charge quantity Q of each of the Nth bit line LBLT-N terminal and the Nth bit line LBLF-N terminal corresponding to each bit_NTAnd Q_NFObtaining the voltage VPavg output by the forward average voltage value output end Pavg and the output voltage value V of the reverse average voltage value output end Navg_Navg(ii) a According to the voltage V output by the forward average voltage value output end Pavg_PavgAnd the reverse average voltage value output end Navg outputs a voltage value V_NavgCalculating an output voltage value V as:

V＝V_Pavg-V_Navg； (1)

optionally, the charge amount Q of each of the nth bit line LBLT-N and the nth bit line LBLF-N corresponding to each bit is set to be larger than the charge amount Q of each of the nth bit line LBLT-N corresponding to each bit_NTAnd Q_NFObtaining the voltage V output by the forward average voltage value output terminal Pavg_PavgAnd the reverse average voltage value output end Navg outputs a voltage value V_NavgThe method comprises the following steps:

the charge quantity Q of the N bit line LBLT-N end corresponding to each bit_NTAnd the number of first capacitors corresponding to the 10T SRAM cells corresponding to each bit is 2^N-1And the charge amount Cu of each first capacitor is summed to obtain a charge amount summation value Q_TAnd the total charge amount N of all the first capacitors_CObtaining the voltage VPavg output by the forward average voltage value output end Pavg according to the charge quantity summation value Q and the first capacitance number summation value C, wherein the voltage VPavg is as follows:

charge quantity Q of N bit line LBLF-N end corresponding to each bit_NFAnd the number of first capacitors corresponding to the 10T SRAM cells corresponding to each bit is 2^N-1And the charge amount Cu of each first capacitor is summed to obtain a charge amount summation value Q_FAnd the first sum of the number of capacitors N_CAccording to the sum Q of the charge quantities_FAnd the total charge amount N of all the first capacitors_CObtaining the output voltage value V of the reverse average voltage value output end Navg_NavgComprises the following steps:

for example, if N is equal to 2, the weight value has two bits, and the following cases are respectively provided:

(1) when the weight value is 00, the charge amount at the end LBL _ T0_0 is Q_1T＝Cu×V_GRBLThe charge amount at the LBL _ T0_1 terminal is Q_2T＝2Cu×V_GRBLThe amount of charge Q at the end of LBL _ F0_0_1F0, the amount of charge Q at the end of LBL _ F0_1_2FIs 0; the sum of the charge amounts Q_T：

Q_T＝Q_1T+Q_2T＝Cu×V_GRBL+2Cu×V_GRBL＝3Cu×V_GRBL； (4)

Q_F＝Q_1F+Q_2F＝0； (5)

N_C＝(1+2)Cu＝3Cu； (6)

Further, the output voltage value V is:

V＝V_Pavg-V_Navg＝V_GRBL； (9)

(2) when the weight value is 10, the charge amount at the end of LBL _ T0_0 is Q_1T＝Cu×V_GRBLThe charge amount at the LBL _ T0_1 terminal is Q_2T0, the amount of charge Q at the end of LBL _ F0_0_1F0, the amount of charge Q at the end of LBL _ F0_1_2FIs 2 CuxV_GRBL(ii) a Then Q is_T＝Q_1T+Q_2T＝Cu×V_GRBL+0＝Cu×V_GRBL；Q_F＝2Cu×V_GRBL；N_C＝(1+2)Cu＝3Cu；Further, the output voltage value V is:

(3) when the weight value is 01, the charge amount at the end of LBL _ T0_0 is Q_1T0, and the charge amount at the LBL _ T0_1 terminal is Q_2TIs 2 CuxV_GRBLAmount of charge Q at LBL _ F0_0 terminal_1FIs Cu x V_GRBLAmount of charge Q at LBL _ F0_1 terminal_2FIs 0; then Q is_T＝Q_1T+Q_2T＝2Cu×V_GRBL；Q_F＝Cu×V_GRBL；N_C＝(1+2)Cu＝3Cu； Further, the output voltage value V is:

(4) when the weight value is 11, the charge amount at the end of LBL _ T0_0 is Q_1T0, and the charge amount at the LBL _ T0_1 terminal is Q_2T0, the amount of charge Q at the end of LBL _ F0_0_1FIs Cu x V_GRBLAmount of charge Q at LBL _ F0_1 terminal_2FIs 2 CuxV_GRBL(ii) a Then Q is_T＝0；Q_F＝3Cu×V_GRBL；N_C＝(1+2)Cu＝3Cu；V_Pavg＝0；V_Navg＝V_GRBL. Further, the output voltage value V is: -V_GRBL；

Fig. 2 shows a schematic structural diagram of a storage and emulation computing system in an embodiment of the present invention.

The system comprises:

an SRAM array 21 composed of a plurality of SRAM-based multi-bit weight storage and calculation circuits 211 as shown in FIG. 1;

and the calculation module 22 is connected with the SRAM array 21 and is configured to perform analog calculation on the output voltage value of the SRAM array based on an analog calculation formula.

The circuit 211 for implementing storage and analog computation based on SRAM comprises: n columns correspond to 10T SRAM cells 2111 of different bits; and the 10T SRAM cell corresponding to the nth bit includes: a 6T SRAM cell having input and output terminals Q1 and Q2 for simultaneously inputting and outputting data; the NMOS transistor comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; one end of the two ends is grounded and is connected in sequence 2^N-1A first capacitor and 2^N-1A second capacitor; the six CMOS transmission gates are sequentially marked as P1-P6; it should be noted that the connection relationship of the specific components is the same as the connection manner of fig. 1, and therefore, the detailed description thereof is omitted.

Optionally, the number of the circuits 211 for implementing storage and analog computation based on SRAM is at least two, and four are taken as an example in fig. 2.

Optionally, the SRAM array 21 may copy a connection method of the circuit 211 for implementing storage and analog computation based on the SRAM, and extend to the SRAM array, and meanwhile, has read-write and operation capabilities. The extending mode may be that N lines are transversely extended in the columns, or K lines are extended in the rows, and the total number of circuits in one array is equal to N × K.

Optionally, the simulation calculation formula includes:

wherein k is a circuit of a k-th row in the SRAM array, i is a circuit of an i-th column in the SRAM array, and V_YTo be the output voltage value, V_PavgIs the forward average voltage value output by the forward average voltage value output terminal Pavg of the SRAM array, the V_NavgOutputting a voltage value for a reverse average voltage value output terminal Navg of the SRAM array, the V_Y,kIs the average value of the output voltage values of each circuit in the SRAM array, w_k,iThe output value V of the input and output ends of the 6T SRAM unit of the 10T SRAM unit corresponding to the Nth bit corresponding to the circuit of the ith row and the ith column_GRBLiThe output voltage value of the output terminal GRBL in the circuit of the kth row and the ith column.

Specifically, the way for the calculation module 22 to perform analog calculation on the output voltage value of the SRAM array based on the analog calculation formula includes:

multiplying output values of 6T SRAM units of 10T SRAM units corresponding to Nth bits and corresponding to circuits of the ith row and the ith column by output voltage values VGRBLi of output ends GRBL in the circuits of the corresponding ith row and the ith column, summing the multiplication values calculated by the circuits and dividing the sum by the number of the circuits to obtain an average value of the output voltage values of the circuits in the SRAM array;

then the output voltage values of the circuits in the same row are summed to be equal to the subtraction value of the forward average voltage value output by the forward average voltage value output terminal Pavg and the reverse average voltage value output by the reverse average voltage value output terminal Navg.

In summary, the circuit for realizing multi-bit weight storage and calculation based on the SRAM and the storage and analog calculation system make full use of the characteristics of the SRAM, so that the SRAM has not only storage capability but also calculation capability, and by additionally adding different capacitance values of the capacitor N columns corresponding to different bits in the storage array, the capacity of weight storage and calculation is given to the SRAM, and the calculation accuracy is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles of the present invention and its efficacy, and are not to be construed as limiting the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.