阅读说明：本技术 用于模拟行存取跟踪的设备和方法 (Apparatus and method for simulating row access tracking ) 是由 吴俊� 李亮 张煜 潘栋 于 2020-08-17 设计创作，主要内容包括：本公开的实施例是针对用于模拟行存取跟踪的设备和方法。提供多个单位单元,所述单位单元中的每一个含有用以跟踪对存储器装置的字线的一部分的存取的一或多个模拟电路。当所述部分中的字线被存取时,所述单位单元可例如通过将电荷添加到电容器,更新累加器电压。比较器电路可确定一或多个累加器电压何时越过阈值(例如,参考电压)。响应于所述累加器电压越过所述阈值,可将侵略者地址加载于目标刷新队列中,或如果所述侵略者地址已经处于所述队列中,可设置与所述地址相关联的优先级旗标。可提供侵略者地址以按基于设置的优先级旗标的数目的次序来刷新所述侵略者地址的受害者。(Embodiments of the present disclosure are directed to apparatus and methods for simulating row access tracking. A plurality of unit cells are provided, each of which contains one or more analog circuits to track access to a portion of a word line of a memory device. When the word line in the portion is accessed, the unit cell can update the accumulator voltage, for example, by adding charge to the capacitor. The comparator circuit may determine when one or more accumulator voltages cross a threshold (e.g., a reference voltage). In response to the accumulator voltage crossing the threshold, an aggressor address may be loaded in a target refresh queue, or if the aggressor address is already in the queue, a priority flag associated with the address may be set. Aggressor addresses may be provided to refresh victims of the aggressor addresses in an order based on the number of priority flags set.)

1. An apparatus, comprising:

a plurality of unit cells, each of the unit cells configured to store one of a plurality of voltages and compare the stored one of the plurality of voltages to a reference voltage, wherein a selected one of the plurality of unit cells is configured to update the stored one of the plurality of voltages in response to a selection signal indicating one of the plurality of unit cells; and

a stack control circuit configured to receive a row address and provide the select signal to one of the plurality of unit cells based on the row address, wherein the stack control circuit is configured to provide a trigger signal in response to the stored one of the plurality of voltages crossing the reference voltage.

2. The apparatus of claim 1, wherein the stack control circuit comprises a decoder circuit configured to receive the row address and provide the selection signal based on a subset of bits of the row address.

3. The apparatus of claim 2, wherein the plurality of unit cells each represent a different value of the subset of bits of the row address, and wherein the plurality of unit cells together represent all values of the subset of bits of the row address.

4. The apparatus of claim 1, wherein each unit cell comprises an accumulator circuit including a capacitor, and wherein the stored voltage is based on a charge on the capacitor, and wherein in response to the select signal, the unit cell is configured to update the charge on the capacitor.

5. The apparatus of claim 1, wherein each of the plurality of unit cells comprises a comparator portion, and wherein the stack control circuit comprises a comparator circuit commonly coupled to the comparator portion in each of the plurality of unit cells, wherein in response to the select signal indicating one of the plurality of unit cells, the comparator circuit and the comparator portion in the one of the plurality of unit cells compare the stored one of the plurality of voltages to the reference voltage.

6. The apparatus of claim 1, further comprising:

a target refresh queue configured to store a plurality of row addresses; and

stealing address circuitry configured to selectively store a queue address based on the received row address in the target refresh queue based in part on the trigger signal.

7. The apparatus of claim 6, wherein one or more victim addresses based on the queue address stored in the target refresh queue are refreshed.

8. An apparatus, comprising:

an accumulator circuit comprising a capacitor, the accumulator circuit configured to provide an accumulator voltage based on a charge of the capacitor, the accumulator circuit further configured to add an amount of charge to the capacitor in response to a selection signal;

a comparator circuit configured to compare the accumulator voltage to a reference voltage and to provide a trigger signal in response to the accumulator voltage being higher than the reference voltage; and

a flag logic circuit configured to set logic levels of a plurality of flag signals based in part on the trigger signal.

9. The apparatus of claim 8, further comprising a decoder circuit configured to receive a row address and provide the select signal based on the row address.

10. The apparatus of claim 8, wherein the amount of charge added to the capacitor is based in part on a bias voltage, and wherein the bias voltage is adjustable.

11. The apparatus of claim 8, wherein the capacitor is a crown capacitor or a switched capacitor.

12. The apparatus of claim 8, further comprising a pulse generator circuit configured to provide an activation signal having a pulse width, wherein the amount of charge added to the capacitor is based in part on the pulse width.

13. The apparatus of claim 8, wherein the flag logic circuit is configured to change the logic level of one of the plurality of flag signals from a low logic level to a high logic level in response to the trigger signal.

14. The apparatus of claim 13, further comprising a discharge logic circuit configured to discharge the capacitor in response to the flag logic circuit changing the logic level of one of the plurality of flag signals.

15. An apparatus, comprising:

a memory including a plurality of word lines associated with a row address;

a stack configured to store a plurality of voltages, wherein each of the plurality of voltages is associated with a portion of the plurality of word lines, wherein the stack is configured to change a selected voltage of the plurality of voltages in response to receiving a row address associated with the portion of the plurality of word lines associated with the selected voltage of the plurality of voltages, and wherein the stack provides a trigger signal if the selected voltage of the plurality of voltages crosses a threshold; and

a target refresh queue configured to store a queue address based on the row address in response to the trigger signal.

16. The apparatus of claim 15, wherein the queue address represents a same portion of the plurality of word lines as the portion of the plurality of word lines associated with the selected one of the plurality of voltages.

17. The apparatus of claim 15, wherein each stored queue address in the target refresh queue is associated with a first priority flag and a second priority flag.

18. The apparatus of claim 17, wherein the first priority flag is set when a first queue address is stored in the target refresh queue, and wherein the second priority flag is set in response to a second queue address provided to the target refresh queue matching the first queue address.

19. The apparatus of claim 17, wherein the target refresh queue is configured to provide one of the stored queue addresses, and wherein one or more of the plurality of word lines are refreshed based on the provided one of the stored queue addresses.

20. The apparatus of claim 19, wherein a stored queue address in which the first priority flag and the second priority flag are in an active state is provided before the stored queue address in which the first priority flag is in the active state and the second priority flag is in an inactive state.

Technical Field

The present disclosure relates to memory devices, and in particular, to apparatus and methods for simulating row access tracking.

Background

Information may be stored as physical signals (e.g., charge on capacitive elements) on individual memory cells of a memory. The memory may be volatile memory and the physical signals may decay over time (which may degrade or destroy information stored in the memory cells). It may be necessary to periodically refresh the information in the memory cells by, for example, overwriting the information to restore the physical signal to an initial value.

As the size of memory bank pieces decreases, the density of memory cells increases dramatically. An auto-refresh operation may be performed in which the sequence of memory cells is periodically refreshed. Repeated access to a particular memory cell or group of memory cells, commonly referred to as 'row hammer,' may result in an increased rate of data degradation in nearby memory cells. In addition to the auto-refresh operation, it may be desirable to identify and refresh memory cells affected by row hammer in the targeted refresh operation.

Disclosure of Invention

In one aspect, the present application provides an apparatus comprising: a plurality of unit cells, each of the unit cells configured to store one of a plurality of voltages and compare the stored one of the plurality of voltages to a reference voltage, wherein a selected one of the plurality of unit cells is configured to update the stored one of the plurality of voltages in response to a selection signal indicating one of the plurality of unit cells; and a stack control circuit configured to receive a row address and provide the select signal to one of the plurality of unit cells based on the row address, wherein the stack control circuit is configured to provide a trigger signal in response to the stored one of the plurality of voltages crossing the reference voltage.

In another aspect, the present application additionally provides an apparatus comprising: an accumulator circuit comprising a capacitor, the accumulator circuit configured to provide an accumulator voltage based on a charge of the capacitor, the accumulator circuit further configured to add an amount of charge to the capacitor in response to a selection signal; a comparator circuit configured to compare the accumulator voltage to a reference voltage and to provide a trigger signal in response to the accumulator voltage being higher than the reference voltage; and a flag logic circuit configured to set logic levels of a plurality of flag signals based in part on the trigger signal.

In yet another aspect, the present application additionally provides an apparatus comprising: a memory including a plurality of word lines associated with a row address; a stack configured to store a plurality of voltages, wherein each of the plurality of voltages is associated with a portion of the plurality of word lines, wherein the stack is configured to change a selected voltage of the plurality of voltages in response to receiving a row address associated with the portion of the plurality of word lines associated with the selected voltage of the plurality of voltages, and wherein the stack provides a trigger signal if the selected voltage of the plurality of voltages crosses a threshold; and a target refresh queue configured to store a queue address based on the row address in response to the trigger signal.

Drawings

Fig. 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

FIG. 2 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure.

FIG. 3 is a block diagram of a row access trace stack according to an embodiment of the present disclosure.

Fig. 4 is a schematic diagram illustrating a stack control circuit according to an embodiment of the present disclosure.

Fig. 5 is a schematic diagram of a unit cell according to an embodiment of the present disclosure.

FIG. 6 is a schematic diagram of a first flag latch and a second flag latch according to an embodiment of the present disclosure.

7A-7B are block diagrams of memory arrays according to embodiments of the present disclosure.

FIG. 8 is a block diagram of a memory array according to an embodiment of the present disclosure.

Detailed Description

The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the disclosure, its application, or uses. In the following detailed description of embodiments of the present systems and methods, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosed systems and methods, and it is to be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Furthermore, for the purpose of clarity, detailed descriptions of certain features will not be discussed when apparent to those of ordinary skill in the art so as not to obscure the description of the embodiments of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

A memory device may include a plurality of memory cells. Memory cells may store information (e.g., as one or more bits) and may be organized at the intersections of word lines (rows) and bit lines (columns). A number of word lines and bit lines may be organized into memory banks. A memory device may include a number of different memory banks. The memory device may receive one or more command signals, which may indicate an operation in one or more of the banks of one or more memory packages. The memory device may enter a refresh mode in which word lines in one or more of the memory banks are refreshed.

The information in the memory cells may decay over time. The memory cells may be refreshed row by row to maintain the information in the memory cells. During a refresh operation, information in one or more rows may be rewritten back to the corresponding row to restore the initial value of the information. Repeated accesses to a given row (e.g., an aggressor row) may cause the rate at which information in one or more neighboring rows (e.g., a victim row) decays to increase. Accesses to different rows of memory may be tracked in order to determine a possible victim row and refresh the victim row as part of a targeted (or 'row hammer') refresh operation. However, tracking each row access separately with a digital counter may be difficult due to space and/or power limitations of the device.

The present disclosure is directed to apparatus, systems, and methods for simulating row access tracking. The refresh control circuit may include a number of analog unit cells, each of which includes a number of circuits to track access to one or more word lines of the memory device. Each unit cell may track access to a portion of a word line, and together the unit cells may track access to all word lines of the memory. When a given word line is accessed, the stack control circuit may send a signal to the unit cell that tracks that word line. In response to those signals, the unit cell may update the voltage (e.g., by increasing the amount of charge on the capacitor). Based on the voltage (e.g., when the voltage crosses a reference voltage), one or more word lines associated with a unit cell may be flagged for a targeted refresh operation.

In some embodiments, the refresh control circuit may also include a target refresh queue that may store addresses for refresh after being flagged for refresh by the unit cell as part of a target refresh operation. When a voltage in one of the unit cells crosses a threshold level (e.g., a reference voltage), one or more addresses associated with the unit cell may be added to the target refresh queue and the voltage in the unit cell may be reset. In some embodiments, each address in the target refresh queue may include one or more priority flags. When the voltage in a unit cell crosses a threshold, one or more of the priority flags (e.g., the levels of the switchable flags) may be set if the address associated with the unit cell is already in the target refresh queue (e.g., when the queue address to be stored matches one of the stored queue addresses). Addresses in the target refresh queue may be refreshed in an order based on the number of priority flags set.

Fig. 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a dxadm device integrated on a single semiconductor chip.

The semiconductor device 100 includes a memory array 112. In some embodiments, memory array 112 may include multiple memory banks. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL and/BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL and/BL. Selection of word line WL is performed by row control 108, and selection of bit lines BL and/BL is performed by column control 110. In some embodiments, there may be a row control 108 and a column control 110 for each of the memory banks.

Bit lines BL and/BL are coupled to respective Sense Amplifiers (SAMP) 117. Read data from the bit line BL or/BL is amplified by the sense amplifier SAMP 117 and transferred to the read/write amplifier 120 via the complementary local data line (LIOT/B), the Transfer Gate (TG)118, and the complementary main data line (MIO). Conversely, the write data output from the read/write amplifier 120 is transferred to the sense amplifier 117 via the complementary main data line MIO, the transfer gate 118, and the complementary local data line LIOT/B, and written in the memory cell MC coupled to the bit line BL or/BL.

The semiconductor device 100 may use a plurality of external terminals including a command and address (C/a) terminal coupled to a command and address bus to receive commands and addresses; a clock terminal which receives clocks CK and/CK; a data terminal DQ, which supplies data; and power supply terminals that receive power supply potentials VDD, VSS, VDDQ, and VSSQ.

The clock terminal is supplied with an external clock CK and/CK, which are supplied to the clock input circuit 122. The external clocks may be complementary. The clock input circuit 122 generates the internal clock ICLK based on the CK and/CK clocks. The ICLK clock is provided to the command control 106 and to the internal clock generator 124. The internal clock generator 124 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock may be used for timing operations of various internal circuits. The internal data clock LCLK is provided to the input/output circuit 126 to time the operation of the circuits included in the input/output circuit 126, e.g., to a data receiver to time the reception of write data.

The C/a terminal may be supplied with a memory address. The memory address supplied to the C/a terminal is transferred to the address decoder 104 via the command/address input circuit 102. Address decoder 104 receives the address and supplies a decoded row address XADD to row control 108 and a decoded column address YADD to column control 110. The row address XADD may be used to specify one or more word lines WL of the memory array 112, and the column address YADD may specify one or more bit lines BL of the memory array 112. The address decoder 104 may also provide a bank address BADD that specifies a particular bank of memory. The bank address BADD may be provided to row control 108 and/or column control 110 to direct access operations to one or more of the banks.

The row address XADD may include a plurality of bits. As used herein, the row address XADD of different bits may be labeled XADD0-XADDn, where n is the total number of bits of the row address. Thus, XADDi may refer to the ith bit of a row address XADD.

Bits of different subsets of the row address XADD may be associated with different levels of organization of the memory array 112. For example, a subset of bits of row address XADD may be a sector address referring to a section of memory array 112 containing a number of word lines, and a different subset of bits of row address XADD may be a word line address referring to a particular word line within the section. In other embodiments, different arrangements of row addresses and word lines may be used. While the nature and use of row addresses is generally described herein, it should be understood that column addresses may be organized in a similar manner in some embodiments.

The command may be supplied to the C/a terminal. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing the memory, such as read commands for performing read operations and write commands for performing write operations, among other commands and operations. An access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate a memory cell to be accessed.

The commands may be provided as internal command signals to the command control 106 via the command/address input circuitry 102. The command control 106 contains circuitry to decode internal command signals to generate various internal signals and commands for performing operations. For example, the command control 106 may provide a row command signal to select a word line and a column command signal to select a bit line.

The device 100 may receive an access command which is a row activate command ACT. When a row activate command ACT is received, the row activate command ACT is supplied for a row address XADD.

The device 100 may receive an access command that is a read command. When a read command is received, the bank address BADD and column YADD address are supplied in time with the read command, reading read data corresponding to the row address XADD and column address YADD from memory cells in the memory array 112. The command control 106 receives a read command that provides an internal command to cause read data from the memory array 112 to be provided to the read/write amplifier 120. The read data is output from the data terminal DQ to the outside via the input/output circuit 126.

The device 100 may receive an access command that is a write command. When a write command is received, the write command is supplied to the bank address and the column address in time, and write data supplied to the data terminal DQ is written to memory cells in the memory array 112 corresponding to the row address and the column address. The command control 106 receives a write command that provides an internal command to cause a data receiver in the input/output circuitry 126 to receive write data. The write clock may also be provided to an external clock terminal for timing the receipt of write data by the data receiver of input/output circuit 126. Write data is supplied to the read/write amplifiers 120 via the input/output circuits 126 and is supplied to the memory array 112 through the read/write amplifiers 120 to be written into the memory cells MC.

The device 100 may also receive commands that cause it to perform refresh operations. The refresh signal AREF may be a pulse signal that is activated when the command decoder 106 receives a signal indicating a refresh mode. In some embodiments, the refresh command may be issued externally to the memory device 100. In some embodiments, a component of the device may periodically generate refresh commands. In some embodiments, the refresh signal AREF may also be activated when the external signal indicates a refresh entry command. The refresh signal AREF may be activated immediately after a command input, and may be activated thereafter at a desired internal timing cycle. Thus, the refresh operation may automatically continue. The self-refresh exit command may cause the automatic activation of the refresh signal AREF to cease and return to the idle state.

The refresh signal AREF is supplied to the refresh control circuit 116. In some embodiments, there may be a refresh control circuit 116 associated with each bank. The bank address BADD may indicate one or more of the refresh control circuits 116 to be activated. The refresh control circuit 116 can collectively receive a refresh signal AREF and can generate and provide one or more refresh row addresses RXADD in order to perform one or more refresh operations in an associated memory bank. In some embodiments, a subset of memory banks may be a given refresh command. For example, one or more additional signals may indicate which refresh control circuits 116 should provide refresh addresses in response to AREFs. In another example, the AREFs may be provided only to the refresh control circuits 116 associated with a subset of the memory banks being refreshed.

Focusing on the operation of a given refresh control circuit, the refresh control circuit 116 supplies a refresh row address RXADD to the row control 108, which row control 108 can refresh one or more word lines WL indicated by the refresh row address RXADD. The refresh control circuit 116 may control the timing of the refresh operation based on the refresh signal AREF. In some embodiments, in response to activation of the AREF, the refresh control circuit 116 can generate one or more activations of the pump signal and can generate and provide a refresh address RXADD for each activation of the pump signal (e.g., each pump).

One type of refresh operation may be an auto-refresh operation. In response to an auto-refresh operation, a memory bank may refresh a row group of memory and then may refresh a next row group of the memory bank in response to a next auto-refresh operation. The refresh control circuit 116 can provide a refresh address RXADD indicating a group of word lines in a memory bank. The refresh control circuit 116 may generate a sequence of refresh addresses RXADD such that over time, an auto-refresh operation may cycle through all word lines WL of a memory bank. The timing of the refresh operations can be such that each word line is refreshed at a frequency that is based on the ordinary rate of data degradation in the memory cells.

Another type of refresh operation may be a targeted refresh operation. Repeated accesses to a particular row of memory (e.g., an aggressor row) may cause an increase in the decay rate in an adjacent row (e.g., a victim row) due to, for example, electromagnetic coupling between the rows. In some embodiments, the victim row may include a row that is physically adjacent to the aggressor row. In some embodiments, the victim row may include rows that are far from the aggressor row. The information in the victim row may decay at a rate such that the victim row may lose data without being refreshed prior to the next auto-refresh operation of the row. To prevent loss of information, it may be desirable to identify an aggressor row and then conduct a targeted refresh operation in which the refresh address RXADD associated with one or more associated victim rows is refreshed.

In some embodiments, the identified row may be a potential aggressor row (and/or a row with a higher likelihood of being an aggressor), and the target refresh operation may be performed on a potential victim row (and/or a row with a higher likelihood of being a victim). For clarity, the identified row will be referred to as an aggressor and the refreshed row will be referred to as a victim, even though the memory may identify aggressor word lines that are not necessarily being accessed enough to cause an increase in the rate of data degradation in neighboring rows, and may refresh victim word lines in which an increase in the rate of data degradation does not necessarily occur.

Refresh control circuit 116 may receive row address XADD provided by address decoder 104 and may determine which word lines are aggressors based on row address XADD. Refresh control circuit 116 may track accesses to word lines based on row address XADD and may determine which word lines are aggressors based on the amount of access. The refresh control circuit may divide the total number of word lines into portions and have an accumulator voltage for each of the portions. For example, a first portion of the word line may be associated with a first accumulator voltage, a second portion of the word line may be associated with a second accumulator voltage, and so on. In some embodiments, the portion of the word line associated with the accumulator voltage may be organized into one or more segments of the word line, each of the segments containing one or more word lines that are physically adjacent to each other. The accumulator voltages can be updated at any time any of the word lines in the portion represented by each accumulator voltage are accessed. For example, in some embodiments, the accumulator voltage may be increased by increasing the charge on the capacitor. In some embodiments, the accumulator voltage may be reduced by reducing the charge on the capacitor. In this way, all accesses to all word lines can be tracked by the accumulator voltage, but there can be fewer count values than the total number of word lines.

In some embodiments, word lines may be grouped together based on the row address associated with those word lines. If only a particular subset of the row address (e.g., a particular value of the subset of bits) is specified, all word lines sharing the specified value of the subset as part of their row address may be identified. For example, each portion of a word line tracked by the accumulator voltage may be specified by a particular value of a subset of the row address XADD. If the row address contains a first subset of a segment specifying a word line (e.g., a segment address) and a second subset specifying a particular word line within the segment (e.g., a word line address), then the subset of word line addresses for the row address may be ignored and the refresh control circuit 116 may have an accumulator voltage associated with the value of the segment address. Thus, the accumulator voltage can update any word line within the segment associated with the segment address at any time. In some embodiments, a sector address may be truncated (e.g., some bits of the sector address may be ignored) into a multi-sector address, which represents all word lines in several different sectors. Each count value may be specified by a particular value of the grouped sector address and may represent an access to any word line in any of the sectors associated with the multi-sector address. It should be understood that row address XADD may include multiple subsets describing multiple different organizational levels, and the example of a particular manner of allocating word lines of memory array 112 based on row address is merely intended to aid in understanding the concepts. In other embodiments, other methods of associating groups of word lines with counter values may be used.

When the refresh control circuit 116 determines that at least one of the portion of the word lines tracked by the accumulator voltage is an aggressor (e.g., when the accumulator voltage crosses a threshold, such as a reference voltage), one or more victim addresses associated with the portion of the word lines represented by the accumulator voltage may be provided. In some embodiments, where each access increases the accumulator voltage, the refresh control circuit 116 can determine when the accumulator voltage is greater than the reference voltage. In some embodiments, where each access decreases the accumulator voltage, the refresh control circuit 116 can determine when the accumulator voltage is less than the reference voltage. Since each accumulator voltage may represent a number of different word lines, each word line in the group associated with a given accumulator voltage may be provided with a victim address. Additionally, a victim address can be provided for a word line that is physically close to (e.g., adjacent to) one or more word lines in the group of word lines associated with the accumulator voltage. For example, if a group of word lines are arranged into one or more segments, a victim address may be associated with each word line in the segment and the word lines of the word lines near the end of the segment.

The refresh control circuit 116 can have a number of accumulator voltages between which access to each word line of the memory array 112 is represented. In some embodiments, the refresh control circuitry 116 may include a target refresh queue that may store addresses for target refresh operations. In some embodiments, the target refresh queue may store victim addresses. In some embodiments, the target refresh queue may store an aggressor address (or a portion of an aggressor address) associated with a portion of a word line represented by an accumulator voltage. When the accumulator voltage crosses a threshold (e.g., a reference voltage), an address associated with the accumulator voltage may be added to the target refresh queue, and the accumulator voltage may be reset to an initial voltage (e.g., ground voltage, a system voltage such as VDD, etc.). When there is a refresh command (e.g., AREF, refresh pump), the address stored in the target refresh queue may be selected, and one or more victim addresses based on the address in the queue may be provided as a refresh address RXADD.

In some embodiments, a memory may perform a target refresh operation on a victim address (e.g., by providing the victim address based on a target refresh queue as a refresh address RXADD) as long as the target refresh queue contains at least one unrefreshed address. In some embodiments, certain refresh operations may be reserved for targeted refresh operations, and if the targeted refresh queue is empty, refresh operations may not be performed during those reserved operations.

The target refresh queue may include one or more priority flags associated with addresses stored therein. Each time the accumulator voltage crosses the threshold, another priority flag may be set and the accumulator voltage may be reset to the initial level if the address associated with the accumulator voltage is already stored in the target refresh queue. For example, when a queue address is added to the target refresh queue, if the queue address is already in the target refresh queue instead of being stored, another priority flag associated with the stored queue address is set. The device 100 may prioritize refresh addresses in the target refresh queue based on the number of priority flags that are set. For example, an address in which more priority flags may be selected for refresh is before an address in which fewer priority flags are set.

The power supply terminals are supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 128. The internal voltage generator circuit 128 generates respective internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals. Internal potential VPP is primarily used in row control 108, internal potentials VOD and VARY are primarily used in sense amplifiers SAMP included in memory array 112, and internal potential VPERI is used in a number of other peripheral circuit blocks.

The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input/output circuit 126. In some embodiments of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input/output circuit 126 so that power supply noise generated by the input/output circuit 126 does not propagate to other circuit blocks.

FIG. 2 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure. In some embodiments, the refresh control circuit 200 may implement the refresh control circuit 116 of FIG. 1. The refresh control circuit 200 receives a row address XADD (e.g., from the address decoder 104 of fig. 1) and a refresh signal AREF, and provides a refresh address RXADD at a timing based on AREF. The refresh address RXADD may be an auto-refresh address RXADD1 as part of an auto-refresh operation or a target refresh address RXADD2 as part of a target refresh operation. The target refresh address RXADD2 may be determined based on tracking the row address XADD over time.

The refresh control circuit 200 includes a row access trace stack 230a (and its associated stack control circuit 231a) and a redundant row access trace stack 230b (and its associated stack control circuit 231 b). The row access trace stack 230a and the redundant row access trace stack 230b each include a number of unit cells 232, each of the unit cells 232 including a number of circuits that store and update one of the accumulator voltages. Although the term stack is used in this disclosure, it should be understood that stacks 230a-b may represent any form of data storage unit including a unit cell 232 as described herein.

The redundant row access trace stack 230b includes a unit cell 232 that tracks accesses to a redundant row of memory (e.g., a row used in a repair operation). The row access trace stack 230a includes unit cells 232 that trace accesses to non-redundant rows of memory. Since there may typically be more non-redundant rows than redundant rows of memory, stack 230a may contain more unit cells 232 than stack 230 b. Stacks 230a and 230b may generally contain similar components and may function in a similar manner. For the sake of brevity, the operation will be described with respect to the general row access trace stack 230 and the stack control circuit 231.

The row access tracking stack 230 includes a number of unit cells 232, each of the unit cells 232 tracking access to a portion of a word line of the memory. The row access trace stack 230 also includes a stack control circuit 231, which includes a number of circuits commonly coupled to different unit cells 232. The stack control circuit 231 may be used to provide signals to all unit cells 232 in common or to one or more specified unit cells 232. Example stack control circuitry that may be used as stack control circuitry 231 is described in more detail in fig. 3-4. An example unit cell that may be used as unit cell 232 is described in more detail in fig. 5-6.

Each time a row address XADD is received, the stack control circuit 231 may selectively activate one of the unit cells 232 associated with the portion of the word line containing the word line represented by the row address XADD. In the embodiment of fig. 2, the activated unit cell 232 may increase the stored accumulator voltage, and the unit cell 232 and the stack control circuit 231 may compare the updated accumulator voltage to the reference voltage. Based on the comparison (e.g., when the accumulator voltage is greater than the reference voltage), the row access tracking stack 230 may change the state of the Flag signal Flag provided by the unit cell 232. It should be understood that while the embodiments discussed herein may generally refer to increasing the accumulator voltage, in some embodiments the activated unit cell 232 may decrease the voltage and the stack control circuit 231 may determine whether the updated accumulator voltage is less than the reference voltage.

In response to the Flag signal Flag of one of the unit cells 232 changing state, the stealing address circuit 234 may store an address in the target refresh queue 236 based on the row address XADD. Target refresh queue 236 includes a number of files, each of which stores a victim address and one or more priority flags. The steal address circuit 234 may use logic that directs a sampler pointer 235, the sampler pointer 235 indicating into which file of the target refresh queue 236 the next address is inserted. In some embodiments, stealing address circuit 234 may determine a victim address based on XADD, and the victim address may be stored in target refresh queue 236. In some embodiments, stealing address circuit 234 may add row address XADD (or a portion of a bit of row address XADD) to target refresh queue 236. In embodiments where XADD (or a portion of XADD) is stored in the target refresh queue 236, the refresh logic circuit 244 may calculate the victim address after receiving the address RXADD2 stored in the target refresh queue 236. Details of determining the victim address are discussed in more detail in figures 7-8.

In the embodiment of fig. 2, the target refresh queue 236 includes a first priority flag 237 and a second priority flag 238. More or fewer priority flags may be used in other embodiments. When the accumulator voltage in the unit cell 232 rises above the threshold, the unit cell 232 may check the status of the first and second priority flags 237, 238. If neither priority flag 237, 238 is high (e.g., neither is set), then steal address circuit 234 may store an address based on address XADD at a location (e.g., a file) based on sample pointer 235 in target refresh queue 236. The accumulator voltage can then be reset to the initial level. If the first flag 237 is already at a high level (e.g., indicating that the accumulator voltage previously rose above the reference voltage), the second priority flag 238 may change to a high level and the first priority flag 237 may remain at a high level. The stealing address circuit 234 may store only the address in the target refresh queue 236 in response to the first priority flag 237 changing from the first state to the second state. Thus, if an address is already in the target refresh queue 236, the address is not loaded a second time.

The refresh logic circuit 244 provides the refresh address RXADD at a timing based on the refresh signal AREF. The refresh address RXADD may be an auto-refresh address RXADD1 provided by the auto-refresh address circuit 242 or a target refresh address (e.g., one or more victim addresses) based on the address RXADD2 provided by the target refresh queue 236. The queue address in the target refresh queue 236 to be provided as address RXADD2 is indicated by a flush pointer 241, which flush pointer 241 is directed by the flush control circuit 240. The flush control circuit 240 may cause the flush pointer 241 to prioritize the files of the target refresh queue 236 based on the number of priority flags 237, 238 that are set. An address in which both the first priority flag 237 and the second priority flag 238 are at a high level may be provided as the target refresh address RXADD2 preceding an address in which only the first priority flag 237 is at a high level.

Stack control circuit 231 may receive row address XADD and provide one of the count values from row counter stack 230 to counter logic circuit 234 based on the values of a subset of bits of row address XADD. Each of the count values of the row counter stack 230 may be associated with a portion of a word line of the memory. Each portion of a word line may be specified by the value of a subset of bits of row address XADD. Each of the count values may be associated with a particular value of a subset of bits of the row address. Thus, there may be a first count value for a first value of the subset of row addresses, a second count value for a second value of the subset of row addresses, and so on. The row count stack 230 may be N registers deep if a subset of the row addresses have N possible values.

A decoder in stack control circuit 231 may receive (and/or focus only on) only a subset of bits of row address XADD. In some embodiments, the target refresh queue may store the same subset of row addresses as stack 230. In turn, refresh logic 244 may determine a victim address based on the subset of row addresses. For example, refresh logic 244 may determine the victim address based on a multi-segment address that includes the fourth through twelfth bits of the row address (e.g., XADD3-XADD 12). Refresh logic 244 may provide a number of victim addresses, including victim addresses associated with all word lines represented by a subset of row addresses. In some embodiments, each victim address may represent multiple word lines of memory, and all word lines represented as a given victim address may be refreshed simultaneously. In some embodiments, refresh logic 244 may also provide a victim address representing a word line not associated with a portion of the row address. The determination of the victim address is discussed in more detail in figures 7-8.

Target flush queue 236 may be a register stack that stores a queue address provided by stealing address circuitry 234. Each register of target refresh queue 236 may include a number of bits that store a queue address provided by stealing address circuitry 234. For example, each register may store the same number of bits as used by the decoder activation unit cell 232 in the stack control circuit 231. In one example, where the decoder is responsive to 10 bits (e.g., XADD3-XADD12), each register of target refresh queue 236 may store a row address XADD of 10-bit worth. In some embodiments, target flush queue 236 may be, for example, 64 registers deep. Other depths of target refresh queue 236 may be used in other examples, such as 50 or 100.

Each register of the target refresh queue 236 may include a number of priority flags (e.g., a first priority flag 237 and a second priority flag 238). Each register may include a certain number of additional storage bits to contain the sodium priority flag. For example, the priority flags 237 and 238 may each be a single bit, and thus each register may include one bit for the first priority flag 237 and one bit for the second priority flag 238. The flags 237 and 238 may be set (e.g., active) when at a high logic level and not set (e.g., inactive) when at a low logic level. Once the priority flag 237/238 is set, it may generally remain set until the address in the register is refreshed, at which point both priority flags 237 and 238 may be reset to an inactive state.

When a unit cell 232 indicates that the current address XADD should be added to target refresh queue 236, the address (or portion thereof) may be inserted into target refresh queue 236 at the register indicated by sample pointer 235. The stealing address circuit 234 may monitor the status of the priority flags 237 and 238 and move the sample pointer 235 based in part on the status of the priority flags. In general, the sample pointer 235 may advance through a sequence of registers (e.g., register (0), register (1), …, register (n), register (0), …, etc.), but may skip certain registers in the sequence based on the state of their flags.

In general, the stealing address circuitry will direct the sample pointer 235 toward a register with a less active priority flag. After the address is added to the current position of the sample pointer 235, the sample pointer 235 may move to the next register in the sequence. If both the first priority flag 237 and the second priority flag 238 are low (e.g., inactive), the sample pointer 235 may remain at that position. If the first priority flag 237 is set, but the second priority flag 238 is not set, the sample pointer 235 may skip the register and move to the next register in the sequence. If all registers in the target refresh queue 236 have the first priority flag 237 set (e.g., after the sample pointer 235 loops back), the sample pointer 235 may remain at the next register with the first priority flag 237 set but without the second priority flag 238. In some embodiments, the stealing address circuit 234 may not point to any register with the second priority flag 238 at a high level. Thus, if the sample pointer 235 moves to a register with the second priority flag 238 at a high level, it may move to the next register. If all registers have the second priority flag 238 at a high level, the stealing address circuit 234 may not add addresses to the target refresh queue 236 and may not add any addresses to the target refresh queue 236 until at least one register is refreshed to cause its priority flag to be reset to an inactive level.

The refresh logic 244 provides the refresh address RXADD at a timing based on the signal AREF. In some embodiments, the refresh logic circuit 244 may provide the refresh address RXADD whenever AREF occurs. In some embodiments, the refresh logic circuit 244 may provide a plurality of refresh addresses RXADD in response to each occurrence of AREF. For example, the refresh logic circuit 244 may provide a set of several 'pumps' in response to receiving an occurrence of AREF, and may provide a refresh address RXADD for each pump.

An auto-refresh address RXADD1 or victim address based on the queue address RXADD2 may be provided as the refresh address RXADD whenever the refresh logic circuit 244 provides the refresh address RXADD. The auto-refresh address circuit 242 may provide the auto-refresh address RXADD 1. Each auto-refresh address RXADD1 may be associated with a number of word lines of the memory. After providing the auto-refresh address RXADD1, the auto-refresh address circuit 242 may provide a next auto-refresh address RXADD1 associated with a next group of word lines in the sequence. The auto-refresh address circuit 242 may provide the auto-refresh address RXADD1 in a sequence such that over time, the auto-refresh address RXADD1 refreshes all of the word lines of the memory array. After the last auto-refresh address RXADD1 in the sequence is provided, the first auto-refresh address RXADD1 in the sequence may be provided again. In some embodiments, the auto-refresh address circuit 242 may determine a sequence of auto-refresh addresses for internal logic. For example, one or more portions of the auto-refresh address RXADD1 may be incremented after each auto-refresh address RXADD1 is provided to determine the next auto-refresh address RXADD 1.

The flush control circuit 240 may direct a flush pointer 241, which flush pointer 241 may indicate which register of the target refresh queue 236 provides the address stored in the indicated register as the queue address RXADD 2. In a manner similar to the sample pointer 235, the flush pointer 241 may generally advance through a sequence of registers (e.g., register (0), register (1), …, register (n), register (0), …, etc.), but certain registers may be skipped based on the number of priority flags 237 and 238 that are set. In general, the flush control circuit 240 may preferentially direct the flush pointer 241 toward the register with the more priority flags 237 and 238 set. It should be noted that sample pointer 235 and clear pointer 241 can generally move independently of each other.

The flush control 240 may move based on the rate of the steal rate control signal, which may indicate the rate of the target refresh operation. In some embodiments, refresh logic 244 may provide a steal rate control signal. In some embodiments, both the refresh logic 244 and the flush control circuit 240 may receive the steal rate control signal from an external source. In an example operation, the flush control circuit 240 may check the state of the priority flags 237 and 238 when the flush pointer 241 moves to the next register. If the second priority flag 238 is active, the flush pointer 241 may remain at that register. If the second priority flag 238 is not active, the flush pointer 241 may be moved to the next register unless no register has the active second priority flag 238, in which case the flush pointer 241 may be stopped at the next register where the first priority flag 237 is active but the second priority flag 238 is not active. If none of the registers in the target refresh queue 236 have active priority flags 237-238, the address may not be provided as the queue address RXADD 2.

In some embodiments, the refresh logic circuit 244 may determine whether to provide the auto-refresh address RXADD1 or an address based on the queue address RXADD2 based on the state of the target refresh queue 236. For example, the refresh logic circuit 244 may provide a target refresh address (e.g., a victim address) as long as the address RXADD2 is being provided by the target refresh queue 236, and may provide the auto-refresh address RXADD1 as the refresh address RXADD if the address RXADD2 is not being provided. In some embodiments, the refresh logic circuit 244 may provide a victim address based on the address RXADD2 at a rate determined by the steal rate control signal, and may skip those refresh operations if no address RXADD2 is available.

FIG. 3 is a block diagram of a row access trace stack according to an embodiment of the present disclosure. In some embodiments, the row access trace stack 300 may be included in the row access trace stack 230 of FIG. 2. The row access trace stack 300 includes a number of different unit cells 348, which unit cells 348 may implement the unit cell 232 of fig. 2 in some embodiments. The row access trace stack 300 also includes various components, such as a decoder circuit 346, a comparator circuit 350, a pulse generator circuit 352, and a sink circuit 354, which may be included in the stack control circuit 231 of fig. 2 in some embodiments.

Decoder circuit 346 receives a row address XADD and provides a select signal Sel to one of unit cells 348. The stack 300 includes a number of different unit cells 348, each of which may be numbered unit cell (0) through unit cell (n). Each unit cell 348 may be activated by select signals Sel (0) to Sel (n). Decoder circuit 346 may provide a select signal sel (i) to unit cell (i) based on the value of the received row address XADD. Select signals Sel (i) may be provided at a high voltage (e.g., a system voltage, such as VDD or VPERI), and other select signals (e.g., Sel (0 to i-1) and Sel (i +1 to n)) may be provided at a low voltage (e.g., a ground voltage, such as VSS).

For example, in some embodiments, the row address XADD may be 17 bits long to represent a total of 2^17 word lines in the bank (excluding redundant word lines). The fourth through sixteenth bits (e.g., XADD3-16) may be a sector address representing a particular section of memory, where each section contains 8 word lines, addressed to the word line address by the first through third bits (e.g., XADD0-XADD 2). Decoder circuit 346 may group some of the bits of a sector address together by ignoring some of the bits, which may be considered a multi-sector address. For example, decoder circuit 346 may only focus on multi-segment addresses that include the fourth through twelfth three bits of the row address (e.g., XADD3-XADD12), such that each multi-segment address represents sixteen of the segments. Each unit cell 348 may thus be associated with a value of a multi-segment address (e.g., XADD3-XADD 12). Thus, the row access tracking stack 300 may include 1024 unit cells (e.g., n 1023), each of the values of the multi-segment addresses XADD3-XADD12 (e.g., 2^10 total values). Each unit cell 348 in such a stack 300 may represent (due to the truncation of the sector address into a multi-sector address) eight word lines in each of 16 different sectors of the memory (due to the omission of the word line address). Thus, in this example embodiment, each unit cell tracks access to a total of 128 word lines. Different organizations of memory and row addresses may be used in other examples. In other embodiments, a row address may have more (or fewer) bits representing more or fewer word lines of the memory.

When a unit cell 348 receives its associated select signal Sel at a high level, the unit cell 348 may be activated. When a given unit cell 348 is activated, it may increase the accumulator voltage on the capacitor in the unit cell 348.

Each of the unit cells 348 may be commonly coupled to a comparator circuit 350. Each of the unit cells 348 may include a comparator section coupled to the voltages MirLeft and MirRight provided by the comparator circuit 350. The voltages MirLeft and MirRight may be commonly coupled to a comparator section in each of the unit cells 348. Each unit cell 342 is also commonly coupled to a sink circuit 354, which sink circuit 354 may generate a sink current iSink that is drained from the unit cell 348 to the sink circuit 354. When the select signal Sel activates the unit cell 348, the comparator section in the unit cell 348 may be coupled between the voltages MirLeft and MirRight and the sink current iSink. A first current may flow from the voltage MirLeft to the sink, and the magnitude of the first current may be based on the reference voltage, and a second current may flow from MirRight to the sink, where the second current has a magnitude based on the accumulator voltage in the unit cell 348. The comparator circuit 350 may provide a trigger signal Trig based on the relative levels of the first and second currents.

The pulse generator circuit 352 receives the signal Trig from the comparator circuit 350 and provides trigger signals TrigPulse0 and TrigPulse 1. The first trigger signal TrigPulse0 may be provided at a first time and the second trigger signal TrigPulse1 may be provided at a second time. The first trigger signal TrigPulse0 and the second trigger signal TrigPulse1 may be provided to the unit cell 348.

The unit cell 348 that is receiving the select signal Sel (e.g., the unit cell 348 that is active) may send one or more Flag signals (e.g., the signal Flag of fig. 2) based on the current state of the Flag signals, as well as a first trigger signal TrigPulse0 and a second trigger signal TrigPulse 1. The unit cell 348 may include flag logic circuitry that determines when to change the state of the flag signal.

Each unit cell may also be commonly coupled to several Control signals Control, which may be used to manage the operation of the different components of the stack 300. For example, the control signals may include signals such as a bias voltage pBias, a reference voltage VRef, a flag reset signal FlushEn, and a voltage reset signal DisChgEn. In some embodiments, the bias voltage pBias may be provided by the sink circuit 354 and may be an adjustable voltage. The pulse generator circuit 352 may receive an activation signal (e.g., Act of fig. 1) and provide a signal ActPulse in response to the activation signal. The pulse generator circuit 352 may provide additional control signals, such as ActPulse, TrigPulse0, and TrigPulse 1. In general, different control signals may be provided in common to each of the unit cells 348, and the select signal Sel may determine which unit cell 348 is active and responsive to the respective control signal.

The discharge logic 353 may provide a voltage reset signal DisChgEn. The voltage reset signal DisChgEn may be provided at a high logic level to cause the accumulator voltage specified by the select signal Sel in the unit cell 348 to be reset to an initial level (e.g., ground voltage). The voltage reset signal DisChgEn may be commonly provided to all of the unit cells 348. In the embodiment of FIG. 3, the discharge logic 353 may cooperate with the decoder 346 to provide a select signal to determine which of the unit cells 348 are reset. In some embodiments (not shown), the discharge logic 353 (e.g., in addition to the decoder 346) may also provide the select signal Sel and use one or more signals and internal logic to determine when to provide the signal DisChgEn and what value of the select signal Sel.

The discharge logic 353 may provide the signal discchgne to the unit cell 348 specified by the select signal Sel in response to a number of different conditions. For example, the discharge logic 353 may provide the signal DisChgEn at a high level whenever the signal FlushEn at a high level is received. Since the signal flush may generally indicate that the word line associated with the unit cell 348 has been refreshed, and since the signal Sel may still indicate which unit cell 348 has been refreshed, the discharge logic 353 may cause the accumulator voltage in the unit cell 348 to be reset when the word line associated with that unit cell is refreshed. The discharge logic circuit may also reset the unit cell 348 whenever a new priority flag associated with the unit cell is set (e.g., as indicated by signals TrigPulse0 or TrigPulse 1). In other words, the discharge logic 353 may reset the accumulator voltage in a given unit cell 348 whenever the accumulator voltage rises above a threshold (e.g., the reference voltage Vref). Thus, in response to receiving TrigPulse0 or TrigPulse1 at a high logic level, the discharge logic 353 may provide the signal discchgne at a high logic level. The discharge logic 348 may also provide the signal DisChgEn at a high logic level whenever the refresh signal AREF is received.

In some cases, the discharge logic 353 may cause all unit cells 348 to be reset (e.g., by providing the signal DisChgEn while the select signal is provided to all unit cells 348). For example, when the system is initialized (e.g., in response to power on, in response to a system reset, etc.). For example, the discharge logic 353 may receive a signal PwrUp indicating whether the system is powered on. If the system is not powered on, the signal PwrUp may be at a low logic level and the discharge logic 353 may provide a signal DisChgEn indicating whether the system is powered on. If the system is not powered on, signal PwrUp may be at a low logic level and discharge logic circuit 353 may provide signal DisChgEn at a high logic level.

Fig. 4 is a schematic diagram illustrating a stack control circuit according to an embodiment of the present disclosure. Stack control circuit 400 includes decoder 446, comparator circuit 450, pulse generator circuit 452, and sink circuit 454. In some embodiments, these decoder 446, comparator circuit 450, pulse generator circuit 452, and sink circuit 454 may be included in decoder 346, comparator circuit 350, pulse generator circuit 352, and sink circuit 354, respectively, of fig. 3. A comparator section 470 of a unit cell (e.g., unit cell 348 of fig. 3) is also shown in fig. 4 to help demonstrate the operation of the comparator circuit 450 and the snubber circuit 454. The comparator section 470 may be repeated in each of the unit cells (e.g., the unit cell 232 of fig. 2 and/or the unit cell 348 of fig. 3).

Decoder 446 receives row address XADD and provides select signal Sel. In some embodiments, the signal Sel may be a multi-bit signal, where each of the bits of the signal Sel are provided to a different one of the unit cells. Each bit of signal Sel may be associated with a value of a subset of bits of row address XADD. There may be a unit cell for each value of a subset of bits of the row address, and the unit cells together may represent all values of the subset. For example, decoder 446 may monitor the fourth through twelfth bits of row address XADD (e.g., XADD <12:3>), which may have 1024 different values. Thus, there may be 1024 different unit cells and 1024 different selection bits (e.g., Sel <1023:0 >).

When the row address XADD is received, bits of a selection signal Sel associated with the row address XADD may be provided at a high level (e.g., a system voltage, such as VPERI). In some embodiments, the bits of the selection signal Sel may be provided at a high level for a set period of time after the row address XADD is received. In some embodiments, the bits of the selection signal Sel may be supplied at a high level as long as the current row address XADD is received.

In response to the associated bit of the select signal Sel being at a high level, the comparator circuit 450 and the sink circuit 454 may work with the comparator section 470 of the unit cell activated by the bit of the select signal Sel to compare the accumulator voltage CapNode of the unit cell with the reference voltage Vref.

The sink circuit 454 includes a first transistor 462 having a source coupled to a system voltage (e.g., VPERI or VSS) and a gate and sink coupled to a bias voltage pBias. The first transistor 462 may be a p-type transistor. The bias voltage pBias is also coupled to a ground voltage (e.g., VSS) through resistor 463. A current I may flow from the first transistor 462 through the resistor 463. In some embodiments, resistor 463 may be an adjustable resistor and may be used to adjust the magnitude of current I and the level of bias voltage pBias. In some embodiments, the current I may be about 0.5 μ A. Other values of current I may be used in other examples.

The sink circuit 454 also includes a second transistor 464 having a gate coupled to the bias voltage pBias, a source coupled to the system voltage, and a drain coupled to the node 465. The second transistor 464 may be a p-type transistor. The sink circuit 454 also includes a third transistor having a drain and a gate commonly coupled to the node 465, and a source coupled to a ground voltage (e.g., VSS). The third transistor 466 may be an n-type transistor. The first, second, and third transistors 462, 464, 465 and the resistor 463 may act as a current mirror, and current I may also flow from the second transistor 464 toward the third transistor 466.

The sinking circuit 454 also includes a fourth transistor 467 having a drain coupled to the output of the comparator section 470, a source coupled to a ground voltage, and a gate coupled to the node 465. When one of the coupled comparator sections 470 is active, the fourth transistor 467 may cause the current iSink to flow through the fourth transistor 467 to a ground voltage. The sink current iSink may have a magnitude greater than the current I. In some embodiments, the sink current iSink may be about 8 μ Α.

The comparator circuit 450 includes a first transistor 455 having a source coupled to a system voltage (e.g., VSS or VPERI) and a gate and a drain commonly coupled to a node 459. The first transistor 455 may be a p-type transistor. The comparator circuit 450 also includes a second transistor 456 having a source coupled to the system voltage, a gate coupled to a node 459, and a drain coupled to a voltage MirLeft. The second transistor 456 may be a p-type transistor. The comparator circuit 450 also includes a third transistor 457 and a fourth transistor 458. The third transistor 457 has a source coupled to the system voltage and a gate and a source commonly coupled to a voltage MirRight. The fourth transistor 458 has a source coupled to the system voltage, a gate coupled to the voltage MirRight, and a drain coupled to the output of the comparator 450. The third transistor 457 and the fourth transistor 458 may be p-type transistors. The comparator circuit 450 also includes a fifth transistor 460 and a sixth transistor 461. The fifth transistor 460 has a drain and a gate commonly coupled to the node 459 and a source coupled to a ground voltage (e.g., VSS). A sixth transistor 461 has a gate coupled to node 459, a drain coupled to a ground voltage placing source, and a drain coupled to the output of the comparator circuit 450. The fifth transistor 460 and the sixth transistor 461 may be n-type transistors.

The first transistor 455, the second transistor 456, and the fifth transistor 460 may operate together as a first current mirror, and the third transistor 457, the fourth transistor 458, and the sixth transistor 461 may operate together as a second current mirror. In general, more current is allowed to flow from the voltage MirLeft through the comparator section 470 to the sink circuit 454, the lower the voltage on the sixth transistor 461, the more active the sixth transistor 461. The more current is allowed to flow from the voltage MirRight through the comparator section 470 to the sink circuit 454, the more active the fourth transistor 458 is. Depending on which of the fourth transistor 458 or the sixth transistor 461 is more active, the output of the comparator circuit 450 may be more strongly coupled to the system voltage through the fourth transistor 458 or to the ground voltage through the sixth transistor 461. Thus, if the current from the voltage MirLeft is greater than the current from the voltage MirRight, the output of the comparator section 450 may be the ground voltage. The output of the comparator section 450 may be a system voltage (e.g., a high voltage) if the current from the voltage MirRight is greater than the current from the voltage MirLeft.

The comparator section 470 can control how much current from the voltages MirLeft and MirRight flows to the sink circuit 454. Only a single comparator section 470 is shown, however, there may be a comparator section 470 for each unit cell that are all commonly coupled to the voltages MirLeft and MirRight and the sink current iSink. The comparator section 470 includes a first transistor 475, a second transistor 477, and a third transistor 476. All three transistors 475-477 may be n-type transistors. The first transistor 475 has a drain coupled to a voltage MirLeft and a gate coupled to a reference voltage Vref. The second transistor 477 has a drain coupled to the voltage MirRight and a gate coupled to the accumulator voltage CapNode < i > of the unit cell (i). The first transistor 475 and the second transistor 477 have sources commonly coupled to a drain of the third transistor 476. The third transistor 476 has a source coupled to the sink current iSink provided by the sink circuit 454 and a gate coupled to a bit of the select signal Sel < i > associated with the unit cell (i) including the comparator section 470.

When the bit of the select signal Sel < i > is at a high level, the third transistor 476 may be active and may couple the sources of both the first transistor 475 and the second transistor 477 to the current iSink. Current may flow from the voltage MirLeft through the first transistor 475 to the current iSink and be proportional to the level of the reference voltage Vref. Current can flow from the voltage MirRight through the second transistor 477 to the current iSink and is proportional to the level of the accumulator voltage CapNode < i >. Thus, if the accumulator voltage CapNode < i > is higher than the reference voltage Vref, the current from MirRight may be greater than the current from MirLeft, and the output of the comparator circuit 450 may be high (e.g., system voltage).

The pulse generator circuit 452 includes a buffer circuit 469 having an input terminal coupled to the output of the comparator circuit 450 and an output terminal that provides a trigger signal Trig. When the input of the buffer circuit 469 rises to a high level (e.g., because the voltage CapNode rises above the voltage Vref), the signal Trig may switch from a low level to a high level. The first rising pulse generator 472 has an input terminal coupled to a signal Trig, and an output terminal providing a signal TrigPulse 0. In response to a rising edge of the signal Trig (e.g., when the signal Trig transitions from a low level to a high level), the first rising pulse generator 472 may provide a first trigger pulse TrigPulse 0. The first trigger pulse TrigPulse0 may be a pulse that remains high for a set length of time (typically short relative to the time between pulses) if the signal transitions from low to high and then transitions back to low. The pulse generator circuit 452 also includes a delay circuit 473 having an input terminal coupled to the signal TrigPulse 0. The delay circuit 473 receives the signal TrigPulse0 at a first time and then provides the signal TrigPulse1 at a second time after the first time.

The pulse generator circuit 452 may also include a second rising pulse generator 468 having an input terminal coupled to the activation signal Act. The second rising pulse generator 468 may provide a pulse of the signal ActPulse when there is a rising edge of the activation signal Act. The width of each pulse of ActPulse (e.g., the duration that ActPulse is high) may be adjustable. The signals TrigPulse0, TrigPulse1, and ActPulse may be supplied to the unit cell in common.

Fig. 5 is a schematic diagram of a unit cell according to an embodiment of the present disclosure. In some embodiments, the unit cell 500 may be included in the unit cell 232 of fig. 2 and/or the unit cell 348 of fig. 3. Unit cell 500 includes accumulator circuit 505, comparator portion 510, and flag logic circuit 515. The comparator portion 510 may be substantially similar to the comparator portion 470 of fig. 4, and the transistors 540 and 544 may be substantially similar to the transistors 475 and 477 of fig. 4. For the sake of brevity, comparator section 510 is not described in detail again.

Accumulator circuit 505 stores a voltage CapNode based on the charge on capacitor 530. In response to the select signal and the activate signal, the voltage CapNode may be increased by adding charge to the capacitor 530. The accumulator circuit includes a NAND gate 516 having an input terminal coupled to a signal ActPulse (e.g., from the pulse generator 468) that is based on the signal Act and indicates an access operation. The other input terminal of NAND gate 516 is coupled to a bit of select signal Sel associated with unit cell 500. Thus, when both ActPulse and Sel are at a high level, it indicates that the address associated with the portion of the word line associated with the unit cell 500 was received as part of an access operation. The NAND gate 516 provides the signal Act1F to the inverter circuit 518, which inverter circuit 518 provides the signal Act 1. Signals Act1F and Act1 may be complementary to each other and have opposite logic levels.

Accumulator circuit 505 includes a first transistor 520 having a source coupled to a system voltage (e.g., VDD, VPERI) and a drain coupled to a voltage chargeLine. The gate of the first transistor 520 is coupled to a bias voltage pBias provided by a sink circuit (e.g., the sink circuit 454 of fig. 4). The first transistor 520 may be a p-type transistor. The bias voltage pBias may be adjustable (e.g., by adjusting the resistance of resistor 463 of fig. 4), which may control how much charge is added to the capacitor 530 (e.g., by controlling how much current flows through the first transistor 520) each time signals Sel and ActPulse are received at a high level.

Accumulator circuit 505 includes a second transistor 522 and a third transistor 524 that are activated to couple voltage chargeLine to voltage CapNode, increasing the charge on the capacitor. The second transistor 522 has a source coupled to the voltage charge line and a drain coupled to the voltage CapNode. The gate of the second transistor 522 is coupled to a signal Act1F, which signal Act1F is at a low level when both signals ActPulse and Sel are high. The second transistor 522 may be a p-type transistor. Third transistor 524 has a source coupled to voltage chargeLine, a drain coupled to voltage CapNode, and a gate coupled to signal Act1, which signal Act1 is at a high level when Act1F is at a low level. The third transistor 524 may be an n-type transistor.

The voltage CapNode is coupled to ground through capacitor 530. Thus, when signal Act1F is at a low level and signal Act1 is at a high level, second transistor 522 and third transistor 524 may be active and current may flow from voltage chargeLine to voltage CapNode, charge may be added to capacitor 530, increasing voltage CapNode. The amount (e.g., step size) of voltage CapNode that is increased in response to signals ActPulse and Sel may be based in part on voltage pBias and the width of signal ActPulse. In some embodiments, voltage pBias may be adjusted by adjusting the resistance of resistor 463 of FIG. 4. In some embodiments, the width of the signal ActPulse may be adjusted by changing the settings of the pulse generator circuit (e.g., by changing the control signal of the rising pulse generator 468 of fig. 4). The step size may also depend in part on the capacitance of capacitor 530. In some embodiments, it may be desirable to use a capacitor 530 having a relatively large capacitance. For example, in some embodiments, the capacitor 530 may be a switched capacitor or a crown capacitor to achieve high capacitance in a relatively small layout area. In some embodiments, the step size may be kept small to limit undesirable coupling, such as parasitic capacitance on the voltage chargeLine. For example, in some embodiments, the step size may be about 1 mV. Other step sizes may be used in other examples. In some embodiments, additional steps may be taken, such as minimizing the length of the conductive element carrying the voltage chargeLine.

In some embodiments, accumulator circuit 505 may also include optional fourth transistor 526 and fifth transistor 528. Fourth transistor 526 may have a drain coupled to voltage CapNode, a gate coupled to signal Act1, and a source that is floating (e.g., not coupled to any component or signal of accumulator circuit 505). The fourth transistor 526 may be a p-type transistor. Fifth transistor 528 may have a drain coupled to voltage CapNode, a gate coupled to signal Act1F, and a source that floats. The fifth transistor 528 may be an n-type transistor. The fourth transistor 526 and the fifth transistor 528 may be activated simultaneously with the second transistor 522 and the third transistor 524 and may help limit the off-coupling effect of the transistors 522 and 524 of the turn-on voltage CapNode.

In some conditions, the voltage CapNode may be discharged to reset the voltage CapNode to an initial voltage (e.g., ground voltage). Accumulator circuit 505 may include a sixth transistor 532 and a seventh transistor 534. The sixth transistor 532 has a drain coupled to the voltage CapNode, a gate coupled to a discharge signal DisChgEn (e.g., provided by the discharge logic circuit 353 of fig. 3), and a source coupled to a drain of the seventh transistor 534. The seventh transistor 534 has a gate coupled to the selection signal Sel, a drain coupled to the source of the sixth transistor 532, and a source coupled to a ground voltage (e.g., VSS). Both the sixth transistor 532 and the seventh transistor 534 may be n-type transistors. When the sixth and seventh transistors 532, 534 are active (e.g., when both signals Sel and DisChgEn are at a high level), the voltage CapNode may provide that the sixth and seventh transistors 532, 534 are coupled to ground. Thus, when both the sixth transistor 532 and the seventh transistor 534 are active, the capacitor 530 may be discharged to ground and the voltage CapNode may be dropped to ground.

The unit cell 500 may also include flag logic circuit 515. The Flag logic circuit 515 may control the levels of Flag signals Flag0 and Flag1, which Flag signals Flag0 and Flag1 may control the state of priority flags in the target refresh queue (e.g., flags 237 and 238 in queue 236 of fig. 2). The states of the Flag signals Flag0 and Flag1 may be determined based on: the current state of the flag signal, trigger pulses TrigPulse0 and TrigPulse1 that may be provided by a pulse generator circuit (e.g., 352 of fig. 3 and/or 452 of fig. 4) in response to the voltage CapNode crossing a voltage (e.g., voltage Vref), a select signal Sel, and a flush enable signal flush that may be provided by a flush control circuit (e.g., 240 of fig. 2).

The flag logic circuit 515 includes a first AND gate 546 having input terminals coupled to TrigPulse0 AND a select signal Sel. When both the signals TrigPulse0 AND Sel are at a high level, the first AND gate 546 provides the signal TrigPulseEn0 at a high level. The flag logic circuit 515 also includes a second AND gate 548 having input terminals coupled to the signals TrigPulse1 AND Sel. The second AND gate 548 provides the signal TrigPulseEn1 at a high level, where TrigPulse1 AND Sel are both at a high level. Since TrigPulse0 is provided at the first time and TrigPulse1 is provided at the second time (e.g., based on delay circuit 473 of fig. 4), it is also possible to provide the signal TrigPulseEn0 first, followed by the signal TrigPulseEn1 after the delay time. The flag logic circuit 515 also includes a NAND gate 550 having input terminals coupled to the signals flushn and Sel, and outputting a signal flushnf that is at a low logic level when both flushn and Sel are at a high level.

The flag logic circuit 515 includes a first flag latch 552 and a second flag latch 554. The first flag latch 552 has an inverted reset terminal RstF coupled to the signal FlushEnF, and a Set terminal Set coupled to the signal TrigPulseEn 0. The first Flag latch 552 stores the state of the first priority Flag and provides signals Flag0 and Flag0F indicating the logic state of the first priority Flag (e.g., the first priority Flag 237 of fig. 2). The signals Flag0 and Flag0F may be complementary to each other and may have opposite logic states. When the signal TrigPulseEn0 is at a high level, indicating that the current unit cell is selected, and the voltage CapNode has increased above a threshold (e.g., the reference voltage Vref), the value of the stored first priority flag may change to a high logic level (or may remain at a high level if the first priority flag is already at a high level). When the first priority Flag is at a high level, the signal Flag0 may be at a high level, and the signal Flag0F is at a low level. When the first flag latch 552 receives the signal FlushEnF at a low logic level, indicating that the word line associated with the unit cell has been refreshed, the state of the first priority flag may be reset to a low logic level. When the first priority Flag is at a low logic level, the signal Flag0 may be at a low level, and the signal Flag0F may be at a high level.

The second flag latch 554 may operate in a substantially similar manner as the first flag latch 552. The second flag latch 554 has an inverted reset input terminal RstF coupled to the signal FlushEnF, and a Set input terminal Set coupled to the signal TrigPulseEn 1. In addition, the second Flag latch 554 includes a set enable terminal SetEn coupled to the signal Flag0 and an inverted set enable terminal SetEnF coupled to the signal Flag 0F. The second Flag latch 554 may provide signals Flag1 and Flag1F that indicate the state of the second priority Flag stored in the second Flag latch 554. When the signal Flag0 is high (and the signal Flag0F is low), the second Flag latch 554 may be enabled and may be responsive to the signal TrigPulseEn 1. Thus, when the first priority flag is at a high level, the second priority flag may change to a high level and receive a signal tripulse 1 indicating that the voltage CapNode has exceeded a threshold (e.g., voltage Vref). The state of the second priority flag may be set to a low level in response to the signal FlushEnF being at a low level.

FIG. 6 is a schematic diagram of a first flag latch and a second flag latch according to an embodiment of the present disclosure. In some embodiments, the first flag latch 605 may be included in the first flag latch 552 of FIG. 5. In some embodiments, the second flag latch 610 may be included in the second flag latch 554 of FIG. 5.

The first flag latch 605 includes a first transistor 612 having a source coupled to the system voltage (e.g., VPERI, VDD), a gate coupled to the Set terminal Set (e.g., signal TrigPulse0En), and a drain coupled to the source of the fifth transistor 620. The second transistor 614 has a source coupled to the system voltage, a gate coupled to the inverted reset terminal RstF (e.g., to the signal flush nf), and a drain coupled to the inverted output terminal OutF (e.g., the signal Flag 0F). The first transistor 612 and the second transistor 616 may be p-type transistors. The third transistor 616 has a drain coupled to a terminal OutF (e.g., Flag0F), a source coupled to a ground voltage (e.g., VSS), and a gate coupled to a Set terminal Set (e.g., TrigPulseEn 0). The fourth transistor 618 has a drain coupled to the source of the sixth transistor 622, a source coupled to the ground voltage, and a gate coupled to the inverted reset terminal RstF. The third transistor 616 and the fourth transistor 618 may be n-type transistors.

The first flag latch 605 also includes transistors 620-626 which act as cross-coupled inverters to form a latch that stores the state of the priority flag. Transistor 612 + 618 may act as a switch that is activated by the signals on terminals Set and RstF to change the state of the flag stored in the latch.

The fifth transistor 620 has a source coupled to the drain of the first transistor 612, a gate coupled to the output terminal Out, and a drain coupled to the inverted output terminal OutF. A sixth transistor 622 has a drain coupled to terminal OutF, a gate coupled to terminal Out, and a source coupled to the drain of transistor 618. The seventh transistor 624 has a source coupled to the system voltage, a gate coupled to the terminal OutF, and a drain coupled to the terminal Out. An eighth transistor 626 has a drain coupled to terminal Out, a gate coupled to terminal OutF, and a source coupled to a ground voltage. Transistors 620 and 624 may be p-type transistors. Transistors 622 and 626 can be n-type transistors.

As can be seen, when the signal on the Set terminal Set is provided at a high level (e.g., when TrigPulse0En is high), the transistor 616 is active and the ground voltage may be coupled to the signal on the terminal OutF. When OutF is at a low level (e.g., ground voltage), transistor 626 may not be active and transistor 624 may be active, which may couple the system voltage to terminal Out to set terminal Out to a high level. When terminal Out is at a high level, transistor 622 may be activated and transistor 620 may not be activated. When the signal on terminal RstF is at a low level (e.g., when flushnf is at a low level), transistor 614 may be active and may couple terminal OutF to a high level. When OutF is at a high level, transistor 626 may be active, which may couple terminal Out to a ground voltage, thus setting it to a low level.

The second flag latch 610 may be substantially similar to the first flag latch 605, and for the sake of brevity, similar components and operations will not be described again. Briefly, the transistors 632 and 646 of the second flag latch 610 may be similar to and function in a similar manner as the transistors 612 and 626 of the first flag latch 605. The second flag latch 610 also includes transistors 648 and 650 to enable the second flag latch 610. The transistor 648 has a source coupled to the system voltage (e.g., VDD, VPERI), a drain coupled to the source of the transistor 640, and a gate coupled to an input terminal SetEnF (e.g., the signal Flag0F provided by the output terminal OutF of the first Flag latch 605). The transistor 650 has a source coupled to a ground voltage, a drain coupled to the source of the transistor 636, and a gate coupled to a terminal SetEn (e.g., the signal Flag0 provided by the output terminal Out of the first Flag latch 605). Thus, when the signal Flag0 is low, the transistors 648 and 650 may not be active, which may prevent the signal on terminal Set from operating the second Flag latch 610.

7A-7B are block diagrams of memory arrays according to embodiments of the present disclosure. FIG. 7A shows a memory array 700 arranged in a plurality of sectors 750. In some embodiments, memory array 700 can implement memory array 112 of FIG. 1. FIG. 7B shows an enlarged view of a portion of FIG. 7A, with several word lines 752 arranged in different sections 750. FIG. 7B also shows a subset of row addresses, which may be used to address different sectors 750 and/or word lines 752. The memory array 700 illustrates an example of a particular manner of organizing word lines of a memory into multiple portions based on row addresses of the memory. The memory array 700 may represent only a portion of a memory array. In other embodiments, other organizations and/or numbers of word lines in a memory array, as well as other organizations and/or lengths of row addresses, may be used.

The memory array 700 includes a number of sectors 750. Each sector 750 includes a number of word lines 752. Within a given section 750, word lines 752 may generally be arranged along one direction and adjacent to each other such that a first word line 752 (e.g., XADD0-3 ═ 000) in section 750 is adjacent to a second word line 752 (e.g., XADD0-3 ═ 001), second word line (001) is adjacent to first word line 752(000) and a third word line 752(010), and so on. Some of the sections 750 may be adjacent to other sections 750, such that, for example, the last wordline 752(111) in a first section 750(XADD 3-12-0000000000) may be adjacent to the first wordline 752(000) in a second section 750(XADD 3-12-0000000001).

As shown in fig. 7B, which shows an enlarged view of some of the sections 750, different portions of the bits of the row address may refer to an organized level of the memory array 700. The real routine address may comprise 17 bits. A subset of the row address, such as a multi-sector address containing the fourth through thirteenth three bits (e.g., XADD3-XADD12), may refer to sixteen different sectors 750 of memory (shown shaded in fig. 7A). Additional bits (e.g., XADD13-16) may be used to specify particular ones of the sixteen segments 750. A word line address including the first through third bits (e.g., XADD0-XADD2) may be used to refer to a particular word line of eight word lines 752 within section 750. The lower portion of fig. 7B shows example values for a multi-sector address (e.g., XADD3-XADD12) and individual bits of a word line address (e.g., XADD0-XADD 2). Although only a single segment is shown for each value of the multi-segment address (XADD3-XADD12), each value of the multi-segment address may represent sixteen different segments (e.g., as shown in phantom in fig. 7A).

As previously discussed, the refresh control circuit (e.g., 116 of FIG. 1, 200 of FIG. 2, and/or 300 of FIG. 3) may have an accumulator voltage (e.g., a unit cell) associated with each value of a subset of the row address. For example, there may be a unit cell for each value of a multi-segment address (e.g., XADD3-XADD 12). Thus, each unit cell may represent a number of accesses to any word line 752 (and, thus, any of the 128 different word lines 752) in any of the sixteen different sections 750 of the memory array. Since there are 1024 different possible values (e.g., 2^10 possible values) for XADD3-XADD12, there may be 1024 different count values that each represent a different set of 16 sectors 750 each containing 8 word lines 752.

Since several word lines 752 are grouped together and associated with the same count value, when the count value exceeds a threshold value, it may indicate that at least one of the word lines 752 represented by the count value is an aggressor. However, since the count value does not distinguish between the word lines, it may not be known which word line 752 is an aggressor. Thus, a victim address may be provided to refresh each of the potential victim word lines of all the word lines represented by the unit cell. FIG. 8 provides an example embodiment of how a victim address may be determined.

FIG. 8 is a block diagram of a memory array according to an embodiment of the present disclosure. In some embodiments, memory array 800 may represent a portion of memory array 700 of FIGS. 7A-7B. The memory array 800 represents an example of how victim word lines may be determined (e.g., by refresh logic 244 of FIG. 2) based on the physical organization of the word lines in the memory. Fig. 8 may be substantially similar to fig. 7B, and for the sake of brevity, similar features will not be described twice.

As described herein, the refresh control circuit (e.g., 116 of fig. 1 and/or 200 of fig. 2) can include a number of unit cells (e.g., unit cell 232), each of which can represent all of the word lines 852 in a number of sections 850 of the memory array 700. In an example embodiment, a given unit cell may represent an access to any of 128 word lines 852 organized into sixteen segments 850 each having eight word lines. In this example, there may be 1024 different count values (each representing sixteen sections 850) corresponding to 1024 different values of a subset of bits of row addresses XADD3-XADD 12. For clarity, fig. 8 shows only a single sector 850 for each value of the row address portion, however, it should be understood that each value of the row address portion may represent additional sectors 850 (e.g., fifteen additional sectors 850) that are not shown.

One or more of the word lines 852 represented by the count value may be aggressors if it is determined that the accumulator voltage in the unit cell exceeds the threshold. A subset of bits of a row address (e.g., XADD3-12) representing a portion of wordline 852 may be held in a target refresh queue (e.g., target refresh queue 236). The addresses stored in the queue may be provided to refresh logic 244, which may perform a targeted refresh operation that refreshes all potential victim word lines for each of the word lines represented by the addresses provided by the queue. FIG. 8 shows an embodiment in which a word line that is physically adjacent to an aggressor word line is not considered a victim. Thus, in order to refresh all potential victims, all word lines physically adjacent to any of the word lines 852 represented by the count value must be refreshed (e.g., their addresses may be provided as a refresh address RXADD). The victim address may be determined utilizing the fact that some of the word lines 852, represented by count values, may be physically adjacent to one another. In some embodiments, this may be done by providing a victim address that specifies only a particular subset of bits of the row address, such that the victim address refers to all word lines that share a particular value of the subset as part of their row address.

Block 854 shows a victim word line that may be refreshed after an accumulator voltage associated with a multi-segment address having a value of 1 (e.g., XADD3-XADD12 ═ 0000000001) exceeds a threshold. Block 854 includes a word line having a multi-segment address of 1 within one of the segments 850 and an adjacent word line in an adjacent segment. Each of the word lines 852 shown within block 854 may be refreshed. Although only a single block 854 is shown, it should be understood that each victim address is associated with multiple word lines (e.g., fifteen other word lines in fifteen other sectors 850). In some embodiments, other word lines associated with the victim address may be arranged in a manner similar to that shown in block 854.

In an example, each section 850 can include eight word lines 852 adjacent to each other. To refresh a word line 852 adjacent to any of these word lines 852, a total of ten victim addresses may be provided (e.g., by refresh logic 244 of FIG. 2). Eight of the victim addresses are associated with eight word lines 852 of the segment 850, and two additional addresses are provided, representing a word line adjacent to the first word line of the segment 850 (e.g., the last word line of the previous segment) and a word line adjacent to the last word line of the segment 850 (e.g., the first word line of the next segment). The word lines to be provided with the victim address are represented by the shaded boxes within box 854.

Each victim address may specify values for both a multi-segment address (e.g., XADD3-12) and a word line address (e.g., XADD 0-2). Thus, each victim address may be associated with a single word line 852 in each of the different segments 850 represented by the multi-segment address (e.g., XADD 3-12). In the example discussed herein, each victim address can thus be associated with a total of sixteen word lines 852 in a total of sixteen segments 850. As an example, a segment associated with a multi-segment address having a value of 1 (e.g., XADD3-XADD12 ═ 0000000001) has been identified as containing an aggressor row (e.g., because a count value associated with the multi-segment address has exceeded a threshold value). In the embodiment of FIG. 4, a total of ten victim word lines may be provided: a last word line address (e.g., XADD0-XADD2 ═ 111) with multi-segment address 0 (e.g., XADD3-XADD12 ═ 0000000000); all values of word line addresses (e.g., XADD0-XADD2 ═ 000 to 111) in the segment associated with the identified aggressor multi-segment address (e.g., XADD3-XADD12 ═ 0000000001); and a first word line address (e.g., XADD0-XADD 2-000) in a multi-segment address (e.g., XADD3-XADD 12-0000000010) having a value of 2. The remaining bits of the victim address (e.g., XADD13-XADD16) can be ignored, and thus each of the victim addresses can be associated with a single word line 852 in each of sixteen different segments 850.

While only a single set of sections 850 is shown, it should be understood that additional sections are present. Thus, each victim address may represent multiple word lines. For example, in an example embodiment, each victim address may represent a word line in each of sixteen different segments 850. Every time a victim address is provided as the refresh address RXADD, all word lines in each of the different sectors represented by the victim address can be refreshed simultaneously. For example, sixteen word lines may be refreshed simultaneously.

Although the example of FIG. 8 shows an embodiment in which the word line adjacent to the aggressor is considered the victim, in other example embodiments, other methods of determining the victim may be used. For example, in some embodiments, word lines adjacent to aggressors (e.g., XADD-1 and XADD +1) and word lines adjacent to adjacent word lines (e.g., XADD-2 and XADD +2) may be considered victims. In this scenario, considering a segment with eight adjacent word lines, a total of twelve victim addresses may be supplied, including two adjacent word lines on either side of segment 850.

Of course, it should be appreciated that any of the examples, embodiments, or processes described herein may be combined or separated with one or more other examples, embodiments, and/or processes and/or performed in separate devices or device portions of systems, devices, and methods in accordance with the disclosure.

Finally, the above-discussion is intended to be merely illustrative of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present system has been described in detail with reference to exemplary embodiments, it should also be appreciated that numerous modifications and alternative embodiments may be devised by those having ordinary skill in the art without departing from the broader and intended spirit and scope of the present system as set forth in the claims that follow. The specification and drawings are accordingly to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.