阅读说明：本技术 用于实现3D铁电非易失性数据储存的3D FeFET的架构、结构、方法和存储阵列 (Architecture, structure, method and memory array of 3D fefets for 3D ferroelectric non-volatile data storage ) 是由 刘峻 于 2020-10-23 设计创作，主要内容包括：一种三维存储架构,所述三维存储架构包括存储单元的顶部单元阵列、存储单元的底部单元阵列、耦合到阵列的多个字线、以及耦合到字线并且可操作以选择性地激活字线的多个字线解码器。多个字线解码器从底部单元阵列的第一边缘和从底部单元阵列的第二边缘延伸,第二边缘与第一边缘是相对的,其中,多个字线解码器包括字线解码器的第一部分和字线解码器的第二部分,并且其中,字线解码器的第一部分相对于字线解码器的第二部分沿平行于、或基本平行于第一边缘和第二边缘的方向移动。(A three-dimensional memory architecture includes a top cell array of memory cells, a bottom cell array of memory cells, a plurality of word lines coupled to the array, and a plurality of word line decoders coupled to the word lines and operable to selectively activate the word lines. The plurality of word line decoders extend from a first edge of the bottom cell array and from a second edge of the bottom cell array, the second edge being opposite the first edge, wherein the plurality of word line decoders includes a first portion of the word line decoder and a second portion of the word line decoder, and wherein the first portion of the word line decoder moves in a direction parallel, or substantially parallel, to the first edge and the second edge relative to the second portion of the word line decoder.)

1. A cross-point architecture for implementing a 3D FeFET memory array, comprising:

including a plurality of cell stacks with vertical gates all around the FeFET cells,

wherein the plurality of cell stacks are stacked;

wherein the vertical gates complete around the FeFET cells to implement a cross-point array and provide an effective cell size of 4F2 per stack;

wherein the vertical gate fully surrounding FeFET achieves a 4F2 cell area; and is

Wherein the plurality of cell stacks share a bit line.

2. The cross-point architecture of claim 1, wherein the vertical gate all-around FeFET cell is a 1T/C cell.

3. A three-dimensional memory array, comprising:

a cross-lattice column architecture, wherein the cross-lattice column architecture comprises:

a plurality of cell stacks including word lines and bit lines,

the word lines of the plurality of cell stacks are parallel or vertical,

the bit lines of the plurality of cell stacks are perpendicular to the word lines, wherein the plurality of cell stacks further comprise FeFET cells.

4. The three dimensional memory array of claim 4 wherein the FeFET cells comprise vertical FeFET transistors.

5. The three dimensional memory array of claim 5 wherein the FeFET cells are accessed by the bit lines through the vertical FeFET transistors.

6. A three-dimensional FeRAM memory cell comprising:

the vertical gate fully surrounds the FeFET,

wherein the vertical gate all-around FeFET comprises a recessed ferroelectric gate dielectric and a solid channel or a hollow channel.

7. The three-dimensional FeRAM memory cell of claim 6, wherein the vertical gate comprises a vertical FeFET transistor.

8. The three-dimensional FeRAM memory cell of claim 6, wherein the vertical gate is accessed by a bit line through the vertical FeFET transistor.

9. A method of fabricating a three-dimensional memory array, comprising:

forming parallel polysilicon word lines for the first stack;

forming an array of vertical channel holes in the parallel polysilicon word lines;

recessing a portion of the array of vertical channel holes;

depositing a ferroelectric gate dielectric material into the recess; and

inserting a vertical transistor into the vertical channel to form a three-dimensional FeFET memory cell on the vertical transistor;

wherein the vertical transistor is solid or hollow.

10. The method of claim 8 further comprising forming parallel bit lines and placing the parallel bit lines perpendicular to the parallel polysilicon word lines.

11. The method of claim 8, wherein the method is repeated to form a second stack.

Technical Field

The present disclosure relates generally to three-dimensional electronic memories including ferroelectric field effect transistors, and more particularly, to increasing data storage density of memory cells and reducing storage bit costs.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. Thus, the storage density of the planar memory cell approaches the upper limit.

Ferroelectric random access memory (FeRAM) uses planar transistors as selection devices for ferroelectric memory cells to form a two-dimensional memory array. FeRAM is a random access memory similar to a Dynamic Random Access Memory (DRAM), but FeRAM uses memory cells with ferroelectric capacitors instead of dielectric capacitors to store data. There are two types of ferams, one using ferroelectric capacitors to store data and the other using ferroelectric field effect transistors (fefets) to store data. In contrast to conventional FeRAM 1T-1C memory cells, FeFET is a 1T/C memory cell without a separate ferroelectric capacitor. Fefets incorporate ferroelectric gate dielectrics in Complementary Metal Oxide Semiconductor (CMOS) transistors. Accordingly, the FeFET exhibits nonvolatile characteristics due to the fact that: the two stable residual polarization states of the ferroelectric gate insulator now modify the threshold voltage even when the supply voltage is removed. Thus, the binary state is encoded in the threshold voltage of the transistor.

The bit density of a two-dimensional planar FeFET is highly dependent on transistor size, with the minimum memory cell size being defined by the capacitance requirement in order to represent the data difference. As a result, there is a need to implement novel three-dimensional (3D) memory cell structures to further reduce cell footprint and bit cost.

Disclosure of Invention

The following summary is included to provide a basic understanding of aspects and features of the disclosure. This summary is not an extensive overview, and thus, it is not intended to identify key or critical elements or to delineate the scope of the disclosure. Its sole purpose is to present concepts in a generalized format.

In one aspect, a new cell structure for implementing a 3D ferroelectric field effect transistor (FeFET) to enable 3D ferroelectric non-volatile data storage is proposed, thereby increasing data storage density and reducing storage bit cost. The 3D FeFET is a vertical gate full wrap-around transistor with a recessed ferroelectric gate oxide to achieve non-volatility in a 4F2 cell footprint, where F is the minimum process size. In the current new cell structure, a cross-point array employs vertical Bit Lines (BL) and vertical Word Lines (WL), and may be stacked with 3D FeFET memory cells in two or more stacks (deck) to achieve an effective cell size of 2F2 in two stacks, and an effective cell size of 1F2 in four stacks, where F is the minimum process size.

The use of fefets results in a minimum 4F2 cell size due to the 3D vertical FeFET memory cell. The 3D vertical FeFET memory cell also has lower process cost due to the 1T/C memory cell that is built into the access transistor. The cross-point architecture and vertical transistors achieve an effective cell size of 4F2 on each stack. By using multiple stacks, the 3D FeFET architecture with shared bit lines increases the storage bit density and reduces silicon cost with multiple stacks. This architecture achieves an effective cell size of 2F2 for two stacks of FeFET cells and 1F2 for four stacks of FeFET cells.

A cross-point architecture for implementing a 3D FeFET memory array includes a plurality of cell stacks including vertical gate full wrap-around FeFET cells, wherein the plurality of cell stacks are stacked. The vertical gates all surround the FeFET cells to implement a cross-point array and provide an effective cell size of 4F2 per stack. The vertical gate fully surrounds the FeFET to achieve a 4F2 cell area, while multiple cell stacks share bitlines. The vertical gate all around FeFET cell is a 1T/C cell.

The three-dimensional memory array includes a cross-point array architecture. The cross-point array architecture includes a plurality of cell stacks including word lines and bit lines. Word lines of the plurality of cell stacks are parallel or vertical, and bit lines of the plurality of cell stacks are perpendicular to the word lines. The plurality of cell stacks further includes FeFET cells. The FeFET cells include vertical FeFET transistors. The FeFET cells are accessed by the bit lines through vertical FeFET transistors.

The three-dimensional FeRAM memory cell includes a vertical gate all-around FeFET. The vertical gate all-around FeFET includes a recessed ferroelectric gate dielectric and a solid or hollow channel.

The method of fabricating a three-dimensional memory array includes: forming parallel polysilicon word lines for the first stack; forming an array of vertical channel holes in the parallel polysilicon word lines; recessing a portion of the array of vertical channel holes; depositing a ferroelectric gate dielectric material into the recess; a vertical transistor is inserted into the vertical channel to form a three-dimensional FeFET memory cell on the vertical transistor. The vertical transistors are solid or hollow. The method may further include forming parallel bit lines and placing the parallel bit lines perpendicular to the parallel polysilicon word lines. The method may be repeated to form a second stack.

Drawings

The foregoing aspects, features and advantages of the disclosure will be further understood when considered in conjunction with the following description of exemplary embodiments and the accompanying drawings, in which like reference numerals identify like elements. In describing exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be employed for the sake of clarity. However, aspects of the present disclosure are not intended to be limited to the specific terminology used.

FIG. 1 is an isometric view of a section of a prior art planar memory cell.

Fig. 2 is a plan view of a sector of a conventional planar memory array.

Fig. 3A and 3B are plan views of a section of a three-dimensional cross-point memory according to an embodiment.

Figure 4 is a plan view of a section of a memory array of a three-dimensional cross-point memory according to the embodiment of figures 3A and 3B.

Fig. 5A and 5B are plan views of sections of a three-dimensional cross-point memory according to additional embodiments.

Fig. 6 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Fig. 7 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Fig. 8 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Fig. 9 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Fig. 10 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Fig. 11 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Fig. 12 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Detailed Description

The technology is applied to the field of three-dimensional memories. Fig. 1 shows a general example of a planar memory cell. Specifically, fig. 1 is a plan view of a conventional ferroelectric random access memory (FeRAM) cell using fefets to store data. The memory cell 10 includes a FeFET 11, the FeFET 11 being attached to a word line 14 extending in the X direction on one surface of the FeFET. The FeFET 11 is also attached to a substrate 12 on the other surface of the FeFET. The memory cell may also include a bit line (not shown) extending in the X direction and a word line 14 extending in the Y direction. In any event, individual memory cells can be accessed by selectively activating the word lines and bit lines corresponding to the cells.

Fig. 2 is a plan view of a section of a planar memory circuit of a conventional configuration. The figure depicts the segments as viewed in the Z (depth) direction. The sector includes word lines 1 extending in a Y (vertical) direction, bit lines 13 extending in an X (horizontal) direction and corresponding to memory cells (not shown). Word lines, top cell bit lines, and bottom cell bit lines (not shown) are typically formed according to a 20nm/20nm line/space (L/S) pattern and are formed on a silicon substrate.

The present technology has been developed in view of the above-described problems, and it is an object of the present technology to provide a technique for improving the performance of a hybrid vehicle.

Fig. 3A and 3B are plan views of a section of a three-dimensional cross-point memory according to an embodiment. Figure 4 is a plan view of a section of a memory array of a three-dimensional cross-point memory according to the embodiment of figures 3A and 3B.

Fig. 3A illustrates a vertical single capacitor 100 according to an embodiment of the present disclosure. The vertical single capacitor 100 includes a first cell stack 111, a second cell stack 112, and a third cell stack 112. The first cell stack 111 is placed between the common substrate 106, which may be a Complementary Metal Oxide Semiconductor (CMOS), and the second cell stack 106, which is placed between the first cell stack 111 and the third cell stack 113, and the third cell stack 113 is placed above the second cell stack 112 to implement a 3D cross-point architecture. The second stack 112 is placed such that the word line 102b and FeFET 103b are offset from the word lines 102a, 102c of the first and third cell stacks and the fefets 103a, 103c of the first and third cell stacks. The cell stacks may be implemented in parallel in all stacks. Alternatively, as can be seen in fig. 5A and 5B, the stack may be implemented vertically. In fig. 5A and 5B, the second cell stack 112 is placed perpendicular to the third stack 113 to further reduce capacitive coupling between the two stacks. The vertical single capacitor 100 may be 1T/C. Each cell stack includes a bitline 101a, 101b, 101c extending in the X-direction and a wordline 102a, 102b, 102c extending in the Y-direction, wherein the wordlines 102a, 102b, and 102c may be perpendicular to the bitlines 101a, 101b, 101 c. As can be seen in fig. 3A, the fefets 103A, 103b, 103c of each stack are placed within the recesses of the word lines 102a, 102b, 102c and connected to vertical transistors 104a, 104b, 104 c. The vertical single capacitor 100 may not be limited to three stacks but may include a plurality of stacks stacked on top of each other. The vertical single capacitor 100 achieves non-volatility in a 4F2 cell footprint with vertical gate full wrap-around transistors 104a, 104b, 104c and recessed ferroelectric gate oxides 103a, 103b, 103c, where F is the minimum process size. Fig. 3B shows a vertical single capacitor 100 according to the embodiment shown in fig. 3A in a three-dimensional view.

Figure 4 is a plan view of a section of a memory array of a three-dimensional cross-point memory according to the embodiment of figures 3A and 3B. Fig. 4 shows a memory array 400 of vertical individual capacitors 100 depicted in fig. 3A and 3B. As can be seen in fig. 4, the first section 414 is configured similarly to the second section 415. The first section 414 as described herein may also be applied to the second section 415. The memory array 400 of single capacitors 100 may be implemented as a cross-point architecture. The memory array 400 includes word lines 402a, 402b, 402c for each cell stack extending in the Y-direction and bit lines 401a, 401b, 401c for each cell stack extending in the X-direction. As described in fig. 3A and 3B, fefets 403A, 403B, 403c and vertical transistors 404a, 404B, 404c may be implemented in each cell stack of memory array 400. The first cell stack 411 is placed between the CMOS 406 and the second cell stack 412. The second unit stack 412 is disposed between the first unit stack 411 and the third unit stack 413. The third unit stack 413 is placed on the second unit stack 412. The word lines and bit lines of the cell stacks 411, 412, 413 may be implemented in parallel in all stacks. Alternatively, the word lines and bit lines of the cell stack may be implemented vertically.

Fig. 7 to 12 show a method of manufacturing the three-dimensional vertical single capacitor according to fig. 3A, 3B and 4. A method of fabricating a three-dimensional vertical single capacitor in accordance with another embodiment is shown. In fig. 6, a common substrate 106 for the first stack is formed. The common substrate may be a complementary metal oxide semiconductor. In fig. 7, parallel word lines 102 for a first stack 111 are formed. The word lines may be doped with polysilicon. As can be seen in fig. 8, a channel hole 107 is formed in the word line 102, wherein the channel hole lands on the common substrate 106. Then, as can be seen in fig. 9, the channel hole 107 is recessed with tetramethylammonium hydroxide. In fig. 10, after forming the recess, ferroelectric gate material 103 is deposited in the recess to form a transistor gate for the vertical FeFET. In fig. 11, a polysilicon channel for the vertical transistor 104 is formed. The vertical transistor 104 may be solid or hollow. In fig. 12, parallel bit lines 101 are formed to be perpendicular to word lines 102. The method may be repeated to form second and third stacks 112, 113, the second and third stacks 112, 113 being stacked to form the vertical 3D FeFET array of fig. 3A and 3B.

Most of the foregoing alternative examples are not mutually exclusive and can be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above can be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. By way of example, the foregoing operations need not be performed in the exact order described above. Rather, the various steps may be processed in a different order (e.g., reversed or simultaneous). Steps may also be omitted unless otherwise specified. In addition, the provision of examples described herein with clauses phrased as "e.g," "including," etc., should not be interpreted as limiting the claimed subject matter to the specific examples; rather, this example is intended to illustrate only one of many possible embodiments. Further, the same reference numbers in different drawings may identify the same or similar elements.

Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.