阅读说明：本技术 铁电随机存取存储器感测方案 (Ferroelectric random access memory sensing scheme ) 是由 艾伦·德维尔比斯 乔纳森·拉赫曼 于 2019-02-15 设计创作，主要内容包括：提供了半导体存储器设备及操作其的方法。操作方法可以包括以下步骤：选择铁电存储器单元用于读操作；耦合第一脉冲信号以询问选定铁电存储器单元,选定铁电存储器单元响应于第一脉冲信号而向位线输出存储器信号；经由位线将存储器信号耦合到感测放大器的第一输入端；使感测放大器与选定铁电存储器单元电气地隔离；以及在感测放大器与选定铁电存储器单元电气地隔离之后启用感测放大器用于感测。还公开了其它实施例。(A semiconductor memory device and a method of operating the same are provided. The method of operation may include the steps of: selecting a ferroelectric memory cell for a read operation; coupling the first pulse signal to interrogate a selected ferroelectric memory cell, the selected ferroelectric memory cell outputting a memory signal to the bit line in response to the first pulse signal; coupling a memory signal to a first input of a sense amplifier via a bit line; electrically isolating the sense amplifier from the selected ferroelectric memory cell; and enabling the sense amplifier for sensing after the sense amplifier is electrically isolated from the selected ferroelectric memory cell. Other embodiments are also disclosed.)

1. A method, comprising:

selecting a ferroelectric memory cell for a read operation;

coupling a first pulse signal to a selected ferroelectric memory cell and interrogating the selected ferroelectric memory cell, the selected ferroelectric memory cell outputting a memory signal to a bit line in response to the first pulse signal;

coupling the memory signal to a first input of a sense amplifier via the bit line;

electrically isolating the sense amplifier from the selected ferroelectric memory cell; and

the sense amplifier is enabled for sensing after the sense amplifier is electrically isolated from the selected ferroelectric memory cell.

2. The method of claim 1, further comprising:

a reference signal is coupled to a second input of the sense amplifier.

3. The method of claim 1, further comprising:

coupling a second pulse signal to and interrogating a complementary ferroelectric memory cell, the complementary ferroelectric memory cell outputting a complementary signal to an anti-phase line in response to the second pulse signal; and

coupling the complementary signal to a second input of the sense amplifier via the bit bar line.

4. The method of claim 1, wherein electrically isolating the sense amplifier within the selected ferroelectric memory cell is performed locally by deactivating a first word line signal coupled to a gate of a pass transistor of the selected ferroelectric memory cell.

5. The method of claim 1 wherein said selected ferroelectric memory cell has a single transistor single capacitor (1T1C) configuration.

6. The method of claim 1, wherein electrically isolating the sense amplifier from the selected ferroelectric memory cell is performed along the bit line using a transistor.

7. The method of claim 1, wherein electrically isolating the sense amplifier from the selected ferroelectric memory cell is performed after the first pulse signal is deactivated.

8. The method of claim 3, wherein enabling the sense amplifier for sensing is performed after the sense amplifier is electrically isolated from the complementary ferroelectric memory cell.

9. The method of claim 3, wherein the first and second pulse signals are low amplitude and V, respectively, having Vss_DDOf high amplitude singular square wave pulse signals.

10. The method of claim 8, wherein the electrical isolation between the sense amplifier and the complementary ferroelectric memory cell is performed by deactivating a second word line signal coupled to a gate of a pass transistor of the complementary ferroelectric memory cell.

11. A memory device, comprising:

a first memory cell comprising a first ferroelectric capacitor coupled to a first pass transistor;

a first plate line coupled to one of two plates of the first ferroelectric capacitor;

a first bit line coupling the first pass transistor to a sense amplifier; and

a first word line coupled to a gate of the first pass transistor;

wherein during a read operation of the first memory cell, a first word line signal on the first word line is deactivated before the sense amplifier is enabled for a sense operation.

12. The memory device of claim 11, wherein the first memory cell has a single transistor single capacitor (1T1C) configuration, and wherein the sensing operation of the sense amplifier compares an amplitude of a memory signal output from the first memory cell to a reference signal.

13. The memory device of claim 11, further comprising:

a second memory cell comprising a second ferroelectric capacitor coupled to a second pass transistor, wherein the first and second memory cells form a complementary memory cell having a two transistor, two capacitor (2T2C) configuration;

a second plate line coupled to one of the two plates of the second ferroelectric capacitor;

a second bit line coupling the second pass transistor to the sense amplifier; and

a second word line coupled to a gate of the second pass transistor;

wherein, during a read operation of the first memory cell, a second word line signal on the second word line is deactivated before the sense amplifier is enabled for the sensing operation.

14. The memory device of claim 11, wherein during a read operation of the first memory cell, a square wave pulse signal is asserted on the first plate line to interrogate the first ferroelectric capacitor, and wherein after the square wave pulse signal on the first plate line is deasserted, a word line signal on the first word line is deasserted.

15. The memory device of claim 13, wherein a sense operation of the sense amplifier compares an amplitude of a memory signal output from the first memory cell with a complementary signal output from the second memory cell.

16. A method of operating a ferroelectric memory array, comprising:

coupling a first plate line to the ferroelectric memory array, wherein the first plate line is associated with a first column, wherein the first plate line is to be coupled to a square wave pulse signal during a read operation of a selected memory cell;

coupling a first word line to the ferroelectric memory array, wherein the first word line is associated with a first row of memory cells, wherein the first word line is to be coupled to a word line signal;

coupling a first bit line to the ferroelectric memory array, wherein the first bit line is associated with the first column and electrically connects the selected memory cell to a sense amplifier when the word line signal is asserted;

deactivating the square wave pulse signal;

deactivating the word line signal; and

after the word line signal is deactivated, an enable signal is coupled to the sense amplifier to begin a sensing operation.

17. The method of claim 16, wherein the word line signal is deactivated after the square wave pulse signal is deactivated.

18. The method of claim 16 wherein the ferroelectric memory array is formed by arranging single transistor single capacitors (1T1C) ferroelectric memory cells in rows and columns.

19. The method of claim 16, wherein during the read operation, the selected memory cell outputs a memory signal in response to the square wave pulse signal, and wherein the sense amplifier compares an amplitude of the memory signal to a reference signal to determine a binary state of the selected memory cell.

20. The method of claim 18 wherein two adjacent 1T1C ferroelectric memory cells of the same row form a two transistor two capacitor (2T2C) complementary memory cell.

Technical Field

The present disclosure relates generally to non-volatile (NV) memory devices and, more particularly, to signal sensing schemes for ferroelectric random access memory (F-RAM) devices.

Background

Memories that retain data even when operating power is not available are classified as non-volatile memories. Examples of non-volatile memory are nvSRAM, F-RAM, electrically erasable programmable read-only memory (EEPROM), and flash memory. Such memories may be used in applications where critical data must be stored after power is removed or when power is interrupted during operation.

The reference voltage of a memory device or cell may be interpreted as a voltage level that separates what is considered to be a stored data value "0" or "1", depending on the charge stored/generated in the memory device or cell. In some embodiments, voltages found on the memory bus that are below the reference voltage are considered "0" and voltages above the reference voltage are considered "1", and vice versa. The reference voltage may be maintained at a constant level, programmable, or a combination thereof, depending on system requirements or design preferences. In some embodiments, no reference voltage/signal will be used. Instead, the complementary memory cells (true and complementary bits) will be compared to each other to determine the binary state of the true memory cell.

In order to achieve accurate and reliable reading, it is important to keep the sensing devices (such as sense amplifiers) as balanced and symmetrical as possible during the read operation.

Brief Description of Drawings

The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

FIG. 1A is a schematic diagram illustrating a single transistor single capacitor (1T1C) memory cell according to one embodiment of the subject matter;

FIG. 1B is a representative flow diagram of a method of operation of an F-RAM during a read operation in accordance with one embodiment of the subject matter;

FIG. 2 is a schematic diagram illustrating a two transistor two capacitor (2T2C) memory cell according to one embodiment of the subject matter;

FIG. 3 is a diagram illustrating the relationship between F-RAM switch entries (P entries) and non-switch entries (U entries) and bit fail counts (F-RAM bit distributions);

FIG. 4 is a schematic diagram illustrating a portion of an F-RAM device according to one embodiment of the subject matter;

FIGS. 5A-5F are representative timing diagrams illustrating signal levels of various nodes of an F-RAM device during a read operation (sensing scheme) according to an embodiment of the subject matter; and

FIG. 6 is a schematic diagram illustrating a portion of a non-volatile memory system.

Detailed Description

The following description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., in order to provide a thorough understanding of several embodiments of the subject matter. It will be apparent, however, to one skilled in the art that at least some embodiments may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram form in order to avoid unnecessarily obscuring the techniques described herein. Therefore, the specific details set forth below are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the spirit and scope of the subject matter.

It is common practice for computers and other processing devices to store information or programs that have been developed or updated in NV memory (such as flash memory, EEPROM, F-RAM) so that data can be retrieved in the event of a power failure or error.

Summary of the examples:

according to one embodiment of a method of operating a non-volatile memory device, the method may comprise the steps of: selecting a ferroelectric memory cell for a read operation; coupling the first pulse signal to interrogate a selected ferroelectric memory cell, the selected ferroelectric memory cell outputting a memory signal to the bit line in response to the first pulse signal; coupling a memory signal to a first input of a sense amplifier via a bit line; electrically isolating the sense amplifier from the selected ferroelectric memory cell; and enabling the sense amplifier for sensing after the sense amplifier is electrically isolated from the selected ferroelectric memory cell.

In one embodiment, the method may further comprise the step of coupling a reference signal to the second input of the sense amplifier.

In another embodiment, the method may further comprise the steps of: coupling the second pulse signal to interrogate a complementary ferroelectric memory cell that outputs a complementary signal to a bit-line-bar line in response to the second pulse signal; the complementary signal is coupled to the second input of the sense amplifier via the bit bar line. The step of enabling the sense amplifier for sensing may be performed after the sense amplifier is electrically isolated from the complementary ferroelectric memory cell.

In one embodiment, the step of electrically isolating the sense amplifier may be performed locally within the selected ferroelectric memory cell by deactivating a first word line signal coupled to the gate of the pass transistor of the selected ferroelectric memory cell. Electrical isolation between the sense amplifier and the complementary ferroelectric memory cell may be performed by deactivating a second word line signal coupled to the gate of the pass transistor of the complementary ferroelectric memory cell.

In one embodiment, the selected ferroelectric memory cell has a single transistor single capacitor (1T1C) configuration.

In one embodiment, the firstThe first pulse signal and the second pulse signal may be low amplitude and V having Vss, respectively_DDOf high amplitude singular square wave pulse signals.

In some embodiments, the step of electrically isolating the sense amplifier from the selected ferroelectric memory cell may be performed along the bit line using a transistor.

In one embodiment, the step of electrically isolating the sense amplifier from the selected ferroelectric memory cell may be performed after the first pulse signal is deactivated.

According to one embodiment of a memory device, the memory device may include: a first memory cell comprising a first ferroelectric capacitor coupled to a first pass transistor; a first plate line coupled to one of two plates of the first ferroelectric capacitor; a first bit line coupling a first pass transistor to a sense amplifier; a first word line coupled to the gate of the first pass transistor, wherein during a read operation of the first memory cell, a first word line signal on the first word line is deactivated before the sense amplifier is enabled for a sensing operation.

In one embodiment, the first memory cell may have a single transistor single capacitor (1T1C) configuration, and wherein the sensing operation of the sense amplifier compares the amplitude of the memory signal output from the first memory cell to a reference signal.

In one embodiment, the memory device may further include: a second memory cell comprising a second ferroelectric capacitor coupled to a second pass transistor, wherein the first memory cell and the second memory cell form a complementary memory cell having a two-transistor, dual-capacitor (2T2C) configuration; a second plate line coupled to one of two plates of the second ferroelectric capacitor; a second bit line coupling a second pass transistor to the sense amplifier; a second word line coupled to a gate of the second pass transistor. During a read operation of the first memory cell, the second word line signal on the second word line may be deactivated before the sense amplifier is enabled for the sensing operation.

In one embodiment, a sensing operation of a sense amplifier may compare an amplitude of a memory signal output from a first memory cell with a complementary signal output from a second memory cell.

In one embodiment, during a read operation of the first memory cell, the square wave pulse signal is asserted on the first plate line to interrogate the first ferroelectric capacitor, and wherein the word line signal on the first word line may be deasserted after the square wave pulse signal on the first plate line is deasserted.

According to one embodiment of a method for operating a ferroelectric memory array, the method may comprise the steps of: coupling a first plateline to the ferroelectric memory array, wherein the first plateline is associated with a first column, and the first plateline can be coupled to a square wave pulse signal during a read operation of a selected memory cell; coupling a first word line to the ferroelectric memory array, wherein the first word line is associated with a first row of memory cells, and the first word line may be coupled to a word line signal; coupling a first bit line to the ferroelectric memory array, wherein the first bit line is associated with a first column and can electrically connect the selected memory cell to the sense amplifier when the word line signal is asserted; disabling the square wave pulse signal; deactivating the word line signal; and coupling an enable signal to the sense amplifier to begin a sensing operation after the word line signal is deactivated.

In one embodiment, the word line signal may be deactivated after the square wave pulse signal is deactivated.

In one embodiment, a ferroelectric memory array may be formed by arranging single transistor single capacitors (1T1C) ferroelectric memory cells in rows and columns.

In one embodiment, two adjacent 1T1C ferroelectric memory cells of the same row may form a two transistor two capacitor (2T2C) complementary memory cell.

In one embodiment, during a read operation, a selected memory cell may output a memory signal in response to a square wave pulse signal, and wherein the sense amplifier may compare the amplitude of the memory signal to a reference signal to determine the binary state of the selected memory cell.

Embodiments of ferroelectric capacitor based memory devices and methods of operating the same that allow for maintaining an optimal balance and symmetry of the sensing device will now be described with reference to the accompanying drawings. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and relative dimensions may not correspond to actual reductions to practice of the subject matter. For the sake of clarity, many details of input devices and methods of operation, which are generally (and particularly) well known and not essential to the present apparatus and methods, have been omitted from the following description.

FIG. 1A is a schematic diagram illustrating a single transistor single capacitor (1T1C) ferroelectric random access memory (F-RAM) sensing circuit 100 according to one embodiment of the subject matter. In one embodiment, the 1T1C F-RAM sensing circuit may include non-volatile memory elements such as ferroelectric capacitor 94 and n-channel or p-channel pass field effect transistor (pass transistor) 96 to form a single memory or F-RAM cell 90.1T 1C F-RAM sensing circuit may also include Bit Line (BL), bit bar (BLB), bit line capacitor 98 and BLB capacitor' 98, which may be Metal Oxide Semiconductor (MOS) capacitors or just parasitic capacitors, and Sense Amplifier (SA). F-RAM ferroelectric capacitor 94 may include a structure of a ferroelectric layer such as lead zirconate titanate (PZT material) disposed between two conductive plates or other similar embodiments known in the art. in one embodiment, one plate of F-RAM ferroelectric capacitor 94 may be coupled to Plate Line (PL), while the other plate may be coupled to BL through the source-drain path of pass transistor 96. The gate of pass transistor 96 may be coupled to a Word Line (WL) and configured to be controlled (turned on or off) by a word line signal. Ferroelectric capacitors, such as F-RAM ferroelectric capacitor 94, may exhibit spontaneous non-zero polarization even when the applied electric field is zero. This distinguishing feature suggests that the spontaneous polarization can be reversed or reversed by a suitably strong electric field applied in the opposite direction. Thus, the polarization depends not only on the currently applied electric field, but also on the current polarity of the ferroelectric capacitor.

In one embodiment, the read and write operations of F-RAM cell 90 are performed by manipulating the plateline signal, bitline signal, and/or wordline signal. Thus, the state representing the polarity of the data value "0" or "1" of the F-RAM ferroelectric capacitor 94 can be flipped, held and output according to the stored data value. In some embodiments, multiple 1T1C F-RAM cells 90 may be arranged in an F-RAM array (not shown in this figure), and each 1T1C F-RAM cell 90 of the same row or column may share a common plate line, bit line, and/or word line. In one embodiment, the charge generated in the F-RAM ferroelectric capacitor 94 during a read operation is output to the Sense Amplifier (SA) through the pass transistor 96 and BL to determine whether the stored data represents a data "0" or "1". It should be appreciated, however, that other types of transistors (such as p-channel FETs) and combinations of different types of transistors, capacitors, resistors may be utilized in some embodiments of the F-RAM cell.

The non-switching term (U term) or U term signal) is the charge generated on the F-RAM ferroelectric capacitor 94 when there is no switching involving polarization after a voltage or electric field is applied across the F-RAM ferroelectric capacitor 94. The switching term (P term (Pterm) or P term signal) is the charge that is generated when there is a switching of polarization. In a 1T1C configuration, in some embodiments, U entries may represent data "0" and P entries may represent data "1", or vice versa. In subsequent sections, the amplitude of the U, P term signal may be represented and compared to other signals in the voltage term.

Referring to the flow chart in FIG. 1B, in step 150, a read operation 120 of a memory cell (such as F-RAM cell 90) begins by selecting a particular cell or cells for reading. In one embodiment, the BL associated with the selected memory cell 90 is precharged to Vss. Then, in step 152, the WL associated with the selected memory cell 90 is activated, turning on the pass transistor 96. In step 154, the BL is then floated.

The plate line coupled to one of the plates in ferroelectric capacitor 94 is pulsed "up and down". In one embodiment, an "up-down" pulse or square wave pulse signal includes transitioning the PL signal from Vss to VDD (the operating voltage), and then back to Vss. The PL pulse interrogates F-RAM memory cell 90 by flipping or holding the polarization state of ferroelectric capacitor 94. In response, ferroelectric capacitor 94 may output either a P term or U term signal. The 1T1C F-RAM architecture, which may include only one ferroelectric capacitor, may utilize the P and U entries of the same ferroelectric capacitor 94 in a 1T1C F-RAM cell to represent the stored data. Thus, a 1T1C F-RAM cell can be considered single-ended. The P or U term signal from the ferroelectric capacitor 94 is output to the Sense Amplifier (SA) through the BL.

Then in step 158, SA is enabled by activating the SA _ enable signal. As shown in fig. 1A, the memory signal (item P or U) of ferroelectric capacitor 94 is coupled to one input of SA, and the reference signal (Vref) is coupled to the other input of SA through the bit Bar Line (BLB). The reference signal or voltage is a voltage that is generated internally or externally in the F-RAM device as a reference to distinguish between the P term and the U term of the ferroelectric capacitor, which in turn represent data "1" and "0", respectively. Because 1T1C F-RAM utilizes the P term and the U term of the same ferroelectric capacitor, a reference voltage may be needed to distinguish between the two signals. In one embodiment, as shown in fig. 3, the reference voltage is generated in a range between the U term signal and the P term signal. Mgn0 is defined as the 1T1C signal margin for data "0", which may be the voltage difference between the reference voltage and the U term signal. Mgn1 is defined as the 1T1C signal margin for data "1", which is the voltage difference between the P term signal and the reference voltage. It will be understood that in some embodiments, the P and U terms may be inverted to represent "0" and "1," respectively. The 1T1C reference voltage separates the total ferroelectric switch charge into two components or portions: a signal margin for data "0" (MgN0) and a signal margin for data "1" (MgN 1).

In step 160, SA will output the result after the memory signal is compared to Vref. In one embodiment, if the memory signal is greater than Vref, it will be considered to be a P term ("0" or "1"). If the memory signal is less than Vref, it will be considered to be a U term ("1" or "0").

FIG. 2 is a schematic diagram illustrating a two transistor two capacitor (2T2C) ferroelectric random access memory (F-RAM) sensing circuit 200 according to one embodiment of the subject matter. In one embodiment, F-RAM cells 90 and' 90 are configured as complementary memory cells. When the F-RAM cell 90 is programmed to one particular polarization state (e.g., "0"), the F-RAM cell' 90 is programmed to the opposite polarization state (e.g., "1"). As shown in FIG. 2, pass transistors 96 and' 96 may be coupled to the same WL. Alternatively, pass transistors 96 and' 96 are coupled to two different WLs and controlled by two different WL signals. Similarly, ferroelectric capacitors 94 and' 94 may be coupled to the same PL or two different PLs, depending on design requirements. In one embodiment, pass transistor' 96 is coupled to BLB, and no Vref may be required for a read operation.

The read operation of the 2T2C F-RAM sensing circuit 200 is similar to that of 1T1C, as shown in FIG. 1B. During a read operation, F-RAM cells 90 and' 90 may be interrogated simultaneously or separately by an "up-down" pulse asserted on a PL (one PL or two separate PLs), as in step 156 of FIG. 1B. The signal output from the F-RAM cell 90 may be considered a true signal or bit, while the signal output from the F-RAM cell' 90 may be considered a complementary signal or bit. As explained above, the true signal and the complementary signal are opposite by design.

In contrast to the 2T2C design, the 1T1C design may only include a maximum of half the signal margin if the reference voltage is perfectly configured at the mid-voltage between the P term and U term signals. Thus, the smaller cell size of the 1T1C design may be at the expense of available signal margin.

In contrast, a 2T2C F-RAM architecture including two ferroelectric capacitors may utilize the P term of one ferroelectric capacitor and the U term of another ferroelectric capacitor in the same 2T2C F-RAM cell to represent the stored data. In one embodiment, a 2T2C F-RAM cell may result in a 2T2C F-RAM cell becoming differential, benefiting from the signal margin of the all ferroelectric capacitor switch charge (i.e., the P term-U term). However, 1T1C F-RAM cells or arrays may have the advantage of smaller cell size compared to 2T2C designs.

To ensure reliable reading, whether it be single ended (e.g., 1T1C) or differential (e.g., 2T2C), it is critical that the sense amplifiers be as balanced and symmetric as possible. Any asymmetry in the sense amplifier may result in an input offset voltage that will directly degrade the sensing margin. In one embodiment, the symmetry and balance of the sense amplifier may be achieved by appropriate layout techniques. For example, the bit lines (e.g., B1 and BLB in FIGS. 1A and 2) can be very closely matched to each other by layout techniques to ensure that the sense amplifiers are balanced and the system input offset is as small as possible. In some embodiments, a small trim capacitor may be selectively added to one input of the sense amplifier in an attempt to increase balance and symmetry. Despite best efforts, the fabrication process of ferroelectric capacitors may not be fully controlled. As a result, the effective area, thickness, and other parameters of the ferroelectric capacitor may vary significantly. In one embodiment, the variable electrical impedance (such as linear capacitance) of the ferroelectric capacitor may also adversely affect the balance and symmetry of the sense amplifier when electrically connected thereto.

The read operation of an F-RAM memory cell is destructive, meaning that the data must be refreshed after the read operation is complete. Referring to FIG. 1B, in step 156, the stored data is corrupted by an interrogation pulse (e.g., an up-down pulse). Thus, ferroelectric capacitor 94 and/or' 94 adds no valuable information to the circuit or read operation after the up and down pulses of PL. Referring to fig. 1A and 1B, before PL is modulated with pulses (step 156), WL is raised (step 152). If WL remains high to turn on pass transistor 96 after interrogation of ferroelectric capacitor 94 and memory signal output is complete, ferroelectric capacitor 94 will remain electrically connected to the sense amplifier input through pass transistor 96. If WL remains high when the sense amplifier is enabled (step 158), then the ferroelectric capacitor remains electrically connected to the sense amplifier during the sensing operation. As explained earlier, the electrical connection between ferroelectric capacitor 94 and SA during sensing does not add any valuable information, since the stored value has been destroyed during the PL pulse (step 156). However, this connection may contribute a significant amount of asymmetry to the sense amplifier, causing the input offset of the sense amplifier to increase and the sensing margin to decrease.

FIG. 4 is a schematic diagram illustrating a portion of an F-RAM device 400. In one embodiment, the F-RAM device 400 will be used herein to illustrate how the WL signal can be configured during a read operation to improve the balance and symmetry of the SAs. It will be appreciated that the disclosed method may be applied to other similar memory devices known in the art.

Referring to FIG. 4, a plurality of 1T1C memory cells 402 may be arranged in rows and columns to form an F-RAM memory array. The 1T1C memory cell 402 may have a similar configuration and structure as shown in FIG. 1A. As best illustrated in fig. 4, the plurality of 1T1C memory cells 402 are arranged in N +1 rows (row 0 through row N) and N +1 columns (column 0 through column N). In one embodiment, 1T1C memory cells in the same column share and are electrically coupled to one Plate Line (PL) and Bit Line (BL). The pass transistors of the 1T1C memory cells 402 of all other columns on the same row (e.g., row 0 and columns 0, 2, … N-1) are coupled to the same Word Line (WL) and controlled by the same WL signal. Two adjacent BL's (e.g., BL <0> and BL <1>) are coupled to Vref transistor 406, which is controlled by the Vref _ Enable signal. In one embodiment, the Vref transistor controls whether a reference signal (Vref) is coupled to BL. Each BL is coupled on the other end to a precharge transistor 408, the precharge transistor 408 controlling the precharging of the BL (steps 150, 154). BL is further coupled to column transistor 410, and column transistor 410 controls the connection of BL to sense amplifier 412. In one embodiment, adjacent BL's (e.g., BL <0:1>) are coupled to two respective inputs of a single SA 412. All SAs 412 are controlled by the SA _ enable signal.

In one embodiment, F-RAM device 400 may be configured to operate as a 1T1C memory array for single ended sensing/reading or a 2T2C memory array for differential sensing/reading. In an embodiment of the 2T2C configuration, two adjacent 1T1C memory cells of the same row may be paired to form the 2T2C memory cell 404. As explained previously, the two 1T1C memory cells of a complementary pair can be programmed to opposite polarization states during the writing of data, and one of them represents a true signal/bit and the other represents a complementary signal/bit.

Fig. 5A through 5F are representative timing diagrams illustrating signal levels of various nodes during read operations/sensing of an F-RAM array, such as F-RAM device 400. In one embodiment, precharge is a signal coupled to the gate of precharge transistor 408. VREF _ enable is a signal coupled to the gate of VREF transistor 406. In one embodiment, the Vref transistor controls the assertion of Vref on BL. For example, VREF _ Enable <0> controls Vref transistors 406 connected to odd BL (such as BL <1>, BL <3>, etc.), while VREF _ Enable <1> controls Vref transistors 406 connected to even BL (such as BL <0>, BL <2>, etc.). WL < odd > controls the pass transistors in odd columns and WL < even > controls the pass transistors in even columns of the same row. Column _ enable is a signal coupled to the gate of column transistor 410 that controls the electrical connection between sense amplifier 412 and each of its respective BL's.

As shown in FIG. 1A, the read operation begins by selecting an F-RAM memory cell for sensing (step 150). Referring to FIG. 5A, F-RAM device 400 is configured to execute as a 1T1CF-RAM array, and 1T1C memory cells 402 in row 0 and column 0 are selected for a read operation. At time t1, the precharge signal is asserted until t3 to enable the precharge transistors of all columns so that all BL's are precharged to Vss, for example. At t2, WL<0>The signal is asserted (step 152) or raised so that the ferroelectric capacitors of column 0, row 0 are electrically connected to BL<0>. In one embodiment, WL<0>The signal is asserted until sensing is complete at t 10. WL<N:1>The signals may be both negated or depressed during sensing so that the unselected 1T1C memory cells 402 in the other rows and columns are not electrically connected to their respective BL. The column _ enable signal is asserted at t3 until t11 during the entire sensing period to ensure that the electrical connection between the sense amplifiers 412 and their respective BL is maintained. In one embodiment, PL<0>The signal is between t4 and t7Is asserted to interrogate the selected 1T1C memory cell 402 (step 156). As shown in FIG. 5A, PL<0>The signal may represent the aforementioned "up-down" or square wave pulse, in which it may be switched from Vss to V_DD(at t4) and then from V_DDSwitching to Vss (at t 7). During T4 and T7, the ferroelectric capacitor in the selected 1T1C memory cell 402 may be due to PL on one of its plates<0>The signal is active and its polarization state is flipped (P term) or held (U term). In response, the selected 1T1C memory cell 402 may output BL in FIG. 5A<0>The corresponding memory signal reflected in (a). Since it is single ended sensing, in BL<0>Will pass through BL<1>The reference signal is compared to a reference signal (Vref), which is controlled by a Vref _ enable signal. As previously mentioned, Vref may be preset to a value between the P and U entries of 1T1C memory cell 402 or other programmable value. In one embodiment, VREF _ Enable<0>The signal is asserted at t5, causing Vref to be applied to BL<1>The above. Because of WL<N:1>Are disabled, so 1T1C memory cell 402 on rank 1 is all aligned with BL<1>Is electrically isolated. At t8, the SA _ Enable signal is asserted, causing all sense amplifiers 412 to be enabled (step 158). BL<0>And BL<1>Respectively, to their respective inputs in the sense amplifier 412. Sense amplifier 412 may then be in the BL<0>Signals on (memory signals), such as their respective amplitudes, and signals at BL<1>The above signals (Vref) are compared and the result is output accordingly (step 160). As an example, in BL<0>The memory signal above is greater than Vref, which represents the P term (binary state "0" or "1"). It will be understood that in BL<0>The memory signal above may also be less than Vref to represent the U term ("1" or "0"). After that, the read operation is completed, and the WL is<0>The signal is deasserted (depressed) at T10 and the column _ enable signal is deasserted at T11, so that all 1T1C memory cells are again electrically isolated from all BL.

FIG. 5B is a representative timing diagram illustrating a read operation of F-RAM device 400 in a 2T2C differential sensing configuration. In one embodiment, 1T1C memory cells 402 in row 0, column 0, and 1 are paired to form 2T2C memory cells 404, which are selected to be read. Memory cell 402 in row 0, column 0, 1T1C is configured as a true cell, while memory cell 402 in row 0, column 1, 1T1C is configured as a complementary cell. The operation of 2T2C sensing is similar to the embodiment shown in FIG. 5A, except that VREF _ Enable <1:0> is disabled. Therefore, Vref is not applied on any BL during the sensing operation. Conversely, the WL <1> signal is asserted with the WL <0> signal at t2, and the PL <1> signal is asserted with the PL <0> signal at t 4. As a result, both the true memory cell and the complementary cell are interrogated by an "up-down" pulse and output their contents to BL <0> and BL <1> respectively. In one embodiment, when SA _ Enable is asserted at T8 to enable sense amplifier 412, sense amplifier 412 having the BL <1:0> signals as its two inputs may compare the true signal via BL <0> to the complementary signal via BL <1> to determine the binary state of 2T2C memory cell 404.

As shown in both FIG. 5A and FIG. 5B, the WL of the selected memory cell (WL <0> in FIG. 5A and WL <1:0> in FIG. 5B) remains activated during sensing (t 8-t 9). As explained previously, once a selected memory cell is interrogated by an "up-down" pulse (at t7), there is no need to maintain an electrical connection between the selected memory cell and the sense amplifier. In fact, this connection may contribute a significant amount of asymmetry to the sense amplifier and disadvantageously reduce the sense margin (1T1C and 2T 2C).

Fig. 5C and 5D illustrate alternative sensing schemes for the F-RAM device 400. Referring to FIG. 5C, a 1T1C sensing operation is illustrated. Similar to the embodiment disclosed in FIG. 5A, the WL <0> signal is asserted at T2 (WL <0> is activated) to turn on the pass transistor and enable an electrical connection between the selected 1T1C memory cell 402 and BL <0 >. PL <0> is asserted between t4 and t7 to interrogate the selected memory cell. The main difference in this scheme is that the WL <0> signal is de-asserted or depressed (WL <0> is deactivated) at t8 shortly after the PL <0> signal is de-asserted. In one embodiment, a small amount of time between t7 and t8 may act as a buffer to allow selected memory cell 402 to fully output its contents to BL <0> before the connection is disabled at t 8. After the ferroelectric capacitor in the selected memory cell is electrically isolated from BL <0> and sense amplifier 412, the SA _ ENABLE signal is asserted to enable sense amplifier 412 and begin sensing at t 9. Without the effect from the ferroelectric capacitor of the selected memory cell (when the pass transistor is off), the sense amplifier 412 can obtain the best balance and symmetry during its sensing operation.

Fig. 5D illustrates an alternative sensing scheme in a 2T2C configuration. Similar to the embodiment disclosed in FIG. 5C, both the WL <0> and WL <1> signals are de-asserted at t8 before the sense amplifier is enabled at t 9. The electrical isolation of the two ferroelectric capacitors in the selected 2T2C memory cell 404 from their respective BLs during sensing (T9-T10) may also improve the balance and symmetry of the sense amplifier 412 during differential sensing.

Fig. 5E and 5F illustrate another alternative sensing scheme for the F-RAM device 400. Referring to fig. 5C and 5D, the ferroelectric capacitor is isolated from the sense amplifier 412 by disabling the WL signal before the sense amplifier is enabled. The WL signal controls the pass transistor local to each 1T1C memory cell 402. Similar to fig. 5C, the 1T1C sensing scheme shown in fig. 5E can also globally electrically disconnect the ferroelectric capacitor of the selected memory cell from the sense amplifier 412 during sensing. Referring to FIG. 5E, while the WL <0> signal remains active during sensing (t9 to t10), at t8 the column _ enable signal is de-asserted or depressed a bit after the "Up and Down" pulse on PL <0> is completed. The deassertion of the column _ enable signal at t8 may electrically isolate BL <0> and the ferroelectric capacitor from sense amplifier 412. The buffering between t7 and t8 may enable the memory signal to be output to the input of sense amplifier 412 before its electrical connection to BL <0> is disabled at t 8.

Fig. 5F illustrates a similar sensing scheme in a 2T2C configuration. In one embodiment, the WL <1:0> signals remain asserted until t 11. The symmetry and balance of the sense amplifier is still improved because the sense amplifier is electrically isolated from both BL <1:0> when the column _ Enable signal is deasserted at t 8.

Another alternative to the sensing scheme may combine the embodiments disclosed in fig. 5C to 5F. In one embodiment, both the WL signal (e.g., the WL <1:0> signals) and the column _ Enable signal are deasserted just after the PL signal (the "Up and Down" pulses) is deasserted and before the sense amplifiers are enabled. This alternative may ensure electrical isolation between the sense amplifier and the ferroelectric capacitor at the individual memory cell level locally and at the BL level globally.

In one embodiment, the disclosed sensing scheme may be applied to any memory technology where there are undesirable variations in the memory cells that would have a direct impact on the sense amplifier, and where data may be extracted from the memory cells so that the sense amplifier may resolve the data after the memory cells are isolated from the sense amplifier inputs. It may be suitable for use in M-RAM devices, for example.

Fig. 6 is a representative block diagram of a semiconductor memory 600 including a memory portion 601. In the memory portion 601, there is a memory array 602 of non-volatile (NV) memory cells 606 arranged in a plurality of rows, each sharing a common Word Line (WL), and a plurality of columns, each sharing a common bit line and a common plate line. In one embodiment, NV memory cell 606 may be a 1T1C F-RAM cell 100 or a 2T2C F-RAM cell 200. In one embodiment, a reference generation array 608, including a MOS reference generation array and possibly a ferroelectric reference generation array, may also be disposed within the memory portion 601. Referring to fig. 6, the semiconductor memory 600 further includes a processing element 610, such as a microcontroller, microprocessor, or state machine. In one embodiment, the processing element 610 may issue command or control signals (such as WL, RWL signals) to each NV memory cell 606 and the reference generation array 608 to perform read, erase, and program operations as described above, as well as other peripheral circuitry for reading from or writing to the memory array 602. The peripheral circuitry includes a row decoder 612 to translate and apply memory addresses to the word lines of NV memory cells 606 of the memory array 602. When a data word is read from the semiconductor memory 600, NV memory cells 606 coupled to the selected Word Line (WL) are read out to the bit lines, and the state of those lines is detected by sense amplifier/driver 614. Column decoder 616 outputs data from the bit lines onto sense amplifiers/drivers 614. In one embodiment, processing element 610 may use the sense amplifier enable signal to enable/disable certain columns of sense amplifiers. The processing element 610 may also translate and apply addresses to the memory array 602 via a row decoder 612 and/or a column decoder 616 to assert or negate word line signals for a particular WL. In one embodiment, the semiconductor memory 600 may employ the sensing scheme disclosed in fig. 5C-5F such that the WL associated with the selected memory cell is disabled before the sense amplifier is enabled for sensing during a read operation. Control may be achieved by firmware applications, circuit design (e.g., timing circuits), or a combination thereof.

Although the present disclosure has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the disclosure. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

The abstract of the disclosure is provided to comply with chapter 37, clause 1, 72, b of the federal regulations compilation of the united states that requires an abstract that allows a reader to quickly ascertain the nature of one or more embodiments of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Reference in the description to one embodiment or an embodiment means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of a circuit or method. The appearances of the phrase "one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

In the foregoing specification, the subject matter has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the subject matter as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.