阅读说明：本技术 减少保持泄漏的sram
(SRAM with reduced retention leakage
) 是由 A·库玛
M·A·阿拉姆 于 2020-04-09 设计创作，主要内容包括：本公开的实施例涉及减少保持泄漏的SRAM。存储器设备包括在虚拟电源和虚拟接地节点之间被供电的存储器阵列。伪存储器阵列在第一和第二节点之间被供电。虚拟电源发生电路根据第一控制电压在虚拟电源节点处生成虚拟电源电压。虚拟接地发生电路根据第二控制电压在虚拟接地节点处生成虚拟接地。耦合在第一节点和电源电压之间的第一控制电压发生电路随着跟踪存储器阵列的保持噪声容限(RNM)而生成第一控制电压,第一控制电压随着RNM的减小而下降。耦合在第二节点和接地之间的第二控制电压发生电路随着跟踪存储器阵列的RNM而生成第二控制电压,第二控制电压随着RNM的减小而上升。(Embodiments of the present disclosure relate to SRAM with reduced retention leakage. The memory device includes a memory array powered between a virtual power supply and a virtual ground node. The dummy memory array is powered between the first and second nodes. The virtual power supply generation circuit generates a virtual power supply voltage at a virtual power supply node in accordance with the first control voltage. The virtual ground generation circuit generates a virtual ground at a virtual ground node in accordance with the second control voltage. A first control voltage generation circuit coupled between the first node and a supply voltage generates a first control voltage as a Retention Noise Margin (RNM) of the memory array is tracked, the first control voltage falling as the RNM decreases. A second control voltage generation circuit coupled between a second node and ground generates a second control voltage as the RNM of the memory array is tracked, the second control voltage rising as the RNM decreases.)
1. A memory device, comprising:
a memory array powered between a supply voltage node and a virtual ground voltage node;
a dummy memory array powered between a first node and a second node, the dummy memory array including transistors that are replicas of the transistors of the memory array;
a virtual ground generation circuit configured to generate a virtual ground voltage at the virtual ground voltage node according to a control voltage; and
a control voltage generation circuit coupled between the second node and ground and configured to generate the control voltage as a Retention Noise Margin (RNM) of the memory array is tracked, the control voltage rising as the RNM decreases.
2. The memory device of claim 1, wherein the control voltage generation circuit comprises a plurality of diode-coupled n-channel transistors coupled between the second node and ground, the control voltage being generated at a drain of one of the plurality of diode-coupled n-channel transistors.
3. The memory device of claim 1, wherein the virtual ground generation circuit comprises:
a first branch comprising at least one diode-coupled n-channel transistor coupled between the virtual ground voltage node and ground, the virtual ground voltage being generated at a drain of the at least one diode-coupled n-channel transistor; and
a second branch comprising an n-channel transistor that enables or disables the second branch in response to the control voltage, the second branch coupled in parallel with the first branch.
4. The memory device of claim 3, wherein the second branch further comprises at least one diode-coupled n-channel transistor connected to the n-channel transistor that enables or disables the second branch.
5. The memory device of claim 1, wherein the virtual ground generation circuit further comprises:
an enable n-channel transistor that selectively couples the virtual ground voltage node to ground in response to an enable signal.
6. The memory device of claim 1, further comprising a virtual power supply generation circuit configured to generate a virtual power supply voltage at the power supply voltage node according to an additional control voltage; and the memory device further includes an additional control voltage generation circuit coupled between the first node and a supply voltage and configured to generate the additional control voltage as the RNM of the memory array is tracked, the additional control voltage decreasing as the RNM decreases.
7. A memory device, comprising:
a memory array powered between a virtual power supply voltage node and a virtual ground voltage node;
a dummy memory array powered between a first node and a second node, the dummy memory array including at least some transistors that are replicas of the transistors of the memory array;
a virtual supply voltage generation circuit configured to generate a virtual supply voltage at the virtual supply voltage node in accordance with a control voltage; and
a control voltage generation circuit coupled between the first node and a supply voltage and configured to generate the control voltage as a Retention Noise Margin (RNM) of the memory array is tracked, the control voltage falling as the RNM decreases.
8. The memory device of claim 7, wherein the control voltage generation circuit comprises a plurality of diode-coupled p-channel transistors coupled between the virtual supply voltage node and the supply voltage, the control voltage being generated at a drain of one of the plurality of diode-coupled p-channel transistors.
9. The memory device according to claim 7, wherein the virtual power supply voltage generation circuit comprises:
a first branch comprising at least one diode-coupled p-channel transistor coupled between the virtual supply voltage node and the supply voltage, the virtual supply voltage being generated at a drain of the at least one diode-coupled p-channel transistor; and
a second branch comprising a p-channel transistor that enables or disables the second branch in response to the control voltage, the second branch coupled in parallel with the first branch.
10. The memory device of claim 9, wherein the second branch further comprises at least one diode-coupled p-channel transistor connected to the p-channel transistor that enables or disables the second branch.
11. The memory device of claim 9, wherein the virtual supply voltage generation circuit further comprises:
an enable p-channel transistor that selectively couples the virtual supply voltage node to the supply voltage in response to an enable signal.
12. A method, comprising:
supplying power to the memory array between the virtual supply voltage and the virtual ground voltage;
monitoring a Retention Noise Margin (RNM) of the memory array;
asserting a control signal in response to the RNM decreasing below a threshold RNM value; and
in response to assertion of the control signal, lowering the virtual ground voltage and/or raising the virtual power supply voltage.
13. The method of claim 12, wherein the virtual ground voltage is lowered and the virtual power supply voltage is raised in response to an assertion of the control signal.
14. The method of claim 12, wherein the first and second light sources are selected from the group consisting of,
further comprising: generating the virtual power supply voltage from a power supply voltage and the virtual ground voltage from a ground voltage; and is
Further comprising: determining whether the RNM of the memory array has dropped below the threshold RNM value by:
generating a pseudo power supply voltage from the power supply voltage and a pseudo ground voltage from the ground voltage;
supplying power to a dummy memory array between the dummy supply voltage and the dummy ground voltage; and
asserting the control signal in response to the pseudo-ground voltage rising above a threshold pseudo-ground voltage value and/or in response to the pseudo-supply voltage falling below a threshold pseudo-supply voltage.
15. A memory device, comprising:
a memory array powered between a first memory power supply node and a second memory power supply node;
a tracking circuit configured to track a voltage at the first memory power supply node and assert a first control signal in response to a relationship between the voltage at the first memory power supply node and a first threshold voltage value indicating that a difference between the voltage at the first memory power supply node and a voltage at the second memory power supply node has decreased below a threshold range value; and
a first virtual power supply voltage generation circuit configured to generate a first virtual power supply voltage to the first memory power supply node when the first control signal is asserted and to generate a second virtual power supply voltage to the first memory power supply node when the first control signal is not asserted.
16. The memory device as set forth in claim 15,
wherein the tracking circuit is further configured to track the voltage at the second memory power supply node and assert a second control signal in response to a relationship between the voltage at the second memory power supply node and a second threshold voltage value indicating that the difference between the voltages at the first and second memory power supply nodes has decreased below the threshold range value; and is
Further comprising a second virtual supply voltage generation circuit configured to: generating a third virtual power supply voltage to the second memory power supply node when the second control signal is asserted and generating a fourth virtual power supply voltage to the second memory power supply node when the second control signal is not asserted.
17. The memory device as set forth in claim 16,
wherein the tracking circuit asserts the first control signal in response to the relationship between the voltage at the first memory power supply node and the first threshold voltage value being that the voltage at the first memory power supply node has dropped below the first threshold voltage value; and is
Wherein the tracking circuit asserts the second control signal in response to the relationship between the voltage at the second memory power supply node and the second threshold voltage value being that the voltage at the second memory power supply node has risen above the second threshold voltage value.
18. The memory device of claim 17, wherein the first virtual supply voltage generation circuit is configured to generate the first virtual supply voltage and the second virtual supply voltage from a supply voltage, wherein a magnitude of the second virtual supply voltage is less than the first virtual supply voltage; and wherein the second virtual power supply voltage generation circuit is configured to generate the third virtual power supply voltage and the fourth virtual power supply voltage from a ground voltage, wherein a magnitude of the fourth virtual power supply voltage is greater than the third virtual power supply voltage.
19. The memory device of claim 15, wherein the tracking circuit comprises:
a dummy memory array comprising at least some transistors that are replicas of the transistors of the memory array; and
a first shrink circuit coupled between a first dummy power supply node for the dummy memory array and a first supply voltage, wherein the first control signal is generated at the first dummy power supply node.
20. The memory device of claim 19, wherein the first shrink circuit comprises a plurality of series-connected diode-coupled p-channel transistors.
21. The memory device of claim 19, wherein the first virtual supply voltage generation circuit is configured to generate the first virtual supply voltage and the second virtual supply voltage from a supply voltage, and wherein the first supply voltage corresponds to a supply voltage.
22. The memory device of claim 19, wherein the first virtual power supply voltage generation circuit is configured to generate the first virtual power supply voltage and the second virtual power supply voltage from a ground voltage, and wherein the first power supply voltage corresponds to a ground voltage.
23. The memory device of claim 16, wherein the tracking circuit comprises:
a dummy memory array comprising at least some transistors that are replicas of the transistors of the memory array;
a first shrink circuit coupled between a first dummy power supply node for the dummy memory array and a first power supply voltage, wherein the first control signal is generated at the first dummy power supply node; and
a second shrink circuit coupled between a second dummy power supply node for the dummy memory array and a second power supply voltage, wherein the second control signal is generated at the second dummy power supply node.
24. The memory device of claim 23, wherein the first shrink circuit comprises a first plurality of series-connected diode-coupled transistors; and wherein the second shrink circuit comprises a second plurality of series-connected diode-coupled transistors.
25. The memory device of claim 15, wherein the first virtual supply voltage generation circuit is configured to generate the first virtual supply voltage and the second virtual supply voltage from a supply voltage.
26. The memory device according to claim 15, wherein the first virtual power supply voltage generation circuit is configured to generate the first virtual power supply voltage and the second virtual power supply voltage from a ground voltage.
27. The memory device according to claim 15, wherein the first virtual power supply voltage generation circuit comprises:
a first transistor branch comprising at least one diode-coupled transistor, the first transistor branch being coupled between the first memory power supply node and a first power supply voltage and generating the second virtual power supply voltage; and
a second transistor branch comprising at least one transistor biased by the first control signal, the second transistor branch coupled between the first memory supply node and the first supply voltage and generating the first virtual supply voltage.
28. The memory device of claim 27, wherein the first virtual supply voltage generation circuit further comprises:
an enable transistor branch comprising at least one enable transistor biased by an enable signal, the enable transistor branch coupled between the first memory supply node and the first supply voltage and responsive to the enable signal to clamp the first memory supply node to the first supply voltage.
29. The memory device of claim 15, wherein the memory array and the tracking circuit are included within a same integrated circuit.
30. A method, comprising:
supplying power to the memory array between a supply voltage and a virtual ground voltage;
asserting a control signal in response to a difference between the power supply voltage and the virtual ground voltage decreasing below a threshold difference value; and
lowering the virtual ground voltage in response to assertion of the control signal.
31. The method of claim 30, wherein said step of selecting said target,
further comprising generating the virtual ground voltage from a ground voltage; and is
Further comprising determining whether the difference between the power supply voltage and the virtual ground voltage has dropped below the threshold difference value by:
generating a pseudo power supply voltage from the power supply voltage and a pseudo ground voltage from the ground voltage;
supplying power to a dummy memory array between the dummy supply voltage and the dummy ground voltage; and
asserting the control signal in response to the pseudo-ground voltage rising above a threshold pseudo-ground voltage value.
Technical Field
The present disclosure relates to the field of virtual power supply and/or virtual ground voltage generation for powering memory arrays.
Background
Static Random Access Memory (SRAM) arrays are often used in electronic products because of their ability to access data quickly. To reduce the die area of SRAM arrays, the size of transistors used in SRAM memory arrays has been shrinking.
An example SRAM cell 19 is shown in fig. 1. As can be seen, the SRAM cell 19 includes a pair of cross-coupled CMOS inverters 21 and 22 powered between a virtual power supply voltage (virtual VDD) node and a virtual ground voltage (virtual GND) node. In response to the assertion of the word line signal WL, the CMOS inverters 21 and 22 are selectively connected to the bit line BL and the complementary bit line BLB through NMOS transistors MN3 and MN 4. The CMOS inverter 21 includes a PMOS transistor MP1, the source of the PMOS transistor MP1 being coupled to the virtual VDD, and the drain and gate thereof being coupled to the drain and gate of the NMOS transistor MN1, respectively. The source of NMOS transistor MN1 is coupled to virtual GND. The CMOS inverter 22 includes a PMOS transistor MP2, the source of the PMOS transistor MP2 being coupled to the virtual VDD and the drain and gate thereof being coupled to the drain and gate of the NMOS transistor MN2, respectively. The source of NMOS transistor MN2 is coupled to virtual VDD. Note that the gates of transistors MP1 and MN1 are coupled to the drains of transistors MP2 and MN2, while the gates of transistors MP2 and MN2 are coupled to the drains of transistors MP1 and MN 1.
The Retention Noise Margin (RNM) is a measure of the stability of an SRAM cell (e.g., SRAM cell 19) during standby (without a read or write operation). RNM is a function of the supply voltage and ground voltage to which SRAM cell 19 is powered. If RNM is sufficiently reduced, inverters 21 and 22 may change state without a write operation, meaning that the data bit stored therein will be lost. This is clearly undesirable. Although some techniques for increasing RNM are known, such techniques may be inadequate for certain use cases. Therefore, further development of circuits for increasing RNM is required.
Disclosure of Invention
Disclosed herein is a memory device including: a memory array powered between a supply voltage node and a virtual ground voltage node, and a dummy memory array powered between a first node and a second node. The dummy memory array includes at least some transistors that are replicas of the transistors of the memory array. The virtual ground generation circuit is configured to generate a virtual ground voltage at a virtual ground voltage node according to a control voltage. The control voltage generation circuit is coupled between the second node and ground and configured to generate a control voltage as a Retention Noise Margin (RNM) of the memory array is tracked, the control voltage rising as the RNM decreases.
The control voltage generation circuit may include a plurality of diode-coupled n-channel transistors coupled between the second node and ground, wherein the control voltage is generated at a drain of one of the plurality of diode-coupled n-channel transistors.
The virtual ground generation circuit may include a first branch including at least one diode-coupled n-channel transistor coupled between a virtual ground voltage node and ground, the virtual ground voltage being generated at a drain of the at least one diode-coupled n-channel transistor. The second branch may include an n-channel transistor that enables or disables the second branch in response to a control voltage, the second branch being coupled in parallel with the first branch.
The second branch may include at least one diode-coupled n-channel transistor connected to enable or disable the n-channel transistor of the second branch.
The virtual ground generation circuit may further include an enable n-channel transistor that selectively couples the virtual ground voltage node to ground in response to an enable signal.
The virtual power supply generation circuit may be configured to generate a virtual power supply voltage at the power supply voltage node in accordance with the additional control voltage. The additional control voltage generation circuit may be coupled between the first node and a supply voltage and configured to generate an additional control voltage as the RNM of the memory array is tracked, the additional control voltage decreasing as the RNM decreases.
Also disclosed herein is a memory device comprising: a memory array powered between the virtual supply voltage node and the virtual ground voltage node, and a dummy memory array powered between the first node and the second node. The dummy memory array includes at least some transistors that are replicas of the transistors of the memory array. The virtual supply voltage generation circuit is configured to generate a virtual supply voltage at a virtual supply voltage node in accordance with the control voltage. The control voltage generation circuit is coupled between the first node and a supply voltage and configured to generate a control voltage as a Retention Noise Margin (RNM) of the memory array is tracked, the control voltage decreasing as the RNM decreases.
The control voltage generation circuit may include a plurality of diode-coupled p-channel transistors coupled between the virtual supply voltage node and the supply voltage, the control voltage being generated at a drain of one of the plurality of diode-coupled p-channel transistors.
The virtual power supply voltage generation circuit may include: a first branch having at least one diode-coupled p-channel transistor coupled between a virtual supply voltage node and a supply voltage, the virtual supply voltage generated at a drain of the at least one diode-coupled p-channel transistor; and a second branch having a p-channel transistor that enables or disables the second branch in response to a control voltage, the second branch coupled in parallel with the first branch.
The second branch may further include at least one diode-coupled p-channel transistor connected to enable or disable the p-channel transistor of the second branch.
The virtual supply voltage generation circuit may also include an enable p-channel transistor that selectively couples the virtual supply voltage node to the supply voltage in response to an enable signal.
Method aspects are also disclosed herein. For example, the method comprises: supplying power to the memory array between the virtual supply voltage and the virtual ground voltage; monitoring a Retention Noise Margin (RNM) of the memory array; asserting a control signal in response to the RNM falling below a threshold RNM value; and lowering the virtual ground voltage and/or raising the virtual power supply voltage in response to assertion of the control signal.
The other method comprises the following steps: supplying power to the memory array between a supply voltage and a virtual ground voltage; monitoring a Retention Noise Margin (RNM) of the memory array; asserting a control signal in response to the RNM falling below a threshold RNM value; and lowering the virtual ground voltage in response to asserting the control signal.
Drawings
FIG. 1 shows a schematic block diagram of an SRAM memory cell.
FIG. 2A is a block diagram of a memory device containing a tracking circuit that generates control signals for a virtual VDD and virtual GND generation circuit that powers a memory array.
FIG. 2B is a block diagram of another memory device including a tracking circuit that generates control signals for a virtual VDD and virtual GND generation circuit that powers a memory array.
FIG. 3A is a schematic block diagram of a memory device containing a tracking circuit that generates control signals for a virtual VDD and virtual GND generation circuit that powers a memory array.
FIG. 3B is a schematic block diagram of a memory device including a tracking circuit that generates control signals for a virtual GND generation circuit of a memory array.
FIG. 3C is a schematic block diagram of a memory device including a tracking circuit that generates control signals for a virtual VDD generation circuit of a memory array.
FIG. 4A is a first embodiment of the memory device of FIG. 3A.
Fig. 4B is a variation of the embodiment of fig. 4A.
FIG. 5A is a second embodiment of the memory device of FIG. 3A.
Fig. 5B is a variation of the embodiment of fig. 5A.
FIG. 6A is a third embodiment of the memory device of FIG. 3A.
Fig. 6B is a variation of the embodiment of fig. 6A.
Fig. 7A is a graph showing rail-to-rail (rail) voltage and virtual ground voltage of the device of the present disclosure at different temperatures and for different process corners (process corner).
Fig. 7B is a graph showing the control voltage and virtual ground voltage of the apparatus of the present disclosure at different temperatures and for different process corners.
Fig. 7C is a graph showing the control voltage and virtual ground voltage of the apparatus of the present disclosure at different temperatures and for different process corners.
Fig. 8 is a graph showing the virtual ground voltage of the apparatus of the present disclosure at different temperatures and for different process corners.
Fig. 9 is a graph showing control signal voltage for the apparatus of the present disclosure at different temperatures and for different process corners.
Detailed Description
The following disclosure enables one of ordinary skill in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of the present disclosure. The present disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.
A block diagram of the memory device 10 will now be described first with reference to fig. 2. The memory device 10 includes: a memory array 30 connected between a power supply voltage VDD and a ground voltage GND; and a tracking circuit 20 also connected between VDD and GND. Memory array 30 includes an array of memory blocks arranged in rows and columns that are represented using letter indices to indicate locations within the array, such that the memory blocks in the first row are labeled 30aa.. 30na, while the memory blocks in the last row are labeled 30am...30nm, and such that the memory blocks in the first column are labeled 30aa.. 30am, and the memory blocks in the last column are labeled 30na...30 nm. As shown in fig. 2A, each memory block of memory array 30 may be an individual memory cell that shares common peripheral circuitry 34.
It should be appreciated that peripheral circuitry 34 is used to generate virtual power and ground voltages, Vvdd and Vgnd, for powering their respective memory cells. To reduce leakage current through memory array 30 and the power consumption resulting therefrom, it is desirable that virtual power supply voltage Vvdd be lower than VDD and virtual ground voltage Vgnd be higher than GND. However, as the difference between the generated virtual power supply voltage Vvdd and the virtual ground voltage Vgnd decreases, the Retention Noise Margin (RNM) of the memory array 30 decreases. When the difference between the generated virtual power supply voltage Vvdd and the virtual ground voltage Vgnd decreases below the threshold difference value, there is a corresponding degradation in the RNM such that the RNM may be low enough that one or more memory cells of the memory array 30 (e.g., such as those "worst case" cells in terms of PVT variations) may experience data loss in the standby mode. Therefore, it is desirable that the virtual power supply voltage Vvdd be lower than VDD, but not so low that RNM degradation causes data loss; also, it is desirable that the virtual ground voltage Vgnd be higher than GND, but not so high that RNM is severely degraded resulting in data loss. Since RNM is affected by operating conditions, setting Vvdd and Vgnd to a level at which RNM degradation does not occur under any expected operating conditions means that Vvdd and Vgnd are set to levels required for worst-case operating conditions, which means that there is excessive leakage current during non-worst-case operating conditions. This is undesirable.
To avoid this and to allow Vvdd and Vgnd to be set appropriately for the existing operating conditions, the tracking circuit 20 is used to track the difference between VDD and GND (or between the virtual power supply voltage Vvdd and the virtual ground voltage Vgnd), in which case the input to the tracking circuit 20 is taken directly or indirectly from the nodes Vvdd (instead of VDD) and Vgnd (instead of GND), and a control signal Ctrl is generated in response to the difference. The control signal Ctrl is received by the peripheral circuitry 34, and depending on the difference between VDD and GND (or between Vvdd and Vgnd), the tracking circuit 20 may instruct the peripheral circuitry 34 to raise the virtual power supply voltage Vvdd and/or lower the virtual ground voltage Vgnd to increase the difference therebetween and re-establish a safe RNM.
In some cases, as shown in FIG. 2B, each memory block 30' may itself be a sub-array of memory cells, the memory cells of each sub-array sharing common peripheral circuitry specific to that sub-array. The peripheral circuits 34' in fig. 2B operate as described above and each receive a control signal Ctrl from which Vvdd and/or Vgnd are generated.
Described now with reference to fig. 3A, fig. 3A is a schematic block diagram of a memory device 50 that includes a tracking circuit 60, the tracking circuit 60 generating control signals for virtual supply voltage Vvdd and virtual ground Vgnd generation circuits 70 and 75, the virtual supply voltage Vvdd and virtual ground Vgnd generation circuits 70 and 75 powering a memory array (e.g., SRAM core) 71.
The virtual power supply generation circuit 70 includes a first branch 72a and a second branch 72b coupled between nodes N3 and VDD, wherein an enable transistor ET1 selectively connects node N3 directly to VDD (thus binding Vvdd to VDD) according to an enable signal En 1. The virtual ground generation circuit 75 includes a first branch 73a and a second branch 73b coupled between nodes N4 and GND, wherein an enable transistor ET2 selectively connects node N4 directly to ground GND (thus binding Vgnd to GND) according to an enable signal En 2.
Tracking circuit 60 includes a dummy column 61 coupled between nodes N1 and N2, dummy column 61 containing replica transistors and replica memory cells of some memory in memory array 71 such that the same PVT variations affecting memory array 71 similarly affect dummy column 61. Tracking circuit 60 also includes puncturing circuit 62 coupled between node N1 and VDD and puncturing circuit 63 coupled between node N2 and GND.
In operation of memory device 50, the difference between GND and VDD (or between virtual power supply Vvdd and virtual ground Vgnd) may drop at different process corners, and if the difference drops sufficiently, as illustrated, the worst-case transistors within memory array 71 for that process corner may switch, causing the memory cells containing them to lose data. Therefore, the shrink circuits 62 and 63 are designed such that the control signal Ctrl1 falls with the fall of Vvdd at a rate sufficient to enable the first branch 72a of the virtual power generation circuit 70 before the difference between Vvdd and Vgnd decreases sufficiently to cause a potential data loss due to a low RNM, and such that the control signal Ctrl2 rises with the rise of Vgnd at a rate sufficient to enable the first branch 73a of the virtual ground generation circuit 75 before the difference between Vvdd and Vgnd decreases sufficiently to cause a potential data loss. The enabling of the first branch 72a causes the first branch 72a to be in parallel with the second branch 72b, with the result that the voltage drop between VDD and Vvdd falls, and hence Vvdd rises; likewise, the enabling of the first branch 73a causes the first branch 73a to be connected in parallel with the second branch 73b, with the result that the voltage drop between GND and Vgnd, and therefore Vgnd, decreases; overall, this increases the difference between Vvdd and Vgnd, raising the RNM to a safe level, and prevents data loss since, as explained, the first branches 72a and 73a are switched on before the RNM drops sufficiently to cause potential data loss.
It should be understood that neither the virtual power supply voltage generation circuit 70 nor the virtual ground voltage generation circuit 75 is required in some applications, and a design in which only one of the virtual power supply voltage generation circuit 70 and the virtual ground voltage generation circuit 75 exists may be used, since the goal is to increase the difference between Vvdd and Vgnd at the process corner. Thus, FIG. 3B shows a design in which the design of the virtual supply voltage generation circuit 70 of FIG. 3A does not exist and it may be assumed that the memory array 71 is tied directly to VDD or receives a virtual supply voltage from a known virtual supply voltage generation circuit. Also, a design is shown in FIG. 3C, where the design of virtual ground generation circuit 75 of FIG. 3A is not present, and it may be assumed that memory array 71 is either tied directly to GND, or receives a virtual ground voltage from a known virtual ground generation circuit.
Described now with reference to fig. 4A, fig. 4A is a schematic block diagram of a memory device 50a that includes a tracking circuit 60, the tracking circuit 60 generating control signals for virtual supply voltage Vvdd and virtual ground Vgnd generation circuits 70 and 75, the virtual supply voltage Vvdd and virtual ground Vgnd generation circuits 70 and 75 powering a memory array (e.g., SRAM core) 71.
Tracking circuit 60 includes a dummy column 61 coupled between nodes N1 and N2, dummy column 61 containing replica transistors and replica memory cells of some memory in memory array 71 such that the same PVT variations affecting memory array 71 similarly affect dummy column 61. The tracking circuit 60 also includes a shrink circuit 62 coupled between node N1 and VDD and a shrink circuit 63 coupled between node N2 and GND.
Shrink circuit 62 includes diode-coupled p-channel transistors T1-T4 connected in series between node N1 and VDD, and shrink circuit 63 includes diode-coupled N-channel transistors M1-M4 connected in series between node N2 and GND. The control signal Ctrl1 is generated at node N1, and the control signal Ctrl2 is generated at node N2.
The virtual power supply voltage Vvdd generation circuit 70 includes: a first branch 72a and a second branch 72b coupled between VDD and a node N3 and used in common for generating a virtual supply voltage Vvdd at a node N3; and an enable transistor ET1 that selectively bypasses the first and second branches 72a and 72b to bind Vvdd directly to VDD.
In particular, the first branch 72a comprises: a diode-coupled p-channel transistor T5 connected to the node N3, and a p-channel transistor T6 connected between the p-channel transistor T5 and VDD. The drain of P-channel transistor T6 is connected to the source of diode-coupled P-channel transistor T5, the source of P-channel transistor T6 is connected to VDD, and the gate of P-channel transistor T6 is connected to node N1 to be biased by control signal Ctrl 1. The second branch 72b includes diode-coupled p-channel transistors T7 and T8 connected in series between node N3 and VDD. The enable transistor ET1 is a p-channel transistor with its drain connected to node N3, its source connected to VDD, and its gate controlled by an enable signal En 1.
The virtual ground voltage Vgnd generation circuit 75 includes: a first branch 73a and a second branch 73b coupled between GND and a node N4 and used in common for generating a virtual ground voltage Vgnd at a node N4; and an enable transistor ET2 that selectively bypasses the first and second branches 73a and 73b to bind Vgnd directly to GND.
In particular, the first branch 73a comprises: a diode-coupled N-channel transistor M5 connected to node N5; and an n-channel transistor M6 connected between the n-channel transistor M5 and GND. The drain of N-channel transistor M6 is connected to the source of diode-coupled N-channel transistor M5, its source is connected to GND, and its gate is connected to node N2 to be biased by control signal Ctrl 2. The second branch 72b includes diode-coupled N-channel transistors M7 and M8 connected in series between node N4 and GND. The enable transistor ET2 is an N-channel transistor with its drain connected to node N4, its source connected to GND, and its gate controlled by an enable signal En 2.
In operation of memory device 50a, the difference between virtual power supply Vvdd and virtual ground Vgnd may drop at different process corners, and as explained, if the difference drops sufficiently, the worse the transistors within memory array 71 for that process corner may switch, causing the memory cells containing them to lose data. Thus, the number of diode-coupled transistors in shrink circuits 62 and 63 is set such that control signal Ctrl1 falls with falling Vvdd at a rate sufficient to turn on p-channel transistor T6 before the difference between Vvdd and Vgnd decreases sufficiently to cause a potential data loss due to low RNM, and such that control signal Ctrl2 rises with rising Vgnd at a rate sufficient to turn on n-channel transistor M6 before the difference between Vvdd and Vgnd decreases sufficiently to cause a potential data loss. Conduction of p-channel transistor T6 causes first branch 72a to be connected in parallel with second branch 72b, with the result that the voltage drop between VDD and Vvdd decreases, and therefore Vvdd increases; likewise, the conduction of the n-channel transistor M6 connects the first branch 73a in parallel with the second branch 73b, as a result of which the voltage drop between GND and Vgnd, and therefore Vgnd, drops; overall, this increases the difference between Vvdd and Vgnd, raising the RNM to a safe level, and prevents data loss because, as previously described, p-channel transistor T6 and n-channel transistor M6 turn on before RNM drops sufficiently to cause potential data loss.
It should be appreciated that branches 72a, 72b and 73a, 73b may each contain any number of diode-coupled transistors to achieve the desired level of increase in Vvdd or decrease in Vgnd.
It should be understood that there need not be shrink circuit 62 and virtual supply voltage generation circuit 70, node N1 (and therefore tracking dummy column 61) may be directly coupled to VDD, and node N3 (and therefore SRAM core 71) may be directly coupled to VDD. This is shown in fig. 4B.
In the operation of memory device 50b, the difference between power supply voltage VDD and virtual ground Vgnd may drop at different process corners, and as explained, if the difference drops sufficiently, the worse condition transistors within memory array 71 for that process corner may switch, causing the memory cells that contain them to lose data. Thus, the number of diode-coupled transistors in shrink circuit 63 is set such that control signal Ctrl2 rises with the rise of Vgnd at a rate sufficient to turn on n-channel transistor M6 before the difference between VDD and Vgnd decreases sufficiently to cause potential data loss. The turning on of the n-channel transistor M6 causes the first branch 73a to be connected in parallel with the second branch 73b, as a result of which the voltage drop between GND and Vgnd, and thus Vgnd, decreases. This increases the difference between VDD and Vgnd, raising RNM to a safe level, and prevents data loss since, as explained, n-channel transistor M6 turns on before RNM drops sufficiently to cause potential data loss.
An embodiment of a transistor with less diode coupling is shown in fig. 5A. Described now with reference to fig. 5A, fig. 5A is a schematic block diagram of a memory device 50a ' including a tracking circuit 60, the tracking circuit 60 generating control signals for a virtual supply voltage Vvdd and virtual ground Vgnd generation circuits 70 ' and 75 ', the virtual supply voltage Vvdd and virtual ground Vgnd generation circuits 70 ' and 75 ' powering a memory array (e.g., SRAM core) 71.
Tracking circuit 60 includes a dummy column 61 coupled between nodes N1 and N2, dummy column 61 containing replica transistors and replica memory cells of some memory in memory array 71 such that the same PVT variations affecting memory array 71 similarly affect dummy column 61. The tracking circuit 60 also includes a shrink circuit 62 coupled between node N1 and VDD and a shrink circuit 63 coupled between node N2 and GND.
Shrink circuit 62 includes diode-coupled p-channel transistors T1-T4 connected in series between node N1 and VDD, and shrink circuit 63 includes diode-coupled N-channel transistors M1-M4 connected in series between node N2 and GND. The control signal Ctrl1 is generated at node N1, and the control signal Ctrl2 is generated at node N2.
The virtual power supply voltage Vvdd generation circuit 70' includes: a first branch 72a 'and a second branch 72 b' coupled between VDD and node N3 and used in common for generating a virtual supply voltage Vvdd at node N3; and an enable transistor ET1 that selectively bypasses the first and second branches 72a 'and 72 b' to bind Vvdd directly to VDD.
In particular, the first branch 72 a' includes a p-channel transistor T6 connected between node N3 and VDD, and the gate of the p-channel transistor T6 is connected to node N1 to be biased by a control signal Ctrl 1. The second branch 72 b' includes a diode-coupled p-channel transistor T7 connected between node N3 and VDD. The enable transistor ET1 is a p-channel transistor with its drain connected to node N3, its source connected to VDD, and its gate controlled by an enable signal En 1.
The virtual ground voltage Vgnd generation circuit 75' includes: a first branch 73a 'and a second branch 73 b' coupled between GND and a node N4 and used in common for generating a virtual ground voltage Vgnd at a node N4; and an enable transistor ET2 that selectively bypasses the first and second branches 73a 'and 73 b' to bind Vgnd directly to GND.
In particular, the first branch 73 a' includes an N-channel transistor M6, the N-channel transistor M6 being connected between node N4 and GND, and its gate being connected to node N2 to be biased by a control signal Ctrl 2. The second branch 72 b' includes a diode-coupled N-channel transistor M7 connected between node N4 and GND. The enable transistor ET2 is an N-channel transistor having its drain connected to the node N4, its source connected to GND, and its gate controlled by an enable signal En 2.
In operation of memory device 50 a', the difference between virtual power supply Vvdd and virtual ground Vgnd may drop at different process corners, and as explained, if the difference drops sufficiently, the poorly performing transistors within memory array 71 for that process corner may switch, causing the memory cells containing them to lose data. Thus, the number of diode-coupled transistors in shrink circuits 62 and 63 is set such that control signal Ctrl1 falls with the fall in Vvdd at a rate sufficient to turn on p-channel transistor T6 before the difference between Vvdd and Vgnd decreases sufficiently to cause potential data loss due to low RNM; and causes control signal Ctrl2 to rise as Vgnd rises at a rate sufficient to turn on n-channel transistor M6 before the difference between Vvdd and Vgnd decreases sufficiently to cause a potential data loss. The conduction of the p-channel transistor T6 connects the first branch 72a 'in parallel with the second branch 72 b', with the result that since the p-channel transistor T7 is effectively short-circuited, meaning that node N3 is shorted to VDD, the voltage drop between VDD and Vvdd falls, so Vvdd rises; likewise, the turning on of the N-channel transistor M6 connects the first branch 73a 'in parallel with the second branch 73 b', with the result that the voltage drop between GND and Vgnd, and therefore Vgnd, drops because the N-channel transistor M7 is effectively shorted, meaning that node N4 is shorted to GND; overall, this increases the difference between Vvdd and Vgnd (by binding Vvdd to VDD and Vgnd to GND), thereby raising RNM to a safe level, and prevents data loss since, as described above, p-channel transistor T6 and n-channel transistor M6 turn on before RNM drops sufficiently to cause potential data loss.
It should be appreciated that the virtual supply voltage generator 70 and the virtual ground generator 75 may have additional branches with additional controls to provide a plurality of different selectable levels of virtual supply Vvdd up and virtual ground Vgnd down.
It should be understood that the shrink circuit 62 need not be present, and that node N1 (and thus the tracking dummy column 61) may be directly coupled to VDD. It should also be understood that the virtual supply voltage generation circuit 70 may include a single diode-coupled transistor T7 and an enable transistor ET1, and need not include any transistors controlled according to Ctrl 1. This is shown in fig. 5B.
In operation of memory device 50 b', the difference between virtual power supply Vvdd and virtual ground Vgnd may drop at different process corners, and as explained, if the difference drops sufficiently, the poorly performing transistors within memory array 71 for that process corner may switch, causing the memory cells containing them to lose data. Thus, the number of diode-coupled transistors in shrink circuit 63 is set such that control signal Ctrl2 rises with the rise of Vgnd at a rate sufficient to turn on n-channel transistor M6 before the difference between Vvdd and Vgnd decreases sufficiently to cause a potential data loss. The turning on of the N-channel transistor M6 connects the first branch 73a 'in parallel with the second branch 73 b', with the result that the voltage drop between GND and Vgnd, and hence Vgnd, drops since the N-channel transistor M7 is effectively shorted, meaning that node N4 is shorted to GND. This increases the difference between Vvdd and Vgnd (by binding Vgnd to GND), thereby raising RNM to a safe level, and prevents data loss because, as described above, n-channel transistor M6 turns on before RNM drops sufficiently to cause potential data loss.
An embodiment with additional branches 72c and 73c in the virtual supply voltage generator 70 and the virtual ground generator 75 is shown in fig. 6A. Described now with reference to fig. 6A, fig. 6A is a schematic block diagram of a memory device 50a ", memory device 50" including a tracking circuit 60, tracking circuit 60 generating control signals for a virtual power supply voltage Vvdd and virtual ground Vgnd generation circuits 70 "and 75", virtual power supply voltage Vvdd and virtual ground Vgnd generation circuits 70 "and 75" powering a memory array (e.g., SRAM core) 71.
Tracking circuit 60 includes a dummy column 61 coupled between nodes N1 and N2, dummy column 61 containing replica transistors and replica memory cells of some memory in memory array 71 such that the same PVT variations affecting memory array 71 similarly affect dummy column 61. The tracking circuit 60 further includes: a shrink circuit 62 coupled between node N1 and VDD; and a shrink circuit 63 coupled between node N2 and GND.
Shrink circuit 62 includes diode-coupled p-channel transistors T1-T4 connected in series between node N1 and VDD, and shrink circuit 63 includes diode-coupled N-channel transistors M1-M4 connected in series between node N2 and GND. The control signal Ctrl1 is generated at node N1, and the control signal Ctrl2 is generated at node N2.
The virtual power supply voltage Vvdd generation circuit 70 ″ includes: a first branch 72a ", a second branch 72 b", and a third branch 72c "coupled between VDD and a node N3 and used in common for generating a virtual supply voltage Vvdd at a node N3; and an enable transistor ET1 that selectively bypasses the first, second and third branches 72a ", 72 b" and 72c "to bind Vvdd directly to VDD.
In particular, the first branch 72a "comprises: a diode-coupled p-channel transistor T5 connected to node N3; and a p-channel transistor T6, the drain of the p-channel transistor T6 being connected to the source of the p-channel transistor T5, the source thereof being connected to the drain of the p-channel transistor T9, and the gate thereof being connected to the node N1 to be biased by a control signal Ctrl 1. The p-channel transistor T9 has its source connected to VDD and its gate biased by the LVB signal (which is the complement of the LV signal).
The second branch 72b "comprises diode-coupled p-channel transistors T7 and T8 connected in series, wherein the diode-coupled p-channel transistor T7 is connected to the node N3. The second branch 72b "further includes a p-channel transistor T10, a drain of the p-channel transistor T10 is connected to a source of the p-channel transistor T8, a source thereof is connected to VDD, and a gate thereof is biased by the LVB signal.
The third branch 72c "includes a series-connected diode-coupled p-channel transistor T11-T13, wherein the diode-coupled p-channel transistor T11 is connected to the node N3. The third branch 72c "further comprises a p-channel transistor T14, a drain of the p-channel transistor T14 being connected to a source of the p-channel transistor T13, a source thereof being connected to VDD, and a gate thereof being biased by the LV signal.
The virtual ground voltage generation circuit 75 ″ includes: a first branch 73a ", a second branch 73 b", and a third branch 73c ", which are coupled between GND and a node N4 and are used in common for generating a virtual ground voltage Vgnd at a node N4; and an enable transistor ET2 that selectively bypasses the first, second, and third branches 73a ", 73 b", and 73c "to bind Vgnd directly to GND.
In particular, the first branch 73a "comprises: a diode-coupled N-channel transistor M5 connected to node N4; and an N-channel transistor M6, the drain of N-channel transistor M6 being connected to the source of N-channel transistor M5, its source being connected to the drain of N-channel transistor M9, and its gate being connected to node N2 to be biased by control signal Ctrl 2. The source of n-channel transistor M9 is connected to GND, and its gate is biased by the LV signal.
The second branch 73b "comprises series-connected diode-coupled N-channel transistors M7 and M8, wherein the diode-coupled N-channel transistor M7 is connected to the node N4. The second branch 73b "further comprises an n-channel transistor M10, the drain of the n-channel transistor M10 being connected to the source of the n-channel transistor M8, its source being connected to GND, and its gate being biased by the LV signal.
The third branch 73c "comprises a series-connected diode-coupled N-channel transistor M11-M13, wherein the diode-coupled N-channel transistor M11 is connected to the node N4. The third branch 73c "also includes an n-channel transistor M14, the drain of which M14 is connected to the source of n-channel transistor M13, the source of which is connected to GND, and the gate of which is biased by the LVB signal.
In operation of memory device 50a ", the difference between virtual power supply Vvdd and virtual ground Vgnd may drop at different process corners, and as explained, if the difference drops sufficiently, the poorly performing transistors within memory array 71 for that process corner may switch, causing the memory cells containing them to lose data. Thus, the number of diode-coupled transistors in shrink circuits 62 and 63 is set such that control signal Ctrl1 falls with falling Vvdd at a rate sufficient to turn on p-channel transistor T6 before the difference between Vvdd and Vgnd decreases sufficiently to cause a potential data loss due to low RNM, and such that control signal Ctrl2 rises with rising Vgnd at a rate sufficient to turn on n-channel transistor M6 before the difference between Vvdd and Vgnd decreases sufficiently to cause a potential data loss. Conduction of the p-channel transistor T6 connects the first branch 72a "in parallel with the second branch 72 b", with the result that if the LVB signal is low, turning on the p-channel transistor T9, the voltage drop between VDD and Vvdd drops, so Vvdd rises; likewise, the turning on of the n-channel transistor M6 connects the first branch 73a "in parallel with the second branch 73 b", with the result that if the LV channel is high to turn on the n-channel transistor M9, the voltage drop between GND and Vgnd, and therefore Vgnd, falls; overall, this increases the difference between Vvdd and Vgnd, raising the RNM to a safe level, and prevents data loss because, as previously described, p-channel transistor T6 and n-channel transistor M6 turn on before RNM drops sufficiently to cause potential data loss.
Note here that when LV is low, the third branch 72 c' is enabled, allowing further control of Vvdd. When the LV is low and the LVB is high, the first and second branches 72a ", 72 b" are disabled, while the third branch 72c "is enabled. Likewise, when the LV is low, the first and second branches 73a "and 73 b" are disabled, while the third branch 73c "is enabled. Thus, when LV is low, the Vvdd voltage is fixed to three diode thresholds below VDD, and the Vgnd voltage is fixed to three diode thresholds above GND. When the LV is high and the LVB is low, the first and second branches 72a ", 72 b" are enabled, and the third branch 72c "is disabled. Likewise, when LV is high, the first and second branches 73a ", 73 b" are enabled, while the third branch 73c "is disabled. Thus, when LV is high, the Vvdd voltage is fixed at two diode thresholds below VDD, but transistor T6 may be enabled by Ctrl1 to lower Vvdd to one diode threshold below VDD. Likewise, when LV is high, Vgnd voltage is fixed at two diode thresholds above GND, but transistor M6 may be enabled by Ctrl2 to reduce Vgnd to one diode threshold above GND.
It should be understood that there need not be shrink circuit 62 and virtual supply voltage generation circuit 70, node N1 (and therefore tracking dummy column 61) may be directly coupled to VDD, and node N3 (and therefore SRAM core 71) may be directly coupled to VDD. This is shown in fig. 6B.
In the operation of memory device 50b ", the difference between power supply voltage VDD and virtual ground Vgnd may drop at different process corners, and as explained, if the difference drops sufficiently, the poorly performing transistors within memory array 71 for that process corner may switch, causing the memory cells containing them to lose data. Thus, the number of diode-coupled transistors in shrink circuit 63 is set such that control signal Ctrl2 rises with the rise of Vgnd at a rate sufficient to turn on n-channel transistor M6 before the difference between VDD and Vgnd decreases sufficiently to cause potential data loss. The conduction of the n-channel transistor M6 connects the first branch 73a "in parallel with the second branch 73 b", with the result that if the LV voltage is at a high level that turns on the n-channel transistor M9, the voltage drop between GND and Vgnd, and therefore Vgnd, falls; overall, this increases the difference between VDD and Vgnd, raising RNM to a safe level, and prevents data loss because, as explained, n-channel transistor M6 is turned on before RNM drops sufficiently to cause potential data loss.
Note that here the third branch 73c "is enabled when LV is low, allowing further control of Vgnd. When LV is low, LVB is high, first and second branches 73a "and 73 b" are disabled, and third branch 73c "is enabled, allowing Vgnd to be set using only the transistors of third branch 73 c". Likewise, when LV is high, LVB is low, first and second branches 73a "and 73 b" are enabled, and third branch 73c "is disabled, allowing Vgnd to be set using only the transistors of first and second branches 73 a" and 73b ". In more detail, when LV is low, Vgnd is fixed at three diode thresholds above GND; when LV is high, Vgnd is fixed at two diode thresholds above GND, but n-channel transistor M6 may be enabled by Ctrl2 to reduce Vgnd to one diode threshold above GND.
Note that although the above shrink circuit 62 is shown as a stack of p-channel transistors and the shrink circuit 63 is shown as a stack of n-channel transistors, each of these shrink circuits may alternatively be a combination of p-channel transistors and n-channel transistors.
Additionally, it should be noted that the advantage provided by memory devices 50a-50b, 50a '-50 b', and 50a "-50 b" is when the processing centers between SRAM 71 and the logic devices are mismatched (eventually slower than SRAM). The increased RNM provided by the control signal Ctrl2 tracking lowers the virtual ground, helping to restore stability in this mismatch situation.
The robust performance provided by memory devices 50a-50B, 50a '-50B', and 50a "-50B" can be seen in the graphs of fig. 7A-7B. Here, the rail-to-rail voltage (difference between Vvdd and Vgnd or VDD and GND) and Vgnd generated by virtual ground generation circuit 75 can be seen for different operating temperatures at different process corners.
In the slow and fast process corners, the stability of the cells of the memory array 30 in standby is at a minimum. Thus, in FIG. 7A, note that for slow and fast process corners at an operating temperature of 125 ℃, the prior art design will have a rail-to-rail voltage slightly in excess of 0.4V, while for memory devices 50a-50b, 50a '-50 b', and 50a "-50 b", the rail-to-rail voltage eventually approaches 0.6V. Likewise, for a slow and fast process corner at 125 ℃, the prior art design will produce a Vgnd of 1.1V, while for memory devices 50a-50b, 50a '-50 b', and 50a "-50 b", the Vgnd produced will be 0.9V. Similarly, in FIG. 7B, note that for a slow fast process corner at an operating temperature of 125 ℃, the prior art design would have a Vgnd of approximately 0.225V, but for memory devices 50a-50B, 50a '-50B', and 50a "-50B", the second control voltage Ctrl2 is increased above 0.4V, causing Vgnd to drop below 0.2V, thereby enhancing RNM.
The disadvantage of reducing Vgnd is small because the leakage current at low temperatures is low, so the rail-to-rail voltage in fig. 7A rises to over 0.6V compared to a little over 0.5V for example at slow process corners where the operating temperature is-40 ℃. Also, note that Vgnd for the prior art design herein will be slightly higher than 0.2V, but as shown in FIG. 7B, the Vgnd for the designs for memory devices 50a-50B, 50a '-50 a', and 50a "-50 a" drops below 0.2V.
It can be noted from FIG. 7B that for process corners with low RNM of less concern, Vgnd for the design of memory devices 50a-50B, 50a '-50 a', and 50a "-50 a" is actually raised above the prior art to reduce leakage current, thereby reducing power consumption.
Shown in fig. 7C is a graph showing a comparison between control signal Ctrl2, virtual grounds Vgnd, and Vgnd from a prior art design for different temperatures and different process corners. For example, for an operating temperature of-40 ℃, the virtual ground for the prior art design would be about 0.21V at the slow and fast process corners, while the virtual ground would be about 0.19V for the design described herein.
Another graph illustrating the virtual ground voltage Vgnd generated by memory devices 50a-50b, 50a '-50 b', and 50a "-50 b" over time for different process corners is included in FIG. 8. Here, note that the top graph shows Vgnd for different process angles at 125 ℃, while the top graph shows Vgnd for different process angles at-40 ℃. Referring first to the top figure, it can be seen that: for the slow and fast angles, Vgnd stabilized around 196.68 mV. For the fast-slow angle, Vgnd stabilized at about 185.02 mV; for the fast-fast angle, Vgnd stabilized at about 228.60 mV; for the slow-slow angle, Vgnd stabilized at about 222.72 mV; and Vgnd stabilized at about 185.02mV for the typical-typical angle. For the bottom diagram, it can be seen that: for the slow and fast angle, Vgnd stabilized at about 185.65 mV; for the fast-slow angle, Vgnd stabilizes at about 183.13V; for the fast-fast angle, Vgnd stabilized at about 158.02 mV; and Vgnd stabilized at about 161.51mV for the typical-typical angle.
Another graph illustrating the control signal Ctrl2 generated by memory devices 50a-50b, 50a '-50 b', and 50a "-50 b" over time for different process corners is included in FIG. 9. Here, note that the top graph shows Ctrl2 for different process angles at 125 ℃, while the top graph shows Ctrl2 for different process angles at-40 ℃. Referring first to the top figure, it can be seen that: for the slow fast angle, Ctrl2 stabilized at about 412.58 mV; for the fast-slow angle, Ctrl2 stabilized at about 180.57 mV; for the fast-fast angle, Ctrl2 stabilized at about 199.47 mV; for the slow-slow angle, Ctrl2 stabilized at about 180.57 mV; for typical-typical angles, Ctrl2 stabilized at about 190.07 mV. For the bottom figure, it can be seen that: for the slow fast angle, Ctrl2 stabilized at about 364.15 mV; for the fast-slow angle, Ctrl2 stabilized at about 183.41 mV; for the fast-fast angle, Ctrl2 stabilized at about 254.17 mV; and Ctrl2 stabilized at about 267.27mV for typical-typical angles.
While the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the disclosure as disclosed herein. Accordingly, the scope of the disclosure should be limited only by the attached claims.
