Controller, memory system including the same, and method of operating the same
阅读说明:本技术 控制器、包括控制器的存储器系统及其操作方法 (Controller, memory system including the same, and method of operating the same ) 是由 赵赞赫 于 2019-10-24 设计创作,主要内容包括:本申请可以提供一种控制器、包括该控制器的存储器系统以及操作该存储器系统的方法。该控制器可以包括:处理器,被配置为响应于从主机接收的读取命令而控制存储器装置的读取操作;以及错误校正电路,被配置为在读取操作期间对从存储器装置接收的读取数据执行错误校正操作。该处理器可以在读取操作期间确定存储器装置的劣化特性,并控制该存储器装置选择并对已执行读取操作的存储器单元执行重新编程操作和回收操作中的任何一个。(The present application may provide a controller, a memory system including the controller, and a method of operating the memory system. The controller may include: a processor configured to control a read operation of the memory device in response to a read command received from a host; and an error correction circuit configured to perform an error correction operation on read data received from the memory device during a read operation. The processor may determine a degradation characteristic of the memory device during a read operation, and control the memory device to select and perform any one of a reprogramming operation and a reclaiming operation on memory cells on which the read operation has been performed.)
1. A controller, comprising:
a processor controlling a read operation of the memory device in response to a read command received from a host; and
error correction circuitry to perform an error correction operation on read data received from the memory device during the read operation,
wherein the processor further determines a degradation characteristic of the memory device during the read operation, and controls the memory device to select and perform any one of a reprogramming operation and a reclaiming operation on the memory cells having performed the read operation.
2. The controller of claim 1, wherein the processor comprises:
a flash translation layer generating a command queue for controlling the read operation of the memory device in response to the read command; and
a retention characteristic improvement block determining the degradation characteristic by comparing a reference read voltage with an optimum read voltage used during the read operation if the read operation fails, selecting any one of the reprogramming operation and the recycling operation in response to the determined degradation characteristic, and controlling the memory device.
3. The controller according to claim 2, wherein the controller is a microprocessor,
wherein, during the read operation, the flash translation layer controls the memory device to perform a first read operation using the reference read voltage and a read voltage set included in a read retry table, and
wherein if a result of a first error correction operation on first read data read during the first read operation indicates that a failure has occurred, the flash translation layer controls the memory device to perform a second read operation using the optimal read voltage.
4. The controller according to claim 3, wherein the controller is a microprocessor,
wherein the flash translation layer controls the memory device to perform an eBoost operation or a soft decode operation as the second read operation,
wherein the eBoost operation or the soft decode operation comprises performing a plurality of read operations while changing a read voltage.
5. The controller of claim 3, wherein if a result of a second error correction operation on second read data read during the second read operation indicates that no erroneous bits are included or a minimum number of erroneous bits are included, the flash translation layer controls the memory device such that a read voltage is set to the optimal read voltage and the second read operation is performed.
6. The controller according to claim 3, wherein the controller is a microprocessor,
wherein the retention characteristic improvement block detects read voltage difference values respectively corresponding to a plurality of program states by comparing the reference read voltage and the optimum read voltage, and
wherein the retention characteristic improvement block determines the degradation characteristic to be a low temperature data retention degradation characteristic (LTDR degradation characteristic) when the read voltage difference value of at least one or more most significant program states having a high threshold voltage among the plurality of program states is greater than the read voltage difference values of the other program states.
7. The controller according to claim 6, wherein the controller is a microprocessor,
wherein the retention characteristic improvement block controls the memory device to perform the reprogramming operation on the memory cells when the degradation characteristic is the LTDR degradation characteristic; and is
Wherein the retention characteristic improvement block controls the memory device to perform the reclamation operation on the memory unit when the degradation characteristic is not the LTDR degradation characteristic.
8. The controller of claim 6, wherein the retention characteristic improvement block comprises:
a read voltage comparison block comparing the reference read voltage and the optimal read voltage and detecting the read voltage difference values respectively corresponding to the plurality of program states;
an LTDR determination block that determines whether a degradation characteristic of the memory cell is the LTDR degradation characteristic based on the read voltage difference values respectively corresponding to the plurality of program states;
an algorithm selection block that selects any one of a reprogramming algorithm and a recycling algorithm based on a result of determining the degradation characteristic of the memory cell by the LTDR determination block;
a reprogramming control block which controls the memory device to perform the reprogramming operation when the reprogramming algorithm is selected; and
a reclamation control block that controls the memory device to perform the reclamation operation when the reclamation algorithm is selected.
9. A memory system, comprising:
a memory device comprising a plurality of data programmed memory cells; and
a controller controlling the memory device to perform a read operation on the plurality of memory cells in response to a read command received from a host,
wherein, when a failure occurs during the read operation, the controller further determines a degradation characteristic of the plurality of memory cells and controls the memory device to perform a reprogramming operation or a recycling operation on the plurality of memory cells.
10. The memory system of claim 9, wherein the controller comprises:
a processor controlling the memory device to perform a first read operation using a reference read voltage and a read retry voltage during the read operation, and to set an optimal read voltage and perform a second read operation if the first read operation fails; and
an error correction circuit that performs an error correction operation on first read data read as a result of the first read operation and performs an error correction operation on second read data read as a result of the second read operation, and determines that the first read operation and the second read operation have failed based on a result of the error correction operation.
11. The memory system according to claim 10, wherein the memory unit is a single memory unit,
wherein the processor controls the memory device to perform an eBoost operation or a soft decode operation as the second read operation, and
wherein the eBoost operation or the soft decode operation comprises performing a plurality of read operations while changing a read voltage.
12. The memory system of claim 10, wherein the processor includes a retention characteristic improvement block that determines the degradation characteristic by comparing the reference read voltage with the optimal read voltage used during the second read operation if the second read operation fails, selects any one of the reprogramming operation and the reclaiming operation in response to the determined degradation characteristic, and controls the memory device.
13. The memory system according to claim 10, wherein when a result of a second error correction operation on the second read data read during the second read operation indicates that no erroneous bits are included or a minimum number of erroneous bits are included, the processor controls the memory device such that a read voltage is set to the optimum read voltage, and the second read operation is performed.
14. The memory system according to claim 10, wherein the memory unit is a single memory unit,
wherein the retention characteristic improvement block detects read voltage difference values respectively corresponding to a plurality of program states by comparing the reference read voltage and the optimum read voltage, and
wherein the retention characteristic improvement block determines the degradation characteristic to be a low temperature data retention degradation characteristic (LTDR degradation characteristic) when the read voltage difference value of at least one or more most significant program states having a high threshold voltage among the plurality of program states is greater than the read voltage difference values of the other program states.
15. The memory system according to claim 14, wherein the memory unit is a single memory unit,
wherein when the degradation characteristic is the LTDR degradation characteristic, the retention characteristic improvement block controls the memory device to perform the reprogramming operation on the memory cells, and
wherein the retention characteristic improvement block controls the memory device to perform the reclamation operation on the memory cells when the degradation characteristic is not the LTDR degradation characteristic.
16. A method of operating a memory system, comprising:
performing a first read operation on a memory cell included in the memory device using the reference read voltage and the read retry voltage;
performing a second read operation on the memory cell using an optimal read voltage when a result of the first read operation indicates that a failure has occurred;
determining a degradation characteristic of the memory cell by comparing the reference read voltage and the optimal read voltage; and is
Selecting and performing any one of a reprogramming operation and a recycling operation on the memory cell based on the determined degradation characteristic.
17. The method of claim 16, wherein the second read operation comprises an eBoost operation or a soft decoding operation.
18. The method of claim 16, wherein determining the degradation characteristic comprises:
comparing the reference read voltage with the optimal read voltage, and detecting read voltage differences corresponding to a plurality of program states, respectively; and is
Determining the degradation characteristic to be a low temperature data retention degradation characteristic, LTDR degradation characteristic, when the read voltage difference value of at least one or more most significant program states having a high threshold voltage among the plurality of program states is greater than the read voltage difference values of other program states.
19. The method of claim 18, wherein the first and second portions are selected from the group consisting of,
wherein when the degradation characteristic is the LTDR degradation characteristic, the reprogramming operation is performed using a first incremental step pulse programming scheme, i.e., a first ISPP scheme, which uses a first start program voltage and a first step voltage, and
wherein when the degradation characteristic is not the LTDR degradation characteristic, the reclamation operation is performed using a second ISPP scheme using a second start program voltage and a second step voltage.
20. The method of claim 19, wherein the first starting programming voltage is higher than the second starting programming voltage, and the first step voltage is lower than the second step voltage.
21. A method of operation of a controller that controls a memory device, the method of operation comprising:
controlling the memory device to perform a first read operation on a memory region using a reference read voltage;
controlling the memory device to perform a second read operation on the memory area with an optimal read voltage when the first read operation fails due to an error of data read from the memory area; and is
Controlling the memory device to perform a re-programming operation on the memory region when a difference between the reference read voltage and the optimal read voltage of a first program state is greater than a difference between the reference read voltage and the optimal read voltage of a second program state,
wherein the first programmed state is a higher effective programmed state than the second programmed state.
22. The method of operation of claim 21, further comprising: controlling the memory device to perform a read reclaim operation on the memory region when the difference in the first program state is not greater than the difference in the second program state.
Technical Field
Various embodiments of the present disclosure generally relate to an electronic device, and in particular, to a controller, a memory system including the controller, and a method of operating the memory system.
Background
More recently, computer environment paradigms have turned into pervasive computing to enable computer systems to be used anytime and anywhere. Therefore, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. In general, portable electronic devices use a memory system employing a memory device to store data, i.e., to serve as a data storage device. The memory device may be used as a primary memory device or a secondary memory device of the portable electronic device.
Since there is no mechanical driving part, the memory system using the memory device provides advantages in that stability and durability are excellent, information access speed is increased, and power consumption is reduced. Examples of the memory system having these advantages may include a Universal Serial Bus (USB) memory device, a memory card having various interfaces, a Solid State Drive (SSD), and the like.
Memory devices may be classified into volatile memory devices and non-volatile memory devices.
Although the nonvolatile memory device has relatively low read and write speeds, the nonvolatile memory device can maintain data stored therein even in the event of power interruption. Therefore, the nonvolatile memory device is used when it is necessary to store data that needs to be held regardless of whether the nonvolatile memory device is connected to a power supply. Representative examples of non-volatile memory devices may include read-only memory (ROM), mask ROM (mrom), programmable ROM (prom), erasable programmable ROM (eprom), electrically erasable programmable ROM (eeprom), flash memory, phase change random access memory (PRAM), magnetic ram (mram), resistive ram (rram), and ferroelectric ram (fram). Flash memories are classified into NOR type memories and NAND type memories.
Disclosure of Invention
Various embodiments of the present disclosure relate to a controller capable of determining a threshold voltage distribution characteristic of a memory cell and performing a retention characteristic improvement operation during a read operation. Various embodiments of the present disclosure also relate to a memory system including a controller and a method of operating the memory system.
Embodiments of the present disclosure may provide a controller, including: a processor configured to control a read operation of the memory device in response to a read command received from a host; and an error correction circuit configured to perform an error correction operation on read data received from the memory device during a read operation. The processor may determine a degradation characteristic of the memory device during a read operation, and control the memory device to select and perform any one of a reprogramming operation and a reclaiming operation on memory cells that have performed the read operation.
Another embodiment of the present disclosure may provide a memory system including: a memory device comprising a plurality of memory cells of programmed data; and a controller configured to control the memory device to perform a read operation on the plurality of memory cells in response to a read command received from the host. When a failure occurs during a read operation, the controller may determine degradation characteristics of the plurality of memory cells and control the memory device to perform a reprogramming operation or a recycling operation on the plurality of memory cells.
Yet another embodiment of the present disclosure may provide a method of operating a memory system, the method including: performing a first read operation on a memory cell included in the memory device using the reference read voltage and the read retry voltage; performing a second read operation on the memory cell using the optimal read voltage when the result of the first read operation indicates that a failure has occurred; determining a degradation characteristic of the memory cell by comparing the reference read voltage and the optimal read voltage; based on the determined degradation characteristic, any one of a reprogramming operation and a recycling operation is selected and performed on the memory cell.
Yet another embodiment of the present disclosure may provide a method of operating a memory system, the method including: controlling a memory device to perform a first read operation on a memory region using a reference read voltage; controlling the memory device to perform a second read operation on the memory area using the optimal read voltage when the first read operation fails due to an error of data read from the memory area; and controlling the memory device to perform a re-programming operation on the memory area when a difference between the reference read voltage and the optimum read voltage of the first program state is greater than a difference between the reference read voltage and the optimum read voltage of the second program state, wherein the first program state is a higher effective program state than the second program state.
These and other advantages and features of the present invention will be better understood by those of ordinary skill in the art from the following detailed description of specific embodiments in conjunction with the following drawings.
Drawings
Fig. 1 is a block diagram illustrating a memory system according to an embodiment of the present disclosure.
Fig. 2 is a block diagram illustrating a configuration of the controller of fig. 1 according to an embodiment of the present disclosure.
Fig. 3 is a block diagram illustrating a retention characteristic improvement block of the controller of fig. 2 according to an embodiment of the present disclosure.
Fig. 4 is a diagram depicting a semiconductor memory of the memory system of fig. 1, in accordance with an embodiment of the present disclosure.
Fig. 5 is a diagram illustrating a memory block of the semiconductor memory of fig. 4 according to an embodiment of the present disclosure.
Fig. 6 is a diagram illustrating a memory block of the semiconductor memory of fig. 4 having a three-dimensional structure according to an embodiment of the present disclosure.
Fig. 7 is a diagram illustrating a memory block of the semiconductor memory of fig. 4 having a three-dimensional structure according to an embodiment of the present disclosure.
FIG. 8 is a flow chart of the operation of a memory system according to an embodiment of the present disclosure.
Fig. 9 is a threshold voltage distribution diagram depicting reference read voltages and eBoost read voltages during a read operation, according to an embodiment of the present disclosure.
Fig. 10 is a diagram illustrating a memory system according to another embodiment of the present disclosure.
11-13 are block diagrams illustrating various memory systems according to embodiments of the present disclosure.
Detailed Description
It is noted that specific structural and functional descriptions in the embodiments of the present disclosure introduced in the specification or application are only for describing the embodiments of the present disclosure. Furthermore, the description should not be construed as limited to the embodiments described in this specification or application.
The present disclosure will now be described in detail based on specific embodiments with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein but should be construed to cover modifications, equivalents, or alternatives falling within the spirit and scope of the inventive concept and technology disclosed herein.
It will be further understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Similarly, a second element may also be referred to as a first element.
It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, there are no intervening elements present. Other expressions describing the relationship between elements, such as "between … …", "directly between", "adjacent to", or "directly adjacent to".
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. In this disclosure, the singular form is also intended to include the plural form unless the context clearly dictates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," and the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations thereof.
Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs in view of this disclosure. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
A detailed description of functions and configurations well known to those skilled in the art will be omitted so as not to obscure the subject matter of the present disclosure. This is intended to omit unnecessary description in order to make the subject matter of the present disclosure clear.
Various embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the disclosure are shown, so that those skilled in the art can implement the technical idea of the invention without undue experimentation.
Fig. 1 is a block diagram illustrating a memory system 1000 according to an embodiment of the present disclosure.
Referring to fig. 1, a memory system 1000 may include a
In fig. 1, a plurality of banks of the
Each of the plurality of groups of semiconductor memories 100 may communicate with the
The
The
The host 1300 may include a portable electronic device such as a computer, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), an MP3 player, a camera, a camcorder, or a mobile phone. The Host 1300 may request a write operation, a read operation, an erase operation, etc. to the memory system 1000 using a Host command Host _ CMD. To perform a write operation of the
The
The
In an embodiment, the memory system 1000 may be provided as one of various elements of an electronic device such as: a computer, an ultra mobile pc (umpc), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an electronic book, a Portable Multimedia Player (PMP), a game machine, a navigation device, a black box, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting/receiving information in a wireless environment, one of various devices for forming a home network, one of various electronic devices for forming a computer network, one of various electronic devices for forming a telematics network, an RFID device, one of various elements for forming a computing system, and the like.
In an embodiment,
Fig. 2 is a diagram illustrating a configuration of the
Referring to FIG. 2,
The
The
The
The
During read operations,
In the case where an eBoost operation or a soft decoding operation is performed because a failure occurs during a read operation, the retention
The
Note that although
Fig. 3 is a block diagram illustrating a configuration of the retention
Referring to fig. 3, the retention
The read voltage comparison block 1222A may compare an optimal read voltage set during an eBoost operation or a soft decoding operation with a reference read voltage for identifying or detecting a plurality of program states. In an embodiment, the reference read voltage may be a read voltage for identifying or detecting each desired program state. For example, the reference read voltage may be an initial set read voltage of the memory device. The optimal read voltage may be a read voltage of a read operation that generates no erroneous bits or only a minimum of erroneous bits during an eBoost operation or a soft decoding operation.
The read voltage comparison block 1222A may detect a read voltage difference value corresponding to each program state by comparing a reference read voltage of each program state with an optimal read voltage.
Based on the read voltage difference values corresponding to the respective program states detected by the read voltage comparison block 1222A, the LTDR determination block 1222B may determine whether a degradation phenomenon due to LTDR has occurred on the memory cells of the memory device on which the read operation has been performed. The degradation phenomenon caused by LTDR refers to a phenomenon in which the threshold voltage distribution of memory cells is reduced due to a charge sharing phenomenon between memory cells at room temperature. In particular, the degradation phenomenon may be exacerbated in a program state having a high threshold voltage distribution. Accordingly, LTDR determination block 1222B may determine that a degradation phenomenon due to LTDR has occurred on memory cells having performed a read operation when a read voltage difference value of at least one or more most significant program states having a relatively high threshold voltage among a plurality of program states is greater than read voltage difference values of other program states.
Based on the result of determining the degradation characteristic of the memory cell by LTDR determination block 1222B, algorithm selection block 1222C may select any of a variety of algorithms to improve retention characteristics. For example, when the LTDR determination block 1222B determines that a degradation phenomenon due to LTDR has occurred on the memory cell, the algorithm selection block 1222C may select a reprogramming algorithm of a plurality of algorithms. When the LTDR determination block 1222B determines that a degradation phenomenon due to a cause other than LTDR has occurred on the memory unit, the algorithm selection block 1222C may select a reclamation algorithm among the plurality of algorithms.
When the algorithm selection block 1222C selects a reprogramming algorithm, the reprogramming control block 1222D may control the
When the algorithm selection block 1222C selects a reclamation algorithm, the reclamation control block 1222E may control the
Fig. 4 is a diagram of a configuration of the semiconductor memory 100 of fig. 1 according to an embodiment.
Referring to fig. 4, the semiconductor memory 100 may include a memory cell array 10 configured to store data. The semiconductor memory 100 may include a peripheral circuit 200, the peripheral circuit 200 being configured to perform a program operation for storing data in the memory cell array 10, a read operation for outputting the stored data, and an erase operation for erasing the stored data. The semiconductor memory 100 may include a control logic 300 configured to control the peripheral circuit 200 under the control of a controller (1200 of fig. 1).
Memory cell array 10 may include a plurality of memory blocks MB1 through MBk, represented generally by the numeral 11, where k is a positive integer. Local lines LL and bit lines BL1 through BLm (where m is a positive integer) may be coupled to each
At least one
Under the control of the control logic 300, the peripheral circuit 200 may perform a program operation, a read operation, or an erase operation on the selected
The voltage generation circuit 210 may generate various operation voltages Vop to be used for a program operation, a read operation, and an erase operation in response to the operation signal OP _ CMD. In addition, the voltage generation circuit 210 may selectively discharge the local line LL in response to the operation signal OP _ CMD. For example, under the control of control logic 300, voltage generation circuit 210 may generate a program voltage, a verify voltage, a pass voltage, and a select transistor operating voltage.
The row decoder 220 may transfer the operation voltage Vop to the local line LL coupled to a selected memory block among the memory blocks 11 in response to the control signal AD _ signals. For example, the row decoder 220 may selectively apply the operating voltages (e.g., the program voltage, the verify voltage, and the pass voltage) generated from the voltage generation circuit 210 to the word line among the local lines LL in response to the row decoder control signal AD _ signals.
During the program voltage applying operation, the row decoder 220 may apply the program voltage generated by the voltage generating circuit 210 to a selected word line of the local line LL and apply the pass voltage generated by the voltage generating circuit 210 to other unselected word lines in response to the control signal AD _ signals. During a read operation, the row decoder 220 may apply a read voltage generated by the voltage generation circuit 210 to a selected word line of the local line LL and apply a pass voltage generated by the voltage generation circuit 210 to other unselected word lines in response to the control signal AD _ signals.
The page buffer bank 230 may include a plurality of page buffers PB1 through PBm, generally indicated by the numeral 231, coupled to bit lines BL1 through BLm, a plurality of page buffers PB1 through PBm. The page buffer 231 may operate in response to the page buffer control signals PBSIGNALS. For example, the page buffer 231 may temporarily store data to be programmed during a program operation, or sense a voltage or current of the bit lines BL1 to BLm during a read or verify operation.
The column decoder 240 may transfer data between the input/output circuit 250 and the page buffer group 230 in response to a column address CADD. For example, the column decoder 240 may exchange data with the page buffer 231 through the data lines DL or with the input/output circuit 250 through the column lines CL.
The input/output circuit 250 may transfer an internal command CMD or an address ADD received from the controller (1200 of fig. 1) to the control logic 300 or exchange data with the column decoder 240.
During a read operation, the PASS/FAIL check circuit 260 may generate a reference current in response to the enable BIT VRY _ BIT < # >, and may compare the sensing voltage VPB received from the page buffer group 230 with a reference voltage generated by the reference current and output a PASS signal PASS or a FAIL signal FAIL.
The source line driver 270 may be coupled to the memory cells included in the memory cell array 10 through the source lines SL, and may control voltages to be applied to the source lines SL. The source line driver 270 may receive a source line control signal CTRL _ SL from the control logic 300 and control a source line voltage to be applied to the source line SL based on the source line control signal CTRL _ SL.
The control logic 300 may control the peripheral circuit 200 by outputting an operation signal OP _ CMD, a control signal AD _ signals, a page buffer control signal PBSIGNALS, and an enable BIT VRY _ BIT < # > in response to the internal command CMD and the address ADD. In addition, in response to PASS signal PASS or FAIL signal FAIL, control logic 300 may determine whether the target memory cell has passed verification during a verification operation.
Fig. 5 is a diagram illustrating a configuration of the memory block MB1 of fig. 4 according to an embodiment. Note that each
Referring to fig. 5, in memory block MBl, a plurality of word lines arranged in parallel with each other may be coupled between a first select line and a second select line. For example, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. In more detail, the memory block MB1 may include a plurality of strings ST coupled between the bit lines BL1 to BLm and the source lines SL. The bit lines BL1 to BLm may be respectively coupled to the strings ST, and the source lines SL may be commonly coupled to the strings ST. The strings ST may have the same configuration; therefore, the string ST coupled to the first bit line BL1 will be described in detail by way of example.
The string ST may include a source select transistor SST, a plurality of memory cells F1 through F16, and a drain select transistor DST, which are coupled in series with each other between a source line SL and a first bit line BL. At least one source select transistor SST and at least one drain select transistor DST may be included in each string ST, and a greater number of memory cells than the number of memory cells F1 through F16 shown in the drawings may be included in each string ST.
A source of the source select transistor SST may be coupled to a source line SL, and a drain of the drain select transistor DST may be coupled to a first bit line BLl. The memory cells F1 through F16 may be coupled in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST may be coupled to a source select line SSL, the gates of the drain select transistors DST may be coupled to a drain select line DSL, and the gates of the memory cells F1 to F16 may be coupled to a plurality of word lines WL1 to WL 16. Among the memory cells included in the different strings ST, a group of memory cells coupled to each word line may be referred to as a physical page PPG. Accordingly, the number of physical pages PPG included in the memory block MB1 may correspond to the number of word lines WL1 to WL 16.
Each memory cell may store 1 bit of data. The memory cell is commonly referred to as a single-level cell (SLC). In this case, each physical page PPG may store data of a single logical page LPG. The data of each logical page LPG may comprise data bits corresponding to the number of cells comprised in a single physical page PPG. Each memory cell may store 2 or more bits of data. The memory cell is commonly referred to as a multi-level cell (MLC). In this case, each physical page PPG may store data of two or more logical pages LPG.
Fig. 6 is a diagram illustrating an example of a memory block MB1 having a three-dimensional structure according to an embodiment of the present disclosure.
Referring to fig. 6, the memory cell array 10 may include a plurality of memory blocks 11, the plurality of memory blocks 11 including memory blocks MB1 through MBk. Each
Each of the plurality of strings ST11 to ST1m and ST21 to ST2m may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.
The source selection transistor SST, the drain selection transistor DST, and the memory cells MC1 through MCn may have structures similar to each other. For example, each of the source selection transistor SST, the drain selection transistor DST, and the memory cells MC1 through MCn may include a channel layer, a tunnel insulation layer, a charge extraction layer, and a blocking insulation layer. For example, a pillar (pilar) for providing a channel layer may be provided in each string. For example, pillars for providing at least one of a channel layer, a tunnel insulating layer, a charge extraction layer, and a blocking insulating layer may be provided in each string.
The source select transistor SST of each string may be coupled between a source line SL and the memory cells MC1 through MCn.
In an embodiment, the source select transistors of the strings arranged in the same row may be coupled to a source select line extending in the row direction. The source select transistors of the strings arranged in different rows may be coupled to different source select lines. In fig. 6, the source select transistors of the strings ST 11-ST 1m in the first row may be coupled to a first source
In an embodiment, the source select transistors of strings ST 11-ST 1m and ST 21-ST 2m may be commonly coupled to a single source select line.
The first to nth memory cells MC1 to MCn in each string may be coupled between the source selection transistor SST and the drain selection transistor DST.
The first to nth memory cells MC1 to MCn may be divided into first to pth memory cells MC1 to MCp and p +1 to nth memory cells MCp +1 to MCn. The first to pth memory cells MC1 to MCp may be sequentially arranged in a vertical direction (i.e., in the Z direction), and coupled in series to each other between the source select transistor SST and the tunnel transistor PT. The p +1 th to nth memory cells MCp +1 to MCn may be sequentially arranged in a vertical direction (Z direction), and are coupled in series with each other between the pipe transistor PT and the drain select transistor DST. The first to pth memory cells MC1 to MCp and the p +1 to nth memory cells MCp +1 to MCn may be coupled to each other through a pipe transistor PT. The gates of the first to nth memory cells MC1 to MCn of each string may be coupled to the first to nth word lines WL1 to WLn, respectively.
In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. In the case where the dummy memory cell is disposed, the voltage or current of the corresponding string may be stably controlled. The gates of the pipe transistors PT of the respective strings may be coupled to the line PL.
The drain select transistor DST of each string may be coupled between a corresponding bit line and the memory cells MCp +1 to MCn. The strings arranged in the row direction may be coupled to respective drain select lines extending in the row direction. The drain select transistors of the strings ST 11-ST 1m in the first row may be coupled to a first drain
Strings arranged in a column direction may be coupled to respective bit lines extending in the column direction. In fig. 6, the strings ST11 and ST21 in the first column may be coupled to a first
Among the strings arranged in the row direction, memory cells coupled to the same word line may form one page. For example, the memory cells coupled to the first word line WL1 in the strings ST 11-ST 1m of the first row may form a single page. The memory cells in the strings ST 21-ST 2m of the second row that are coupled to the first word line WL1 may form another single page. When any one of the drain select lines DSL1 and DSL2 is selected, strings arranged in the corresponding row may be selected. When any one of the word lines WL1 to WLn is selected, a corresponding single page may be selected from the selected string.
Fig. 7 is a diagram illustrating an example of a memory block MB1 having a three-dimensional structure according to an embodiment of the present disclosure.
Referring to fig. 7, memory cell array 10 may include a plurality of memory blocks MB1 through MBk, generally indicated by the numeral 11. Each
Each of the strings ST11 'to ST1m' and ST21 'to ST2m' may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.
The source select transistor SST of each string may be coupled between a source line SL and the memory cells MC1 through MCn. The source select transistors of strings arranged in the same row may be coupled to the same source select line. The source select transistors of the strings ST11 'to ST1m' arranged in the first row may be coupled to a first source
The first to nth memory cells MC1 to MCn in each string may be coupled in series between the source selection transistor SST and the drain selection transistor DST. The gates of the first to nth memory cells MC1 to MCn may be coupled to the first to nth word lines WL1 to WLn, respectively.
In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. In the case where the dummy memory cell is disposed, the voltage or current of the corresponding string may be stably controlled. Thus, the reliability of the data stored in each
The drain select transistor DST of each string may be coupled between a respective bit line and the memory cells MC1 through MCn. The drain select transistors DST of the strings arranged in the row direction may be coupled to respective drain select lines extending in the row direction. The drain select transistors DST of the strings ST11 'to ST1m' in the first row may be coupled to a first drain
FIG. 8 is a flow chart of the operation of a memory system according to an embodiment of the present disclosure.
Fig. 9 is a threshold voltage distribution diagram for describing a reference read voltage and an eBoost read voltage during a read operation according to an embodiment of the present disclosure. FIG. 9 illustrates threshold voltage distributions of Triple Layer Cells (TLC) having seven programmed states P1-P7 and an erased state E. As illustrated in fig. 9, the program state P6 or P7 may be a higher effective program state than any of the remaining program states P1 through P5. The more efficient programming states P6 and P7 may have higher threshold voltage distributions than the less efficient programming states P1 through P5. The dotted lines shown in fig. 9 may represent the degraded threshold voltage distributions of the respective program states P1 through P7. As described above and illustrated in fig. 9, degradation may be exacerbated in the higher effective programmed states (e.g., programmed states P6 and P7) having higher threshold voltage distributions.
The operation of the memory system according to an embodiment of the present disclosure will be described with reference to fig. 1 to 9.
In step S810, when a Host command Host _ CMD, i.e., a read command, is received from the Host 1300, the
Then, the
In step S820, the
In step S830, the
If the result of the above-described determination operation (S830) indicates that the error correction operation has Passed (PASS), the read data transferred and stored in the
If the result of the above operation S830 indicates that the error correction operation has Failed (FAIL), the
If the result of step S850 indicates that the number of times the read operation has failed is less than the preset value a (NO), one of the plurality of read voltage sets included in the read retry table is selected and the read voltages respectively corresponding to the plurality of program states P1 through P7 are changed in step S860.
Thereafter, the process may be repeated from step S820 using the read voltage changed according to the read retry table.
If the result of step S850 indicates that the number of times the read operation has failed is equal to or greater than the preset value a (yes), the
The eBoost operation may determine (e.g., find) an optimal read voltage that minimizes the number of erroneous bits. The eBoost operation may set an optimal read voltage to an eBoost read voltage (e.g., R1_1 to R7_1 of fig. 9), and then perform a read operation using the eBoost read voltages R1_1 to
The
If the result of the determination operation (S880) indicates that the error correction operation has Passed (PASS), the read voltage comparison block 1222A of the retention
Based on the read voltage difference values corresponding to the respective program states detected by the read voltage comparison block 1222A, the LTDR determination block 1222B may determine whether a degradation phenomenon due to LTDR has occurred on the memory cells of the memory device on which the read operation has been performed. In other words, LTDR determination block 1222B may determine that a degradation phenomenon due to LTDR has occurred on memory cells having performed a read operation when a read voltage difference value of at least one or more most significant program states (e.g., program states P6 and P7) having relatively higher threshold voltages among the plurality of program states is greater than that of the other program states. Although the two program states P6 and P7 are defined as the most effective program states in the present embodiment, the present disclosure is not limited thereto, and at least one or more program states having the highest threshold voltage among the plurality of program states may be defined as the most effective program states.
In step S900, the algorithm selection block 1222C may determine whether to perform a reprogramming operation based on the result of determining the degradation characteristic of the memory cell through the LTDR determination block 1222B.
If the result of the above-described determination operation (S900) indicates that the reprogramming operation is not to be performed (no), the read data transferred and stored in the
If the result of the above determination operation (S900) indicates that a reprogramming operation is to be performed (yes), the reprogramming control block 1222D controls the
After the reprogramming operation has been performed on the memory cells on which the read operation has been performed, the read data transferred and stored in the
If the result of the determination operation (S880) indicates that the error correction operation has Failed (FAIL), the
In an embodiment, the soft decoding operation may be a decoding operation using soft decision data read with a soft decoding read voltage. The soft decoding read voltages may include the above-described eBoost read voltages R1_1 through
In step S930, if the result of the soft decoding operation indicates that the number of error bits included in the soft decision data is equal to or less than the maximum allowable number of error bits of the
When the result of the determination operation (S930) indicates that the error correction operation has Passed (PASS), the read voltage comparison block 1222A of the retention
Based on the read voltage difference values corresponding to the respective program states detected by the read voltage comparison block 1222A, the LTDR determination block 1222B may determine whether a degradation phenomenon due to LTDR has occurred on the memory cells of the memory device on which the read operation has been performed. In other words, LTDR determination block 1222B may determine that a degradation phenomenon due to LTDR has occurred on memory cells having performed a read operation when a read voltage difference value of at least one or more most significant program states (e.g., program states P6 and P7) having a relatively high threshold voltage among the plurality of program states is greater than that of the other program states.
In step S950, the algorithm selection block 1222C determines whether to perform a reprogramming operation or a recycling operation based on the result of the degradation characteristic of the memory cell determined by the LTDR determination block 1222B. For example, the algorithm selection block 1222C may select a reprogramming algorithm when the LTDR determination block 1222B determines that a degradation phenomenon due to LTDR has occurred on the memory cell. The algorithm selection block 1222C may select a reclamation algorithm when the LTDR determination block 1222B determines that a degradation phenomenon has occurred on the memory unit due to a reason other than LTDR.
When the RE-programming algorithm (RE-PROGRAM) has been selected in step S950, the reprogramming control block 1222D controls the
When the reclamation algorithm (recycling) has been selected in step S950, the reclamation control block 1222E controls the
After step 960 or step S970, the read data transferred and stored in the
As described above, in various embodiments of the present disclosure, during an eBoost operation and a soft decoding operation, it is determined whether a degradation phenomenon of a memory cell having performed a read operation is a degradation phenomenon due to LTDR. If it is determined that the degradation phenomenon is due to LTDR, a reprogramming operation is performed. If it is determined that the deterioration phenomenon is caused by a cause other than LTDR, a recovery operation is performed. Accordingly, the threshold voltage distribution of the memory cell in which the degradation phenomenon due to LTDR has occurred is restored to the normal range, so that the data retention characteristic of the memory system may be improved. Further, when the degradation phenomenon is due to LTDR, instead of the reclamation operation, a reprogramming operation having a relatively short program time and requiring no map data update operation is performed. Accordingly, the operating speed and current consumption of the memory system can be improved.
Fig. 10 is a diagram illustrating a
Referring to fig. 10, the
Data programmed to
The
In one embodiment, the
Fig. 11 is a diagram illustrating a
Referring to fig. 11, the
The
The
The
Fig. 12 is a diagram illustrating a
Referring to fig. 12, the
The
The
In an embodiment, the
Fig. 13 is a diagram illustrating a memory system 70000 according to an embodiment of the present disclosure.
Referring to fig. 13, the memory system 70000 may be implemented in a memory card or a smart card. The memory system 70000 may include a
The
The card interface 7100 can interface data exchange between the host 60000 and the
When the memory system 70000 is connected to a host interface 6200 of a host 60000 such as a PC, a tablet computer, a digital camera, a digital audio player, a cellular phone, console video game hardware, or a digital set-top box, the host interface 6200 can perform data communication with the
In various embodiments of the present disclosure, during a read operation of a memory system, a degradation characteristic is determined according to a threshold voltage distribution of memory cells. A reprogramming operation or a recycling operation is performed based on the degradation characteristic, so that the retention characteristic of the memory cell can be improved.
Although embodiments of the present disclosure have been disclosed, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure.
The scope of the disclosure, therefore, is not to be restricted except in light of the foregoing description, by the appended claims and their equivalents.
In the embodiments discussed above, all steps may be selectively performed or skipped. In addition, the steps in each embodiment may not always be performed in a fixed order. Furthermore, the embodiments disclosed in the specification and the drawings are intended to help those of ordinary skill in the art clearly understand the present disclosure, and are not intended to limit the scope of the present disclosure. In other words, those having ordinary skill in the art to which the present disclosure pertains will readily appreciate that various modifications are possible based on the technical scope of the present disclosure.
The embodiments of the present disclosure have been described with reference to the accompanying drawings, and specific terms or words used in the description should be construed according to the spirit of the present disclosure without limiting the subject matter thereof. It should be understood that many variations and modifications of the basic inventive concepts described herein will still fall within the spirit and scope of the present disclosure, as defined by the appended claims and their equivalents.
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