阅读说明：本技术 一种三维沟槽型铁电存储器及其制备方法 (Three-dimensional groove type ferroelectric memory and preparation method thereof ) 是由 曾斌建 周益春 廖敏 于 2020-06-30 设计创作，主要内容包括：一种三维沟槽型铁电存储器及其制备方法,包括基底(1)和设置在基底(1)上的导电层(2)；导电层(2)上设置的层叠结构包括多层水平且交叠排布的隔离层(3)和控制栅电极(4)；多个沟槽型存储单元串(5)竖直贯穿层叠结构,其包括：竖直贯穿层叠结构且槽底嵌入导电层(2)中的沟槽孔(11)；沟槽孔(11)的侧壁和槽底依次铺设有缓冲层(6)、铁电薄膜层(7)、沟道层(8)和填充层(9)；控制栅电极(4)、缓冲层(6)、铁电薄膜层(7)、沟道层(8)组成多个相互串联的铁电场效应晶体管。本发明的铁电存储器能获得更为紧凑的布线,有利于实现更高密度集成；制备时依次沉积所需材料即可,无需刻蚀,保证铁电存储器的可靠性。(A three-dimensional groove type ferroelectric memory and a preparation method thereof, comprising a substrate (1) and a conducting layer (2) arranged on the substrate (1); the laminated structure arranged on the conductive layer (2) comprises a plurality of layers of isolation layers (3) and control gate electrodes (4) which are horizontally arranged in an overlapped mode; a plurality of trench-type memory cell strings (5) vertically penetrate a stacked structure, comprising: a groove hole (11) vertically penetrating through the laminated structure and embedding the bottom of the groove into the conductive layer (2); a buffer layer (6), a ferroelectric thin film layer (7), a channel layer (8) and a filling layer (9) are sequentially laid on the side wall and the bottom of the groove hole (11); the control gate electrode (4), the buffer layer (6), the ferroelectric thin film layer (7) and the channel layer (8) form a plurality of ferroelectric field effect transistors which are mutually connected in series. The ferroelectric memory can obtain more compact wiring, and is beneficial to realizing higher-density integration; the required materials are deposited in sequence during preparation, etching is not needed, and the reliability of the ferroelectric memory is guaranteed.)

1. A three-dimensional trench ferroelectric memory, comprising:

a substrate (1); and

a conductive layer (2) disposed on the substrate (1);

a laminated structure is arranged on the conducting layer (2), the laminated structure comprises a plurality of layers of isolating layers (3) and control gate electrodes (4) which are horizontally arranged, and the control gate electrodes (4) are arranged between every two adjacent isolating layers (3);

a plurality of groove-type memory cell strings (5) vertically penetrate through the laminated structure, and the bottoms of the groove-type memory cell strings (5) are embedded in the conductive layer (2);

the trench-type memory cell string (5) includes: a trench hole (10) vertically penetrating through the laminated structure, wherein the bottom of the trench hole (10) is embedded in the conductive layer (2);

a buffer layer (6), a ferroelectric thin film layer (7), a channel layer (8) and a filling layer (9) are sequentially laid on the side wall and the bottom of the groove hole (10);

the control gate electrode (4), the buffer layer (6), the ferroelectric thin film layer (7) and the channel layer (8) jointly form a plurality of ferroelectric field effect transistors which are mutually connected in series.

2. The three-dimensional trench ferroelectric memory according to claim 1,

the lengths of the buffer layer (6), the ferroelectric thin film layer (7) and the channel layer (8) are less than or equal to the lengths of the side wall and the bottom of the groove.

3. The three-dimensional trench ferroelectric memory according to claim 1,

the cross section of each groove hole (10) is rectangular, trapezoidal or V-shaped.

4. The three-dimensional trench ferroelectric memory according to claim 1,

the substrate (1) is a semiconductor substrate and comprises silicon (Si), germanium (Ge), silicon germanium (SiGe) and gallium arsenide (GaAs);

the conducting layer (2) is a metal electrode or a heavily doped semiconductor material.

5. The three-dimensional trench ferroelectric memory according to claim 1,

the buffer layer (6) is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) One or more of (a).

6. The three-dimensional trench ferroelectric memory according to claim 1,

the ferroelectric film layer (7) is hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Zirconium oxide (ZrO) doped with other elements₂) Or hafnium oxide (HfO) doped with other elements₂)；

The doping element comprises one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge) and nitrogen (N).

7. The three-dimensional trench ferroelectric memory according to claim 1,

the channel layer (8) is made of oxide semiconductor material with high carrier mobility, such as indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium tin zinc oxide (InSnZnO), zinc tin oxide (ZnSnO), zinc aluminum tin oxide (ZnAlSnO), silicon zinc tin oxide (SiZnSnO), indium aluminum zinc oxide (InAlZnO), indium zirconium zinc oxide (InZrZnO), indium hafnium zinc oxide (InHfZnO), zinc oxide (ZnO) or gallium oxide (Ga)₂O₃) One kind of (1).

8. The three-dimensional trench ferroelectric memory according to claim 1,

the filling layer (9) is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Or silicon oxynitride (SiON).

9. The three-dimensional trench ferroelectric memory according to claim 1,

the isolating layer (3) is silicon oxide (SiO)₂) Or a dielectric constant less than that of silicon oxide (SiO)₂) The insulating material of (a);

the control gate electrode (4) is a heavily doped polysilicon, nitride metal electrode or tungsten (W).

10. A preparation method of a three-dimensional groove type ferroelectric memory is characterized by comprising the following steps:

arranging a conductive layer (2) on a substrate (1);

sequentially overlapping and depositing a preset number of layers of isolating layers (3) and control gate electrodes (4) on the conducting layers (2);

forming a plurality of trench holes (10) penetrating through the isolation layer (3) and the control gate electrode (4), and embedding the bottom of each trench hole (10) in the conductive layer (2);

sequentially laying a buffer layer (6), a ferroelectric thin film layer (7) and a channel layer (8) on the side wall and the bottom of each groove hole (10);

depositing a filling layer (9) on the inner wall of the channel layer (8) to fill the groove hole (10) to complete the preparation of the three-dimensional groove type ferroelectric memory;

the control gate electrode (4), the buffer layer (6), the ferroelectric thin film layer (7) and the channel layer (8) jointly form a plurality of ferroelectric field effect transistors which are mutually connected in series.

Technical Field

The invention relates to the technical field of memories, in particular to a three-dimensional groove type ferroelectric memory and a preparation method thereof.

Background

A ferroelectric field effect transistor (FeFET) as a transistor type ferroelectric memory is characterized in that a ferroelectric thin film material is used for replacing a gate dielectric layer in a field effect transistor (MOSFET), and the conduction and the cut-off of channel current are controlled by changing the polarization direction of the ferroelectric thin film material, so that the information storage is realized. The FeFET memory has the advantages of nonvolatility, low power consumption, high read-write speed and the like, and the unit structure is simple and the theoretical storage density is high. Thus, FeFET memory is considered one of the most promising new types of memory.

However, the practical storage density of FeFET memories has been greatly different from the theoretical value for a long time, which also limits the development of FeFET memories. Three-dimensional integration technology is an important approach for realizing high-density FeFET memories. However, a three-dimensional integration technology capable of simultaneously ensuring high-density integration, low-cost manufacturing and high reliability is yet to be broken through.

Disclosure of Invention

Objects of the invention

The invention aims to provide a three-dimensional groove type ferroelectric memory and a preparation method thereof, so as to further improve the storage density and reliability of the ferroelectric memory and reduce the production cost.

(II) technical scheme

To solve the above problems, according to an aspect of the present invention, there is provided a three-dimensional trench type ferroelectric memory comprising: a substrate; and a conductive layer disposed on the substrate; a laminated structure is arranged on the conducting layer, the laminated structure comprises a plurality of layers of horizontally arranged isolation layers and control gate electrodes, and a control gate electrode is arranged between every two adjacent isolation layers; the groove-type storage cell strings vertically penetrate through the laminated structure, and the bottoms of the groove-type storage cell strings are embedded into the conductive layer; the trench type memory cell string includes: the groove hole vertically penetrates through the laminated structure, and the bottom of the groove hole is embedded into the conductive layer; a buffer layer, a ferroelectric thin film layer, a channel layer and a filling layer are sequentially paved on the side wall and the bottom of the groove hole; the control gate electrode, the buffer layer, the ferroelectric thin film layer and the channel layer jointly form a plurality of ferroelectric field effect transistors which are mutually connected in series.

Further, the lengths of the buffer layer, the ferroelectric thin film layer and the channel layer are less than or equal to the lengths of the side walls and the bottom of the groove.

Further, the cross section of each trench hole is rectangular, trapezoidal or V-shaped.

Further, the base is a semiconductor substrate comprising silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs); the conductive layer is a metal electrode or a heavily doped semiconductor material.

Further, the buffer layer is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) One or more of (a).

Further, the ferroelectric thin film layer is hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Zirconium oxide (ZrO) doped with other elements₂) Or hafnium oxide (HfO) doped with other elements₂) (ii) a The doping element comprises one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge) and nitrogen (N).

Further, the channel layer is an oxide semiconductor material having high carrier mobility, and is indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium tin zinc oxide (insznzno), zinc tin oxide (ZnSnO), zinc aluminum tin oxide (ZnAlSnO), silicon zinc tin oxide (SiZnSnO), indium aluminum zinc oxide (InAlZnO), indium zirconium zinc oxide (inzrnzno), indium hafnium zinc oxide (InHfZnO), zinc oxide (ZnO), or gallium oxide (Ga)₂O₃) One kind of (1).

Further, the filling layer is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Or silicon oxynitride (SiON).

Further, the isolation layer is silicon oxide (SiO)₂) Or a dielectric constant less than that of silicon oxide (SiO)₂) Insulating material ofFeeding; the control gate electrode is a heavily doped polysilicon, nitride metal electrode, or tungsten (W).

According to another aspect of the present invention, there is provided a method for manufacturing a three-dimensional trench ferroelectric memory, comprising:

arranging a conductive layer on a substrate; sequentially overlapping and depositing a preset number of isolation layers and control gate electrodes on the conductive layer; forming a plurality of trench holes penetrating through the isolation layer and the control gate electrode, wherein the bottom of each trench hole is embedded in the conductive layer; sequentially laying a buffer layer, a ferroelectric thin film layer and a channel layer on the side wall and the bottom of each groove hole; depositing a filling layer on the inner wall of the channel layer to fill the groove hole, and completing the preparation of the three-dimensional groove type ferroelectric memory; the control gate electrode, the buffer layer, the ferroelectric thin film layer and the channel layer jointly form a plurality of ferroelectric field effect transistors which are mutually connected in series.

(III) advantageous effects

The technical scheme of the invention has the following beneficial technical effects:

according to the groove type memory cell string, the memory cells can be formed on two sides of the groove, so that more memory cells can be obtained; and when the selection transistors are arranged at the two ends of the groove, more compact wiring can be obtained, and higher-density integration is facilitated.

Meanwhile, the buffer layers sequentially arranged in the groove type memory cell string can be used as a seed layer or a stress control layer for the growth of the ferroelectric thin film layer, so that the generation of ferroelectric phases in the ferroelectric thin film layer is facilitated, and the performance of the ferroelectric thin film layer can be improved; the problems of element diffusion and interface reaction caused by direct contact between the ferroelectric film layer and the control gate electrode can be avoided, and the performance degradation of the ferroelectric film layer is prevented. In addition, the oxide semiconductor material with high carrier mobility is selected as the channel layer, so that higher reading current and reading speed can be obtained, and smaller working voltage can be realized because an interface layer is almost not arranged between the ferroelectric thin film layer and the oxide semiconductor channel layer.

The preparation method provided by the invention avoids the etching of the ferroelectric film layer, and further increases the reliability of the ferroelectric memory.

Drawings

Fig. 1 is a schematic perspective view of a three-dimensional trench ferroelectric memory according to the present invention;

fig. 2 is a top view of a trench type memory cell string in a three-dimensional trench type ferroelectric memory provided by the present invention;

FIG. 3 is a schematic cross-sectional view of a three-dimensional trench ferroelectric memory according to the present invention;

FIG. 4 is a schematic structural diagram of a first step in a method for manufacturing a three-dimensional trench ferroelectric memory according to the present invention;

FIG. 5 is a schematic structural diagram of step two in the method for manufacturing a three-dimensional trench ferroelectric memory according to the present invention;

fig. 6 is a schematic structural diagram of step three in the method for manufacturing a three-dimensional trench ferroelectric memory according to the present invention;

fig. 7 is a schematic structural diagram of step four in the method for manufacturing a three-dimensional trench ferroelectric memory according to the present invention.

Reference numerals:

1-a substrate; 2-a conductive layer; 3(3a-3g) -spacer layer; 4(4a-4f) -control gate electrode; 5-trench type memory cell strings; 6-a buffer layer; 7-a ferroelectric thin film layer; 8-a channel layer; 9-a filling layer; 10-trench hole.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.

The present invention will be described in detail below with reference to the accompanying drawings and examples.

Fig. 1 is a schematic perspective view of a three-dimensional trench ferroelectric memory according to the present invention, fig. 2 is a top view of a trench memory cell string in the three-dimensional trench ferroelectric memory according to the present invention, and fig. 3 is a schematic cross-sectional view of the three-dimensional trench ferroelectric memory according to the present invention, please see fig. 1 and fig. 3.

The invention provides a three-dimensional groove type ferroelectric memory, comprising: a substrate 1, a conductive layer 2 disposed on the substrate 1; the conducting layer 2 is provided with laminated structure above, and laminated structure includes isolation layer 3 and control gate electrode 4 that the multilayer level was arranged, and isolation layer 3 and control gate electrode 4 overlap each other and arrange, all is equipped with control gate electrode 4 between two adjacent isolation layers 3 promptly, all is equipped with isolation layer 3 between two adjacent control gate electrode 4.

Wherein, isolation layer 3 is used for insulating, sets up isolation layer 3 at 2 upper surfaces of conducting layer with the level at first, sets up control gate electrode 4 at the upper surface of isolation layer 3 again, sets up isolation layer 3 at the upper surface of control gate electrode 4 again, so as to analogize for isolation layer 3 and control gate electrode 4 overlap each other and the level is arranged in conducting layer 2 top, until isolation layer 3 blocks the top.

In fig. 1 and 3, a-g and a-f of 3a-3g and 4a-3f are predetermined number of layers, and the number of layers of the isolation layer 3 and the control gate electrode 4 may be determined according to circumstances.

The three-dimensional trench ferroelectric memory of the present invention further includes a plurality of trench type memory cell strings 5 vertically penetrating the stacked structure, and the bottom of each trench type memory cell string 5 is embedded in the conductive layer 2.

The trench type memory cell string 5 includes: the groove bottom of the groove hole 10 is embedded into the conducting layer 2; the side wall and the bottom of the groove hole 10 are sequentially provided with a buffer layer 6, a ferroelectric film layer 7, a channel layer 8 and a filling layer 9.

Finally, the control gate electrode 4, the buffer layer 6, the ferroelectric thin film layer 7 and the channel layer 8 jointly form a plurality of ferroelectric field effect transistors which are mutually connected in series. Please refer to the area enclosed by the rectangular box in fig. 3, which is the ferroelectric field effect transistor.

Optionally, the lengths of the buffer layer 6, the ferroelectric thin film layer 7 and the channel layer 8 are less than the lengths of the side wall and the bottom of the groove; or the lengths of the buffer layer 6, the ferroelectric thin film layer 7 and the channel layer 8 are equal to the lengths of the side walls and the groove bottom.

Referring to fig. 1 and 2, when a plurality of trench-type memory cell strings 5 are adjacent, the ferroelectric field effect transistors in different three-trench-type memory cell strings 5 should be isolated, so that the lengths of the buffer layer 6, the ferroelectric thin film layer 7 and the channel layer 8 in the trench-type memory cell strings 5 are smaller than the lengths of the sidewalls and the bottom of the trench, so that only a part of the trench hole 10 contains the ferroelectric field effect transistors, and the other part is used for isolating the ferroelectric field effect transistors in the adjacent trench-type memory cell strings 5.

When there is only one trench type memory cell string 5, the buffer layer 6, the ferroelectric thin film layer 7, and the channel layer 8 in the trench type memory cell string 5 may completely fill the trench hole 10, and thus the length of each layer of substance in the trench type memory cell string 5 is equal to the length of the sidewall and the bottom of the trench.

Alternatively, the number of the ferroelectric field effect transistors in each trench type memory cell string 5 is twice the number of layers of the control gate electrodes 4.

Alternatively, the cross-section of each trench hole 10 is rectangular, trapezoidal, or "V" shaped.

The buffer layer 6 is arranged between the ferroelectric thin film layer 7 and the control gate electrode layer 4, so that direct contact, element diffusion and chemical reaction between the ferroelectric thin film layer 7 and the control gate electrode layer 4 can be effectively avoided. The buffer layer 6 can also be used as a seed layer of the ferroelectric thin film layer 7 to induce the growth of the thin film, or as a stress control layer, which is beneficial to promoting the generation of ferroelectric phase in the ferroelectric thin film layer 7, thereby improving the performance of the ferroelectric thin film layer 7. Meanwhile, the leakage current can be effectively reduced, and the retention performance of the three-dimensional groove type ferroelectric memory is improved.

The channel layer 8 is a part of a ferroelectric field effect transistor, and its resistance can be changed by changing polarization in the ferroelectric thin film layer 7 by a voltage applied to the control gate electrode layer 4, to be turned on and off, thereby accessing data. The thickness of the channel layer 8 is smaller than the thickness of its depletion layer to form a fully depleted transistor. Wherein the depletion layer is a generic name in semiconductors, the thickness of which is related to the properties of the chosen semiconductor material.

Meanwhile, the source and drain selection transistors of the conventional three-dimensional transistor type ferroelectric memory are respectively positioned at the upper and lower ends of the memory cell string, which may affect metal wiring in the subsequent process. Referring to fig. 3, two black arrows in fig. 3 indicate two ends of the trench type memory cell string 5, and it can be seen that the two ends of the trench type memory cell string 5 are both located on the same horizontal line, and this structure can obtain more compact metal wiring, which is beneficial to realizing higher density integration.

Optionally, the substrate 1 is a semiconductor substrate including, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), etc.; the conductive layer 2 is a metal electrode or a heavily doped semiconductor material.

If the conducting layer 2 is a metal electrode, a layer of insulating material is arranged between the substrate 1 and the conducting layer 2; optionally, the conductive layer 2 may be one or more of Ti, Ta, HfN, TiN, W, TaN, and other metal electrodes.

If the conducting layer 2 is made of heavily doped semiconductor material, the conducting layer 2 and the substrate 1 form a pn junction; alternatively, when the substrate 1 is a p-type semiconductor, the conductive layer 2 is a medium-doped n-type semiconductor. Wherein, heavily doped means that the concentration is very high.

Optionally, the buffer layer 6 is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) One or more of (a).

Optionally, the ferroelectric thin film layer 7 is hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Zirconium oxide (ZrO) doped with other elements₂) Or hafnium oxide (HfO) doped with other elements₂) (ii) a The doping element comprises one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge) and nitrogen (N).

Optionally, the channel layer 8 is made of an oxide semiconductor material with high carrier mobility, which can promote the ferroelectric thin film layer 7 to generate a ferroelectric phase, improve the performance of the ferroelectric thin film layer 7, and has weak chemical reaction with the ferroelectric thin film layer 7 and hardly generates an interface layer, including but not limited to indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium tin zinc oxide (InSnZnO), and indium tin zinc oxide (InSnZnO)Zinc tin (ZnSnO), zinc aluminum tin oxide (ZnAlSnO), silicon zinc tin oxide (SiZnSnO), indium aluminum zinc oxide (InAlZnO), indium zirconium zinc oxide (InZrZnO), indium hafnium zinc oxide (InHfZnO), zinc oxide (ZnO), gallium oxide (Ga)₂O₃) And the like.

The oxide semiconductor material with high carrier mobility is used as the channel layer 8, so that higher reading current and reading speed can be obtained, and a smaller working voltage can be realized because an interface layer is almost not arranged between the ferroelectric thin film layer 7 and the oxide semiconductor channel layer 8.

Optionally, the filling layer 9 is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Or silicon oxynitride (SiON).

Optionally, the isolation layer 3 is silicon oxide (SiO)₂) Or a dielectric constant less than that of silicon oxide (SiO)₂) The dielectric constant of (2).

Optionally, the control gate electrode 4 is a heavily doped polysilicon, nitride metal electrode or tungsten (W), where heavily doped means high concentration and high conductivity.

The invention also provides a preparation method of the three-dimensional groove type ferroelectric memory, which comprises the following steps:

the method comprises the following steps: a conductive layer 2 is provided on a substrate 1.

Fig. 4 is a schematic structural diagram of a first step in the method for manufacturing a three-dimensional trench ferroelectric memory according to the present invention, please refer to fig. 4.

The method of providing the conductive layer 2 on the substrate 1 is: if the conductive layer 2 is a heavily doped semiconductor material, ions are implanted into the surface of the substrate 1 by using an ion implantation process to form the conductive layer 2 on the surface of the substrate 1, and the conductive layer 2 and the substrate 1 form a pn junction. For example: the substrate 1 is a p-type semiconductor, and the conductive layer 2 is a heavily doped n-type semiconductor, where heavily doped means high concentration. If the conductive layer 2 is a metal electrode, a layer of insulating material is formed on the substrate 1, and then the metal electrode is deposited to form the conductive layer 2.

Optionally, the substrate 1 is a semiconductor substrate including, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), and the like.

Step two: and sequentially and alternately depositing a preset number of layers of isolation layers 3 and control gate electrodes 4 on the conductive layer 2.

Fig. 5 is a schematic structural diagram of a second step in the method for manufacturing a three-dimensional trench ferroelectric memory according to the present invention, please refer to fig. 5.

Depositing an isolation layer 3 on the surface of the conductive layer 2, depositing a control gate electrode 4 on the surface of the isolation layer 3, depositing an isolation layer 3 on the surface of the control gate electrode 4, and so on, so that the isolation layer 3 and the control gate electrode 4 are horizontally arranged above the conductive layer 2 in an overlapped manner until the isolation layer 3 is capped.

Optionally, the isolation layer 3 is silicon oxide (SiO)₂) Or a dielectric constant less than that of silicon oxide (SiO)₂) The dielectric constant of (2). The control gate electrode 4 is a heavily doped polysilicon, nitride metal electrode or tungsten (W), and heavily doped means high concentration and high conductivity.

Alternatively, a skilled person can set the predetermined number of layers of the isolation layer 3 and the control gate electrode 4 according to the situation, and fig. 5 only shows 7 isolation layers 3(3a-3g) and 6 control gate electrodes 4(4a-4 f).

Optionally, the deposition method of the isolation layer 3 and the control gate electrode 4 includes any one or more of Chemical Vapor Deposition (CVD), magnetron sputtering (sputtering), Metal Organic Chemical Vapor Deposition (MOCVD), and Atomic Layer Deposition (ALD).

Step three: a plurality of trench holes 10 penetrating the isolation layer 3 and the control gate electrode 4 are formed, and the bottom of each trench hole 10 is embedded in the conductive layer 2.

Fig. 6 is a schematic structural diagram of a third step in the method for manufacturing a three-dimensional trench ferroelectric memory according to the present invention, please refer to fig. 6. The control gate electrode 4, the isolation layer 3 and the conductive layer 2 are etched by a wet etching process or a dry etching process to form a plurality of trench holes 10, each trench hole 10 is rectangular, trapezoidal or V-shaped, each trench hole 10 penetrates through all the isolation layers 3 and the control gate electrode 4, the bottom of each trench hole 10 is embedded in the conductive layer 2, and only two trench holes 10 are shown in fig. 6.

Step four: a buffer layer 6, a ferroelectric film layer 7 and a channel layer 8 are sequentially deposited on the inner wall of each groove hole 10; and depositing a filling layer 9 in each trench hole 10 based on the channel layer 8 to fill each trench hole 10 to form a trench type memory cell string 5, thereby completing the preparation of the three-dimensional trench type ferroelectric memory.

Fig. 7 is a schematic structural diagram of step four in the method for manufacturing a three-dimensional trench ferroelectric memory according to the present invention, please refer to fig. 7. The control gate electrode 4, the buffer layer 6, the ferroelectric thin film layer 7 and the channel layer 8 jointly form a plurality of ferroelectric field effect transistors which are mutually connected in series. Please refer to the area enclosed by the rectangular box in fig. 6, which is the ferroelectric field effect transistor.

Optionally, the lengths of the buffer layer 6, the ferroelectric thin film layer 7 and the channel layer 8 are less than the lengths of the side wall and the bottom of the groove; or the lengths of the buffer layer 6, the ferroelectric thin film layer 7 and the channel layer 8 are equal to the lengths of the side walls and the groove bottom.

Referring to fig. 1 and 2, when a plurality of trench-type memory cell strings 5 are adjacent, the ferroelectric field effect transistors in different three-trench-type memory cell strings 5 should be isolated, so that the lengths of the buffer layer 6, the ferroelectric thin film layer 7 and the channel layer 8 in the trench-type memory cell strings 5 are smaller than those of the sidewalls and the bottom of the trench, so that only a part of the trench hole 10 contains the ferroelectric field effect transistors, and the other part is used for isolating the ferroelectric field effect transistors in the adjacent trench-type memory cell strings 5.

When there is only one trench type memory cell string 5, the buffer layer 6, the ferroelectric thin film layer 7, and the channel layer 8 in the trench type memory cell string 5 may completely fill the trench hole 10, and thus the length of each layer of substance in the trench type memory cell string 5 is equal to the length of the sidewall and the bottom of the trench.

The buffer layer 6 is arranged between the ferroelectric thin film layer 7 and the control gate electrode layer 4, so that direct contact, element diffusion and chemical reaction between the ferroelectric thin film layer 7 and the control gate electrode layer 4 can be effectively avoided. The buffer layer 6 can be used as a seed layer of the ferroelectric thin film layer 7 to induce the growth of the thin film, or as a stress control layer to promote the crystallization of the ferroelectric thin film layer 7 and generate a ferroelectric phase, thereby improving the performance of the ferroelectric thin film layer 7. Meanwhile, the leakage current can be effectively reduced, and the retention performance of the three-dimensional ferroelectric memory is improved.

The channel layer 8 is a part of the ferroelectric field effect transistor, and its resistance can be changed by changing polarization in the ferroelectric thin film layer 7 by a voltage applied to the control gate electrode layer 4, to be turned on and off, thereby reading data. The thickness of the channel layer 8 is smaller than the thickness of its depletion layer to form a fully depleted transistor. Wherein the depletion layer is a generic name in semiconductors, the thickness of which is related to the properties of the chosen semiconductor material.

Meanwhile, the source and drain selection transistors of the conventional three-dimensional ferroelectric memory are respectively located at the upper and lower ends of the memory cell string, which may affect metal wiring in the subsequent process. Two black arrows in fig. 6 indicate two ends of the trench type memory cell string 5, and it can be seen that the two ends of the trench type memory cell string 5 are both located on the same horizontal line, so as to obtain more compact metal wiring, which is beneficial to realizing higher density integration.

Optionally, the buffer layer 6 is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) One or more of (a).

Optionally, the ferroelectric thin film layer 7 is hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Zirconium oxide (ZrO) doped with other elements₂) Or hafnium oxide (HfO) doped with other elements₂) (ii) a The doping element comprises one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge) and nitrogen (N).

Optionally, the channel layer 8 is made of an oxide semiconductor material with high carrier mobility, and has a weak chemical reaction with the ferroelectric thin film layer 7, and hardly generates an interface layer, and can also promote the ferroelectric thin film layer 7 to generate a ferroelectric phase.

Including but not limited to indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium tin zinc oxide (InSnZnO), zinc tin oxide (ZnSnO), zinc aluminum tin oxide (ZnAlSnO), silicon oxideZinc tin (SiZnSnO), indium aluminum zinc oxide (InAlZnO), indium zirconium zinc oxide (InZrZnO), indium hafnium zinc oxide (InHfZnO), zinc oxide (ZnO), gallium oxide (Ga)₂O₃) And the like.

The oxide semiconductor material with high carrier mobility is used as the channel layer 8, so that larger reading current and reading speed can be obtained, and a smaller working voltage can be realized because an interface layer is almost not arranged between the ferroelectric thin film layer 7 and the oxide semiconductor channel layer 8.

Optionally, the filling layer 9 is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Or silicon oxynitride (SiON).

Alternatively, the deposition methods of the buffer layer 6, the ferroelectric thin film layer 7, the channel layer 8 and the filling layer 9 in the present invention may be the same or different, and are Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).

Optionally, in the third step, the isolation layer 3 is deposited on the conductive layer 2 by a Chemical Vapor Deposition (CVD) method, a magnetron sputtering method (sputtering) method, or an Atomic Layer Deposition (ALD) method.

Optionally, in the third step, the control gate electrode 4 is deposited on the conductive layer 2 by any one or more of a Chemical Vapor Deposition (CVD) method, a magnetron sputtering method (sputtering), an Atomic Layer Deposition (ALD) method, and a Metal Organic Chemical Vapor Deposition (MOCVD) method.

The etching step in the existing three-dimensional ferroelectric memory process can damage the ferroelectric thin film layer, thereby affecting the reliability of the ferroelectric memory. Specifically, in the existing manufacturing method, after the ferroelectric thin film layer is deposited, the extra ferroelectric thin film layer at some positions needs to be etched, so that the quality of the ferroelectric thin film layer is affected. The structure of the three-dimensional groove type ferroelectric memory is groove type, and the buffer layer 6, the ferroelectric film layer 7 and the channel layer 8 are deposited in sequence during preparation without adopting an etching process, so that the reliability of the ferroelectric memory can be improved.

The invention aims to protect a three-dimensional ferroelectric memory and a preparation method thereof, wherein the preparation method comprises the following steps: a substrate 1 and a conductive layer 2 disposed on the substrate 1; the laminated structure arranged on the conductive layer 2 comprises a plurality of layers of isolation layers 3 and control gate electrodes 4 which are mutually overlapped and horizontally arranged; the plurality of groove holes 10 penetrate through the laminated structure, and the groove bottoms of the groove holes 10 are embedded into the conductive layer 2; the side wall and the bottom of the groove hole 10 are sequentially paved with a buffer layer 6, a ferroelectric thin film layer 7, a channel layer 8 and a filling layer 9. The three-dimensional ferroelectric memory can obtain more compact wiring and is beneficial to realizing higher-density integration. Meanwhile, the buffer layer 6 arranged in the groove type memory cell string 5 can guarantee the quality and the performance of the ferroelectric thin film layer and the memory thereof. In addition, an oxide semiconductor material with high carrier mobility is selected as the channel layer 8, so that higher reading current and reading speed can be obtained, and a smaller working voltage can be realized because an interface layer is almost not arranged between the ferroelectric thin film layer 7 and the oxide semiconductor channel layer 8.

It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.