Semiconductor device including control logic structure, electronic system, and related method
阅读说明:本技术 包含控制逻辑结构的半导体装置、电子系统和相关方法 (Semiconductor device including control logic structure, electronic system, and related method ) 是由 K·D·拜格尔 S·E·西里斯 于 2018-12-26 设计创作,主要内容包括:一种半导体装置包含包括叠层的堆叠结构。所述堆叠结构的每个叠层包括:存储器元件层级,所述存储器元件层级包括存储器元件;以及控制逻辑层级,所述控制逻辑层级与所述存储器元件层级电通信,所述控制逻辑层级包括:第一子叠层结构,所述第一子叠层结构包括第一数量的晶体管,所述第一数量的晶体管包括P型沟道区域或N型沟道区域;以及位于所述第一子叠层结构之上的第二子叠层结构,所述第二子叠层结构包括第二数量的晶体管,所述第二数量的晶体管包括P型沟道区域或N型沟道区域中的另一个。公开了相关的半导体装置和形成所述半导体装置的方法。(A semiconductor device includes a stacked structure including a stack of layers. Each stack of the stacked structure comprises: a memory element hierarchy comprising memory elements; and a control logic hierarchy in electrical communication with the memory element hierarchy, the control logic hierarchy comprising: a first sub-stack structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region; and a second sub-stack structure located over the first sub-stack structure, the second sub-stack structure comprising a second number of transistors, the second number of transistors comprising the other of the P-type channel region or the N-type channel region. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.)
1. A semiconductor device, comprising:
a stack structure comprising a stack of layers, each stack of the stack structure comprising:
a memory element hierarchy comprising memory elements; and
a control logic hierarchy in electrical communication with the memory element hierarchy, the control logic hierarchy comprising: a first sub-stack structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region; and a second sub-stack structure located over the first sub-stack structure, the second sub-stack structure including a second number of transistors, the second number of transistors including the other of the P-type channel region and the N-type channel region.
2. The semiconductor device of claim 1, further comprising a base control logic structure in electrical communication with the stacked structures and comprising a control logic device, wherein the control logic hierarchy of at least one stack in the stacked structures is in electrical communication with the base control logic structure.
3. The semiconductor device of claim 2, wherein the control logic devices of the base control logic structure exhibit different configurations and have different operational functions than control logic devices of the control logic hierarchy of each of the tiers of the stacked structure.
4. The semiconductor device according to claim 2, wherein:
at least one stack of the stacked structure comprises control logic devices comprising one or more of a local stack decoder, a column decoder, a row decoder, a sense amplifier, a word line driver, a repair device, a memory test device, a multiplexer, an error check and correction device, and a self refresh device; and is
The control logic devices of the base control logic structure include one or more of a charge pump, a delay locked loop device, and a drain supply voltage regulator.
5. The semiconductor device of claim 1, wherein the control logic level of at least one stack of the stack structure is higher than the memory element level of the at least one stack of the stack structure.
6. The semiconductor device of claim 1, wherein the control logic level of at least one stack of the stack structure is lower than the memory element level of the at least one stack of the stack structure.
7. The semiconductor device of claim 1, wherein the first number of transistors of at least one stack of the stacked structure comprises a gate-all-around transistor.
8. The semiconductor device of claim 1, wherein the first number of transistors of at least one stack of the stacked structure comprises single-gate transistors.
9. The semiconductor device of claim 1, wherein the first number of transistors of at least one stack of the stacked structure comprises gate two-sided transistors.
10. The semiconductor device of claim 1, wherein the first number of transistors of at least one stack of the stacked structure comprises a channel region configured to cause current to flow in at least one of a lateral direction and a vertical direction.
11. The semiconductor device of claim 1, wherein the first number of transistors of at least one stack of the stacked structures comprises at least some transistors electrically isolated from other structures in the at least one stack.
12. The semiconductor device of claim 1, wherein the control logic level of each stack in the stacked structure is substantially the same.
13. The semiconductor device according to claim 1, wherein the first number of transistors and the second number of transistors comprise vertical transistors or planar transistors.
14. The semiconductor device of claim 1, wherein each stack in the stack structure further comprises an access device level comprising access devices electrically connected to the memory elements of the memory element level.
15. The semiconductor device of claim 1, wherein a gate electrode of at least one transistor of the first number of transistors is in electrical communication with a gate electrode of a corresponding transistor of the second number of transistors through a gate contact extending between the first and second sub-stack structures.
16. The semiconductor device of claim 1, wherein the stack structure comprises:
a first stack comprising a first memory element level, a first access device level, and a first control logic level; and
a second stack structure over the first stack structure, the second stack structure comprising a second memory element level, a second access device level, and a second control logic level,
wherein at least one of the first and second control logic levels comprises at least one CMOS device in electrical communication with a base control logic structure.
17. A method of forming a semiconductor device, the method comprising:
forming a stack structure over a substrate, wherein forming the stack structure includes forming each stack structure to include a memory element level and a control logic level, forming at least one control logic level of at least one stack structure includes:
forming a first sub-stack structure comprising first transistors, at least some of the first transistors comprising one of an N-type channel region or a P-type channel region;
forming a second sub-stack structure comprising second transistors over the first sub-stack structure, at least some of the second transistors comprising the other of the N-type channel region or the P-type channel region; and
electrically connecting the at least some of the first transistors to the at least some of the second transistors to form a device.
18. The method of claim 17, wherein forming a first sub-stack structure comprises
Forming a sacrificial material over the first transistor; and
the sacrificial material is removed from over a surface of the first transistor and a conductive contact is formed over the first transistor.
19. An electronic system comprising the semiconductor device of claim 1.
20. A method of operating the semiconductor device of claim 1, the method comprising:
controlling a function of the stacked structure; and
controlling additional functions of the stacked structure using a base control logic structure in electrical communication with the control logic hierarchy of the stacked structure.
Technical Field
Embodiments of the present disclosure relate to the field of semiconductor device design and manufacture. More particularly, embodiments of the present disclosure relate to control logic devices including stacked stacks of transistors, control logic assemblies, semiconductor devices including control logic devices, and methods of forming control logic devices and semiconductor devices.
Background
Semiconductor device designers often desire to increase the level of integration or density of features within a semiconductor device by reducing the size of individual features and reducing the spacing distance between adjacent features. In addition, semiconductor device designers often desire to design architectures that are not only compact, but also provide performance advantages and simplify the design.
One example of a semiconductor device is a memory device. Memory devices are often provided in computers or other electronic devices as internal integrated circuits. There are many types of memory, including but not limited to Random Access Memory (RAM), Read Only Memory (ROM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), flash memory, and resistance variable memory. Non-limiting examples of resistance variable memory include resistive random access memory (ReRAM), conductive bridge random access memory (conductive bridge RAM), Magnetic Random Access Memory (MRAM), Phase Change Material (PCM) memory, Phase Change Random Access Memory (PCRAM), Spin Torque Transfer Random Access Memory (STTRAM), oxygen vacancy based memory, and programmable conductor memory.
A typical memory cell of a memory device includes an access device (e.g., a transistor) and a memory storage structure (e.g., a capacitor). Modern applications of semiconductor devices may employ a large number of memory cells arranged in a memory array exhibiting rows and columns of memory cells. Memory cells in a memory array can be electrically accessed by digit lines (e.g., bit lines) and word lines (e.g., access lines) arranged along rows and columns of memory cells. The memory array may be two-dimensional (2D) to reveal a single stack (e.g., single layer, single level) of memory cells, or may be three-dimensional (3D) to reveal multiple stacks (e.g., multiple levels, multiple layers) of memory cells.
Control logic devices within a base control logic structure below a memory array of a memory device have been used to control operations (e.g., access operations, read operations, write operations) on memory cells of the memory device. The assembly of control logic devices may be provided in electrical communication with the memory cells in the memory array through wiring and interconnect structures. However, as the number of memory cells and the corresponding number of stacked layers of a 3D memory array increase, the assembly of electrically connecting memory cells of different stacks of the 3D memory array to control logic devices within a base control logic structure positioned below the memory array may cause sizing and spacing complications associated with increased number and size of routing and interconnect structures required to facilitate the electrical connections. In addition, the number, size, and arrangement of the different control logic devices employed in the base control logic structure may also adversely impede a reduction in the size of the memory devices, an increase in the storage density of the memory devices, and/or a reduction in manufacturing costs.
Accordingly, it would be desirable to have improved semiconductor devices, control logic assemblies, and control logic devices, and methods of forming semiconductor devices, control logic assemblies, and control logic devices that facilitate higher packing densities.
Disclosure of Invention
Embodiments disclosed herein relate to control logic devices including stacked stacks of transistors, control logic assemblies, semiconductor devices including control logic devices, and methods of forming control logic devices and semiconductor devices. For example, in accordance with at least some embodiments, a semiconductor device includes a stacked structure including stacked layers, each stacked layer of the stacked structure including: a memory element hierarchy comprising memory elements; and a control logic hierarchy in electrical communication with the memory element hierarchy, the control logic hierarchy comprising: a first sub-stack structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region; and a second sub-stack structure located over the first sub-stack structure, the second sub-stack structure including a second number of transistors, the second number of transistors including the other of the P-type channel region and the N-type channel region.
In further embodiments, a semiconductor device includes a stacked structure including a plurality of stacked layers. Each stack of the stacked structure comprises: a memory element hierarchy comprising memory elements; an access device hierarchy comprising access devices electrically connected to the memory elements of the memory element hierarchy; and a control logic hierarchy. The control logic hierarchy includes: a first sub-stack structure comprising a first number of transistors, each transistor of the first number of transistors comprising one of an N-type channel region or a P-type channel region; and a second sub-stack structure over the first sub-stack structure and including a second number of transistors, each transistor of the second number of transistors including the other of the N-type channel region or the P-type channel region.
In further embodiments, a semiconductor device includes: a first stack comprising a first memory element level, a first access device level, and a first control logic level; and a second stacked structure over the first stacked structure, the second stacked structure comprising a second memory element level, a second access device level, and a second control logic level, wherein at least one of the first control logic level and the second control logic level comprises at least one CMOS device in electrical communication with a base control logic structure.
In further embodiments, a method of forming a semiconductor device includes forming stacked structures over a substrate, wherein forming the stacked structures includes forming each stacked structure to include a memory element level and a control logic level. Forming at least one control logic level of the at least one stack structure comprises: forming a first sub-stack structure comprising first transistors, at least some of the first transistors comprising one of an N-type channel region or a P-type channel region; forming a second sub-stack structure comprising second transistors over the first sub-stack structure, at least some of the second transistors comprising the other of the N-type channel region or the P-type channel region; and electrically connecting the at least some of the first transistors to the at least some of the second transistors to form a device.
In yet further embodiments, a method of operating a semiconductor device includes: controlling a function of a stacked structure having a plurality of stacked layers using a control logic level of the plurality of stacked layers, each of the stacked structures including a memory cell, the control logic level each including at least one control logic device including a first sub-stacked structure over a second sub-stacked structure, the first sub-stacked structure including a transistor having one of a P-type channel region and an N-type channel region, the second sub-stacked structure including a transistor having the other of the P-type channel region and the N-type channel region; and controlling additional functions of the stacked structure using a base control logic structure in electrical communication with the control logic hierarchy of the stacked structure.
In a further embodiment, an electronic system includes a memory device in communication with at least one of an electronic signal processor device, an input device, and an output device, the memory device including a stacked structure including a stack of layers. Each stack of the stacked structure comprises: a memory element hierarchy comprising memory elements; and a control logic hierarchy in electrical communication with the memory element hierarchy, the control logic hierarchy comprising: a first sub-stack structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region; and a second sub-stack structure over the first sub-stack structure and including a second number of transistors including the other of the P-type channel region and the N-type channel region.
Drawings
Fig. 1 is a simplified side elevational view of a semiconductor device according to an embodiment of the present disclosure;
fig. 2 is a simplified block diagram of a Thin Film Transistor (TFT) control logic level of the semiconductor device shown in fig. 1, according to an embodiment of the present disclosure;
fig. 3A and 3B are simplified cross-sectional views of a TFT control logic level including a metal-oxide-semiconductor (CMOS) circuit, according to an embodiment of the present disclosure;
FIG. 3C is a perspective view of the CMOS inverter of FIGS. 3A and 3B;
FIG. 4 is a simplified perspective view of a dual input NAND (NAND) circuit according to an embodiment of the present disclosure;
FIG. 5 is a simplified perspective view of a balanced CMOS inverter according to an embodiment of the present disclosure;
fig. 6 is a simplified perspective view of a CMOS transmission pass gate according to an embodiment of the present disclosure;
FIG. 7 is a simplified perspective view of a balanced dual input NAND circuit according to an embodiment of the present disclosure;
FIG. 8A is a simplified perspective view of a ring oscillator according to an embodiment of the present disclosure;
FIG. 8B is a simplified perspective view of another ring oscillator according to other embodiments of the present disclosure;
FIG. 9 is a simplified perspective view of a balanced dual-input NAND circuit including NMOS and PMOS transistors with planar channel regions, according to an embodiment of the present disclosure;
10A-10Z are simplified partial cross-sectional views showing a method of forming a semiconductor device including an array of CMOS inverters, according to an embodiment of the present disclosure;
fig. 11A and 11B are simplified cross-sectional views of a semiconductor device including a vertical NMOS transistor and a vertical PMOS transistor according to an embodiment of the present disclosure;
fig. 12A and 12B are simplified cross-sectional views of semiconductor devices including vertical NMOS transistors and vertical PMOS transistors according to other embodiments of the present disclosure; and is
Fig. 13 is a schematic block diagram of an electronic system according to an embodiment of the present disclosure.
Detailed Description
The illustrations contained herein are not meant to be actual views of any particular system or semiconductor structure, but are merely idealized representations which are employed to describe the embodiments herein. Elements and features that are common between figures may retain the same numerical designation except where: for ease of the following description, in most cases, the reference numerals begin with the reference numeral that introduces or most fully describes the element.
The following description provides specific details such as material types, material thicknesses, and processing conditions in order to provide a thorough description of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments disclosed herein may be practiced without these specific details. Indeed, the embodiments may be practiced in conjunction with conventional fabrication techniques employed in the semiconductor industry. Additionally, the descriptions provided herein do not form a complete description of semiconductor devices, thin film transistor control logic structures, or a complete description of the process flow for fabricating such semiconductor devices or control logic structures. Only those process acts and structures necessary to understand the embodiments described herein are described in detail below. Additional acts for forming a complete semiconductor device or control logic structure including the structures described herein may be performed by conventional techniques.
According to embodiments disclosed herein, a semiconductor device includes a multi-stack structure including a base control logic structure and a stack structure over the base control logic structure. The stacked structure includes tiers, each of which includes a tier of memory elements, a tier of access devices, and a tier of Thin Film Transistor (TFT) control logic (e.g., a tier of control logic that includes one or more field effect transistors that include films of active semiconductor material, dielectric material, and metal contacts). The TFT control logic level in some embodiments includes a TFT CMOS device and includes a first substack structure including one of an NMOS transistor and a PMOS transistor and a second substack structure over the first substack structure and including the other of the NMOS transistor and the PMOS transistor. The first and second sub-stack structures may be displaced from each other in a vertical direction. The NMOS transistor, the PMOS transistor, or both may include a vertically extending channel region extending in a direction substantially orthogonal to the base control logic structure. In other embodiments, the NMOS transistor, the PMOS transistor, or both may include a laterally extending channel region and may include a planar transistor.
Arranging the semiconductor devices to include stacks, each stack including a TFT control logic level, may reduce the interconnect circuitry between each stack and the base control logic structure and any access device levels and memory element levels associated with each stack. Accordingly, the thin film transistor control logic level may be formed to include CMOS circuitry with a reduced number (e.g., no) of sockets or interconnects to the base control logic structure between each stacked memory element and access device and the base control logic structure. In addition, since the sub-stack structure is vertically shifted, NMOS transistors and PMOS transistors may be formed separately and associated with a particular stack having its own memory element level and access device level.
As used herein, the terms "longitudinal," "vertical," "lateral," and "horizontal" refer to a major plane of a substrate (e.g., base material, base structure, base construction, etc.) in or on which one or more structures and/or features are formed and are not necessarily defined by the earth's gravitational field. A "lateral" or "horizontal" direction is a direction substantially parallel to the major plane of the substrate, while a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the major plane of the substrate. The main plane of the substrate is defined by the surface of the substrate having a relatively larger area than the other surfaces of the substrate.
As used herein, spatially relative terms, such as "below," "lower," "bottom," "above," "upper," "top," "front," "rear," "left," "right," and the like, may be used for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Unless otherwise indicated, spatially relative terms are intended to encompass different orientations of the material in addition to the orientation depicted in the figures. For example, if the materials in the figures are inverted, elements described as "below" or "beneath" or "bottom" other elements or features would then be oriented "above" or "top" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below, as will be apparent to those of ordinary skill in the art, depending on the context in which the term is used. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped, etc.) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes a degree of variation that one of ordinary skill in the art would understand to some extent the given parameter, property, or condition meets, such as within acceptable manufacturing tolerances. For example, depending on the particular parameter, property, or condition being substantially met, the parameter, property, or condition may be met by at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.
As used herein, the term "about" with respect to a given parameter includes the stated value and has the meaning dictated by the context (e.g., the term includes the degree of error associated with measurement of the given parameter).
As used herein, the term "NMOS" transistor means and includes so-called metal oxide transistors having a P-type channel region. The gate of the NMOS transistor may comprise a conductive metal, another conductive material such as polysilicon, or a combination thereof. As used herein, the term "PMOS" transistor means and includes so-called metal oxide transistors having an N-type channel region. The gate of the PMOS transistor may comprise a conductive metal, another conductive material such as polysilicon, or a combination thereof. Thus, the gate structure of such transistors may comprise a conductive material that is not necessarily a metal.
Fig. 1 shows a simplified side elevation view of a semiconductor device 100 (e.g., a 3D memory device) according to an embodiment of the present disclosure. As shown in fig. 1, the
The base
With continued reference to fig. 1, the
Although fig. 1 shows that each of the first, second, and
The memory element levels (e.g., first
The memory elements in the array may include RAM elements, ROM elements, DRAM elements, SDRAM elements, flash memory elements, resistance variable memory elements, or another type of memory element. In some embodiments, the memory elements comprise DRAM elements. In further embodiments, the memory element comprises a resistance variable memory element. Non-limiting examples of resistance variable memory elements include ReRAM elements, conductive bridge RAM elements, MRAM elements, PCM memory elements, PCRAM elements, STTRAM elements, oxygen vacancy based memory elements, and programmable conductor memory elements.
The access device levels (e.g., first
The access devices of the access device hierarchy and the memory elements of the memory element hierarchy operatively associated therewith may together form a memory cell for each of the
The TFT control logic levels (e.g., first TFT
The devices and circuitry of the TFT control logic level of each of the
Accordingly, a semiconductor device in accordance with an embodiment of the present disclosure includes a base control logic structure including a control logic device and a stacked structure in electrical communication with the base control logic structure. The stacked structure includes stacked tiers, each of the stacked tiers individually including a memory element tier containing memory elements, an access device tier including an access device electrically connected to the memory elements of the memory element tier, and a control logic tier in electrical communication with the memory element tier and the access device tier and including additional control logic devices. At least one of the further control logic devices of the control logic level of one or more of the stacks in the stack comprises a CMOS device comprising a first number of transistors disposed over a second number of transistors, the first number of transistors comprising one of an N-type channel region or a P-type channel region, the second number of transistors comprising the other of the N-type channel region and the P-type channel region. The TFT control logic level may further be in electrical communication with the base control logic structure.
Fig. 2 is a block diagram of a configuration of a TFT control logic level 200 for use in one or more of the stacks 104 (fig. 1) of the stack structure 103 (fig. 1) of the
As shown in fig. 2, one or more overlay external devices 236 positioned outside of the TFT control logic level 200 (e.g., in the base
A first MUX 204a (e.g., a row MUX) of TFT control logic level 200 may be in electrical communication with a local stack decoder 202 and a row decoder 208 of TFT control logic level 200. The first MUX 204a may be activated by one or more signals from the local stack decoder 202 and may be configured and operable to selectively forward at least one row address signal 230 from the off-stack device 236 to the row decoder 208. The row decoder 208 may be configured and operable to select a particular word line containing a stack of TFT control logic levels 200 (e.g., one of the
With continued reference to fig. 2, the row repair device 218 of the TFT control logic level 200 may be in electrical communication with the row decoder 208 and may be configured and operable to replace a defective row of memory elements of a memory element array of a memory element level (e.g., one of the
The WL driver 214 of the TFT control logic level 200 may be in electrical communication with the row decoder 208 and configured and operable to activate a wordline containing a stack of the TFT control logic level 200 (e.g., one of the
The self-refresh/wear leveling device 224 of the TFT control logic hierarchy 200 may be in electrical communication with the row decoder 208 and may be configured and operable to periodically recharge data stored in memory elements of a memory element hierarchy (e.g., one of the
Still referring to fig. 2, a second MUX 204b (e.g., a column MUX) of the TFT control logic level 200 may be in electrical communication with the local stack decoder 202 and the column decoder 206 of the TFT control logic level 200. The second MUX 204b may be activated by one or more signals from the local stack decoder 202 and may be configured and operable to selectively forward at least one column address signal 232 from the off-stack device 236 to the column decoder 206. The column decoder 206 may be configured and operable to select a particular digit line (e.g., a bit line) that includes a stack of TFT control logic levels 200 (e.g., one of the
Column repair device 216 of TFT control logic level 200 may be in electrical communication with column decoder 206 and may be configured and operable to replace a defective row of a memory element array of a memory element level (e.g., one of
The ECC apparatus 220 of the TFT control logic hierarchy 200 may be configured and operable to generate an ECC code (also referred to as a "check bit"). The ECC code may correspond to a particular data value and may be stored with the data value in a memory element of a memory element level (e.g., one of the
The memory test device 222 of the TFT control logic level 200 may be configured and operated to identify a defective (e.g., failing) memory element of a memory element array of a memory element level (e.g., one of the
With continued reference to FIG. 2, the local I/O devices 212 of the TFT control logic level 200 may be configured and operated to receive data from the digit lines selected by the column decoder 206 during a read operation and to output data to the digit lines selected by the column decoder 206 during a write operation. As shown in fig. 2, local I/O device 212 may include sense amplifiers 210 configured and operative to receive digit line inputs from digit lines selected by column decoder 206 and to generate digital data values during read operations. During a write operation, local I/O devices 212 may program data into memory elements of a hierarchy of memory elements operatively associated with TFT control logic hierarchy 200 by placing appropriate voltages on the digital lines selected by column decoder 206. For binary operation, one voltage level is typically placed on the digit line to represent a binary "1" and the other voltage level represents a binary "0".
The third MUX 204c of the TFT control logic hierarchy 200 may be in electrical communication with the local I/O device 212 and the local stack decoder 202. The third MUX 204c may be activated by one or more signals received from the local stack decoder 202 and may be configured and operable to receive digital data values generated by the local I/O device 212 and thereby generate a global data signal 228. The global data signal 228 may be forwarded to one or more overlay outside devices 236 (e.g., controllers).
According to embodiments of the present disclosure, one or more of the components of the TFT control logic hierarchy 200 (e.g., one or more of the local stack decoder 202, the MUX 204 (first MUX 204a, second MUX 204b, third MUX 204c), the column decoder 206, the row decoder 208, the sense amplifier 210, the local I/O device 212, the WL driver 214, the column repair device 216, the row repair device 218, the ECC device 220, the memory test device 222, the self-refresh/wear leveling device 224) may employ one or more TFT CMOS devices that present one of PMOS transistors and NMOS transistors on top of the other of PMOS transistors and NMOS transistors. In other words, the PMOS transistor may be vertically displaced from the NMOS transistor (e.g., positioned above or below). For example, a first substack structure may contain PMOS transistors arranged in a pattern, group, arrangement, array, etc. and may be located over a second substack structure containing NMOS transistors arranged in a pattern, group, arrangement, array, etc. The PMOS transistor may be a vertical PMOS transistor having a vertically oriented (e.g., in a direction perpendicular to a major surface of a substrate (e.g., base control logic structure 102) on which the first substack is formed) channel region. In other embodiments, the PMOS transistor may be a planar PMOS transistor having a laterally oriented channel region. The NMOS transistor may be a vertical NMOS transistor, a planar NMOS transistor, or a combination thereof.
Accordingly, one or more components of at least one of the TFT control logic levels (e.g., the first TFT
Accordingly, a TFT control logic assembly according to an embodiment of the present disclosure includes a TFT control logic device selected from the group consisting of: decoders, sense amplifiers, word line drivers, repair devices, memory test devices, multiplexers, error checking and correction devices, and self-refresh/wear leveling devices. At least one of the TFT control logic devices includes a first substack structure including one of an NMOS transistor and a PMOS transistor, the first substack structure being disposed over a second substack structure including the other of the NMOS transistor and the PMOS transistor. The NMOS transistors may each include a vertically oriented channel region and may be referred to as vertical NMOS transistors. Similarly, the PMOS transistors may each include a vertically oriented channel region and may be referred to as vertical PMOS transistors. In other embodiments, one or both of the NMOS transistors may include a laterally extending channel region and may be referred to as a planar NMOS transistor, and each of the PMOS transistors may include a laterally extending channel region and may be referred to as a planar PMOS transistor. The NMOS transistors and PMOS transistors may be arranged as bottom-gate transistors, top-gate transistors, double-gate transistors, gate-all-around (GAA) transistors, saddle-gate transistors, or other transistor structures.
Accordingly, in some embodiments, a method of operating a semiconductor device includes: controlling a function of a stacked structure having a plurality of stacked layers using a control logic level of the plurality of stacked layers, each of the stacked structures including a memory cell, the control logic level each including at least one control logic device including a first sub-stacked structure over a second sub-stacked structure, the first sub-stacked structure including a transistor having one of a P-type channel region and an N-type channel region, the second sub-stacked structure including a transistor having the other of the P-type channel region and the N-type channel region; and controlling additional functions of the stacked structure using a base control logic structure in electrical communication with the control logic hierarchy of the stacked structure.
Fig. 3A is a simplified cross-sectional view of a TFT control logic level 300 including a TFT CMOS circuit according to an embodiment of the present disclosure. FIG. 3B is a simplified cross-sectional view of the TFT control logic level taken along section line B-B of FIG. 3A. Fig. 3C is a simplified perspective view of a single CMOS TFT inverter 300' according to an embodiment of the present disclosure. The CMOS TFT inverter 300' may include a portion of at least one TFT control logic level (e.g., at least one of the first TFT
TFT control logic level 300 may include vertically stacked sub-stacked structures (e.g., levels), such as a first sub-stacked (e.g., sub-level) structure 301 disposed above a substrate 305 and a second sub-stacked (e.g., sub-level) structure 302 above the first stacked structure 301. The substrate 305 may include, for example, one or more of the stack layers (e.g., the first stack layer 104 (fig. 1) and the base control logic level 102 (fig. 1)). The first sub-stack structure 301 may be in electrical communication with the second sub-stack structure 302 via an output structure 303, as will be described herein. The first substack structure 301 may include vertical NMOS transistors 310 (e.g., an array of vertical NMOS transistors 310) that each include a semiconductor pillar 311 that includes an N-type source region 310a, an N-type drain region 310c, and a P-type channel region 310b between the N-type source region 310 and the N-type drain region 310 c. The N-type source region 310a and the N-type drain region 310c of the vertical NMOS transistor 310 may each be independently formed of and include at least one N-type conductive material. As used herein, an N-type conductive material may comprise, for example, polysilicon doped with at least one N-type dopant (e.g., arsenic ions, phosphorous ions, antimony ions). The P-type channel region 310b of the vertical NMOS transistor 310 may be formed of and include at least one P-type conductive material. As used herein, a P-type conductive material may comprise, for example, polysilicon doped with at least one P-type dopant (e.g., boron ions).
The second sub-stack structure 302 may include vertical PMOS transistors 320 (e.g., an array of vertical PMOS transistors) each including a semiconductor pillar 321 including a P-type source region 320a, a P-type drain region 320c, and an N-type channel region 320b between the P-type source region 320a and the P-type drain region 320 c. The P-type source region 320a and the P-type drain region 320c may include a P-type conductive material and may include the same material as the P-type channel material 310b of the vertical NMOS transistor 310. The N-type channel region 320b may include an N-type conductive material and may include the same material as one or both of the N-type source region 310a and the N-type drain region 310c of the vertical NMOS transistor 310.
The vertical NMOS transistor 310 may exhibit any desired dimensions (e.g., channel width, channel thickness, channel length). By way of non-limiting example, in some embodiments, the channel width (extending in the y-direction) of each of the semiconductor pillars 310 may be in the range of about 20nm to about 200nm, and the channel thickness (extending in the x-direction) of each of the semiconductor pillars 310 may be in the range of about 10nm to about 50 nm. In some embodiments, the channel length (extending in the z-direction) may be in the range of about 50nm to about 200 nm. Similarly, the vertical PMOS transistor 320 may exhibit any desired dimensions (e.g., channel width, channel thickness, channel length). By way of non-limiting example, in some embodiments, the channel width (extending in the y-direction) of each of the semiconductor pillars 311 may be in the range of about 20nm to about 200nm, and the channel thickness (extending in the x-direction) of each of the semiconductor pillars 311 may be in the range of about 10nm to about 50 nm. In some embodiments, the channel length (extending in the z-direction) is in the range of about 50nm to about 200 nm. In some embodiments, the size of the vertical NMOS transistor 310 is substantially the same as the size of the vertical PMOS transistor 320.
In some embodiments, at least one (e.g., each) of the vertical NMOS transistors 310 of the first substack structure 301 may be electrically coupled to and associated with a corresponding vertical PMOS transistor 320 through the output structure 303 to form a CMOS circuit (e.g., a CMOS inverter). The vertical PMOS transistor 320 associated with a particular vertical NMOS transistor 310 may be positioned directly above the particular vertical NMOS transistor 310. However, the present disclosure is not so limited, and the vertical PMOS transistor 320 may not be positioned directly above and may be laterally offset from the associated vertical NMOS transistor 310.
The vertical NMOS transistors 310 may each include a source contact 312 in electrical communication with an N-type source region 310 a. The source contact 312 may be in electrical communication with a Ground (GND) structure 314.
The vertical NMOS transistor 310 may further include a drain contact 316 in electrical communication with the N-type drain region 310 c. Drain contact 316 may provide electrical communication between N-type drain region 310c and output structure 303.
In some embodiments, at least some of the vertical NMOS transistors 310 may not be in electrical communication with the output structure 303. In some such embodiments, at least some of the vertical NMOS transistors 310 are electrically isolated from the output structure 303 by the dielectric material 319. In still other embodiments, substantially all of the vertical NMOS transistors are in electrical communication with output structure 303.
The vertical PMOS transistors 320 may each include a source contact 322 in electrical communication with the P-type source region 320 a. The source contact 322 may be connected to VDDStructure (also referred to as a "drain supply voltage" structure) 324 is in electrical communication. Thus, the source contact 322 may be in the P-type source regions 320a and VDDElectrical communication is provided between the structures 324.
In some embodiments, at least some of the vertical PMOS transistors 320 may not be aligned with VDDThe structure 324 is in electrical communication. In some such embodiments, at least some of the vertical PMOS transistors 320 may be formed, for example, by dielectric material 348 and VDDStructure 324 is electrically isolated and the dielectric material may comprise, for example, silicon dioxide, silicon nitride, silicon oxynitride, or combinations thereof. In other embodiments, substantially all of the vertical PMOS transistors 320 are connected to VDDThe structure 324 is in electrical communication.
The vertical PMOS transistor 320 may further include a drain contact 326 in electrical communication with the P-type drain region 320 c. Drain contact 326 may provide electrical communication between P-type drain region 320c and output structure 303. Thus, each of the vertical NMOS transistors 310 may be in electrical communication with a corresponding vertical PMOS transistor 320 through a corresponding drain contact 316, 326.
With continued reference to fig. 3A-3C, the vertical NMOS transistors 310 may each include a gate dielectric material 317 and a gate electrode 318 over the gate dielectric material 317. The gate electrode 318 is shown in dashed lines in fig. 3B to illustrate the relative position of the gate electrode 318, but it is understood that the gate electrode 318 will not be in the cross-sectional view of fig. 3B. The gate dielectric material 317 of each vertical NMOS transistor 310 may extend over at least the sidewalls of the semiconductor pillar 311 (e.g., over the sidewalls of the N-type source region 310a, the P-type channel region 310b, and the N-type drain region 310 c). In some embodiments, the gate dielectric material 317 extends over the sidewalls of the source contact 312 and the drain contact 316.
The gate dielectric material 317 may comprise an electrically insulating material such as phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, a nitride material (e.g., silicon nitride (Si)3N4) Silicon oxynitride (e.g., silicon oxynitride)), another gate dielectric material, a dielectric carbon nitride material (e.g., silicon carbonitride (SiCN)), a dielectric silicon oxynitride material (e.g., silicon oxycarbonitride (sinx))(SiOCN)) or combinations thereof.
The gate electrode 318 may extend over at least the sidewalls of the P-type channel region 310b, and in some embodiments, may extend over at least a portion of each of the N-type source region 310a and the N-type drain region 310 c. However, the present disclosure is not limited thereto, and in other embodiments, the gate electrode 318 may not extend over sidewalls of the N-type source region 310a and the N-type drain region 310c and may extend only over sidewalls of the P-type channel region 310 b.
The gate electrode 318 can comprise a conductive material. As used herein, "conductive material" may refer to one or more of the metals: such as tungsten, titanium, nickel, platinum, ruthenium, aluminum, copper, molybdenum, gold, metal alloys, metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, conductively-doped silicon germanium, etc.), polysilicon, other materials exhibiting electrical conductivity, or combinations thereof. The conductive material may include at least one of: titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), elemental titanium (Ti), elemental platinum (Pt), elemental rhodium (Rh), elemental ruthenium (Ru), elemental molybdenum (Mo), elemental iridium (Ir), iridium oxide (IrO)x) Elemental ruthenium (Ru), ruthenium oxide (RuO)x) Elemental tungsten (W), elemental aluminum (Al), elemental copper (Cu), elemental gold (Au), elemental silver (Ag), polysilicon, alloys thereof, or combinations thereof. In some embodiments, gate electrode 318 comprises titanium nitride.
The gate electrode 318 can be formed to exhibit any desired dimensions (e.g., length, width, height). By way of non-limiting example, the width of each gate electrode 318 may be in the range of about 1nm to about 30nm (e.g., about 5nm to about 20nm, or about 5nm to about 10nm), and the height may be in the range of about 5nm to about 100nm (e.g., about 10nm to about 50nm, or about 20nm to about 30 nm).
Each of the vertical PMOS transistors 320 may include a gate dielectric material 327 and a gate electrode 328 over the gate dielectric material 327. The gate dielectric material 327 of each of the PMOS transistors 320 may extend over at least sidewalls of the semiconductor pillars 321 (e.g., over sidewalls of the P-type source regions 320a, the N-type channel regions 320b, and the P-type drain regions 320 c). In some embodiments, the gate dielectric material 327 extends over sidewalls of the source contact 322 and the drain contact 326. In still other embodiments, the gate dielectric material 327 extends over sidewalls of only one of the source contact 322 and the drain contact 326.
The gate electrode 328 may extend over at least a sidewall of the N-type channel region 320b, and in some embodiments, may extend over at least a portion of a sidewall of each of the P-type source region 320a and the P-type drain region 320 c. However, the present disclosure is not limited thereto, and in other embodiments, the gate electrode 328 may not extend over the sidewalls of the P-type source region 320a and the P-type drain region 320 c.
The gate dielectric material 327 and the gate electrode 328 may comprise the same materials described above with reference to the gate dielectric material 317 and the gate electrode 318, respectively. In some embodiments, the gate dielectric material 327 and the gate electrode 328 comprise the same material as the gate dielectric material 317 and the gate electrode 318, respectively.
In some embodiments, a gate contact 340 may electrically connect the gate electrode 318 of at least one vertical NMOS transistor 310 to the gate electrode 328 of at least one corresponding vertical PMOS transistor 320. The gate contact 340 may comprise a conductive material, such as titanium, tungsten, copper, aluminum, gold, silver, platinum, rhodium, ruthenium, molybdenum, iridium, titanium nitride, tantalum nitride, titanium aluminum nitride, polysilicon, another conductive material, or a combination thereof. In other embodiments, at least some of the gate electrodes 318 may be electrically isolated from the gate contact 340 by a dielectric material. In some embodiments, at least one other gate contact 345 comprising a conductive material may be electrically coupled to VDDStructure 324 and may electrically couple at least one of the gate electrodes 318, 328 to a word line driver, such as word line driver 214 (fig. 2).
Adjacent vertical NMOS transistors 310 may be electrically isolated from each other via one or more dielectric materials 343 (fig. 3A). Similarly, adjacent vertical PMOS transistors 320 may be electrically isolated from each other by one or more dielectric materials 344 (fig. 3A). The vertical NMOS transistor 310 and the vertical PMOS transistor 320 may be isolated from each other by another dielectric material 342. Each of the dielectric materials 342, 343, 344 can include an electrically insulating material, such as silicon dioxide, silicon nitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, another electrically insulating material, or a combination thereof.
In some embodiments, the liner material 332 may be over sidewalls of the gate dielectric material 317, 327 and the gate electrode 318, 328 between the adjacent vertical NMOS transistor 310 and the adjacent vertical PMOS transistor 320, respectively. The liner material 332 may comprise, for example, silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof.
Referring to fig. 3B, liner material 313 may be located over the sides of vertical NMOS transistor 310 and may be located over the sidewalls of, for example, source contact 312, N-type source region 310a, P-type channel region 310B, N-type drain region 310c, and drain contact 316. In some embodiments, the liner material 313 can be located over sidewalls of the GND structures 314 and sidewalls of the output structures 303.
Similarly, liner material 323 may be located over sidewalls of vertical PMOS transistor 320. The liner material 323 may be located over sidewalls of the P-type drain region 320c, the N-type channel region 320b, and the P-type source region 320 a. In some embodiments, liner material 323 is over the sidewalls of source contact 322.
Referring to fig. 3C, input structure 334 may be electrically connected to at least one of gate electrode 318 and gate electrode 328, such as through contact structure 336.
Each of GND structure 314, VDD structure 324, output structure 303, and input structure 334 of TFT control logic level 300 may exhibit a conventional configuration (e.g., conventional size, conventional shape, conventional conductive material composition, conventional material distribution, conventional orientation, conventional arrangement) that is not described in detail herein. Each of GND structure 314, VDD structure 324, output structure 303 and input structure 334 may comprise a suitable conductive material.
Although FIGS. 3A-3C show the second substack 302 including the vertical PMOS transistor 320 in the first substack including the vertical NMOS transistor 310Directly above the sub-stack 301, but the disclosure is not so limited. In other embodiments, the first sub-stack structure 301 is located above the second sub-stack structure 302 such that the vertical NMOS transistor 310 is located above the vertical PMOS transistor 320. In some such embodiments, VDDThe location of structure 324 and the location of GND structure 314 may be located at suitable locations, as will be understood by those of ordinary skill in the art.
Accordingly, the TFT control logic level of the semiconductor device may include a first sub-stack structure of the vertical NMOS transistor and the vertical PMOS transistor and a second stack structure of the other of the vertical NMOS transistor and the vertical PMOS transistor on the first sub-stack structure. The first and second sub-stack structures may be arranged to include a plurality of CMOS circuits, such as a plurality of CMOS inverters.
Fig. 4-12B are simplified perspective views of additional TFT CMOS devices that may be included in the TFT control logic levels of the present disclosure (e.g., the TFT control logic level 200 of fig. 2; one or more of the first TFT
Fig. 4 is a simplified perspective view of a dual-
The first
The first
The
The first
The first
The
The N-
The P-
P-type source regions 4 of respective first and second
The
The
Thus, the dual-
Although fig. 4 has been described and shown as including only a single two-
Fig. 5 is a simplified perspective view of a
As shown in fig. 5, the
The
The second
The
The first
The P-
The P-
The
The
Thus, the
Fig. 6 is a simplified perspective view of a CMOS pass-gate 600 according to an embodiment of the present disclosure. The CMOS pass gate 600 includes a CMOS circuit 605, an output structure 603, an input structure 624, a first gate input structure 672, and a second gate input structure 670.
The CMOS transfer pass gate 600 may include a first sub-stack structure 601 and a second sub-stack structure 602 vertically disposed above the first sub-stack structure 601. The first sub-stack structure 601 may include a vertical NMOS transistor 610, and the second sub-stack structure 602 may include a plurality of (e.g., more than one) vertical PMOS transistors, such as a first vertical PMOS transistor 620, a second vertical PMOS transistor 650, and a third vertical PMOS transistor 660. Accordingly, the CMOS circuit 605 of the CMOS transmission pass gate 600 may include a vertical NMOS transistor 610 in the first sub-stack structure 601 and a plurality of vertical PMOS transistors in the second sub-stack structure 602.
Multiple vertical PMOS transistors 620, 650, 660 may be employed to balance the drive strength of the different transistors (e.g., vertical NMOS transistor 610, first vertical PMOS transistor 620, second vertical PMOS transistor 650, and third vertical PMOS transistor 660) of the CMOS circuit 605 in order to maximize noise margin and obtain symmetric characteristics. Although fig. 6 shows the CMOS circuit 605 including a single vertical NMOS transistor 610 and three vertical PMOS transistors, the disclosure is not so limited. In other embodiments, the CMOS circuit 605 includes a different number of vertical PMOS transistors, e.g., a single vertical PMOS transistor or two vertical PMOS transistors.
The vertical NMOS transistor 610 of the CMOS circuit 605 may include an N-type source region 610a, an N-type drain region 610c, and a P-type channel region (not shown in the view of fig. 6) between the N-type source region 610a and the N-type drain region 610 c. In addition, each of the first, second, and third vertical PMOS transistors 620, 650, and 660 individually includes a P-type source region 620a, 650a, 660a, a P-type drain region 620c, 650c, 660c, and an N-type channel region 620b, 650b, 660b between the respective P-type drain region and P-type source region.
The vertical NMOS transistor 610 may include a gate electrode 618 disposed around at least a side of the P-type channel region. Gate electrode 618 may be in electrical communication with first gate input structure 672 via a gate contact 619, which may comprise a suitable conductive material.
The first vertical PMOS transistor 620 may include a gate electrode 628 disposed around at least a side of the N-type channel region 620b, the second vertical PMOS transistor 650 may include a gate electrode 658 disposed around at least a side of the N-type channel region 650b, and the third vertical PMOS transistor 660 may include a gate electrode 668 disposed around at least a side of the N-type channel region 660 b. In some embodiments, each of the gate electrodes 628, 658, 668 are vertically aligned with one another. Each of the gate electrodes 628, 658, 668 may be in electrical communication with the second gate input structure 670 via respective gate contacts, such as respective first, second, and third gate contacts 636, 637, 638, each of which may comprise a suitable conductive material.
The input structure 624 may be in electrical communication with each of the vertical NMOS transistor 610, the first vertical PMOS transistor 620, the second vertical PMOS transistor 650, and the third vertical PMOS transistor 660. By way of non-limiting example, the input structure 624 may include a first portion in electrical communication with the vertical NMOS transistor 610 through a conductive source contact 680. The first portion of the input structure 624 may be in electrical communication with the second portion of the input structure 624 through the conductive contact structure 682. The second portion may be positioned in the second sub-stack structure 602 and may be in electrical communication with each of the first, second, and third vertical PMOS transistors 620, 650, and 660 through respective source contacts 622, 652, and 662, each of which may include a conductive material.
The output structure 603 may be in electrical communication with each of the vertical NMOS transistor 610, the first vertical PMOS transistor 620, the second vertical PMOS transistor 650, and the third vertical PMOS transistor 660. By way of non-limiting example, output structure 603 may be in electrical communication with vertical NMOS transistor 610 through drain contact 616. Output structure 603 may be in electrical communication with first vertical PMOS transistor 620 via drain contact 626, second vertical PMOS transistor 650 via drain contact 656, and third vertical PMOS transistor 660 via drain contact 666. Each of the drain contacts 616, 626, 656, 666 may include a conductive material.
The output structure 603, the input structure 624, the first gate input structure 672, and the second gate input structure 670 of the CMOS pass-through gate 600 may exhibit conventional configurations (e.g., conventional size, conventional shape, conventional conductive material composition, conventional material distribution, conventional orientation, conventional arrangement) that are not described in detail herein. Each of output structure 603, input structure 624, first gate input structure 672, and second gate input structure 670 can comprise a suitable conductive material.
Fig. 7 is a simplified perspective view of a balanced dual-input NAND circuit 700, according to an embodiment of the present disclosure. The balanced dual-input NAND circuit 700 includes a CMOS circuit 705, an additional CMOS circuit 715, a GND structure 714, VDDStructure 724, interconnect structure 707, output structure 703, first input structure 770, and second input structure 774.
As shown in fig. 7, a balanced dual-input NAND circuit 700 includes a first sub-stack structure 701 and a second sub-stack structure 702 located above the first stack structure 701.
The balanced dual-input NAND circuit 700 may be similar to the dual-
The vertical NMOS transistor 710 of the CMOS circuit 705 includes an N-type source region 710a, an N-type drain region 710c, and a P-type channel region 710b between the N-type source region 710a and the N-type drain region 710 c. In addition, each of the vertical PMOS transistors 720 of the CMOS circuit 705 includes a P-type source region 720a, a P-type drain region 720c, and an N-type channel region 720b between the P-type source region 720a and the P-type drain region 720 c.
The vertical NMOS transistor 711 of the CMOS circuit 715 includes an N-type source region 711a, an N-type drain region 711c, and a P-type channel region 711b between the N-type source region 711a and the N-type drain region 711 c. In addition, each of the vertical PMOS transistors 750 of the CMOS circuit 715 includes a P-type source region 750a, a P-type drain region 750c, and an N-type channel region 750b between the P-type source region 750a and the P-type drain region 750 c.
The vertical NMOS transistor 710 may further include a gate electrode 718 disposed around at least two sides of the P-type channel region 710 b. The vertical NMOS transistor 711 may further include a gate electrode 717 disposed around at least a side of the P-type channel region 711 b.
The gate electrode 728 may extend along and be disposed around at least a side of the P-type channel region 720b of each of the vertical PMOS transistors 720. A gate electrode 728 may be shared between each of the vertical PMOS transistors 720. Similarly, gate electrode 758 may extend along and be disposed around at least a side of P-type channel region 750b of each of vertical PMOS transistors 750 and may be shared between each of vertical PMOS transistors 750.
The vertical NMOS transistor 710 may be in electrical communication with the GND structure 714 through a source contact 712. The vertical NMOS transistor 710 may further be in electrical communication with the interconnect structure 707 through a drain contact 716. The interconnect structure 707 may be in electrical communication with the vertical NMOS transistor 711 of the CMOS circuit 715 through a source contact (not shown in the view shown in fig. 7) electrically connected to the N-type source region 711 a.
Vertical NMOS transistor 711 may be in electrical communication with output structure 703 through drain contact 760. Output structure 703 may further be in electrical communication with each of vertical PMOS transistor 720 and vertical PMOS transistor 750 through respective drain contacts 726, 756 that are electrically connected to respective P-type drain regions 720c, 750c of vertical PMOS transistor 720 and vertical PMOS transistor 750. Each of the drain contacts 760, 726, 756 may comprise a conductive material.
Vertical PMOS transistor 720 and vertical PMOS transistor 750 may be electrically coupled to a P-type source region 720a of each of vertical PMOS transistors 720A respective source contact 722 and a respective source contact 752 and V electrically coupled to the P-type source region 750a of each of the vertical PMOS transistors 750DDThe structure 724 is in electrical communication. Each of the source contacts 722, 752 may include a conductive material.
The gate electrode 728 of the vertical PMOS transistor 720 may be in electrical communication with the first input structure 770 through a gate contact 772 that includes a conductive material. The gate electrode 728 may further be in electrical communication with the gate electrode 718 of the vertical NMOS transistor 710 through a gate contact 740 comprising a conductive material.
The gate electrode 758 of the vertical PMOS transistor 750 may be in electrical communication with the second input structure 774 through a gate contact 776 comprising a conductive material. The gate electrode 758 may further be in electrical communication with the gate electrode 717 of the vertical NMOS transistor 711 via a gate contact comprising a conductive material 778 extending between the gate electrode 758 and the gate electrode 717.
GND structure 714, V of balanced dual-input NAND circuit 700DDStructure 724, interconnect structure 707, output structure 703, first input structure 770, and second input structure 772 may exhibit conventional configurations (e.g., conventional dimensions, conventional shapes, conventional conductive material compositions, conventional material distributions, conventional orientations, conventional arrangements) that are not described in detail herein. GND structure 714, VDDEach of structure 724, interconnect structure 707, output structure 703, first input structure 770, and second input structure 772 may comprise a suitable conductive material.
Figure 8A is a simplified perspective view of a
The first stacked structure 801 may include a plurality of
The
The
The
The
Figure 8B is a simplified perspective view of another embodiment of a ring oscillator 800' according to an embodiment of the present disclosure. The ring oscillator 800' may include
Thus, the
Although fig. 3-8B have been shown as including a first sub-stack structure comprising an array of vertical NMOS transistors or vertical PMOS transistors and a second sub-stack structure over the first sub-stack structure comprising an array of the other of vertical NMOS transistors or vertical PMOS transistors, the disclosure is not so limited. In other embodiments, one or both of the first substack and the second substack may comprise a planar NMOS transistor array and/or a planar PMOS transistor array.
Referring to fig. 9, a balanced dual-input NAND circuit 900 is depicted that includes NMOS and PMOS transistors with planar channel regions, in accordance with an embodiment of the present disclosure. The balanced dual-input NAND circuit 900 includes GND structures 914, VDDStructure 924, output structure 903, first input structure 970, and second input structure 974.
As shown in fig. 9, a balanced dual-input NAND circuit 900 includes a first sub-stack structure 901 and a second sub-stack structure 902 located above the first sub-stack structure 901.
Balanced dual-input NAND circuit 900 may include a first CMOS circuit including a planar NMOS transistor 910 in electrical communication with a plurality of (e.g., more than one) planar PMOS transistors 920. The second CMOS circuit of the balanced dual-input NAND circuit 900 can include a planar NMOS transistor 911 in electrical communication with a plurality (e.g., more than one) of planar PMOS transistors 950. In some embodiments, the first CMOS circuit comprises one planar NMOS transistor 910 and three planar PMOS transistors 920, and the second CMOS circuit comprises one planar NMOS transistor 911 and three planar PMOS transistors 950. In further embodiments, the first CMOS circuit and/or the second CMOS circuit each include a different number of respective planar PMOS transistors 920 and planar PMOS transistors 950. For example, the first CMOS circuit and/or the second CMOS circuit may include two planar PMOS transistors 920 and two planar PMOS transistors 950, respectively.
The planar NMOS transistor 910 includes an N-type source region 910a, an N-type drain region 910c, and a P-type channel region 910b between the N-type source region 910a and the N-type drain region 910 c. Each of the planar PMOS transistors 920 includes a P-type source region 920a, a P-type drain region 920c, and an N-type channel region 920b between the P-type source region 920a and the P-type drain region 920 c. In the view of fig. 9, portions of the P-type source region 920, the P-type drain region 920c, and the N-type channel region 920b under the second input structure 974 are shown in dashed lines.
The planar NMOS transistor 911 comprises an N-type source region 911a, an N-type drain region 911c, and a P-type channel region 911b disposed between the N-type source region 911a and the N-type drain region 911 c. Each of the planar PMOS transistors 950 includes a P-type source region 950a, a P-type drain region 950c, and an N-type channel region 950b located between the P-type source region 950a and the P-type drain region 950 c. In the view of fig. 9, portions of the P-type source region 950a, the P-type drain region 950c, and the N-type channel region 950b under the second input structure 974 are shown in dashed lines.
The planar NMOS transistor 910 includes a gate electrode 918 disposed over a P-type channel region 910 b. In the view shown in fig. 9, gate electrode 918 is located over P-type channel region 910b, and the associated planar NMOS transistor 910 may be referred to as a so-called "top-gate" transistor. In other embodiments, gate electrode 918 may underlie P-type channel region 910b, and planar NMOS transistor 910 may be referred to as a so-called "bottom-gate" transistor. In still other embodiments, planar NMOS transistor 910 may include a gate electrode located above P-type channel region 910b and below P-type channel region 910b, and may include, for example, a double gate transistor. In further embodiments, NMOS transistor 910 may include a gate electrode 918 disposed on one or more sides of P-type channel region 910 b.
The planar NMOS transistor 911 may include a gate electrode 917 located over the P-type channel region 911 b. In other embodiments, the planar NMOS transistor 911 includes a gate electrode located below the P-type channel region 911b, gate electrodes located above and below the P-type channel region 911b, or gate electrodes on one or more sides of the P-type channel region 911 b.
A gate electrode 928 may be disposed over the N-type channel region 920b of each of the planar PMOS transistors 920. The gate electrode 928 may be shared between the set of planar PMOS transistors 920. Similarly, a gate electrode 958 may be disposed over the N-type channel region 950b of each of the planar PMOS transistors 950, and the gate electrodes 958 may be shared between the set of planar PMOS transistors 950. As described above with reference to the gate electrodes 917, 918, the gate electrodes 928, 958 may be located above the respective N-type channel regions 920b, 950b, or may be located below the respective N-type channel regions 920b, 950 b. In other embodiments, planar PMOS transistor 920 and planar PMOS transistor 950 may each include a gate electrode located above respective N-type channel region 920b, 950b and below respective N-type channel region 920b, 950 b. In still other embodiments, each of planar PMOS transistor 920 and planar PMOS transistor 950 may each include a gate electrode on one or more sides of the respective N-type channel region 920b, 950 b.
The planar NMOS transistor 911 may be in electrical communication with the GND structure 914 through a source contact 913, which may include a conductive material. Planar NMOS transistor 911 may further be in electrical communication with planar NMOS transistor 910 through an N-type source region 911a, which may be in electrical communication with an N-type drain region 910c of planar NMOS transistor 910.
Planar NMOS transistor 910 may be in electrical communication with output structure 903 through drain contact 960. Output structure 903 may further be in electrical communication with each of planar PMOS transistor 920 and planar PMOS transistor 950 through drain contact 956, which may be electrically coupled to P-type drain regions 920c, 950c of respective planar PMOS transistor 920 and planar PMOS transistor 950. Each of the drain contacts 956, 960 may comprise a conductive material.
Planar PMOS transistor 920 and planar PMOS transistor 950 may be electrically coupled to respective source contact 922 of P-type source region 920a of each of planar PMOS transistors 920 and to respective source contact 952 and V of P-type source region 950a of each of planar PMOS transistors 950DDThe structure 924 is in electrical communication. Each of the source contacts 922, 952 may comprise a conductive material.
Gate electrode 928 of planar PMOS transistor 920 may be in electrical communication with first input structure 970 through gate contact 972. A conductive interconnect structure 941 may be in electrical communication with the gate electrode 928 through a gate contact 943. Conductive interconnect structure 941 may be in electrical communication with gate electrode 918 of planar NMOS transistor 910 through a gate contact 940 electrically coupled to conductive interconnect structure 941 and gate electrode 918.
The gate electrode 958 of the planar PMOS transistor 950 may be in electrical communication with the second input structure 974 through a gate contact 976. The gate electrode 958 can further be in electrical communication with a gate electrode 917 of the planar NMOS transistor 911 through a gate contact 980 that is in electrical communication with the gate electrode 958 and a conductive interconnect structure 979 that is, in turn, in electrical communication with a gate contact 978 that is in electrical communication with the gate electrode 917.
The GND structure 914, the VDD structure 924, the output structure 903, the first input structure 970, and the second input structure 974 of the balanced dual-input NAND circuit 900 can exhibit conventional configurations (e.g., conventional size, conventional shape, conventional conductive material composition, conventional material distribution, conventional orientation, conventional arrangement) that are not described in detail herein. Each of GND structure 914, VDD structure 924, output structure 903, first input structure 970, and second input structure 974 of balanced dual-input NAND circuit 900 can include a suitable conductive material.
Although fig. 9 shows the second sub-stack structure 902 including the lateral PMOS transistor being located above the first sub-stack structure 901 including the lateral NMOS transistor 910, the disclosure is not limited thereto. In other embodiments, the array of lateral NMOS transistors 910 may be located above the array of lateral PMOS transistors 920.
Although the NMOS and PMOS transistors of fig. 3A-9 have been described and illustrated as including a vertical channel region or a horizontal channel region and having a particular orientation, the disclosure is not so limited. In other embodiments, each of the NMOS transistor and the PMOS transistor may comprise any transistor structure known in the art, such as a bottom-gate transistor, a top-gate transistor, a double-gate transistor, a gate-all-around (GAA) transistor, a single-gate transistor, a transistor containing a saddle-shaped channel region, or other transistor structure.
Accordingly, in at least some embodiments, a semiconductor device includes a stacked structure including stacked layers, each stacked layer of the stacked structure including: a memory element hierarchy comprising memory elements; and a control logic hierarchy in electrical communication with the memory element hierarchy, the control logic hierarchy comprising: a first sub-stack structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region; and a second sub-stack structure located over the first sub-stack structure, the second sub-stack structure comprising a second number of transistors, the second number of transistors comprising the other of the P-type channel region and the N-type channel region.
Accordingly, in some embodiments, a semiconductor device includes a stacked structure including a plurality of stacked layers. Each stack of the stacked structure comprises: a memory element hierarchy comprising memory elements; an access device hierarchy comprising access devices electrically connected to the memory elements of the memory element hierarchy; and a control logic hierarchy. The control logic hierarchy includes: a first sub-stack structure comprising a first number of transistors, each transistor of the first number of transistors comprising one of an N-type channel region or a P-type channel region; and a second sub-stack structure over the first sub-stack structure and including a second number of transistors, each transistor of the second number of transistors including the other of the N-type channel region or the P-type channel region.
Accordingly, in some embodiments, a semiconductor device includes: a first stack comprising a first memory element level, a first access device level, and a first control logic level; and a second stacked structure over the first stacked structure, the second stacked structure comprising a second memory element level, a second access device level, and a second control logic level, wherein at least one of the first control logic level and the second control logic level comprises at least one CMOS device in electrical communication with a base control logic structure.
Referring to fig. 10A-10Z, a method of forming a TFT control logic level (e.g., TFT
Referring to fig. 10A, a
An N-
A
Fig. 10B is a cross-sectional view of the
Referring to fig. 10C,
Fig. 10D is a cross-sectional view of the
Although fig. 10D shows substantially all of the N-
Referring to fig. 10E and 10F, a
The
After forming
Referring to fig. 10F, the
Although fig. 10E and 10F show the
Referring to fig. 10G, a
With continued reference to fig. 10G, in some embodiments, the
In some embodiments, the
Although fig. 10G shows the
Although fig. 10A-10G have been described as including
Referring to fig. 10H and 10I, a conductive material may be formed over the
Referring to fig. 10J,
A dielectric material 1025 may be formed between the
Fig. 10K is a cross-sectional view of the semiconductor device of fig. 10J taken along section line K-K of fig. 10J. In some embodiments, a
Referring to fig. 10L, a second
Referring to fig. 10M, the
After forming
Referring to fig. 10N, each of the rows of vertical
Referring to fig. 10O and 10P, a
A
Referring to fig. 10Q, sacrificial material 1029 (fig. 10P) can be removed and replaced with
Although fig. 10Q has been described as including removing
Although fig. 10L-10P have been described as including
With continued reference to fig. 10Q, the
A dielectric material 1044 may be formed in regions between adjacent vertical
Referring to fig. 10R, one or
In some embodiments, all of the
Referring to fig. 10S and 10T, a
Referring to fig. 10U and 10V, the
Referring to fig. 10W and 10X, a conductive material may be formed and patterned over the
Since
Referring to fig. 10Y and 10Z, a
Forming the
Accordingly, in some embodiments, a method of forming a semiconductor device includes forming a stack of structures over a substrate, wherein forming the stack of structures includes forming each stack of structures to include a memory element level and a control logic level. Forming at least one control logic level of the at least one stack structure comprises: forming a first sub-stack structure comprising first transistors, at least some of the first transistors comprising one of an N-type channel region or a P-type channel region; forming a second sub-stack structure comprising second transistors over the first sub-stack structure, at least some of the second transistors comprising the other of the N-type channel region or the P-type channel region; and electrically connecting the at least some of the first transistors to the at least some of the second transistors to form a device.
Although fig. 3-8B and 10A-10Z have been described and shown as including a transistor structure including a dual gate structure in which the channel region of an NMOS transistor and the channel region of a PMOS transistor include gates on both sides thereof, the present disclosure is not limited thereto. In other embodiments, the NMOS transistors and PMOS transistors of the semiconductor device may be arranged as bottom-gate transistors, top-gate transistors, gate-all-around (GAA) transistors, saddle-gate transistors, or other transistor structures.
Fig. 11A and 11B are simplified cross-sectional views of a portion of a TFT control logic level 200 (fig. 2) including vertical transistors arranged as single-gate transistors. Referring to fig. 11A, a portion of a
The
A
The
A
A
With continued reference to fig. 11A and 11B, each of the
Referring to fig. 12A and 12B, a portion of a
The
The
The
A
Thus, in some embodiments, the devices described above with reference to fig. 3-8B and 10A-10Z may include one or more
In further embodiments, the devices described above with reference to fig. 3 to 10Z may comprise a transistor structure comprising so-called saddle channel regions. In some such embodiments, the one or more transistors (e.g., one or more NMOS transistors, one or more PMOS transistors, or a combination thereof) may comprise transistors that include saddle-shaped channels, with channel regions shaped and configured such that current flows in both a lateral direction and a vertical direction.
Although fig. 3A-12B have been shown to include only a particular arrangement of NMOS and PMOS transistors, the disclosure is not so limited. In some embodiments, the devices and structures described above with reference to fig. 3A-12B may include one or more NMOS transistors and/or one or more PMOS transistors in electrical communication with a CMOS device not shown. In some embodiments, the devices and structures described above with reference to fig. 3A-12B may include one or more NMOS transistors and/or one or more PMOS transistors that are not in electrical communication with any other device.
Including semiconductor device structures and circuits (e.g., the circuits, structures and devices described above with reference to fig. 3A-9) according to embodiments of the present disclosureSemiconductor devices (e.g.,
Additional non-limiting example embodiments of the present disclosure are set forth below:
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