Semiconductor memory device with a plurality of memory cells
阅读说明：本技术 半导体存储装置 (Semiconductor memory device with a plurality of memory cells ) 是由 高际辉男 于 2019-07-05 设计创作，主要内容包括：实施方式提供一种能够高速动作的半导体存储装置。实施方式的半导体存储装置(1)具备：第1存储单元；配线(BLI＜1＞),连接于所述第1存储单元,在金属配线层(L1)中沿着第1方向(D1)延伸；感测放大器单元(SAU＜1＞),连接于所述配线(BLI＜1＞)；配线(rBLI＜1＞),连接于所述感测放大器单元(SAU＜1＞),在所述金属配线层(L1)中沿着所述第1方向延伸；及锁存电路(XDL＜1＞),连接于所述配线(rBLI＜1＞)；且所述配线(BLI＜1＞)中朝向所述第1方向那侧的端面和所述配线(rBLI＜1＞)中朝向与所述第1方向相反的方向那侧的端面对向。(Embodiments provide a semiconductor memory device capable of operating at high speed. A semiconductor memory device (1) according to an embodiment includes: a 1 st storage unit; a wiring (BLI < 1 >) connected to the 1 st memory cell and extending in a 1 st direction (D1) in the metal wiring layer (L1); a sense amplifier unit (SAU < 1 >) connected to the wiring (BLI < 1 >); a wiring (rBLI < 1 >) connected to the sense amplifier unit (SAU < 1 >) and extending in the 1 st direction in the metal wiring layer (L1); and a latch circuit (XDL < 1 >) connected to the wiring (rBLI < 1 >); and an end face of the wiring (BLI < 1 >) facing the 1 st direction side and an end face of the wiring (rBLI < 1 >) facing the direction opposite to the 1 st direction are opposed to each other.)
1. A semiconductor memory device includes:
a 1 st storage unit;
a 1 st wiring connected to the 1 st memory cell and extending in a 1 st direction in a 1 st wiring layer;
a 1 st sense amplifier connected to the 1 st wiring;
a 2 nd wiring connected to the 1 st sense amplifier and extending in the 1 st direction in the 1 st wiring layer; and
a 1 st latch circuit connected to the 2 nd wiring; and is
An end surface of the 1 st wiring facing the 1 st direction and an end surface of the 2 nd wiring facing a direction opposite to the 1 st direction are opposed to each other.
2. The semiconductor memory device according to claim 1, further comprising a 3 rd wiring in the 2 nd wiring layer,
the 3 rd wiring is connected to the 1 st sense amplifier and the 2 nd wiring, and is located at a position different from the 1 st wiring layer in the lamination direction.
3. The semiconductor memory device according to claim 2, wherein
The 3 rd wiring extends along the 1 st direction, and
the semiconductor memory device further includes a 4 th wire, wherein the 4 th wire is connected to the 3 rd wire and the 2 nd wire, and extends in a 2 nd direction intersecting the 1 st direction in the 2 nd wire layer.
4. The semiconductor memory device according to claim 2, wherein
The width of the 3 rd wiring is wider than that of the 1 st wiring.
5. The semiconductor memory device according to claim 1, wherein
The width of the 1 st wiring is the same as the width of the 2 nd wiring.
6. The semiconductor memory device according to claim 1, further comprising a shield wiring for the 2 nd wiring.
7. The semiconductor memory device according to claim 1, further comprising a wiring connected in parallel to the 2 nd wiring.
8. The semiconductor memory device according to claim 7, further comprising a shield wiring for the 2 nd wiring.
9. The semiconductor memory device according to claim 1, further comprising:
a 2 nd storage unit;
a 5 th wiring connected to the 2 nd memory cell and extending in the 1 st direction in the 1 st wiring layer;
a 2 nd sense amplifier connected to the 5 th wiring; and
and a 2 nd latch circuit connected to the 2 nd sense amplifier via the 2 nd wiring.
10. The semiconductor memory device according to claim 9, further comprising a 3 rd wiring in the 2 nd wiring layer,
the 3 rd wiring is connected to the 1 st sense amplifier, the 2 nd sense amplifier, and the 2 nd wiring, and is located at a position different from the 1 st wiring layer in a lamination direction.
11. The semiconductor memory device according to claim 9, wherein
An end surface of the 5 th wiring line facing the 1 st direction is located at the same position in the 1 st direction as an end surface of the 1 st wiring line facing the 1 st direction.
12. The semiconductor memory device according to claim 9, further comprising a 6 th wiring extending in the 1 st direction in the 1 st wiring layer, wherein
An end surface of the 5 th wiring facing the 1 st direction side and an end surface of the 6 th wiring facing a direction opposite to the 1 st direction are opposed,
the 6 th wiring is a shield wiring.
13. The semiconductor memory device according to claim 12, wherein
An end surface of the 6 th wiring facing a side opposite to the 1 st direction and an end surface of the 2 nd wiring facing a side opposite to the 1 st direction are located at the same position in the 1 st direction.
14. The semiconductor memory device according to claim 9, further comprising a 6 th wiring extending in the 1 st direction in the 1 st wiring layer, wherein
An end surface of the 5 th wiring facing the 1 st direction side and an end surface of the 6 th wiring facing a direction opposite to the 1 st direction are opposed,
the 2 nd wiring and the 6 th wiring are connected in parallel.
15. The semiconductor memory device according to claim 14, wherein
An end surface of the 6 th wiring facing a side opposite to the 1 st direction and an end surface of the 2 nd wiring facing a side opposite to the 1 st direction are located at the same position in the 1 st direction.
16. The semiconductor memory device according to claim 14, further comprising:
a 3 rd storage unit;
a 7 th wiring connected to the 3 rd memory cell and extending in the 1 st direction in the 1 st wiring layer;
a 3 rd sense amplifier connected to the 7 th wiring;
a 3 rd latch circuit connected to the 3 rd sense amplifier via the 2 nd wiring; and
an 8 th wiring extending along the 1 st direction in the 1 st wiring layer; and is
An end surface of the 7 th wiring line facing the 1 st direction and an end surface of the 8 th wiring line facing a direction opposite to the 1 st direction are opposed to each other,
the 8 th wiring is a shield wiring.
17. The semiconductor memory device according to claim 2, further comprising:
a 4 th sense amplifier;
a 9 th wiring connected to the 4 th sense amplifier and extending in the 1 st direction in the 2 nd wiring layer; and
a 4 th latch circuit connected to the 9 th wiring; and is
The 3 rd wiring extends along the 1 st direction,
an end surface of the 3 rd wiring facing the 1 st direction and an end surface of the 9 th wiring facing a direction opposite to the 1 st direction are opposed to each other.
18. The semiconductor memory device according to claim 3, further comprising:
a 5 th sense amplifier;
a 10 th wiring connected to the 5 th sense amplifier and extending in the 1 st direction in the 2 nd wiring layer; and
and a 5 th latch circuit connected to the 10 th wiring so as not to pass through a wiring extending in the 2 nd direction in the 2 nd wiring layer.
Technical Field
Background
As a semiconductor memory device, a NAND (Not And) type flash memory is known.
Disclosure of Invention
Drawings
Fig. 1 is a block diagram showing an example of the configuration of a memory system including the semiconductor memory device according to
Fig. 2 is a block diagram showing an example of the configuration of the semiconductor memory device according to
Fig. 3 is a diagram showing an example of a circuit configuration of a memory cell array in the semiconductor memory device according to
Fig. 4 is a diagram showing an example of a part of a cross-sectional structure of a memory cell array in the semiconductor memory device according to
Fig. 5 is a block diagram showing an example of the configuration of the sense amplifier module and the data register in the semiconductor memory device according to
Fig. 6 is a diagram showing an example of a part of the circuit configuration of the sense amplifier module in the semiconductor memory device according to
Fig. 7 is a diagram showing an example of the connection relationship between a plurality of sense amplifier units SAU and a plurality of latch circuits XDL in the semiconductor memory device according to the comparative example of
Fig. 8 is a diagram showing an example of the connection relationship between a plurality of sense amplifier units SAU and a plurality of latch circuits XDL in the semiconductor memory device according to
Fig. 9 is a diagram showing an example of a cross-sectional structure of the semiconductor memory device according to
Fig. 10 is a diagram showing an example of the layout of a plurality of sense amplifier units SAU and a bus cDBUS in the semiconductor memory device according to the comparative example of
Fig. 11 is a diagram showing an example of the layout of a plurality of sense amplifier units SAU and a bus DBUS in the semiconductor memory device according to
Fig. 12 is a diagram for comparing the widths of the wires in the respective metal wire layers in the semiconductor memory device according to
Fig. 13 is a diagram showing another example of the layout of a plurality of sense amplifier units SAU and a bus DBUS in the semiconductor memory device according to
Fig. 14 is a diagram showing another example of the layout of a plurality of sense amplifier units SAU and a bus DBUS in the semiconductor memory device according to
Fig. 15 is a diagram showing another example of the layout of a plurality of sense amplifier units SAU and a bus DBUS in the semiconductor memory device according to
Fig. 16 is a diagram showing an example of the layout of a bus line cDBUS and a plurality of latch circuits XDL in the semiconductor memory device according to the comparative example of
Fig. 17 is a diagram showing an example of the layout of the bus DBUS and the plurality of latch circuits XDL in the semiconductor memory device according to
Fig. 18 is a diagram showing an example of a circuit configuration related to a data transfer operation between the latch circuit SDL and the latch circuit XDL in the semiconductor memory device according to
Fig. 19 is a timing chart showing an example of temporal changes in the voltages of various control signals and the voltages applied to various circuit components in the data transfer operation from the latch circuit XDL to the latch circuit SDL in the semiconductor memory device according to
Fig. 20 is a timing chart showing an example of temporal changes in the voltages of various control signals and the voltages applied to various circuit components in the data transfer operation from the latch circuit SDL to the latch circuit XDL in the semiconductor memory device according to
Fig. 21 is a current waveform diagram showing an example of a data transfer operation from 16 sense amplifier units SAU to 16 latch circuits XDL in the semiconductor memory device according to the comparative example of
Fig. 22 is a current waveform diagram showing an example of a data transfer operation from 16 sense amplifier units SAU to 16 latch circuits XDL in the semiconductor memory device according to
Fig. 23 is a current waveform diagram showing an example of a data transfer operation from 16 sense amplifier units SAU to 16 latch circuits XDL in the semiconductor memory device according to
Fig. 24 is a current waveform diagram showing an example of a data transfer operation from 16 sense amplifier units SAU to 16 latch circuits XDL in the semiconductor memory device according to
Fig. 25 is a diagram showing an example of the layout of a plurality of sense amplifier units SAU and a bus DBUS in the semiconductor memory device according to
Embodiments relate to a semiconductor memory device.
- 上一篇：一种医用注射器针头装配设备
- 下一篇：非易失性存储器装置及其操作方法和贮存装置