阅读说明：本技术 非易失性存储器装置及其操作方法和贮存装置 (Nonvolatile memory device, method of operating the same, and storage device ) 是由 尹铉竣 于 2020-03-04 设计创作，主要内容包括：公开了一种非易失性存储器及其操作方法和一种贮存装置。一种非易失性存储器装置包括：存储器单元阵列,其包括按照行和列布置的存储器单元；行解码器电路,其通过字线连接到存储器单元的行并控制字线的电压；以及页缓冲器电路,其通过位线连接到存储器单元的列,并且包括被配置为感测位线的电压的第一晶体管以及被配置为反相并感测位线的电压的第二晶体管。页缓冲器电路被配置为通过经由第一晶体管对位线中的第一位线执行第一感测操作来获得第一值,并且通过经由第二晶体管对位线中的第二位线执行第二感测操作来获得第二值,其中,第一值或第二值被反相。(A nonvolatile memory, an operating method thereof, and a storage device are disclosed. A non-volatile memory device comprising: a memory cell array including memory cells arranged in rows and columns; a row decoder circuit connected to a row of memory cells through word lines and controlling voltages of the word lines; and a page buffer circuit connected to the columns of the memory cells through the bit lines and including a first transistor configured to sense a voltage of the bit line and a second transistor configured to invert and sense the voltage of the bit line. The page buffer circuit is configured to obtain a first value by performing a first sensing operation on a first bit line of the bit lines via a first transistor, and obtain a second value by performing a second sensing operation on a second bit line of the bit lines via a second transistor, wherein the first value or the second value is inverted.)

1. A non-volatile memory device, comprising:

a memory cell array including memory cells arranged in rows and columns;

a row decoder circuit connected to a row of the memory cells by a word line and configured to control a voltage of the word line; and

a page buffer circuit connected to a column of the memory cells through a bit line and including a first transistor configured to transmit a voltage of the bit line to be sensed and a second transistor configured to transmit a voltage of the bit line to be inverted and sensed, wherein the page buffer circuit is configured to:

obtaining a first value by performing a first sensing operation on a first one of the bit lines through the first transistor, an

A second value is obtained by performing a second sensing operation on a second one of the bit lines via the second transistor.

2. The non-volatile memory device of claim 1, wherein the first bit line is different from the second bit line.

3. The non-volatile memory device of claim 1,

wherein the page buffer circuit includes:

first page buffers respectively connected to the first bit lines, and

second page buffers respectively connected to the second bit lines,

wherein each of the first and second page buffers is connected to a corresponding bit line and includes a sense latch including a first node and a second node,

wherein, in the first sensing operation, the first page buffer is configured to store values respectively corresponding to first voltages of the first bit lines as the first values at the first nodes of the sense latches of the first page buffer via first transistors of the first page buffer, and

wherein, in the second sensing operation, the second page buffer is configured to store values to be respectively corresponding to second voltages of the second bit lines as the second values at the second nodes of the sense latches of the second page buffer via second transistors of the second page buffer.

4. The non-volatile memory device of claim 3,

wherein the first transistors of the first page buffer are commonly controlled by a first signal line,

wherein the second transistors of the first page buffer are commonly controlled by a second signal line,

wherein the first transistors of the second page buffer are commonly controlled by a third signal line different from the first signal line, and

wherein the second transistors of the second page buffer are commonly controlled by a fourth signal line different from the second signal line.

5. The non-volatile memory device of claim 3,

wherein each of the first and second page buffers includes a selection block configured to selectively connect the corresponding bit line and the sense latch, and

wherein the selection block of each of the first and second page buffers is configured to be controlled by a common signal line.

6. The non-volatile memory device of claim 1,

wherein the page buffer circuit is configured to perform the first sensing operation and the second sensing operation, and

wherein the row decoder circuit is configured to apply a voltage to a word line selected from the word lines and maintain the voltage.

7. The non-volatile memory device of claim 1, wherein the page buffer circuit comprises:

first page buffers respectively connected to the first bit lines, and

second page buffers respectively connected to the second bit lines, and

wherein the page buffer circuit is further configured to apply a precharge voltage to the bit line before performing the first and second sensing operations.

8. The non-volatile memory device of claim 7, wherein after applying the precharge voltage and before the first and second sensing operations, the first page buffer is further configured to obtain a third value by performing a third sensing operation on the first bit line via the second transistor.

9. The non-volatile memory device of claim 8, wherein the page buffer circuit is further configured to avoid performing a sense operation on the second bit line during the third sense operation on the first bit line.

10. The non-volatile memory device of claim 8, wherein the row decoder circuit is configured to adjust a voltage of a selected word line from the word lines after performing the third sensing operation.

11. The non-volatile memory device of claim 8, wherein after the first and second sensing operations, the second page buffer is further configured to obtain a fourth value by performing a fourth sensing operation on the second bit line via the first transistor.

12. The non-volatile memory device of claim 11, wherein the page buffer circuit is further configured to avoid performing a sense operation on the first bit line during the fourth sense operation on the second bit line.

13. The non-volatile memory device of claim 11, wherein the row decoder circuit is configured to adjust a voltage of a selected one of the word lines after the first and second sensing operations and before the third sensing operation.

14. The non-volatile memory device of claim 11, wherein the page buffer circuit is further configured to integrate and output results of the first, second, third, and fourth sense operations after the fourth sense operation.

15. A storage device, comprising:

a non-volatile memory device including a first memory cell connected to a first bit line and a second memory cell connected to a second bit line; and

a controller circuit configured to control the non-volatile memory device to:

performing a first sensing operation to read the first memory cell,

performing a second sensing operation to read the first memory cell and the second memory cell after the first sensing operation, an

Performing a third sensing operation to read the second memory cell after the second sensing operation.

16. The storage device of claim 15, wherein the controller circuit is further configured to control the non-volatile memory device to:

storing a result of the first sense operation for the first memory cell in the first sense operation, an

Storing a result of the second sense operation for the first memory cell, the result of the second sense operation being inverted before being stored.

17. The storage device of claim 15, wherein the controller circuit is further configured to cause the non-volatile memory device to adjust a level of a read voltage to be applied to the first memory cell and the second memory cell during the first sensing operation, the second sensing operation, and the third sensing operation.

18. The storage device as set forth in claim 15,

wherein the controller circuit is further configured to control the non-volatile memory device by sending a first request to check a state of the first and second memory cells and a second request to read the first and second memory cells, and

wherein, in response to the second request, the controller circuit is further configured to control the non-volatile memory device to:

performing a read operation on the first memory cell and the second memory cell, an

Performing the first sensing operation, the second sensing operation, and the third sensing operation after the read operation.

19. A method of operating a non-volatile memory device including a first memory cell, a second memory cell, a first bit line connected to the first memory cell, and a second bit line connected to the second memory cell, the method comprising:

applying a precharge voltage to the first bit line and the second bit line;

performing a first sensing operation on the first bit line to obtain a first value;

performing a second sensing operation on the second bit line to obtain a second value; and

inverting one of the first value and the second value.

20. The method of claim 19, further comprising:

performing a third sensing operation on the first bit line to obtain a third value after applying the precharge voltage and before the first and second sensing operations;

performing a fourth sensing operation on the second bit line to obtain a fourth value after the third sensing operation; and

integrating results of the first and third sensing operations, integrating results of the second and fourth sensing operations, and outputting the integrated results.

Technical Field

Example embodiments of the inventive concepts disclosed herein relate to semiconductor circuits including non-volatile memory devices, methods of operating non-volatile memory devices, and/or storage devices including non-volatile memory devices.

Background

The storage device may be configured to store data under control of a host device such as a computer, smartphone, and smart tablet. As an example, the storage device may store data on a magnetic disk such as a Hard Disk Drive (HDD) or a semiconductor memory, in particular on a non-volatile memory such as a Solid State Drive (SSD) or a memory card.

Some examples of non-volatile memory include read-only memory (ROM), programmable ROM (prom), electrically programmable ROM (eprom), electrically erasable programmable ROM (eeprom), flash memory devices, phase-change ram (pram), magnetic ram (mram), resistive ram (rram), ferroelectric ram (fram), and the like.

Some non-volatile memory devices may be configured to store data in memory cells. There are various ways to read the memory cells of a non-volatile memory device according to its operating characteristics and the requests to access and/or manage the non-volatile memory device. However, there is still room to introduce new ways of reading memory cells that may exhibit increased speed and/or reliability of non-volatile memory devices.

Disclosure of Invention

Some example embodiments of some inventive concepts include a memory device capable of improving a speed of determining a state of data stored in a memory cell of the non-volatile memory device, an operating method of the non-volatile memory device, and/or a storage device including the non-volatile memory device.

According to some example embodiments, a non-volatile memory device includes: a memory cell array including memory cells arranged in rows and columns; and a processing circuit connected to the row of memory cells by word lines and to the column of memory cells by bit lines, wherein the processing circuit is configured to control a voltage of the word lines, sense a voltage of the bit lines, invert and sense the voltage of the bit lines, obtain a first value by performing a first sense operation on a first one of the bit lines, obtain a second value by performing a second sense operation on a second one of the bit lines, and invert one of the first value or the second value.

According to some example embodiments, a storage device may include: a non-volatile memory device including a first memory cell connected to a first bit line, a second memory cell connected to a second bit line; and a controller circuit configured to control the non-volatile memory device to: in response to the request, performing a first sense operation that reads the first memory cell; performing a second sensing operation of reading the first memory cell and the second memory cell after the first sensing operation; and performing a third sensing operation of reading the second memory cell after the second sensing operation.

According to some example embodiments, an operating method of a nonvolatile memory device including a first memory cell, a second memory cell, a first bit line connected to the first memory cell, and a second bit line connected to the second memory cell, may include: applying a precharge voltage to the first bit line and the second bit line; performing a first sensing operation on a first bit line to obtain a first value; performing a second sensing operation on the second bit line to obtain a second value; and inverting one of the first value and the second value.

Drawings

The above and other objects and features of some inventive concepts will become apparent by describing in detail some exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a block diagram illustrating a non-volatile memory device according to some example embodiments of some inventive concepts.

Fig. 2 is a circuit diagram illustrating an example of one of the memory blocks of fig. 1.

FIG. 3 shows selected memory cells in a selected memory block of the memory cell array and a page buffer circuit.

Fig. 4 is a flowchart illustrating an operation method of a nonvolatile memory device according to some example embodiments of some inventive concepts.

Fig. 5 shows an example of a k-th page buffer which is one of the first to eighth page buffers.

Fig. 6 is a timing diagram of signals applied to the page buffer circuit when sensing the threshold voltage of the selected memory cell.

Fig. 7 illustrates an example of performing a sensing operation of a page buffer when the page buffer belongs to a first group of page buffers.

Fig. 8 illustrates an example of performing a sensing operation of a page buffer when the page buffer belongs to the second group of page buffers.

FIG. 9 illustrates an example of a change in threshold voltage of a selected memory cell.

Fig. 10 is an enlarged view of the sixth and seventh programmed states.

Fig. 11 is a flowchart illustrating a method of a non-volatile memory device performing a valley search according to some example embodiments of some inventive concepts.

Fig. 12 is a timing diagram of signals applied to a page buffer circuit when the method of fig. 11 is performed.

Fig. 13 shows an example of an ith page buffer as another one of the first to eighth page buffers.

Fig. 14 is a block diagram illustrating a storage device according to some example embodiments of some inventive concepts.

Fig. 15 is a flowchart illustrating an operation method of a storage device according to some example embodiments of some inventive concepts.

Detailed Description

In the following, some example embodiments of some inventive concepts are described in detail.

Fig. 1 is a block diagram illustrating a non-volatile memory device 100 according to some example embodiments of some inventive concepts. Referring to fig. 1, a nonvolatile memory device 100 includes a memory cell array 110, a row decoder circuit 120, a page buffer circuit 130, a data input and output circuit 140, and a control logic circuit 150.

Memory cell array 110 includes a plurality of memory blocks BLK1 through BLKz. Each of the memory blocks BLK1 through BLKz includes a plurality of memory cells. Each of the memory blocks BLK1 through BLKz may be connected to the row decoder circuit 120 through at least one ground selection line GSL, a word line WL, and at least one string selection line SSL. Some of the word lines WL may be used as dummy word lines.

Each of the memory blocks BLK1 through BLKz may be connected to the page buffer circuit 130 through a plurality of bit lines BL. For example, a plurality of memory blocks BLK1 through BLKz may be commonly connected to a plurality of bit lines BL, or different memory blocks may be connected to different bit lines BL. The memory cells of the plurality of memory blocks BLK1 through BLKz may have the same or similar structure or may have different structures.

In some example embodiments, each of the memory blocks BLK1 through BLKz may correspond to a unit of an erase operation. The memory cells of the memory cell array 110 may be erased in units of memory blocks. Memory cells belonging to one memory block can be erased simultaneously. In another example embodiment, each of the memory blocks BLK1 through BLKz may be divided into a plurality of sub-blocks. Each of the plurality of sub-blocks may correspond to a unit of an erase operation.

The row decoder circuit 120 may be connected to the memory cell array 110 through ground select lines GSL, word lines WL, and string select lines SSL. The row decoder circuit 120 may operate under the control of control logic circuit 150.

The row decoder circuit 120 may decode a row address RA received from an external device (e.g., the controller circuit 420 of fig. 14) through a first channel (e.g., input and output channels), and may control voltages to be applied to the string selection lines SSL, the word lines WL, and the ground selection lines GSL based on the decoded address.

The page buffer circuit 130 may be connected to the memory cell array 110 through a plurality of bit lines BL. In some example embodiments, a first memory cell of the memory cell array 110 may be connected to a first bit line BL, such as the even-numbered bit lines BL2, BL4, etc., and a second memory cell of the memory cell array 110 may be connected to a second bit line BL, such as the odd-numbered bit lines BL1, BL3, etc. The page buffer circuit 130 may be connected to the data input and output circuit 140 through a plurality of data lines DL. The page buffer circuit 130 may operate under the control of the control logic circuit 150. .

In an example write operation, the page buffer circuit 130 may store data to be written into the memory cells. The page buffer circuit 130 may apply a voltage to one or more of the plurality of bit lines BL based on the stored data. In an example read operation or in an example verify read operation that may be performed in a write operation or an erase operation, the page buffer circuit 130 may sense the voltage of the bit line BL, and in some examples, may store the sensed result.

The data input and output circuit 140 may be connected to the page buffer circuit 130 through a plurality of data lines DL. The data input and output circuit 140 may receive the column address CA through the first channel. The data input and output circuit 140 may output the data read by the page buffer circuit 130 to an external device through a first channel based on the column address CA. The data input and output circuit 140 may provide data received from an external device to the page buffer circuit 130 through the first channel based on the column address CA.

The control logic circuit 150 may receive a command CMD from an external device through a first channel and/or may exchange a control signal CTRL with the external device through a second channel (e.g., a control channel). The control logic circuit 150 may receive a command CMD through the first channel in response to the control signal CTRL, may route the row address RA and the column address CA received through the first channel to the row decoder circuit 120 and the DATA input and output circuit 140, respectively, and/or may route the DATA "received through the first channel to the DATA input and output circuit 140.

Control logic circuit 150 may decode the received command CMD and, in some examples, may control non-volatile memory device 100 based on the decoded command. For example, the control logic circuit 150 may allow the row decoder circuit 120 and the page buffer circuit 130 to perform a check operation for checking the state of the memory cells. In some example embodiments, the check operation may involve the page buffer circuit 130 sensing the voltage of the bit line BL using two or more different methods.

Fig. 2 is a circuit diagram of an example of one memory block BLKa among the memory blocks BLK1 through BLKz of fig. 1. Referring to fig. 1 and 2, a plurality of cell strings CS may be arranged on (or in) a substrate SUB in rows and columns. The cell strings may be commonly connected to a common source line CSL formed on (or in) the substrate SUB. In fig. 2, as an example of the structure of the memory block BLKa, the position of the substrate SUB is included.

In an example embodiment such as that shown in fig. 2, the common source line CSL may be connected to the lower end of the cell string CS. In some example embodiments, the common source line CSL may be physically located at the lower end of the cell string CS. An example embodiment of a cell string CS arranged in a 4X4 matrix is shown in fig. 2. In other example embodiments, the configuration of the cell string CS may vary; for example, the number of cell strings CS in the memory block BLKa may be larger or smaller.

The cell strings CS of each row may be connected to corresponding ones of the first to fourth ground selection lines GSL1 to GSL4 and/or corresponding ones of the first to fourth string selection lines SSL1 to SSL 4. The cell strings CS of the respective columns may be connected to corresponding ones of the first to fourth bit lines BL1 to BL 4. For a brief illustration, the cell string CS connected to the second string select line SSL2 and the third string select line SSL3 is shown as a dotted line.

Each of the cell strings CS may include at least one ground selection transistor GST connected to a ground selection line GSL, a plurality of memory cells MC1 to MC8 respectively connected to a plurality of word lines WL1 to WL8, and/or a string selection transistor SST respectively connectable to a string selection line SSL1, SSL2, SSL3, or SSL 4. For example, a string select line closer to the bit lines BL1 to BL4 among the string select lines SSL1 of the first row may be an upper string select line, which may be marked with "SSL 1 u" using a reference character "u". Among the string select lines SSL1 of the first row, the string select line closer to the memory cells MC1 to MC8 may be a lower string select line, which is marked with "SSL 1 l" using a reference character "l". That is, the first string select line SSL1 may include a first upper string select line SSL1u and a first lower string select line SSL1 l. The second string select line SSL2 may include a second upper string select line SSL2u and a second lower string select line SSL2 l. The third string select lines SSL3 may include a third upper string select line SSL3u and a third lower string select line SSL3 l. The fourth string select line SSL4 may include a fourth upper string select line SSL4u and a fourth lower string select line SSL4 l. Also, the string selection transistors SST of the first row may include first upper string selection transistors SST1u and first lower string selection transistors SST1 l. The string selection transistors SST of the second row may include second upper string selection transistors SST2u and second lower string selection transistors SST2 l. The string selection transistors SST of the third row may include third upper string selection transistors SST3u and third lower string selection transistors SST3 l. The string selection transistors SST of the fourth row may include fourth upper string selection transistors SST4u and fourth lower string selection transistors SST4 l.

In each cell string CS, the ground selection transistor GST, the memory cells MC1 through MC8, and/or the string selection transistor SST may be connected (e.g., connected in series) in a direction perpendicular to the substrate SUB and/or may be sequentially stacked in the direction perpendicular to the substrate SUB. In each cell string CS, one or more of the memory cells MC1 through MC8 may be used as dummy memory cells. In some example embodiments, the dummy memory cells may be program inhibited, i.e., not programmed; in other example embodiments, the dummy memory cells may be programmed differently from the memory cells other than the dummy memory cells among the memory cells MC1 through MC 8.

Fig. 3 illustrates an example embodiment including selected memory cells MC _ S in a selected memory block BLK _ S of the memory cell array 110 and a page buffer circuit 130. Components corresponding to the first bit line BL1 through the eighth bit line BL8 are shown in fig. 3 as an example. Referring to fig. 1 to 3, when sensing the state of a memory cell MC _ S selected from among the memory cells MC1 through MC8 of a selected memory block BLK _ S, the row decoder circuit 120 may apply a first pass voltage to unselected word lines among the word lines WL of the selected memory block BLK _ S. The first pass voltage may turn on the unselected memory cells. Therefore, the unselected memory cells are turned on and serve as channels for transmitting voltages. Fig. 3 omits the unselected memory cells of the selected memory block BLK _ S.

When sensing the selected memory cell MC _ S of the selected memory block BLK _ S, the row decoder circuit 120 may apply a second pass voltage to a selected string selection line corresponding to the selected memory cell MC _ S, and may apply a first OFF voltage to unselected string selection lines. The second pass voltage may turn on a selected string selection transistor corresponding to the selected memory cell MC _ S. Thus, the selected string selection transistor may be used as a channel for transmitting a voltage and is omitted from fig. 3. The first OFF voltage may turn OFF the unselected string selection transistors. Accordingly, the cell strings corresponding to the unselected string selection transistors are electrically disconnected from the first to eighth bit lines BL1 to BL 8.

Fig. 3 omits the electrically disconnected cell string.

When sensing the selected memory cell MC _ S of the selected memory block BLK _ S, the row decoder circuit 120 may apply a third pass voltage to the selected ground selection line corresponding to the selected memory cell MC _ S, and may apply a second OFF voltage to the unselected ground selection line. The third pass voltage may turn on a selected ground select transistor corresponding to the selected memory cell MC _ S. Thus, the selected select transistor can be used as a pass for the pass voltage and is omitted from FIG. 3. The second OFF voltage may turn OFF the unselected selection transistor. Therefore, the cell string corresponding to the unselected selection transistor is electrically disconnected from the common source line CSL. Fig. 3 omits the electrically disconnected cell string.

When sensing the selected memory cell MC _ S of the selected memory block BLK _ S, as shown in fig. 3, the memory cell array 110 may be simplified into a state in which the selected memory cell MC _ S is connected between the first to eighth bit lines BL1 to BL8 and the common source line CSL supplied with the ground voltage GND.

When sensing a selected memory cell MC _ S of a selected memory block BLK _ S, the row decoder circuit 120 may apply a voltage (e.g., a read voltage) for sensing to a selected word line WL _ S. The page buffer circuit 130 may sense voltages of the first to eighth bit lines BL1 to BL8, and may determine whether a threshold voltage of the selected memory cell MC _ S is greater than (or equal to or less than) the sensing voltage. The first to eighth page buffers 131 to 138 may output the result of the sensing operation to the data input and output circuit 140.

The page buffer circuit 130 may include first to eighth page buffers 131 to 138 corresponding to the first to eighth bit lines BL1 to BL8, respectively. When sensing the selected memory cells MC _ S of the selected memory block BLK _ S, the first to eighth page buffers 131 to 138 may be divided into two or more groups, and the page buffers in the groups may be controlled to differently sense the voltages of the corresponding bit lines.

For example, even-numbered page buffers 132, 134, 136, and 138 of the first to eighth page buffers 131 to 138 may constitute a first page buffer group. The bit lines connected to the page buffers 132, 134, 136 and 138 of the first group (i.e., the even-numbered bit lines BL2, BL4, BL6 and BL8 of the first to eighth bit lines BL1 to BL8) may constitute a first bit line group.

For example, odd-numbered page buffers 131, 133, 135, and 137 of the first to eighth page buffers 131 to 138 may constitute a second page buffer group. The bit lines connected to the page buffers 131, 133, 135, and 137 of the second group (i.e., the odd bit lines BL1, BL3, BL5, and BL7 among the first to eighth bit lines BL1 to BL8) may constitute a second bit line group.

In example embodiments, the page buffers and the bit lines may be grouped for even and odd numbers, but some example embodiments of some inventive concepts are not limited thereto. For example, the references to grouping the page buffers and bit lines may be modified or changed based on operating characteristics or process characteristics of the non-volatile memory device 100.

In some example embodiments, the first signal line SIGL1 for controlling the first group of page buffers 132, 134, 136 and 138 and the second signal line SIGL2 for controlling the second group of page buffers 131, 133, 135 and 137 may be separately disposed such that the first group of page buffers 132, 134, 136 and 138 and the second group of page buffers 131, 133, 135 and 137 may sense voltages of corresponding bit lines using different methods.

In some example embodiments, a common signal line SIGC for controlling a common part of the operations of the first and second groups of page buffers 132, 134, 136 and 138 and 131, 133, 135 and 137 may be commonly provided to the first and second groups of page buffers 132, 134, 136 and 138 and 131, 133, 135 and 137.

Fig. 4 is a flowchart illustrating an operation method of the nonvolatile memory device 100 according to an embodiment. Referring to fig. 1, 3 and 4, the page buffer circuit 130 may precharge the first to eighth bit lines BL1 to BL8 in operation S110. The first to eighth page buffers 131 to 138 may apply voltages (e.g., power supply voltages) to the first to eighth bit lines BL1 to BL8, respectively.

In operation S120, the page buffers 132, 134, 136, and 138 of the first group may perform a first sensing operation on the bit lines BL2, BL4, BL6, and BL8 of the first group and may obtain a first value. In operation S130, the page buffers 131, 133, 135, and 137 of the second group may perform a second sensing operation on the bit lines BL1, BL3, BL5, and BL7 of the second group and may obtain a second value.

The first sensing operation may be different from the second sensing operation. For example, one of the result of the first sensing operation and the result of the second sensing operation may be inverted. As an example, a first value may be obtained as a result of a first sense operation, and a second value may be obtained by inverting a result of a second sense operation. As another example, the first value may be obtained by inverting the result of the first sensing operation, and the second value may be obtained as a result of the second sensing operation. As an example, the first sensing operation and the second sensing operation may be performed simultaneously and/or at least partially simultaneously. As another example, the first sensing operation and the second sensing operation may be performed sequentially, such as continuously over a period of time.

Fig. 5 shows an example of a k-th page buffer 13k as one of the first to eighth page buffers 131 to 138. In the example embodiment of fig. 5, components associated with a sensing operation among the components of the k-th page buffer 13k are shown, and the remaining components are omitted. In example embodiments, the structures of the first to eighth page buffers 131 to 138 may be the same as those shown in fig. 5. In some example embodiments, the page buffer circuit 130 may be configured to perform the first sensing operation and/or the second sensing operation. Further, the page buffer circuit 130 may be configured to invert one of the first sensing voltage of the first sensing operation and the second sensing voltage of the second sensing operation in various ways. As such an example, the page buffer circuit 130 may invert the sensing voltage of a selected one of the bit lines BL during the first sensing operation or the second sensing operation.

In some example embodiments and as shown in fig. 1, 3 and 5, the k-th page buffer 13k may include a sensing latch 210, a selection block 220, a precharge block 230, a latch block 240, a transmission block 250, a first transistor 260, a second transistor 270 and a first reset block 280.

In some example embodiments, the controller circuit 420 (see fig. 14) may be configured to control the non-volatile memory device 100 to store a result of a first sense operation for a first memory cell in a first sense operation, and to invert and store a result of a second sense operation for the first memory cell. For example, the sense latch 210 may include an inverter connected between the first node N1 and the second node N2. The inverters may be cross-coupled. The sense latch 210 may be configured to store the result of a sense operation performed on the bit line BL.

The selection block 220 is connected between the bit line BL and the sense node SN. The selection block 220 may be controlled by a selection signal SEL supplied through a signal line (e.g., a first common signal line) in the common signal line SIGC. That is, the selection blocks 220 of the first to eighth page buffers 131 to 138 may be simultaneously controlled in common by the selection signal SEL of the first common signal line. In response to a selection signal SEL, the selection block 220 may electrically connect the sensing node SN and the bit line BL or may disconnect the sensing node SN from the bit line BL.

The precharge block 230 is connected to the sensing node SN. The precharge block 230 may be controlled by a precharge signal PRE supplied through a signal line (e.g., a second common signal line) in the common signal line SIGC. That is, the precharge blocks 230 of the first to eighth page buffers 131 to 138 may be simultaneously controlled in common by the precharge signal PRE of the second common signal line. In some example embodiments, the page buffer circuit 130 may be configured to apply a precharge voltage to the bit line BL before performing the first and second sensing operations. For example, precharge block 230 may apply a precharge voltage to sense node SN in response to precharge signal PRE.

The latch block 240 is connected to the sensing node SN and to the first transistor 260 and the second transistor 270. The latch block 240 may be controlled by a latch signal LAT supplied through a signal line (e.g., a third common signal line) in the common signal line SIGC. That is, the latch blocks 240 of the first to eighth page buffers 131 to 138 may be simultaneously controlled in common by the latch signal LAT of the third common signal line. The latch block 240 may transmit the voltage of the sensing node SN to the first transistor 260 and the second transistor 270 in response to the latch signal LAT.

The transmission block 250 is connected to a first transistor 260 and a second transistor 270. The transfer block 250 may be controlled by a transfer signal TRS supplied through a signal line (e.g., a fourth common signal line) in the common signal line SIGC. That is, the transfer blocks 250 of the first to eighth page buffers 131 to 138 may be simultaneously controlled in common by the transfer signal TRS of the fourth common signal line. The transfer block 250 may output a voltage provided by the first transistor 260 or the second transistor 270 to the outside in response to the transfer signal TRS.

The first transistor 260 is connected between the first node N1 of the sense latch 210 and the latch block 240. When the k-th page buffer 13k belongs to the page buffers 132, 134, 136 and 138 of the first group, the first transistor 260 may be controlled by a first sensing signal SEN1 transmitted through a signal line (e.g., a first line) of the first signal lines SIGL 1. That is, the first transistors 260 of the page buffers 132, 134, 136 and 138 of the first group may be simultaneously controlled in common by the first sensing signal SEN1 of the first line in the first signal line SIGL 1.

The second transistor 270 is connected between the second node N2 of the sense latch 210 and the latch block 240. When the kth page buffer 13k belongs to the page buffers 132, 134, 136, and 138 of the first group, the second transistor 270 may be controlled by a second sensing signal SEN2 transmitted through a signal line (e.g., a second line) of the first signal lines SIGL 1. That is, the second transistors 270 of the page buffers 132, 134, 136 and 138 of the first group may be simultaneously controlled in common by the second sensing signal SEN2 of the second line in the first signal line SIGL 1.

When the k-th page buffer 13k belongs to the page buffers 131, 133, 135, and 137 of the second group, the first transistor 260 may be controlled by the third sensing signal SEN3 transmitted through a signal line (e.g., a first line) of the second signal lines SIGL 2. That is, the first transistors 260 of the page buffers 131, 133, 135, and 137 of the second group may be simultaneously controlled in common by the third sensing signal SEN3 of the first line in the second signal line SIGL 2.

When the kth page buffer 13k belongs to the page buffers 131, 133, 135, and 137 of the second group, the second transistor 270 may be controlled by a fourth sensing signal SEN4 transmitted through a signal line (e.g., a second line) of the second signal lines SIGL 2. That is, the second transistors 270 of the page buffers 131, 133, 135, and 137 of the second group may be simultaneously controlled in common by the fourth sensing signal SEN4 of the second line in the second signal line SIGL 2.

The first reset block 280 is connected to the first transistor 260 and the second transistor 270. The first reset block 280 may be controlled by a first reset signal RST1 provided through a signal line (e.g., a fifth common signal line) in the common signal line SIGC. That is, the first reset blocks 280 of the first to eighth page buffers 131 to 138 may be simultaneously controlled in common by the first reset signal RST1 of the fifth common signal line. The first reset block 280 may apply a ground voltage (or a power supply voltage) to the first transistor 260 or the second transistor 270 in response to the first reset signal RST 1.

Fig. 6 is a timing diagram of signals applied to the page buffer circuit 130 when sensing the threshold voltage of the selected memory cell MC _ S. Referring to fig. 1, 3, 5, and 6, at a first time T1, the first reset signal RST1 is activated and set to the ON voltage VON. When the first reset signal RST1 is set to the ON voltage VON, the first reset block 280 may apply a power supply voltage to the first and second transistors 260 and 270.

When the page buffer 13k belongs to the page buffers 132, 134, 136 and 138 of the first group, the page buffer 13k may receive the first sensing signal SEN1 and the second sensing signal SEN 2. At a first time T1, the second sense signal SEN2 maintains an inactive state, and the first sense signal SEN1 is activated and set to the ON voltage VON. The ON voltage VON may turn ON the first transistor 260.

With the first transistor 260 turned on, the first node N1 of the sense latch 210 may be set to a power supply voltage (e.g., a high level). The second node N2 of the sense latch 210 may be set to an opposite voltage of the power supply voltage, for example, a ground voltage (e.g., a low level).

When the page buffer 13k belongs to the page buffers 131, 133, 135, and 137 of the second group, the page buffer 13k may receive the third sensing signal SEN3 and the fourth sensing signal SEN 4. At the first time T1, the fourth sensing signal SEN4 maintains an inactive state, and the third sensing signal SEN3 is activated and set to the ON voltage VON. The ON voltage VON may turn ON the first transistor 260.

With the first transistor 260 turned on, the first node N1 of the sense latch 210 may be set to a high level. The second node N2 of the sense latch 210 may be set to a level opposite to the high level (e.g., a low level).

At a second time T2, the precharge signal PRE is activated and set to the ON voltage VON. With precharge signal PRE set to ON voltage VON, precharge block 230 may apply a voltage (e.g., a power supply voltage) to sensing node SN.

At a second time T2, the selection signal SEL is activated and set to the ON voltage VON. With the select signal SEL set to the ON voltage VON, the select block 220 may electrically connect the bit line BL and the sense node SN. With the bit line BL and the sense node SN electrically connected, the bit line BL may be charged (e.g., precharged) using a voltage (e.g., a power supply voltage).

At a third time T3, the row decoder circuit 120 may apply the read voltage VRD to the selected word line WL _ S. The read voltage VRD may have a level targeted for comparison with a threshold voltage of the selected memory cell MC _ S among various levels shown in fig. 6.

When the threshold voltage of the selected memory cell connected to the bit line BL connected to the page buffer 13k is greater than the read voltage VRD, the selected memory cell may be turned off. In this case, the precharge voltage of the bit line BL may be maintained. When the threshold voltage of the selected memory cell connected to the bit line BL connected to the page buffer 13k is equal to or less than the read voltage VRD, the selected memory cell may be turned on. In this case, the precharge voltage of the bit line BL may be discharged.

An example when the read voltage VRD is applied to the selected word line WL _ S after the precharge operation is described with reference to fig. 6. However, the timing of performing the precharge operation and the timing of applying the read voltage VRD to the selected word line WL _ S may be variously changed and modified.

At a fourth time T4, the latch signal LAT is activated and set to the ON voltage VON. The second sense signal SEN2 and the third sense signal SEN3 are also activated and set to the ON voltage VON. The first sense signal SEN1 and the fourth sense signal SEN4 may maintain an inactive state.

When the page buffer 13k belongs to the first group of page buffers 132, 134, 136 and 138, the page buffer 13k may receive the second sensing signal SEN 2. With the second sense signal SEN2 activated and set to the ON voltage VON, the latch block 240 may be connected to the sense latch 210 through the second transistor 270.

When the latch signal LAT is set to the ON voltage VON, the latch block 240 may apply the voltage level of the sensing node SN to the second node N2 of the sensing latch 210 through the second transistor 270. As described above, the first node N1 of the sense latch 210 may have a power supply voltage (e.g., a high level) or a ground voltage (e.g., a low level) according to any operation after the second time T2 and before the fourth time T4. A more detailed embodiment is shown in connection with fig. 12.

When the voltage of the sensing node SN is the precharge voltage, the latch block 240 may adjust the voltage of the second node N2 of the sensing latch 210 to the ground voltage through the second transistor 270 in response to the ON voltage VON of the latch signal LAT. In this case, the second node N2 of the sense latch 210 may be set to the ground voltage.

When the voltage of the sense node SN is the ground voltage, the latch block 240 may refrain from adjusting the voltage of the second node N2 of the sense latch 210 in response to the ON voltage VON of the latch signal LAT (or may retain the voltage of the second node N2 of the sense latch 210 without modification). Accordingly, the first node N1 of the sense latch 210 may be maintained at the power supply voltage, and the second node N2 may be maintained at the ground voltage.

When the page buffer 13k belongs to the page buffers 131, 133, 135, and 137 of the second group, the page buffer 13k may receive the third sensing signal SEN 3. With the third sense signal SEN3 activated and set to the ON voltage VON, the latch block 240 may be connected to the sense latch 210 through the first transistor 260.

When the latch signal LAT is set to the ON voltage VON, the latch block 240 may apply the voltage level of the sensing node SN to the first node N1 of the sensing latch 210 through the first transistor 260. As described above, the first node N1 of the sense latch 210 may have a supply voltage.

When the voltage of the sensing node SN is the precharge voltage, the latch block 240 may adjust the voltage of the first node N1 of the sensing latch 210 to the ground voltage through the first transistor 260 in response to the ON voltage VON of the latch signal LAT. In this case, the first node N1 of the sense latch 210 may be set to the ground voltage.

When the voltage of the sense node SN is the ground voltage, the latch block 240 may avoid adjusting the voltage of the first node N1 of the sense latch 210 in response to the ON voltage VON of the latch signal LAT (or may retain the voltage of the first node N1 of the sense latch 210 without modification). Accordingly, the second node N2 of the sense latch 210 may be maintained at the power supply voltage, and the first node N1 may be maintained at the ground voltage.

At a fifth time T5, the transmission signal TRS is activated and set to the ON voltage VON. When the transfer signal TRS is set to the ON voltage VON, the transfer block 250 may output a signal provided through the first transistor 260 or the second transistor 270.

When the page buffer 13k belongs to the first group of page buffers 132, 134, 136 and 138, the page buffer 13k may receive the second sensing signal SEN 2. At a fifth time T5, the second sense signal SEN2 is activated and set to the ON voltage VON. The ON voltage VON may turn ON the second transistor 270. Accordingly, the transmission block 250 may output a logic level of the second node N2 of the sense latch 210.

When the page buffer 13k belongs to the page buffers 131, 133, 135, and 137 of the second group, the page buffer 13k may receive the fourth sensing signal SEN 4. At a fifth time T5, the fourth sense signal SEN4 is activated and set to the ON voltage VON. The ON voltage VON may turn ON the second transistor 270. Accordingly, the transmission block 250 may output a logic level of the second node N2 of the sense latch 210.

Fig. 7 illustrates an example of performing a sensing operation of the page buffer 13k when the page buffer 13k belongs to the first group of page buffers 132, 134, 136 and 138. Referring to fig. 1, 3, 6 and 7, the first node N1 of the sense latch 210 may be initialized to a high level (e.g., a power supply voltage). As marked by the first arrow a1, the voltage change of the bit line BL may be transmitted to the latch block 240.

As indicated by the second arrow A2, the latch block 240 may apply a voltage change of the bit line BL to the second node N2 of the sense latch 210. The voltage change of the bit line BL can also be applied to the first node N1 of the sense latch 210 through the cross-coupled inverter structure of the sense latch 210.

Fig. 8 illustrates an example of performing a sensing operation of the page buffer 13k when the page buffer 13k belongs to the page buffers 131, 133, 135 and 137 of the second group. Referring to fig. 1, 3, 6 and 8, the first node N1 of the sense latch 210 may be initialized to a high level (e.g., a power supply voltage).

As marked by the third arrow a3, the voltage change of the bit line BL may be transmitted to the latch block 240. As indicated by the fourth arrow A4, the latch block 240 may apply a voltage change of the bit line BL to the first node N1 of the sense latch 210.

In the page buffer 13k described with reference to fig. 7, the voltage change of the bit line BL is transmitted to the second node N2 of the sense latch 210 without passing through the internal inverter of the sense latch 210. In the page buffer 13k described with reference to fig. 8, the voltage change of the bit line BL is transmitted to the second node N2 of the sense latch 210 through the internal inverter of the sense latch 210.

That is, the page buffer 13k of fig. 8 may invert the sensing result of the voltage change of the bit line BL and may apply the inverted sensing result to the second node N2 of the sense latch 210. The page buffer 13k of fig. 7 may apply the sensing result of the voltage change of the bit line BL to the second node N2 of the sense latch 210 without inversion.

That is, each of the first to eighth page buffers 131 to 138 may perform a sensing operation on a selected memory cell in a different manner based on whether or not the respective page buffers belong to any page buffer group. This sensing scheme can accelerate the checking operation of the nonvolatile memory device 100 to determine the state of the selected memory cell MC _ S.

Fig. 9 shows an example of a change in the threshold voltage of the selected memory cell MC _ S. In fig. 9, the horizontal axis represents the threshold voltage VTH of the memory cell, and the vertical axis represents the number of memory cells.

Referring to fig. 1, 3, and 9, before a program operation is performed, for example, after an erase operation is performed on a selected memory cell MC _ S, the threshold voltage of the selected memory cell MC _ S may belong to a range corresponding to an erase state "E", as shown in a first block B1.

After the program operation is performed, the threshold voltages of the selected memory cells MC _ S may belong to ranges corresponding to the erase state "E" and the first through seventh program states P1 through P7, respectively, as shown in the second block B2. For example, each of the selected memory cells MC _ S may be controlled to have a threshold voltage belonging to a range corresponding to one of the erase state "E" and the first through seventh program states P1 through P7 based on data to be written therein.

In the selected memory cell MC _ S, degradation of retention may occur in the selected memory cell MC _ S over time after a program operation is performed on the selected memory cell MC _ S. As the degradation of retention occurs, the threshold voltages of some memory cells of the selected memory cells MC _ S may exceed the range to which some memory cells belong.

For example, as the boundary level of the range to which the threshold voltage belongs becomes lower or higher, the deterioration of the retention may become more serious. As the boundary level of the range to which the threshold voltage belongs becomes close to the center of the entire range of the threshold voltage, the deterioration of the retention may weakly occur. In some example embodiments, the degradation of retention that occurs in the erase state "E" and the seventh program state P7 is shown in the third block B3 of fig. 9.

Referring to third block B3, the threshold voltages of some of the memory cells having an erase state "E" may increase and may exceed the range of the erase state "E". In addition, the threshold voltages of some of the memory cells having the seventh program state P7 may be reduced and may exceed the range of the seventh program state P7.

When degradation of retention occurs, the threshold voltages of some of the memory cells having the erased state "E" may move to a range of the first programmed state P1. In addition, the threshold voltages of some of the memory cells having the seventh program state P7 can be moved to a range of sixth program state P6. Such shifts can lead to errors in the read operation.

In the case where an error occurs in the read operation, the nonvolatile memory device 100 may perform a check operation on the selected memory cell MC _ S for the purpose of resolving the error and completing the read operation. In addition, the nonvolatile memory device 100 may perform a check operation through the sensing operation described with reference to fig. 4 and 6, thus reducing time required for the check operation. For example, the controller circuit 420 may be configured to control the non-volatile memory 100 by sending a first request to check the state of the first and second memory cells and a second request to read the first and second memory cells. In response to the second request, the controller circuit 420 may be further configured to control the non-volatile memory device 100 to perform a read operation on the first memory cell and the second memory cell, and then perform the first sensing operation and the second sensing operation after the read operation.

FIG. 10 is an enlarged view of the sixth program state P6 and the seventh program state P7. In fig. 10, the horizontal axis represents the threshold voltage VTH of the memory cell, and the vertical axis represents the number of memory cells.

Referring to fig. 1, 3 and 10, a valley "V" may be formed at a point where the threshold voltage distribution of the memory cell of the sixth program state P6 and the threshold voltage distribution of the memory cell of the seventh program state P7 cross each other. When a read operation is performed by using the read voltage VRD (refer to fig. 6) having a level corresponding to the valley "V", a read error may be minimized.

The nonvolatile memory device 100 may be configured to perform a check operation for searching for a valley "V", and the check operation is referred to as a "valley search". The nonvolatile memory device 100 may shorten the time required for the check operation by using the sensing operation described with reference to fig. 4 and 6.

The valley search may be performed by performing a sensing operation using a level close to a level expected as the valley "V" and counting the number of memory cells based on the result of the sensing operation. For example, the non-volatile memory device 100 may perform a sensing operation by using the first voltage V1 and the second voltage V2, and may count memory cells having a threshold voltage between the first voltage V1 and the second voltage V2.

The nonvolatile memory device 100 may perform a sensing operation by using the second voltage V2 and the third voltage V3, and may count memory cells having a threshold voltage between the second voltage V2 and the third voltage V3. The non-volatile memory device 100 may identify a valley "V" based on the count result.

As another example, the nonvolatile memory device 100 may output the result of the sensing operation using the first voltage V1, the second voltage V2, and the third voltage V3 to an external device. The external device may perform a counting operation by using the result of the sensing operation, and may identify the valley "V".

Fig. 11 is a flowchart illustrating a method of the nonvolatile memory device 100 performing a valley search according to some example embodiments of some inventive concepts. Referring to fig. 1, 3, 5, 10, and 11, the nonvolatile memory device 100 may perform a reset operation and a precharge operation in operation S210.

For example, as described with reference to fig. 6, each of the page buffers 132, 134, 136, and 138 of the first group may set the second node N2 of the sense latch 210 to a low level and may set the first node N1 of the sense latch 210 to a high level through the second transistor 270. As another example, each of the page buffers 132, 134, 136 and 138 of the first group may set the first node N1 of the sense latch 210 to a low level and may set the second node N2 of the sense latch 210 to a high level through the first transistor 260.

The first to eighth page buffers 131 to 138 may precharge the first to eighth bit lines BL1 to BL8 to a power supply voltage through the selection block 220 and the precharge block 230.

In operation S220, the row decoder circuit 120 may adjust the voltage of the selected word line WL _ S to a first voltage V1. In operation S230, the non-volatile memory device 100 may perform a third sensing operation on the bit lines BL2, BL4, BL6, and BL8 of the first group and may obtain a third value. The third sensing operation may be performed before the first sensing operation described with reference to fig. 4.

In operation S240, the row decoder circuit 120 may adjust the voltage of the selected word line WL _ S to the second voltage V2. In operation S250, the non-volatile memory device 100 may perform a first sensing operation on the bit lines BL2, BL4, BL6, and BL8 of the first group and may obtain a first value. The first sensing operation may correspond to the first sensing operation described with reference to fig. 4.

The third value and the first value may be integrated in the page buffers 132, 134, 136, and 138 of the first group. In a particular page buffer of the first group of page buffers 132, 134, 136 and 138, the second node N2 of the sense latch 210 being at the high level may indicate that the threshold voltage of a particular memory cell corresponding to the particular page buffer is greater than the first voltage V1 and is the second voltage V2 or less.

The case where the second node N2 of the sense latch 210 of the specific page buffer is at a low level may indicate that the threshold voltage of the specific memory cell is less than the first voltage V1 or greater than the second voltage V2. That is, the number of memory cells between the first voltage V1 and the second voltage V2 may be counted by counting the number of high levels at the second node N2 of the latches in the page buffers 132, 134, 136 and 138 of the first group.

In operation S260, the non-volatile memory device 100 may perform a second sensing operation on the bit lines BL1, BL3, BL5, and BL7 of the second group and may obtain a second value. The second sensing operation may correspond to the second sensing operation described with reference to fig. 4.

In operation S270, the row decoder circuit 120 may adjust the voltage of the selected word line WL _ S to the third voltage V3. In operation S280, the non-volatile memory device 100 may perform a fourth sensing operation on the bit lines BL1, BL3, BL5, and BL7 of the second group and may obtain a fourth value. The fourth sensing operation may be performed before the second sensing operation described with reference to fig. 4.

The second value and the fourth value may be integrated in the page buffers 131, 133, 135, and 137 of the second group. In a specific page buffer of the second group of page buffers 131, 133, 135, and 137, the second node N2 of the sense latch 210 being at the high level may indicate that the threshold voltage of a specific memory cell corresponding to the specific page buffer is greater than the second voltage V2 and is the third voltage V3 or less.

The case where the second node N2 of the sense latch 210 of the specific page buffer is at the low level may indicate that the threshold voltage of the specific memory cell is less than the second voltage V2 or greater than the third voltage V3. That is, the number of memory cells between the second voltage V2 and the third voltage V3 may be counted by counting the number of high levels at the second node N2 of the latches in the page buffers 131, 133, 135, and 137 of the second group.

As described with reference to fig. 11, the number of memory cells having a threshold voltage between the first voltage V1 and the second voltage V2 and the number of memory cells having a threshold voltage between the second voltage V2 and the third voltage V3 may be identified by performing the third sensing operation, the first sensing operation, the second sensing operation, and the fourth sensing operation.

Since the memory cells are completely counted by one operation from the reset and precharge operation to the data transfer operation, the time required for the check operation can be significantly shortened.

Fig. 12 is a timing diagram of signals applied to the page buffer circuit 130 when the method of fig. 11 is performed. Referring to fig. 1, 3, 5 and 12, the reset operation at the first time T1 and the precharge operation at the second time T2 are performed the same as those described with reference to fig. 6. Therefore, additional description will be omitted to avoid redundancy.

At a third time T3, the row decoder circuit 120 may adjust the read voltage VRD to be applied to the selected word line WL _ S to the first voltage V1. When the threshold voltage of the memory cell connected to the bit line BL is the first voltage V1 or less, the voltage of the bit line BL may be discharged to the ground voltage. When the threshold voltage of the memory cell connected to the bit line BL is greater than the first voltage V1, the voltage of the bit line BL may be maintained at the precharge voltage.

At a fourth time T4, a third sensing operation may be performed. The latch signal LAT may be activated and may be set to the ON voltage VON; the first sense signal SEN1 may be activated and may be set to the ON voltage VON. As described with reference to fig. 8, the latch block 240 may apply the sensing result of the voltage change of the bit line BL to the first node N1 of the sense latch 210.

When the voltage of the bit line BL is the precharge voltage, the latch block 240 may change the voltage of the first node N1 of the sense latch 210 to the ground voltage. When the voltage of the bit line BL is the ground voltage, the latch block 240 may avoid changing the voltage of the first node N1 of the sense latch 210 (or may retain the voltage of the first node N1 of the sense latch 210 without modification). That is, through the first sensing operation, the first node N1 of the sense latch 210 of the page buffer corresponding to the memory cell having the threshold voltage greater than the first voltage V1 among the page buffers 132, 134, 136, and 138 of the first group may be set to a low level.

At a third time T5, the row decoder circuit 120 may regulate the read voltage VRD to a second voltage V2. When the threshold voltage of the memory cell connected to the bit line BL is the second voltage V2 or less, the voltage of the bit line BL may be discharged to the ground voltage. When the threshold voltage of the memory cell connected to the bit line BL is greater than the second voltage V2, the voltage of the bit line BL may be maintained at the precharge voltage.

At a sixth time T6, the first sensing operation may be performed. The latch signal LAT may be activated and may be set to the ON voltage VON; the second sense signal SEN2 may be activated and may be set to the ON voltage VON. As described with reference to fig. 7, the latch block 240 may apply the sensing result of the voltage change of the bit line BL to the second node N2 of the sense latch 210.

When the voltage of the bit line BL is the precharge voltage, the latch block 240 may change the voltage of the second node N2 of the sense latch 210 to the ground voltage. When the voltage of the bit line BL is the ground voltage, the latch block 240 may avoid changing the voltage of the second node N2 of the sense latch 210 (or may retain the voltage of the second node N2 of the sense latch 210 without modification). That is, through the first sensing operation, the second node N2 of the sense latch 210 of the page buffer corresponding to the memory cell having the threshold voltage greater than the second voltage V2 among the page buffers 132, 134, 136, and 138 of the first group may be set to a low level.

The case where the second node N2 of the sense latch 210 of the page buffer 13k is at the high level after the third and first sensing operations are performed may indicate that the threshold voltage of the memory cell connected to the bit line BL is between the first voltage V1 and the second voltage V2. The second node N2 of the sense latch 210 of the page buffer 13k being at the low level may indicate that the threshold voltage of the memory cell connected to the bit line BL is less than the first voltage V1 or greater than the second voltage V2.

At a sixth time T6, a second sensing operation may be further performed. The second sensing operation may be performed as the third sensing operation except that the second sensing operation is performed in the second group of page buffers 131, 133, 135, and 137. Therefore, additional description will be omitted to avoid redundancy. Embodiments are described in which a first sensing operation and a second sensing operation are simultaneously performed. However, the first and second sensing operations may be sequentially performed with a time difference based on the operating characteristics and the process characteristics of the nonvolatile memory device 100.

At a third time T7, the row decoder circuit 120 may regulate the read voltage VRD to a third voltage V3. When the threshold voltage of the memory cell connected to the bit line BL is the third voltage V3 or less, the voltage of the bit line BL may be discharged to the ground voltage. When the threshold voltage of the memory cell connected to the bit line BL is greater than the third voltage V3, the voltage of the bit line BL may be maintained at the precharge voltage.

At an eighth time T8, a fourth sensing operation may be performed. The fourth sensing operation may be performed as the first sensing operation, except that the fourth sensing operation is performed in the second group of page buffers 131, 133, 135, and 137. Therefore, additional description will be omitted to avoid redundancy.

After the fourth sensing signal, one page buffer of the page buffers 131, 133, 135 and 137 of the second group having a high level at the second node N2 indicates that the corresponding memory cell has a threshold voltage between the second voltage V2 and the third voltage V3. One page buffer of the page buffers 131, 133, 135 and 137 of the second group having a low level at the second node N2 indicates that the corresponding memory cell has a threshold voltage less than the second voltage V2 or greater than the third voltage V3.

At the ninth time T9, the second sensing signal SEN2, the fourth sensing signal SEN4, and the transfer signal TRS are activated and set to the ON voltage VON. The logic level of the second node N2 of the latches in the first to eighth page buffers 131 to 138 may be output through the second transistor 270 and the transmission block 250.

Fig. 13 shows an example of an ith page buffer 13i as another one of the first to eighth page buffers 131 to 138. Referring to fig. 1, 3 and 13, the page buffer 13i may include a sensing latch 210, a selection block 220, a precharge block 230, a latch block 240, a transfer block 250, a first transistor 260, a second transistor 270, a first reset block 280, a bias block 290, a data latch 310, a dump block 320, a second reset block 330, a data block 340, a third transistor 350 and a fourth transistor 360.

The configurations and operations of the sensing latch 210, the selection block 220, the precharge block 230, the latch block 240, the transmission block 250, the first transistor 260, the second transistor 270, and the first reset block 280 may be the same as those described with reference to fig. 5.

The bias block 290 is connected between the second node N2 of the sense latch 210 and the sense node SN. The BIAS block 290 may be controlled by a BIAS signal BIAS supplied through a signal line (e.g., a sixth common signal line) in the common signal line SIGC. That is, the BIAS blocks 290 of the first to eighth page buffers 131 to 138 may be simultaneously controlled in common by the BIAS signal BIAS of the sixth common signal line. In a programming operation, the BIAS block 290 may apply a voltage to the bit line BL (or may BIAS the bit line BL) based on the logic level of the second node N2 of the sense latch 210 in response to the BIAS signal BIAS.

The data latch 310 may include an inverter connected between the third node N3 and the fourth node N4. The inverters may be cross-coupled. The data latch 310 may receive the logic level sensed by the sense latch 210 through the transmission block 250 and may store the received logic level. In addition, the data latch 310 may receive a logic level to be transmitted to the sense latch 210 from an external device, and may store the received logic level.

Dump block 320 is connected between fourth node N4 of data latch 310 and sense node SN. The DUMP block 320 may be controlled by a DUMP signal DUMP supplied through a signal line (e.g., a seventh common signal line) in the common signal line SIGC. That is, the DUMP blocks 320 of the first to eighth page buffers 131 to 138 may be simultaneously controlled in common by the DUMP signal DUMP of the seventh common signal line. In a programming operation, DUMP block 320 may transfer the logic level of fourth node N4 of data latch 310 to sense latch 210 through sense node SN and latch block 240 in response to DUMP signal DUMP.

The second reset block 330 is connected to the third transistor 350 and the fourth transistor 360. The second reset block 330 may be controlled by a second reset signal RST2 supplied through a signal line (e.g., an eighth common signal line) in the common signal line SIGC. That is, the second reset blocks 330 in the first to eighth page buffers 131 to 138 may be simultaneously controlled in common by the second reset signal RST2 of the eighth common signal line. The second reset block 330 may apply the ground voltage to the third transistor 350 or the fourth transistor 360 and to the data latch 310 in response to the second reset signal RST 2.

The data block 340 may be configured to output the logic level of the third node N3 or the fourth node N4 of the data latch 310 to an external device.

The third transistor 350 is coupled between the third node N3 of the data latch 310 and the data block 340. The third transistor 350 may be controlled by a first signal S1 supplied through a signal line (e.g., a ninth common signal line) in the common signal line SIGC. That is, the third transistors 350 of the first to eighth page buffers 131 to 138 may be simultaneously controlled in common by the first signal S1 of the ninth common signal line. For example, the first signal S1 may have a logic level input to the page buffer 13i for the purpose of a program operation.

The fourth transistor 360 is connected between the fourth node N4 of the data latch 310 and the data block 340. The fourth transistor 360 may be controlled by a second signal S2 supplied through a signal line (e.g., a tenth common signal line) in the common signal line SIGC. That is, the fourth transistors 360 of the first to eighth page buffers 131 to 138 may be simultaneously controlled in common by the second signal S2 of the tenth common signal line. For example, the second signal S2 may have an inverted version of the logic level input to the page buffer 13i for the purpose of a program operation.

As described with reference to fig. 13, the page buffer 13i may include two or more latches. The remaining latches other than sense latch 210 may be data latches. The data latches may be connected to sense node SN through dump block 320 and may be connected to transfer block 250. The data latch may include a reset block, a data block, and a transistor between the data block and the data latch. The data latch may be configured to swap logic levels between the sense latch 210 and an external device.

In some example embodiments, the page buffers 132, 134, 136 and 138 of the first group may be configured to perform sensing on the bit lines BL2, BL4, BL6 and BL8 of the first group by using the sense latch 210, and perform sensing on the bit lines BL1, BL3, BL5 and BL7 of the second group by using the data latch 310. In this case, a node between the third transistor 350 and the data block 340 and a node between the fourth transistor 360 and the data block 340 may be further connected to the latch block 240.

When the page buffer 13i belongs to the page buffers 132, 134, 136, and 138 of the first group, the first transistor 260 may be controlled by a first sensing signal SEN1 transmitted through a signal line (e.g., a first line) in the first signal line SIGL 1. The second transistor 270 may be controlled by a second sensing signal SEN2 provided through a signal line (e.g., a second line) of the first signal line SIGL 1.

When the page buffer 13i belongs to the page buffers 131, 133, 135, and 137 of the second group, the third transistor 350 may be controlled by a third sensing signal SEN3 transmitted through a signal line (e.g., a first line) in the second signal line SIGL 2. The fourth transistor 360 may be controlled by a fourth sensing signal SEN4 provided through a signal line (e.g., a second line) of the second signal line SIGL 2.

Fig. 14 is a block diagram illustrating a storage device 400 according to some example embodiments of some inventive concepts. Referring to fig. 14, the storage device 400 may include a non-volatile memory device 410 and a controller circuit 420.

The non-volatile memory device 410 may include the non-volatile memory device 100 according to some example embodiments of some inventive concepts. The controller circuit 420 may be configured to control the non-volatile memory device 410. Controller circuit 420 may provide commands CMD and addresses ADDR (including row address RA and column address CA) to non-volatile memory device 410 through a first channel.

The controller circuit 420 may exchange DATA "with the non-volatile memory device 410 through the first channel. The DATA "may include two or more bits, and each of the bits may include a logic level indicating one of a high level and a low level. The controller circuit 420 may exchange control signals CTRL with the non-volatile memory device 410 via a second channel.

Fig. 15 is a flowchart illustrating an operation method of the storage apparatus 400 according to some example embodiments of some inventive concepts. Referring to fig. 15, the controller circuit 420 may transmit a first command CMD1 and a first address ADDR1 to the nonvolatile memory device 410 in operation S310. For example, first command CMD1 may have a format for requesting a check operation.

In response to the first command CMD1, the nonvolatile memory device 410 may perform the operations described with reference to fig. 11 and 12, for example, a check operation including a valley search on the memory cell indicated by the first address ADDR1 in operation S320. In operation S330, the non-volatile memory device 410 may transmit a response of the check operation to the controller circuit 420.

For example, the response may include DATA "indicating values of the memory cells, each of which has a threshold voltage between the first voltage V1 and the second voltage V2 and is obtained in operations S230 and S250 of fig. 11. In addition, the response may include DATA "indicating values of the respective memory cells, each of which has a threshold voltage between the second voltage V2 and the third voltage V3 and is obtained in operations S260 and S280 of fig. 11.

The controller circuit 420 may count the high levels from the response to count the number of memory cells each having a threshold voltage between the first voltage V1 and the second voltage V2 and to count the number of memory cells each having a threshold voltage between the second voltage V2 and the third voltage V3. The controller circuit 420 may identify a valley "V" based on the count thus calculated. The controller circuit 420 may adjust a parameter (e.g., the level of the read voltage VRD) used to access the non-volatile memory device 100 based on the identified valley "V".

In operation S340, the controller circuit 420 may send a second command CMD2 and a second address ADDR2 to the nonvolatile memory device 410. For example, second command CMD2 may have a format for requesting a read operation.

In response to the second command CMD2, the nonvolatile memory device 410 may perform an operation indicated by the second command CMD2, for example, a read operation for a memory cell indicated by the second address ADDR2 in operation S350. Based on the read operation, in operation S360, the nonvolatile memory device 410 may perform the operations described with reference to fig. 11 and 12, for example, a check operation including performing a valley search on the memory cell indicated by the second address ADDR 2.

In operation S370, the nonvolatile memory device 410 may transmit a response (e.g., the results of the read operation and the check operation) of the operation indicated by the second command CMD2 to the controller circuit 420. The response to the read operation may include data read from the memory cell indicated by second address ADDR 2. The response of the checking operation may include the values obtained according to the method of fig. 11.

As discussed herein, some example embodiments may include various forms of processing circuitry, such as row decoder circuitry 120, page buffer circuitry 130, data input and output circuitry 140, control logic circuitry 150, and/or controller circuitry 420. In some example embodiments, the processing circuitry may comprise hardware, such as logic circuitry; a hardware/software combination such as a processor executing software; or a combination thereof. For example, a processor may include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and so forth.

Moreover, some example embodiments may be described using example architectures, but other example embodiments may include different architectures without departing from the scope of the present disclosure. For example, in fig. 1, a nonvolatile memory device 100 includes a memory cell array 110, a row decoder circuit 120, a page buffer circuit 130, a data input and output circuit 140, and a control logic circuit 150. However, it will be understood that other example embodiments may include different structures of the processing circuitry, such as more or fewer components; different sets of relationships and interconnections; and/or different arrangements of functions between components. In some example embodiments, the first component may include the second component, while in other example embodiments, the first component and the second component may be separate and distinct. In some example embodiments, functionality may be implemented by a single component, while in other example embodiments, functionality may be distributed across two or more components. In various example embodiments, two or more components may operate synchronously and/or asynchronously. In various example embodiments, two or more components may operate sequentially and/or simultaneously.

According to some example embodiments of some inventive concepts, a nonvolatile memory device performs a first sensing operation on a first memory cell and a second sensing operation on a second memory cell, and inverts a result of one of the first sensing operation and the second sensing operation and obtains the inverted result. Accordingly, there are provided a nonvolatile memory device that provides a sensing operation so that a checking operation for checking a state of data stored in a first memory cell and a second memory cell can be accelerated, an operating method of the nonvolatile memory device, and a storage device including the nonvolatile memory device.

Although some examples of the inventive concept have been described with reference to some example embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made to some example embodiments of the inventive concept without departing from the spirit and scope of some inventive concepts set forth in the following claims.