阅读说明：本技术 3d nand存储器及其形成方法 (3D NAND memory and forming method thereof ) 是由 徐文祥 王贝寒 徐伟 黄攀 夏季 于 2020-06-03 设计创作，主要内容包括：一种3D NAND存储器及其形成方法,所述形成方法,在半导体衬底上形成堆叠结构,所述堆叠结构中形成有若干隔开的子阵列共源极结构,所述子阵列共源极沿垂直于半导体衬底的方向贯穿所述堆叠结构,且相邻子阵列共源极之间通过位于部分堆叠结构中的第一隔断结构隔开；在所述第一隔断结构上形成绝缘层；在所述堆叠结构上形成桥接结构,所述桥接结构包括设于所述绝缘层上的导电桥以及设于导电桥的两端的导电插塞,所述导电桥通过所述导电插塞连通相邻所述子阵列共源极结构。所述绝缘层由于覆盖所述第一隔断结构表面,因而在形成桥接结构时,能防止桥接结构与堆叠结构中的顶部选择栅或者顶部选择栅短接或者防止两者之间产生漏电。(A3D NAND memory and a forming method thereof are provided, wherein a stacked structure is formed on a semiconductor substrate, a plurality of separated subarray common-source structures are formed in the stacked structure, the subarray common-source structures penetrate through the stacked structure along a direction perpendicular to the semiconductor substrate, and adjacent subarray common-sources are separated by a first partition structure located in part of the stacked structure; forming an insulating layer on the first partition structure; and forming a bridging structure on the stacked structure, wherein the bridging structure comprises a conductive bridge arranged on the insulating layer and conductive plugs arranged at two ends of the conductive bridge, and the conductive bridge is communicated with the adjacent subarray common source structure through the conductive plugs. The insulating layer covers the surface of the first partition structure, so that when a bridging structure is formed, the bridging structure can be prevented from being short-circuited with the top selection gate or the top selection gate in the stacked structure or generating electric leakage between the bridging structure and the top selection gate or the top selection gate in the stacked structure.)

1. A method for forming a 3D NAND memory, comprising:

providing a semiconductor substrate, wherein a stacked structure with control gates and isolation layers stacked alternately is formed on the semiconductor substrate, a plurality of separated subarray common-source structures are formed in the stacked structure, the subarray common-source structures penetrate through the stacked structure along a direction perpendicular to the semiconductor substrate, and adjacent subarray common-sources are separated by a first separation structure located in part of the stacked structure;

forming an insulating layer on the first partition structure;

and forming a bridging structure on the stacked structure, wherein the bridging structure comprises a conductive bridge arranged on the insulating layer and conductive plugs arranged at two ends of the conductive bridge, and the conductive bridge is communicated with the adjacent subarray common source structure through the conductive plugs.

2. The method of forming a 3D NAND memory of claim 1, wherein the forming of the insulating layer and the bridge structure comprises: forming an isolation material layer covering the top surface of the stacked structure and the surfaces of the plurality of subarray common source structures and the first partition structure; carrying out first etching to remove the isolation material layer with partial thickness on the first partition structure, and forming a groove in the isolation material layer, wherein the width of the groove is greater than that of the first partition structure; performing second etching to remove the bottom parts of the two ends of the groove or parts of the isolation material layers on the two sides of the groove, and forming through holes penetrating through the isolation material layers at the two ends of the groove; and filling metal in the groove and the through holes at the two ends to form a conductive bridge and conductive plugs connected with the two ends of the conductive bridge, wherein the residual isolating material layer at the bottom of the groove is used as an insulating layer.

3. The method of forming a 3D NAND memory of claim 1, wherein the forming of the insulating layer and the bridge structure comprises: forming an isolation material layer covering the top surface of the stacked structure and the surfaces of the plurality of subarray common source structures and the first partition structure; performing first etching to remove partial isolation material layers on two sides of the first partition structure, and forming through holes respectively exposing partial surfaces of the subarray common source structures on two sides of the first partition structure; performing second etching to remove the isolation material layer with partial thickness between the two through holes, wherein the rest isolation material layer is used as an insulating layer, and the width of the insulating layer is greater than that of the first partition structure; and filling metal in the insulating layer and the through hole insulators on the two sides to form a conductive bridge and conductive plugs connected with the two ends of the conductive bridge.

4. The method of claim 2 or 3, wherein the via is square or elongated in shape, and the conductive plug is square or elongated in shape; the size of the insulating layer is larger than that of the first partition structure.

5. The method of forming a 3D NAND memory as claimed in claim 1 wherein the stacked structure includes a number of second gate spacer regions and a bank region located between adjacent second gate spacer regions, each of the second gate spacer regions having a second array common source therein extending vertically through the stacked structure, the bank region including a core region and a step region, the sub-array common source structure being located in the core region and/or the step region within the bank region.

6. The method according to claim 5, wherein the core region of the memory block region comprises a plurality of through hole regions parallel to the first direction and a plurality of first gate spacer regions separating the plurality of through hole regions, at least one control gate at the topmost layer in the stacked structure is used as a top select gate, a part of the subarray common source structures are distributed in the first gate spacer region along the direction in which the first gate spacer regions extend, and adjacent subarray common source structures in the first gate spacer region are separated by a first partition structure penetrating the top select gate; and a second partition structure is formed in the top selection grid of the through hole region, and the second partition structure is used for disconnecting the top selection grid of the through hole region along the direction parallel to the first direction.

7. The method of forming a 3D NAND memory of claim 5 wherein the first and second spacer structures are formed in the same process step.

8. The method for forming a 3D NAND memory according to claim 5, wherein the step region of the memory block region comprises a plurality of third gate spacer regions, the third gate spacer regions are distributed in a staggered manner with respect to the first gate spacer regions, a part of the subarray common source structures are distributed in the third gate spacer regions along a direction in which the third gate spacer regions extend, and adjacent subarray common source structures in the third gate spacer regions are separated by a first partition structure penetrating through at least one step.

9. The method of forming a 3D NAND memory as claimed in claim 6, wherein a plurality of channel vias and dummy channel vias are formed in the via region to vertically penetrate the stack structure, the channel vias having memory structures formed therein, and the dummy channel vias having dummy channel structures formed therein.

10. A3D NAND memory, comprising:

a semiconductor substrate;

a stack structure disposed on the semiconductor substrate, the stack structure including control gates and isolation layers alternately stacked; a plurality of spaced sub-array common-source structures penetrating the stacked structure in a direction perpendicular to the semiconductor substrate;

the first partition structure partitions the adjacent subarray common source structures;

the bridging structure comprises a conductive bridge arranged on the insulating layer and conductive plugs arranged at two ends of the conductive bridge, and the conductive bridge is communicated with the adjacent subarray common source structure through the conductive plugs.

11. The 3D NAND memory of claim 10 wherein the conductive plug is square or elongated in shape; the size of the insulating layer is larger than that of the first partition structure.

12. The 3D NAND memory of claim 10 wherein the stack structure comprises a number of second gate spacer regions and a bank region between adjacent second gate spacer regions, each of the second gate spacer regions having a second array common source therein extending vertically through the stack structure, the bank region comprising a core region and a mesa region, the sub-array common source structure being located at the core region and/or the mesa region within the bank region.

13. The 3D NAND memory of claim 12 wherein the core region of the memory block region includes a plurality of via regions parallel to the first direction and a plurality of first gate spacer regions separating the plurality of via regions, at least one control gate of a topmost layer in the stack structure being a top select gate, portions of the sub-array common source structures being distributed in the first gate spacer region in a direction in which the first gate spacer regions extend, adjacent ones of the sub-array common source structures in the first gate spacer region being separated from each other by a first partition structure extending through the top select gate; and a second partition structure is formed in the top selection grid of the through hole region, and the second partition structure is used for disconnecting the top selection grid of the through hole region along the direction parallel to the first direction.

14. The 3D NAND memory of claim 13 wherein the step regions of the memory block region include a plurality of third gate spacer regions, the third gate spacer regions being staggered from the first gate spacer regions, portions of the subarray common source structures being distributed in the third gate spacer regions along a direction in which the third gate spacer regions extend, adjacent subarray common source structures in the third gate spacer regions being separated from each other by a first partition structure that extends through at least one step.

15. The 3D NAND memory of claim 14 further comprising a number of channel vias and dummy channel vias in the via region that vertically traverse the stacked structure; a memory structure in the channel via, a dummy channel structure in the dummy channel via.

16. The 3D NAND memory of claim 15 wherein the memory structure comprises a charge storage layer on a sidewall surface of the trench via and a channel layer on a sidewall surface of the charge storage layer, the charge storage layer comprising a blocking layer on a sidewall surface of the trench via, a charge trapping layer on a sidewall surface of the blocking layer, and a tunneling layer on a sidewall surface of the charge trapping layer.

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a 3D-reduced NAND memory and a method thereof.

Background

The NAND flash memory is a nonvolatile memory product with low power consumption, light weight and good performance, and is widely applied to electronic products. At present, a NAND flash memory with a planar structure is approaching the limit of practical expansion, and in order to further improve the storage capacity and reduce the storage cost per bit, a NAND memory with a 3D structure is proposed.

The formation process of existing 3D NAND memories generally includes: forming a stacked structure in which isolation layers and sacrificial layers are alternately stacked on a substrate; etching the stacked structure to form a channel through hole in the stacked structure, etching the substrate at the bottom of the channel through hole after the channel through hole is formed, and forming a groove in the substrate; forming an Epitaxial silicon layer, also commonly referred to as SEG, in the recess at the bottom of the trench via by Selective Epitaxial Growth (Selective Epitaxial Growth); forming a charge storage layer and a channel layer in the channel through hole, wherein the channel layer is connected with the epitaxial silicon layer; and removing the sacrificial layer, and forming a control gate or a word line at the position where the sacrificial layer is removed.

The existing memory generally comprises a plurality of memory blocks (blocks) and a plurality of Finger storage areas (changers) located in the memory blocks (blocks), the memory blocks and the Finger storage areas are generally separated by gate slots penetrating through the stacked structure along the vertical direction and array common sources located in the gate slots, in order to improve the strength of the stacked structure and prevent the stacked structure from inclining or collapsing, part of the array common sources are made into an "H" type structure, specifically, a plurality of sub-array common source structures penetrating through the stacked structure are formed in the stacked structure, adjacent sub-array common source structures are separated by partition structures formed in the stacked structure, and then, a connecting bridge for connecting a plurality of subarray common source structures is formed on the partition structure, but the problem of electric leakage easily exists between the existing connecting bridge and the top selection gate.

Disclosure of Invention

The invention aims to solve the technical problem that electric leakage is easy to exist between a connecting bridge and a top selection grid.

To this end, the present invention provides a method of forming a 3D NAND memory, comprising:

providing a semiconductor substrate, wherein a stacked structure with control gates and isolation layers stacked alternately is formed on the semiconductor substrate, a plurality of separated subarray common-source structures are formed in the stacked structure, the subarray common-source structures penetrate through the stacked structure along a direction perpendicular to the semiconductor substrate, and adjacent subarray common-sources are separated by a first separation structure located in part of the stacked structure;

forming an insulating layer on the first partition structure;

forming a bridging structure on the stacked structure, wherein the bridging structure comprises a conductive bridge arranged on the insulating layer and conductive plugs arranged at two ends of the conductive bridge, and the conductive bridge is communicated with the adjacent subarray common source structure through the conductive plugs to form an insulating layer on the first partition structure;

and forming a bridging structure on the stacked structure, wherein the bridging structure comprises a conductive bridge arranged on the insulating layer and conductive plugs arranged at two ends of the conductive bridge, and the conductive bridge is communicated with the adjacent subarray common source structure through the conductive plugs.

Optionally, the forming process of the insulating layer and the bridge structure includes: forming an isolation material layer covering the top surface of the stacked structure and the surfaces of the plurality of subarray common source structures and the first partition structure; carrying out first etching to remove the isolation material layer with partial thickness on the first partition structure, and forming a groove in the isolation material layer, wherein the width of the groove is greater than that of the first partition structure; performing second etching to remove the bottom parts of the two ends of the groove or parts of the isolation material layers on the two sides of the groove, and forming through holes penetrating through the isolation material layers at the two ends of the groove; and filling metal in the groove and the through holes at the two ends to form a conductive bridge and conductive plugs connected with the two ends of the conductive bridge, wherein the residual isolating material layer at the bottom of the groove is used as an insulating layer.

Optionally, the forming process of the insulating layer and the bridge structure includes: forming an isolation material layer covering the top surface of the stacked structure and the surfaces of the plurality of subarray common source structures and the first partition structure; performing first etching to remove partial isolation material layers on two sides of the first partition structure, and forming through holes respectively exposing partial surfaces of the subarray common source structures on two sides of the first partition structure; performing second etching to remove the isolation material layer with partial thickness between the two through holes, wherein the rest isolation material layer is used as an insulating layer, and the width of the insulating layer is greater than that of the first partition structure; and filling metal in the insulating layer and the through hole insulators on the two sides to form a conductive bridge and conductive plugs connected with the two ends of the conductive bridge.

Optionally, the through hole is square or long-strip shaped, and the conductive plug is square or long-strip shaped; the size of the insulating layer is larger than that of the first partition structure.

Optionally, the stacked structure includes a plurality of second gate spacer regions and a memory block region located between adjacent second gate spacer regions, each of the second gate spacer regions has a second array common source vertically penetrating through the stacked structure, the memory block region includes a core region and a step region, and the sub-array common source structure is located in the core region and/or the step region in the memory block region.

Optionally, the core region of the memory block region includes a plurality of via regions parallel to the first direction and a plurality of first gate spacer regions separating the plurality of via regions, at least one control gate on the topmost layer in the stacked structure is used as a top select gate, a part of the subarray common source structures are distributed in the first gate spacer region along a direction in which the first gate spacer region extends, and adjacent subarray common source structures in the first gate spacer region are separated by a first partition structure penetrating through the top select gate; and a second partition structure is formed in the top selection grid of the through hole region, and the second partition structure is used for disconnecting the top selection grid of the through hole region along the direction parallel to the first direction.

Optionally, the first partition structure and the second partition structure are formed in the same process step.

Optionally, the step region of the memory block region includes a plurality of third gate isolation trench regions, the third gate isolation trench regions are staggered from the first gate isolation trench regions, a portion of the subarray common source structures are distributed in the third gate isolation trench regions along a direction in which the third gate isolation trench regions extend, and adjacent subarray common source structures in the third gate isolation trench regions are separated by a first partition structure penetrating through at least one step.

Optionally, a plurality of channel through holes and dummy channel through holes vertically penetrating through the stacked structure are formed in the through hole region, a storage structure is formed in the channel through holes, and a dummy channel structure is formed in the dummy channel through holes.

The present invention also provides a 3D NAND memory, comprising:

a semiconductor substrate;

a stack structure disposed on the semiconductor substrate, the stack structure including control gates and isolation layers alternately stacked; a plurality of spaced sub-array common-source structures penetrating the stacked structure in a direction perpendicular to the semiconductor substrate;

the first partition structure partitions the adjacent subarray common source structures;

the bridging structure comprises a conductive bridge arranged on the insulating layer and conductive plugs arranged at two ends of the conductive bridge, and the conductive bridge is communicated with the adjacent subarray common source structure through the conductive plugs.

Optionally, the conductive plug is square or long; the size of the insulating layer is larger than that of the first partition structure.

Optionally, the stacked structure includes a plurality of second gate spacer regions and a memory block region located between adjacent second gate spacer regions, each of the second gate spacer regions has a second array common source vertically penetrating through the stacked structure, the memory block region includes a core region and a step region, and the sub-array common source structure is located in the core region and/or the step region in the memory block region.

Optionally, the core region of the memory block region includes a plurality of via regions parallel to the first direction and a plurality of first gate spacer regions separating the plurality of via regions, at least one control gate on the topmost layer in the stacked structure is used as a top select gate, a part of the subarray common source structures are distributed in the first gate spacer region along a direction in which the first gate spacer region extends, and adjacent subarray common source structures in the first gate spacer region are separated by a first partition structure penetrating through the top select gate; and a second partition structure is formed in the top selection grid of the through hole region, and the second partition structure is used for disconnecting the top selection grid of the through hole region along the direction parallel to the first direction.

Optionally, the step region of the memory block region includes a plurality of third gate isolation trench regions, the third gate isolation trench regions are staggered from the first gate isolation trench regions, a portion of the subarray common source structures are distributed in the third gate isolation trench regions along a direction in which the third gate isolation trench regions extend, and adjacent subarray common source structures in the third gate isolation trench regions are separated by a first partition structure penetrating through at least one step.

Optionally, the memory further includes a plurality of channel vias and dummy channel vias in the via region and vertically penetrating the stacked structure; a memory structure in the channel via, a dummy channel structure in the dummy channel via.

Optionally, the storage structure includes a charge storage layer on a sidewall surface of the trench via and a channel layer on a sidewall surface of the charge storage layer, where the charge storage layer includes a blocking layer on a sidewall surface of the trench via, a charge trapping layer on a sidewall surface of the blocking layer, and a tunneling layer on a sidewall surface of the charge trapping layer.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the forming method of the 3D NAND memory, a stacking structure is formed on a semiconductor substrate, a plurality of separated subarray common source structures are formed in the stacking structure, the subarray common sources penetrate through the stacking structure along the direction perpendicular to the semiconductor substrate, and adjacent subarray common sources are separated by a first partition structure located in part of the stacking structure; forming an insulating layer on the first partition structure; and forming a bridging structure on the stacked structure, wherein the bridging structure comprises a conductive bridge arranged on the insulating layer and conductive plugs arranged at two ends of the conductive bridge, and the conductive bridge is communicated with the adjacent subarray common source structure through the conductive plugs. The insulating layer covers the surface of the first partition structure, so that when a bridging structure is formed, the bridging structure can be prevented from being short-circuited with the top selection gate or the top selection gate in the stacked structure or generating electric leakage between the bridging structure and the top selection gate or the top selection gate in the stacked structure.

Furthermore, the size of the formed insulating layer is larger than that of the first partition structure, that is, the insulating layer covers not only the surface of the first partition structure but also the surfaces of the subarray common source structure and the part of the stacked structure around the first partition structure, so that when the bridging structure is formed, the bridging structure can be better prevented from being shorted with the top select gate or the top select gate in the stacked structure or from generating electric leakage between the bridging structure and the top select gate or the top select gate in the stacked structure.

Further, the conductive plug in the bridging structure is square or long, compared with the circular conductive plug, the size (length) of the square or long conductive plug in the extending direction of the subarray common source structure can be made longer, that is, the photoetching process when the square or long conductive plug is formed is not limited by the width of the subarray common source structure, so that the window of the photoetching process when the conductive plug is formed is enlarged, the contact area between the conductive plug and the subarray common source structure is enlarged, and the contact resistance between the bridging structure and the subarray common source structure is reduced.

Further, the forming process of the insulating layer and the bridging structure comprises the following steps: forming an isolation material layer covering the top surface of the stacked structure and the surfaces of the plurality of subarray common source structures and the first partition structure; carrying out first etching to remove the isolation material layer with partial thickness on the first partition structure, and forming a groove in the isolation material layer, wherein the width of the groove is greater than that of the first partition structure; performing second etching to remove the bottom parts of the two ends of the groove or parts of the isolating material layers on the two sides of the groove, and forming through holes penetrating through the isolating material layers at the two ends of the groove, wherein the through holes are square or long-strip; and filling metal in the groove and the through holes at the two ends to form a conductive bridge and conductive plugs connected with the two ends of the conductive bridge, wherein the residual isolating material layer at the bottom of the groove is used as an insulating layer. When the insulating layer and the bridging structure are formed, only one step of isolation material layer forming process and one step of metal filling process are needed, and the forming process of the insulating layer and the bridging structure is simplified.

Further, the forming process of the insulating layer and the bridging structure comprises the following steps: forming an isolation material layer covering the top surface of the stacked structure and the surfaces of the plurality of subarray common source structures and the first partition structure; performing first etching to remove partial isolation material layers on two sides of the first partition structure, and forming through holes respectively exposing partial surfaces of the subarray common source structures on two sides of the first partition structure, wherein the through holes are square or long-strip; performing second etching to remove the isolation material layer with partial thickness between the two through holes, wherein the rest isolation material layer is used as an insulating layer, and the width of the insulating layer is greater than that of the first partition structure; and filling metal in the insulating layer and the through hole insulators on the two sides to form a conductive bridge and conductive plugs connected with the two ends of the conductive bridge. When the insulating layer and the bridging structure are formed, only one step of isolation material layer forming process and one step of metal filling process are needed, and the forming process of the insulating layer and the bridging structure is simplified.

According to the 3D NAND memory, the insulating layer covers the surface of the first partition structure, so that when the bridge structure is formed, the bridge structure can be prevented from being short-circuited with the top selection gate or the top selection gate in the stacked structure or electric leakage between the bridge structure and the top selection gate or the top selection gate in the stacked structure can be prevented.

Drawings

FIG. 1 is a schematic diagram of a 3D NAND memory according to an embodiment of the present invention;

FIGS. 2-3 are schematic structural diagrams of a 3D NAND memory according to another embodiment of the invention.

FIGS. 4-12 are schematic structural diagrams illustrating a 3D NAND memory formation process according to another embodiment of the present invention.

Detailed Description

As mentioned in the background, the current method for forming the connecting bridge and the top select gate is prone to have a leakage problem.

It has been found that, in one embodiment, with reference to fig. 1, the 3D NAND memory comprises: a semiconductor substrate 100, a stacked structure in which control gates 127 and isolation layers 104 are alternately stacked on the semiconductor substrate 100; an array common-source penetrating the stacked structure, the array common-source comprising a plurality of sub-common-sources 125 penetrating the stacked structure, adjacent sub-common-sources 125 being isolated by a partition structure 112 located in the stacked structure, each sub-common-source comprising a polysilicon layer 125a and a metal layer 125b located on the polysilicon layer 125 a; and the connecting bridge 142 is positioned on the partition structure 112 and is in contact with the adjacent common source 125, and the material of the connecting bridge 142 is metal.

Further research shows that the formation process of the connecting bridge 142 is as follows: forming a dielectric layer 141 on the stacked structure; forming a mask layer (not shown in the figure) on the dielectric layer, wherein the mask layer is provided with a plurality of openings exposing the surface of the dielectric layer, and the positions of the openings correspond to the positions of the connecting bridges to be formed; etching the dielectric layer 141 along the opening by taking the mask layer as a mask, and forming an etching groove corresponding to the opening in the dielectric layer 141, wherein the etching groove exposes the surface of the partition structure 112 and part of the top surface of the subarray common source structure 125; the etched groove is filled with metal to form a connecting bridge 142. In the process of etching the dielectric layer 141 to form an etched trench, the exposed blocking structure 112 at the bottom of the etched trench is easily over-etched, so that the top control gate or the top select gate on both sides of the bottom of the etched trench is easily exposed (the blocking structure 112 penetrates through the top control gate or the top select gate between the common source structures 125 of adjacent subarrays), and the connecting bridge 142 formed in the etched trench is easily shorted with the top control gate (or the top select gate) or generates electric leakage.

In order to solve the aforementioned problem that the connection bridge 142 is easily shorted to the top control gate (or the top select gate) or leakage occurs, in another embodiment, referring to fig. 2 and fig. 3, fig. 2 is a schematic cross-sectional structure view of fig. 3 along the direction of the cutting line CD, before forming the connection bridge 145, an insulating layer 144 is formed on the surface of the partition structure 112, a connection bridge 145 for connecting the two adjacent subarray common source structures 125 is formed on the surface of the insulating layer 144 and on a portion of the surface of the two adjacent subarray common source structures 125, and specifically, the connection bridge 145 includes a conductive bridge crossing over a portion of the surface of the insulating layer 144 and circular hole plugs connected to both ends of the conductive bridge on the surface of the subarray common source structures 125. The step of forming the circular hole-type plug is to form a circular through hole exposing part of the surface of the subarray common source structure 125 in the dielectric layer 141, and then fill metal in the circular through hole. Since the width (dimension along the y-axis direction in fig. 3) of the sub-array common-source structure 125 is limited, the size of the circular hole pattern plug in the formed connection bridge 145 is also limited, so that the size of the circular through hole is also limited, and therefore the size of the window of the photolithography process when the circular through hole is formed is limited, and the size of the circular hole pattern plug is limited, so that the contact area between the circular hole pattern plug and the sub-array common-source structure 125 is small, and the contact resistance is increased.

The invention provides a 3D NAND memory and a forming method thereof, wherein a stacked structure is formed on a semiconductor substrate, a plurality of separated subarray common-source structures are formed in the stacked structure, the subarray common-source structures penetrate through the stacked structure along the direction vertical to the semiconductor substrate, and adjacent subarray common-sources are separated by a first partition structure in part of the stacked structure; forming an insulating layer on the first partition structure; and forming a bridging structure on the stacked structure, wherein the bridging structure comprises a conductive bridge arranged on the insulating layer and conductive plugs arranged at two ends of the conductive bridge, and the conductive bridge is communicated with the adjacent subarray common source structure through the conductive plugs. The insulating layer covers the surface of the first partition structure, so that when a bridging structure is formed, the bridging structure can be prevented from being short-circuited with the top selection gate or the top selection gate in the stacked structure or generating electric leakage between the bridging structure and the top selection gate or the top selection gate in the stacked structure.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

Fig. 4-12 are schematic structural diagrams of a 3D NAND formation process according to another embodiment of the invention.

Referring to fig. 4-7, wherein fig. 5 is a schematic cross-sectional structure view along a cutting line AB in fig. 4, fig. 6 is a schematic cross-sectional structure view along a cutting line CD in fig. 4, fig. 7 is a schematic cross-sectional structure view along a cutting line EF in fig. 4, a semiconductor substrate 100 (see fig. 5-7) is provided, a stacked structure 131 in which a control gate 127 and an isolation layer 104 are alternately stacked is formed on the semiconductor substrate 100, a plurality of spaced sub-array common source structures 125 are formed in the stacked structure 131, the sub-array common source structures 125 penetrate through the stacked structure 131 in a direction perpendicular to the semiconductor substrate 100, and adjacent sub-array common sources 125 are spaced apart from each other by a first partition structure 112 located in a part of the stacked structure 131.

The material of the semiconductor substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 100 is single crystal silicon (Si).

The stack structure 131 in which the control gates 127 and the isolation layers 104 are alternately stacked means that: a control gate 127 has a corresponding spacer 104 thereon, the control gate 127 and spacers 104 being alternately arranged. In this embodiment, the Bottom layer of the stacked structure 131 is a control Gate, the top layer is an isolation layer 104, at least one control Gate (specifically, one or two control gates) at the Bottom layer in the stacked structure is used as a Bottom Selective Gate (BSG) 128, and at least one control Gate (specifically, one or two control gates) at the top layer in the stacked structure 131 is used as a Top Selective Gate (TSG) 129. The number of the stacked structures 131 is determined according to the number of memory cells required to be formed in the vertical direction, the number of the stacked structures 131 may be 8, 32, 64, and the like, and the greater the number of the stacked structures 131, the higher the integration level can be.

In an embodiment, the control gate 127 includes a high-K dielectric layer and a metal gate located on the surface of the high-K dielectric layer, and the metal gate may be made of one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni. HfO as the material of the high-K dielectric layer₂、TiO₂、HfZrO、HfSiNO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃Or BaSrTiO. In other embodiments, the control gate 127 may include a silicon oxide dielectric layer and a polysilicon gate on the dielectric layer. The material of the isolation layer 104 may be one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.

In an embodiment, the first partition structure 112, the plurality of subarray common source structures 125, and the control gate 127 are formed by: forming an initial stacked structure of alternately stacked sacrificial layers (not shown) and isolation layers 104 on the semiconductor substrate 100, wherein the material of the sacrificial layers is different from that of the isolation layers 104, the material of the sacrificial layers may be silicon nitride, and subsequently forming control gates at positions where the sacrificial layers are removed; forming a plurality of discrete grooves penetrating at least one sacrificial layer (specifically, one or two sacrificial layers) on the topmost layer, wherein the plurality of grooves are sequentially arranged along the direction extending along the first direction (x axis); filling an isolation material in the grooves to form a plurality of first partition structures 112; etching the initial stacking structure to form a plurality of channel through holes and pseudo channel through holes which vertically penetrate through the initial stacking structure; a memory structure 119 is formed in the channel via hole, and a dummy channel structure (not shown in the figure) is formed in the dummy channel via hole; etching the initial stacked structure between the first partition structures 112, and forming a sub-gate partition groove penetrating through the initial stacked structure in the initial stacked structure between the first partition structures 112; removing the sacrificial layer along the sub-gate separation groove; correspondingly forming a control gate 127 at the position where the sacrificial layer is removed; and filling a conductive material in the sub-gate isolation grooves to form a plurality of subarray common source structures 125, wherein the control gates 127 and the isolation layers 104 are alternately stacked to form a stacked structure 131.

The material of the first partition structure 112 may be silicon oxide, silicon nitride, silicon oxynitride, or other suitable isolation materials.

In an embodiment, each subarray common source structure 125 includes a polysilicon layer 125a and a metal layer 125b (refer to fig. 6 or fig. 7) on the polysilicon layer 125a, and the material of the metal layer 125b may be W, Cu, Ti, or other suitable metal.

In an embodiment, the subarray common-source structure 125 is further isolated from the stacked structure 131 by an isolation spacer 136 (refer to fig. 4 or fig. 6), and the subarray common-source structure 125 is isolated from the control gate 127 (and the top select gate 129 and the bottom select gate 128) by the isolation spacer 136. The isolation sidewall 136 may be made of one or more of silicon oxide, silicon nitride, and silicon oxynitride.

In an embodiment, referring to fig. 4, the stacked structure 131 includes several second gate spacer regions 23 and a memory block region 41 located between adjacent second gate spacer regions 23, each second gate spacer region 23 has a second array common source 126 vertically penetrating through the stacked structure 131, the memory block region 41 includes a core region and a step region (only the core region in the memory block region 41 is shown in fig. 4, the step region is not shown), and the sub-array common source structure 125 is located in the core region and/or the step region within the memory block region 41. Only two second gate spacer regions 23 and one memory block region 41 located between the two second gate spacer regions 23 are shown in fig. 4 as an example for illustration. It should be noted that, the number of the second gate spacer regions in the stacked structure may be other, the number of the memory block regions may also be other, and the number of the second gate spacer regions and the number of the memory blocks should not limit the protection scope of the present invention. In this embodiment, the x-axis direction is taken as the first direction.

The core area of the memory block area 41 is used for forming a memory array of a 3D NAND memory, and the step area has a plurality of steps which are raised step by step and a plug connected to each step. The step areas may be located at two sides of the core area, or may be located in the middle of the core area, which is not limited herein.

In an embodiment, referring to fig. 4, the core region of the memory block region 41 includes a plurality of via regions 21 parallel to the first direction and a plurality of first gate spacer regions 22 separating the plurality of via regions 21, a portion of the subarray common source structures 125 are distributed in the first gate spacer region 22 along a direction (x-axis direction) in which the first gate spacer region 22 extends, adjacent subarray common source structures 125 in the first gate spacer region 22 are separated by a first separation structure 112 penetrating through the top select gate, and then adjacent subarray common source structures in the first gate spacer region 22 are connected by forming a bridge structure. In other embodiments, the step region of the memory block region 41 includes a plurality of third gate spacer regions, the third gate spacer regions are staggered from the first gate spacer regions, a portion of the subarray common source structures are distributed in the third gate spacer regions along a direction in which the third gate spacer regions extend, adjacent subarray common source structures in the third gate spacer regions are separated by a first partition structure penetrating through at least one step, and then adjacent subarray common source structures in the third gate spacer regions are connected by forming a bridge structure.

In one embodiment, the core region of each memory block region 41 includes at least two via regions 21 and at least one first gate spacer region 22 separating the two via regions 21, the via region 21 has formed therein a number of trench vias and memory structures located in the trench vias, the first gate spacer region 22 has a plurality of sub-array common-source structures 125 arranged along a first direction and a first spacer structure 112 located between adjacent sub-array common-source structures, in fig. 4, only one core region including three via regions 21 and at least two first gate spacer regions 22 separating the three via regions 21 per memory block region 41 is taken as an example to illustrate, and it should be noted that, in other embodiments, the core region of each memory block region 41 includes other numbers of via regions 21 and first gate spacer regions 22, and the numbers of via regions 21 and first gate spacer regions 22 in each memory block region 41 should not limit the scope of the present invention.

In an embodiment, referring to fig. 4 and 5 in combination, the top select gate 129 of the via region 21 has a second blocking structure 111 formed therein, and the second blocking structure 111 blocks the top select gate 129 of the via region 21 in a direction parallel to the first direction. The top control gates 129 in each memory block 41 may be disconnected into a number of strips by the second partition structures 111, and thus each memory block (block) may be divided into a number of finger storage regions (fingers) corresponding to the number of strips of disconnected top select gates 129 (each disconnected top select gate may be independently applied with a voltage to perform a corresponding operation, including an erase operation, on the corresponding memory structure in the corresponding finger storage region). In a specific embodiment, the second partition structure 111 may be formed simultaneously with the first partition structure 125.

In an embodiment, referring to fig. 4 and 5 in combination, the via region 21 has a plurality of channel vias and dummy channel vias vertically penetrating the stacked structure 131, the channel vias having the memory structures 119 formed therein, and the dummy channel vias having dummy channel structures (not shown) formed therein.

The memory structure 119 includes a charge storage layer 118 on a sidewall surface of the channel via and a channel layer 117 on a sidewall surface of the charge storage layer 118.

In one embodiment, the charge storage layer 118 includes a blocking layer on a sidewall surface of the trench via, a charge trapping layer on a sidewall surface of the blocking layer, and a tunneling layer on a sidewall surface of the charge trapping layer; the channel layer 117 fills the remaining channel vias. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The charge trapping layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof, and the channel layer 117 material may be polysilicon doped with N-type impurity ions, such as phosphorus ions. In a specific embodiment, the charge storage layer 118 may be a composite layer of silicon oxide/silicon oxynitride (or silicon nitride)/silicon oxide (ONO).

The dummy channel structure may be a single-layer or multi-layer stack structure for improving mechanical strength and stability of the stack structure during formation of the 3D NAND memory.

In an embodiment, referring to fig. 5, a groove is formed in the semiconductor substrate 100 at the bottom of the channel via, a first semiconductor epitaxial layer 116 is formed in the groove and in a part of the channel via, the top surface of the first semiconductor epitaxial layer 116 is higher than the top surface of the bottom select gate 128 and is lower than the top surface of the lowermost isolation layer 104, the material of the first semiconductor epitaxial layer 116 may be silicon, germanium or silicon germanium, and the memory structure 119 is located in the channel via on the first semiconductor epitaxial layer 116; the top surface of the memory structure 119 is higher than the top surface of the top select gate 106 than the top surface of the topmost isolation layer 104, a connection plug 120 is formed on the top surface of the memory structure 119, and the material of the connection plug 120 may be silicon, germanium, silicon germanium or metal.

Referring to fig. 8, fig. 8 is performed on the basis of fig. 6, and an isolation material layer 137 is formed to cover the top surface of the stacked structure and the surfaces of the several sub-array common source structures 125 and the first partition structure 112.

The layer 137 of isolating material is used to define the location of the bridging structure and to form an insulating layer.

In a specific embodiment, the material of the isolation material layer 137 may be one or more of silicon oxide, FSG (fluorine doped silicon dioxide), BSG (boron doped silicon dioxide), PSG (phosphorus doped silicon dioxide), or BPSG (boron doped silicon dioxide), or other suitable isolation materials. The isolation material layer 137 is formed by chemical vapor deposition, and may be plasma-enhanced chemical vapor deposition, atmospheric pressure chemical vapor deposition, low-pressure chemical vapor deposition, high-density plasma chemical vapor deposition, or atomic layer chemical vapor deposition.

Referring to fig. 9, a first etching is performed to remove a partial thickness of the isolation material layer 137 on the first partition structure 112, and a trench 138 is formed in the isolation material layer 137, wherein a width of the trench 138 is greater than a width of the first partition structure 112.

In an embodiment, before performing a first etching and etching on the isolation material layer 137, forming a first photoresist layer on the surface of the isolation material layer 137, exposing and developing the first photoresist layer, forming a first opening in the first photoresist layer to expose a part of the surface of the isolation material layer 137, etching and removing the isolation material layer with a partial thickness along the first opening with the first photoresist layer as a mask, forming a trench 138 in the isolation material layer 137, where the trench 138 is located above the first partition structure 112, the width of the trench 138 is greater than the width of the first partition structure 112, and the remaining isolation material layer at the bottom of the trench 138 is subsequently used as an insulating layer; and removing the first photoresist layer. It should be noted that the width of the groove 138 and the width of the first blocking structure 112 refer to the dimension of the groove 138 and the first blocking structure 112 along the x-axis direction.

Referring to fig. 10, performing a second etching to remove the bottom of the trench 138 or portions of the isolation material layer 137 at both ends of the trench 138, forming through holes 139 penetrating through the isolation material layer 137 at both ends of the trench 138, where the bottoms of the through holes 139 respectively expose portions of the surfaces of the subarray common source structures 125 at both sides of the first partition structure 112.

In an embodiment, before the second etching, a second photoresist layer is formed in the trench 138 and on the isolation material layer 137, the second photoresist layer is exposed and developed, and a square opening exposing the bottom of both ends of the trench 138 or a portion of the surface of the isolation material layer 137 at both sides of the trench is formed in the second photoresist layer; and etching the isolation material layer 137 along the square opening by using the second photoresist layer as a mask, and forming through holes 139 penetrating through the isolation material layer 137 at two ends of the trench 138.

The cross section of the through hole 139 is square or elongated, specifically, the square is rectangular, because the length (the dimension along the x axis or the extending direction of the array common source) of the sub-array common source structure 125 is greater than the width thereof, that is, the length of the square or elongated through hole 139 formed to expose a part of the surface of the sub-array common source structure 125 at two sides of the first partition structure 112 is longer, compared with the smaller process window of the photolithography process when forming the circular groove (the circular groove is limited by the width of the sub-array common source structure 125, the diameter cannot be too large, so the process window when forming the circular groove is limited), the window of the photolithography process when forming the square or elongated through hole 139 is increased, particularly, the photolithography process window in the extending direction of the x axis or the array common source is increased, and the square or elongated conductive plug 142 is formed in the square or elongated through hole 139 later (refer to subsequent figures) 11, and 12), the contact area between the square or strip-shaped conductive plug and the subarray common-source structure 125 is increased, so that the contact resistance between the bridge structure and the subarray common-source structure 125 is reduced.

It should be noted that, in other embodiments, the via in the isolation material layer may be formed before the trench, and the specific process includes: forming an isolation material layer covering the top surface of the stacked structure and the surfaces of the plurality of subarray common source structures and the first partition structure; performing first etching to remove part of the isolation material layers on the two sides of the first partition structure, and forming through holes respectively exposing part of surfaces of the subarray common source structures on the two sides of the first partition structure, wherein the through holes can be square or long strips; performing second etching to remove the isolation material layer with partial thickness between the two through holes, wherein the rest isolation material layer is used as an insulating layer, and the width of the insulating layer is greater than that of the first partition structure; and filling metal in the insulating layer and the through hole insulators on the two sides to form a conductive bridge and conductive plugs connected with the two ends of the conductive bridge.

Referring to fig. 11 and 12, fig. 12 is a schematic top view structure diagram of a part of the surface of fig. 11, a metal is filled in the trench 138 (see fig. 10) and the via 139 (see fig. 10) at both ends to form a conductive bridge 141 and a conductive plug 142 connected to both ends of the conductive bridge 141, the conductive bridge 141 and the conductive plug 142 form a bridge structure 143 that electrically connects the adjacent subarray common source structures 125, the remaining isolation material layer at the bottom of the trench serves as an insulating layer 145, and the insulating layer 145 covers the surface of the first partition structure 112 and the subarray common source structure 125 and a part of the surface of the stacked structure around the first partition structure 112.

In an embodiment, the shape of the formed conductive plug is square or long strip.

The metal can be one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni.

Specifically, the conductive bridge 141 and the conductive plug 142 are formed in the same step, the forming process of the conductive bridge 141 and the conductive plug 142 may be an electroplating process, and the forming process of the conductive bridge 141 and the conductive plug 142 may also be a sputtering and planarization process.

In an embodiment, the size of the formed insulating layer 145 is larger than that of the first partition structure 112, that is, the insulating layer 145 covers not only the surface of the first partition structure 112 but also the sub-array common-source structure 125 and the surface of the stacked structure portion around the first partition structure 112, so that when the bridging structure 143 is formed, the bridging structure 143 can be better prevented from being shorted with the top select gate or the top select gate in the stacked structure or from generating a leakage current therebetween. Moreover, since the bridging structure 143 includes the conductive plug 142, the conductive plug 142 is square or long, and compared with the circular conductive plug, the dimension (length) of the square or long conductive plug 142 in the extending direction of the subarray common-source structure can be made longer, that is, the photolithography process when forming the square or long conductive plug 142 is not limited by the width of the subarray common-source structure, so that the window of the photolithography process when forming the conductive plug 142 is increased, and the contact area between the conductive plug 142 and the subarray common-source structure 125 is increased, thereby reducing the contact resistance between the bridging structure 143 and the subarray common-source structure 125.

In other embodiments, the size of the insulating layer may be equal to the size of the first partition structure.

In this embodiment, the insulating layer 145 and the bridge structure 143 are formed through the foregoing steps, and since only one step of forming the isolation material layer and one step of metal filling are required, the steps of forming the insulating layer 145 and the bridge structure 143 are simplified.

In other embodiments, an insulating layer covering the surface of the first partition structure 112 and the surface of the sub-array common source structure 125 and the surface of the stacked structure portion around the first partition structure 112 may be formed first; then forming a dielectric layer covering the insulating layer and the surface of the stacked structure; then forming a square opening exposing part of the surface of the insulating layer and the surface of the subarray common source structure measured by the insulating layer in the dielectric layer; and filling metal in the square openings to form a bridging structure, wherein the bridging structure comprises a conductive bridge which spans on part of the insulating layer and two square conductive plugs which connect two ends of the conductive bridge with the corresponding subarray common source structures respectively.

An embodiment of the present invention also provides a 3D NAND memory, referring to fig. 4, 5, 11, and 12, including:

a semiconductor substrate 100;

a stack structure 131 disposed on the semiconductor substrate 100, the stack structure 131 including control gates 127 and isolation layers 104 alternately stacked; a number of spaced sub-array common-source structures 125, the sub-array common-source structures 125 penetrating the stacked structure 131 in a direction perpendicular to the semiconductor substrate 100;

at least one first partition structure 112 and an insulating layer 145 disposed on the first partition structure 112, wherein the first partition structure 112 partitions adjacent subarray common-source structures 125;

a bridge structure 143, where the bridge structure 143 includes a conductive bridge 141 disposed on the insulating layer 145 and conductive plugs 142 disposed at two ends of the conductive bridge 141, and the conductive bridge 141 communicates with the adjacent subarray common source structure 125 through the conductive plugs 142.

Specifically, the material of the conductive bridge 141 and the conductive plug 142 is metal. The conductive plug 142 is square or strip.

In an embodiment, the stacked structure 131 includes several second gate spacer regions 23 and a memory block region 41 located between adjacent second gate spacer regions 23, each second gate spacer region 23 has a second array common source 126 vertically penetrating through the stacked structure 131, the memory block region 41 includes a core region and a step region (only the core region in the memory block region 41 is shown in fig. 4, the step region is not shown), and the subarray common source structure 125 is located in the core region and/or the step region in the memory block region 41.

In an embodiment, the core region of the memory block region 41 includes a plurality of via regions 21 parallel to the first direction and a plurality of first gate spacer regions 22 separating the plurality of via regions 21, a portion of the subarray common source structures 125 are distributed in the first gate spacer regions 22 along a direction (x-axis direction) in which the first gate spacer regions 22 extend, and adjacent subarray common source structures 125 in the first gate spacer regions 22 are separated by first partition structures 112 penetrating through the top select gates. In other embodiments, in an embodiment, the step region of the memory block region 41 includes a plurality of third gate spacer regions, the third gate spacer regions are distributed in a staggered manner with respect to the first gate spacer regions, a portion of the subarray common-source structures are distributed in the third gate spacer regions along a direction in which the third gate spacer regions extend, and adjacent subarray common-source structures in the third gate spacer regions are separated by a first partition structure penetrating through at least one step.

Referring to fig. 4 and 5, a number of channel vias and dummy channel vias are also included in the via region 21, which vertically penetrate the stacked structure; a memory structure 119 located in the channel via, and a dummy channel structure located in the dummy channel via.

The memory structure 119 includes a charge storage layer 118 on a sidewall surface of the trench via and a channel layer 117 on a sidewall surface of the charge storage layer 118, and the charge storage layer 118 includes a blocking layer on a sidewall surface of the trench via, a charge trapping layer on a sidewall surface of the blocking layer, and a tunneling layer on a sidewall surface of the charge trapping layer.

It should be noted that other limitations or descriptions related to the 3D NAND memory in this embodiment are not repeated in this embodiment, and specific reference is made to relevant limitations or descriptions of the 3D NAND memory forming process in the foregoing embodiment.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.