阅读说明：本技术 一种显示基板及其制备方法、驱动方法、显示装置 (Display substrate, preparation method and driving method thereof, and display device ) 是由 刘鹏 徐敬义 刘弘 霍培荣 张永强 于 2020-06-17 设计创作，主要内容包括：一种显示基板及其制备方法、驱动方法、显示装置,显示基板包括：基底以及设置在基底上的开关结构,开关结构,分别与控制信号端、信号输入端和信号输出端电连接；开关结构包括：开关单元；开关单元包括：第一晶体管和第二晶体管；第一晶体管和第二晶体管的类型相反；第一晶体管包括：第一有源层、第一栅电极、第一源电极和第一漏电极,第二晶体管包括：第二有源层、第二栅电极、第二源电极和第二漏电极；第一栅电极和第二栅电极分别与控制信号端电连接,第一源电极和第二源电极分别与信号输入端电连接,第一漏电极和第二漏电极分别与信号输出端电连接；第一有源层在基底上的正投影与第二有源层在基底上的正投影重合。(A display substrate, a preparation method thereof, a driving method thereof and a display device are provided, wherein the display substrate comprises: the switch structure is electrically connected with the control signal end, the signal input end and the signal output end respectively; the switch structure includes: a switch unit; the switch unit includes: a first transistor and a second transistor; the first transistor and the second transistor are opposite in type; the first transistor includes: a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor includes: a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; the first gate electrode and the second gate electrode are respectively and electrically connected with a control signal end, the first source electrode and the second source electrode are respectively and electrically connected with a signal input end, and the first drain electrode and the second drain electrode are respectively and electrically connected with a signal output end; the orthographic projection of the first active layer on the substrate is coincident with the orthographic projection of the second active layer on the substrate.)

1. A display substrate, comprising: the switch structure is respectively electrically connected with a control signal end, a signal input end and a signal output end and is arranged to provide a signal of the signal input end for the signal output end under the control of the control signal end;

the switch structure includes: a switch unit; the switching unit includes: a first transistor and a second transistor; the first transistor and the second transistor are opposite in type;

the first transistor includes: a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, the second transistor including: a second active layer, a second gate electrode, a second source electrode, and a second drain electrode;

the first gate electrode and the second gate electrode are respectively electrically connected with the control signal end, the first source electrode and the second source electrode are respectively electrically connected with the signal input end, and the first drain electrode and the second drain electrode are respectively electrically connected with the signal output end;

the orthographic projection of the first active layer on the substrate is coincident with the orthographic projection of the second active layer on the substrate.

2. The display substrate according to claim 1, wherein the number of the switch units is N;

a first source electrode of the first switch unit is electrically connected with the signal input end, a first drain electrode of the jth switch unit is electrically connected with a first source electrode of the (j + 1) th switch unit, and a first drain electrode of the Nth switch unit is electrically connected with the signal output end;

the first gate electrodes and the second gate electrodes of all the switch units are respectively electrically connected with the control signal end, N is more than or equal to 1, and 1< j < N.

3. The display substrate of claim 1, further comprising: scanning signal lines, data signal lines, a common electrode and pixel electrodes disposed on the substrate;

the scanning signal line is electrically connected with the control signal end and is arranged to provide signals for the control signal end;

the data signal line is connected with the signal input end and is used for providing signals to the signal input end;

the signal output end is connected with the pixel electrode and is used for providing signals for the pixel electrode;

the common electrode is positioned on one side of the pixel electrode close to the substrate and is arranged to form an electric field with the pixel electrode.

4. The display substrate according to claim 3, wherein the first gate electrode and the second gate electrode are the same electrode;

the first active layer is positioned on one side of the first gate electrode close to the substrate; the second active layer is positioned on one side of the first gate electrode, which is far away from the substrate; the second active layer is connected to the first active layer.

5. The display substrate according to claim 4, wherein when the first transistor is an N-type transistor and the second transistor is a P-type transistor;

the first active layer includes: the first channel region, the first doping region, the second doping region, the third doping region and the fourth doping region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer;

the first doping region and the second doping region have the same doping type and are respectively positioned at two sides of the first channel region;

the third doping region and the fourth doping region are the same in doping type, the third doping region is located on one side, away from the first channel region, of the first doping region, and the fourth doping region is located on one side, away from the first channel region, of the second doping region;

the doping concentration of the third doping area is greater than that of the first doping area;

the second active layer includes: the second channel region, the fifth doped region and the sixth doped region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer;

the fifth doping region and the sixth doping region have the same doping type and are respectively located on two sides of the second channel region.

6. The display substrate according to claim 5, wherein when the number of the switching cells is one, in the switching cells, the second source electrode and the second drain electrode are provided on a side of the second active layer away from the base; the second source electrode is electrically connected with the third doped region through the fifth doped region, and the second source electrode and the fifth doped region are reused as a first source electrode; the second drain electrode is electrically connected with the fourth doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as a first drain electrode;

when the number of the switching cells is at least two, in each switching cell, the second source electrode and the second drain electrode are disposed on a side of the second active layer away from the substrate; the second source electrode is electrically connected with the third doped region through the fifth doped region, and the second source electrode and the fifth doped region are reused as a first source electrode; the second drain electrode is electrically connected with the fourth doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as a first drain electrode; the second drain electrode of the ith switch unit and the second source electrode of the (i + 1) th switch unit are the same electrode, and i is more than or equal to 1 and is less than N;

or when the number of the switching units is at least two, the second source electrode of the first switching unit is arranged on one side, away from the substrate, of the second active layer of the first switching unit, and the second drain electrode of the last switching unit is arranged on one side, away from the substrate, of the second active layer of the last switching unit; in the first switch unit, the second source electrode is electrically connected with the third doped region through the fifth doped region, and the second source electrode and the fifth doped region are reused as the first source electrode; the sixth doped region is reused as a second drain electrode, and the fourth doped region is reused as a first drain electrode; in the jth switch unit, the fifth doped region is reused as a second source electrode, the third doped region is reused as a first source electrode, the sixth doped region is reused as a second drain electrode, the fourth doped region is reused as a first drain electrode, and j is more than 1 and less than N; the sixth doped region of the j-1 th switch unit and the fifth doped region of the j-1 th switch unit are the same doped region, and the fourth doped region of the j-1 th switch unit and the third doped region of the j-1 th switch unit are the same doped region; in the last switch unit, the fifth doped region is reused as a second source electrode, the third doped region is reused as a first source electrode, the second drain electrode is electrically connected with the fourth doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as a first drain electrode.

7. The display substrate according to claim 6, wherein when the first transistor is a P-type transistor and the second transistor is an N-type transistor;

the first active layer includes: the first channel region, the first doping region and the second doping region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer;

the first doping region and the second doping region have the same doping type and are respectively positioned at two sides of the first channel region;

the second active layer includes: the second channel region, the third doped region, the fourth doped region, the fifth doped region and the sixth doped region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer;

the third doping region and the fourth doping region have the same doping type and are respectively positioned at two sides of the second channel region;

the fifth doping region and the sixth doping region are the same in doping type, the fifth doping region is located on one side, away from the second channel region, of the third doping region, and the sixth doping region is located on one side, away from the second channel region, of the fourth doping region;

the doping concentration of the fifth doping area is larger than that of the third doping area.

8. The display substrate according to claim 7, wherein when the number of the switching cells is one, in the switching cells, the second source electrode and the second drain electrode are provided on a side of the second active layer away from the base; the second source electrode is electrically connected with the first doped region through the fifth doped region, and the second source electrode and the fifth doped region are multiplexed to be a first source electrode; the second drain electrode is electrically connected with the second doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as a first drain electrode;

when the number of the switching cells is at least two, in each switching cell, the second source electrode and the second drain electrode are disposed on a side of the second active layer away from the substrate; the second source electrode is electrically connected with the first doped region through the fifth doped region, and the second source electrode and the fifth doped region are multiplexed to be a first source electrode; the second drain electrode is electrically connected with the second doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as a first drain electrode; the second drain electrode of the ith switch unit and the second source electrode of the (i + 1) th switch unit are the same electrode, and i is more than or equal to 1 and is less than N;

or when the number of the switching units is at least two, the second source electrode of the first switching unit is arranged on one side, away from the substrate, of the second active layer of the first switching unit, and the second drain electrode of the last switching unit is arranged on one side, away from the substrate, of the second active layer of the last switching unit; in the first switch unit, the second source electrode is electrically connected with the first doped region through the fifth doped region, and the second source electrode and the fifth doped region are multiplexed to be the first source electrode; the sixth doped region is reused as a second drain electrode, and the second doped region is reused as a first drain electrode; in the jth switch unit, the fifth doped region is reused as a second source electrode, the first doped region is reused as a first source electrode, the sixth doped region is reused as a second drain electrode, the second doped region is reused as a first drain electrode, and j is more than 1 and less than N; the sixth doped region of the j-1 th switch unit and the fifth doped region of the j-th switch unit are the same doped region, and the second doped region of the j-1 th switch unit and the first doped region of the j-th switch unit are the same doped region; in the last switch unit, the fifth doped region is reused as a second source electrode, the first doped region is reused as a first source electrode, the second drain electrode is electrically connected with the second doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as a first drain electrode.

9. The display substrate according to any one of claims 5 to 8, wherein an orthographic projection of the first channel region on the base coincides with an orthographic projection of the second channel region on the base;

an orthographic projection of the first channel region on the substrate at least partially overlaps an orthographic projection of the first gate electrode on the substrate.

10. The display substrate of claim 9, further comprising: a light-shielding layer;

the light shielding layer is located on one side, close to the substrate, of the first active layer, and an orthographic projection of the light shielding layer on the substrate covers an orthographic projection of the first channel region on the substrate.

11. The display substrate of claim 10, wherein the display substrate comprises: the first metal layer, the first insulating layer, the first polysilicon layer, the second insulating layer, the second metal layer, the third insulating layer, the second polysilicon layer, the fourth insulating layer and the third metal layer are sequentially arranged along the direction vertical to the substrate;

the first metal layer includes: a light-shielding layer, the first polysilicon layer including: a first active layer, the second metal layer comprising: a first gate electrode and a scan signal line, the second polysilicon layer including: a second active layer, the third metal layer comprising: a second source electrode, a second drain electrode, and a data signal line.

12. The display substrate of claim 11, further comprising: the flat layer, the first transparent conducting layer, the fifth insulating layer and the second transparent conducting layer;

the flat layer is positioned on one side of the third metal layer far away from the substrate, and a first through hole exposing the second drain electrode is formed in the flat layer;

the first transparent conducting layer is positioned on one side, away from the substrate, of the flat layer, and a second through hole exposing the first through hole is formed in the first transparent conducting layer; the orthographic projection of the second via hole on the substrate covers the orthographic projection of the first via hole on the substrate; the first transparent conductive layer includes: a common electrode;

the fifth insulating layer is positioned on one side, away from the substrate, of the first transparent conducting layer, and a third through hole exposing the second through hole is formed in the fifth insulating layer;

the second transparent conductive layer is located on one side, away from the substrate, of the fifth insulating layer, and the second transparent conductive layer includes: and the pixel electrode is connected with the second drain electrode through the first via hole, the second via hole and the third via hole.

13. A display device, comprising: a display substrate according to any one of claims 1 to 12.

14. A method of manufacturing a display substrate, arranged to form a display substrate as claimed in any one of claims 1 to 12, the method comprising:

providing a substrate;

forming a switch structure on the substrate; the switch structure is respectively electrically connected with the control signal end, the signal input end and the signal output end and is arranged to provide the signal of the signal input end for the signal output end under the control of the control signal end; the switch structure includes: a switch unit; the switching unit includes: a first transistor and a second transistor; the first transistor and the second transistor are opposite in type; the first transistor includes: a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, the second transistor including: a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; the first gate electrode and the second gate electrode are respectively electrically connected with the control signal end, the first source electrode and the second source electrode are respectively electrically connected with the signal input end, and the first drain electrode and the second drain electrode are respectively electrically connected with the signal output end; the orthographic projection of the first active layer on the substrate is coincident with the orthographic projection of the second active layer on the substrate.

15. The method of claim 14, wherein the forming a switching structure on the substrate comprises:

sequentially forming a first metal layer and a first insulating layer on a substrate; the first metal layer includes: a light-shielding layer;

forming a first polysilicon layer on the first insulating layer; the first polysilicon layer includes: a first active layer;

sequentially forming a second insulating layer and a second metal layer on the first insulating layer on which the first polysilicon layer is formed; the second metal layer includes: a first gate electrode and a scanning signal line; the first gate electrode and the second gate electrode are the same electrode;

forming a third insulating layer on the second insulating layer on which the second metal layer is formed;

forming a second polysilicon layer on the third insulating layer, the second polysilicon layer comprising: a second active layer;

sequentially forming a fourth insulating layer and a third metal layer on the third insulating layer on which the second polysilicon layer is formed, the third metal layer including: a second source electrode, a second drain electrode, and a data signal line.

16. The method of claim 15, wherein after sequentially forming a fourth insulating layer and a third metal layer on the third insulating layer on which the second polysilicon layer is formed, the method further comprises:

forming a flat layer on the fourth insulating layer on which the third metal layer is formed;

forming a first transparent conductive layer on the planarization layer, the first transparent conductive layer comprising: a common electrode;

forming a fifth insulating layer on the first transparent conductive layer;

forming a second transparent conductive layer on the fifth insulating layer, the second transparent conductive layer including: and a pixel electrode.

17. The method of claim 16, wherein when the first transistor is an N-type transistor and the second transistor is a P-type transistor,

the forming a first polysilicon layer on the first insulating layer includes:

depositing a first amorphous silicon film on the first insulating layer, crystallizing the first amorphous silicon film, and processing the crystallized first amorphous silicon film through a composition process to form a first polycrystalline silicon film; the first polysilicon film includes: the first region, the second region, the third region, the fourth region and the fifth region are arranged along a direction perpendicular to the arrangement direction of the first active layer and the second active layer, the second region and the third region are respectively positioned at two sides of the first region, the fourth region is positioned at one side of the second region far away from the first region, and the fifth region is positioned at one side of the third region far away from the first region;

carrying out threshold voltage doping treatment on the first polycrystalline silicon thin film;

carrying out N-type heavy doping treatment on the fourth region and the fifth region of the first polycrystalline silicon film;

carrying out N-type light doping treatment on the second region and the third region of the first polycrystalline silicon thin film to form a first polycrystalline silicon layer;

the forming a second polysilicon layer on the third insulating layer includes:

depositing a second amorphous silicon film on the third insulating layer, crystallizing the second amorphous silicon film, and processing the crystallized second amorphous silicon film through a composition process to form a second polycrystalline silicon film; the second polysilicon film includes: the first region, the second region and the third region are arranged along a direction vertical to the arrangement direction of the first active layer and the second active layer, and the second region and the third region are respectively positioned at two sides of the first region;

carrying out P-type doping treatment on the second region and the third region of the second polycrystalline silicon thin film to form a second polycrystalline silicon layer;

when the first transistor is a P-type transistor and the second transistor is an N-type transistor,

the forming a first polysilicon layer on the first insulating layer includes:

depositing a first amorphous silicon film on the first insulating layer, crystallizing the first amorphous silicon film, and processing the crystallized first amorphous silicon film through a composition process to form a first polycrystalline silicon film; the first polysilicon film includes: the first region, the second region and the third region are arranged along a direction vertical to the arrangement direction of the first active layer and the second active layer, and the second region and the third region are respectively positioned at two sides of the first region;

carrying out P-type doping treatment on the second region and the third region of the first polycrystalline silicon thin film to form a first polycrystalline silicon layer;

the forming a second polysilicon layer on the third insulating layer includes:

depositing a second amorphous silicon film on the third insulating layer, crystallizing the second amorphous silicon film, and processing the crystallized second amorphous silicon film through a composition process to form a second polycrystalline silicon film; the second polysilicon film includes: the first region, the second region, the third region, the fourth region and the fifth region are arranged along a direction perpendicular to the arrangement direction of the first active layer and the second active layer, the second region and the third region are respectively positioned at two sides of the first region, the fourth region is positioned at one side of the second region far away from the first region, and the fifth region is positioned at one side of the third region far away from the first region;

carrying out threshold voltage doping treatment on the second polycrystalline silicon thin film;

carrying out N-type heavy doping treatment on the fourth region and the fifth region of the second polycrystalline silicon film;

and carrying out N-type light doping treatment on the second region and the third region of the second polycrystalline silicon film to form a second polycrystalline silicon layer.

18. A method of driving a display substrate, for driving a display substrate as claimed in any one of claims 1 to 12, the method comprising:

the control signal terminal is provided with a control signal to provide the signal of the signal input terminal to the signal output terminal.

19. The method of claim 18, wherein providing the control signal to the control signal terminal when the signal at the signal input terminal is a high level signal comprises:

providing a first control signal to a control signal end, wherein the first control signal is a low-level signal;

when the signal of the signal input end is a low level signal, the providing the control signal to the control signal end comprises:

and providing a second control signal to the control signal end, wherein the second control signal is a high-level signal.

Technical Field

The present disclosure relates to but not limited to the field of display technologies, and in particular, to a display substrate, a manufacturing method thereof, a driving method thereof, and a display device.

Background

In recent years, flat panel displays, such as Thin Film Transistor-liquid crystal displays (TFT-LCDs) and Active Matrix Organic Light Emitting Diode (AMOLED), have been widely used in electronic products such as televisions and mobile phones because of their advantages of light weight, Thin thickness, and low power consumption.

With the development of display technology, high frequency driving display products are becoming a trend. However, the high frequency driving of the display product may cause the charging time of each row of pixels in the display product to be reduced, so that the charging rate of the display product is reduced, and the display effect of the display product is affected.

Disclosure of Invention

The disclosure provides a display substrate, a manufacturing method thereof, a driving method thereof and a display device, which can improve the charging rate of a display product and improve the display effect.

In a first aspect, the present disclosure provides a display substrate comprising: the switch structure is respectively electrically connected with a control signal end, a signal input end and a signal output end and is arranged to provide a signal of the signal input end for the signal output end under the control of the control signal end;

the switch structure includes: a switch unit; the switching unit includes: a first transistor and a second transistor; the first transistor and the second transistor are opposite in type;

the first transistor includes: a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, the second transistor including: a second active layer, a second gate electrode, a second source electrode, and a second drain electrode;

the first gate electrode and the second gate electrode are respectively electrically connected with the control signal end, the first source electrode and the second source electrode are respectively electrically connected with the signal input end, and the first drain electrode and the second drain electrode are respectively electrically connected with the signal output end;

the orthographic projection of the first active layer on the substrate is coincident with the orthographic projection of the second active layer on the substrate.

In some possible implementations, the number of the switch units is N;

a first source electrode of the first switch unit is electrically connected with the signal input end, a first drain electrode of the jth switch unit is electrically connected with a first source electrode of the (j + 1) th switch unit, and a first drain electrode of the Nth switch unit is electrically connected with the signal output end;

the first gate electrodes and the second gate electrodes of all the switch units are respectively electrically connected with the control signal end, N is more than or equal to 1, and 1< j < N.

In some possible implementations, the display substrate further includes: scanning signal lines, data signal lines, a common electrode and pixel electrodes disposed on the substrate;

the scanning signal line is electrically connected with the control signal end and is arranged to provide signals for the control signal end;

the data signal line is connected with the signal input end and is used for providing signals to the signal input end;

the signal output end is connected with the pixel electrode and is used for providing signals for the pixel electrode;

the common electrode is positioned on one side of the pixel electrode close to the substrate and is arranged to form an electric field with the pixel electrode.

In some possible implementations, the first gate electrode and the second gate electrode are the same electrode;

the first active layer is positioned on one side of the first gate electrode close to the substrate; the second active layer is positioned on one side of the first gate electrode, which is far away from the substrate; the second active layer is connected to the first active layer.

In some possible implementations, when the first transistor is an N-type transistor and the second transistor is a P-type transistor;

the first active layer includes: the first channel region, the first doping region, the second doping region, the third doping region and the fourth doping region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer;

the first doping region and the second doping region have the same doping type and are respectively positioned at two sides of the first channel region;

the third doping region and the fourth doping region are the same in doping type, the third doping region is located on one side, away from the first channel region, of the first doping region, and the fourth doping region is located on one side, away from the first channel region, of the second doping region;

the doping concentration of the third doping area is greater than that of the first doping area;

the second active layer includes: the second channel region, the fifth doped region and the sixth doped region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer;

the fifth doping region and the sixth doping region have the same doping type and are respectively located on two sides of the second channel region.

In some possible implementations, when the number of the switching cells is one, in the switching cells, the second source electrode and the second drain electrode are disposed on a side of the second active layer away from the substrate; the second source electrode is electrically connected with the third doped region through the fifth doped region, and the second source electrode and the fifth doped region are reused as a first source electrode; the second drain electrode is electrically connected with the fourth doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as a first drain electrode;

when the number of the switching cells is at least two, in each switching cell, the second source electrode and the second drain electrode are disposed on a side of the second active layer away from the substrate; the second source electrode is electrically connected with the third doped region through the fifth doped region, and the second source electrode and the fifth doped region are reused as a first source electrode; the second drain electrode is electrically connected with the fourth doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as a first drain electrode; the second drain electrode of the ith switch unit and the second source electrode of the (i + 1) th switch unit are the same electrode, and i is more than or equal to 1 and is less than N;

or when the number of the switching units is at least two, the second source electrode of the first switching unit is arranged on one side, away from the substrate, of the second active layer of the first switching unit, and the second drain electrode of the last switching unit is arranged on one side, away from the substrate, of the second active layer of the last switching unit; in the first switch unit, the second source electrode is electrically connected with the third doped region through the fifth doped region, and the second source electrode and the fifth doped region are reused as the first source electrode; the sixth doped region is reused as a second drain electrode, and the fourth doped region is reused as a first drain electrode; in the jth switch unit, the fifth doped region is reused as a second source electrode, the third doped region is reused as a first source electrode, the sixth doped region is reused as a second drain electrode, the fourth doped region is reused as a first drain electrode, and j is more than 1 and less than N; the sixth doped region of the j-1 th switch unit and the fifth doped region of the j-1 th switch unit are the same doped region, and the fourth doped region of the j-1 th switch unit and the third doped region of the j-1 th switch unit are the same doped region; in the last switch unit, the fifth doped region is reused as the second source electrode, the third doped region is reused as the first source electrode, the second drain electrode is electrically connected with the fourth doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as the first drain electrode

In some possible implementations, when the first transistor is a P-type transistor and the second transistor is an N-type transistor;

the first active layer includes: the first channel region, the first doping region and the second doping region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer;

the first doping region and the second doping region have the same doping type and are respectively positioned at two sides of the first channel region;

the second active layer includes: the second channel region, the third doped region, the fourth doped region, the fifth doped region and the sixth doped region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer;

the third doping region and the fourth doping region have the same doping type and are respectively positioned at two sides of the second channel region;

the fifth doping region and the sixth doping region are the same in doping type, the fifth doping region is located on one side, away from the second channel region, of the third doping region, and the sixth doping region is located on one side, away from the second channel region, of the fourth doping region;

the doping concentration of the fifth doping area is larger than that of the third doping area.

In some possible implementations, when the number of the switching cells is one, in the switching cells, the second source electrode and the second drain electrode are disposed on a side of the second active layer away from the substrate; the second source electrode is electrically connected with the first doped region through the fifth doped region, and the second source electrode and the fifth doped region are multiplexed to be a first source electrode; the second drain electrode is electrically connected with the second doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as a first drain electrode;

when the number of the switching cells is at least two, in each switching cell, the second source electrode and the second drain electrode are disposed on a side of the second active layer away from the substrate; the second source electrode is electrically connected with the first doped region through the fifth doped region, and the second source electrode and the fifth doped region are multiplexed to be a first source electrode; the second drain electrode is electrically connected with the second doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as a first drain electrode; the second drain electrode of the ith switch unit and the second source electrode of the (i + 1) th switch unit are the same electrode, and i is more than or equal to 1 and is less than N;

or when the number of the switching units is at least two, the second source electrode of the first switching unit is arranged on one side, away from the substrate, of the second active layer of the first switching unit, and the second drain electrode of the last switching unit is arranged on one side, away from the substrate, of the second active layer of the last switching unit; in the first switch unit, the second source electrode is electrically connected with the first doped region through the fifth doped region, and the second source electrode and the fifth doped region are multiplexed to be the first source electrode; the sixth doped region is reused as a second drain electrode, and the second doped region is reused as a first drain electrode; in the jth switch unit, the fifth doped region is reused as a second source electrode, the first doped region is reused as a first source electrode, the sixth doped region is reused as a second drain electrode, the second doped region is reused as a first drain electrode, and j is more than 1 and less than N; the sixth doped region of the j-1 th switch unit and the fifth doped region of the j-th switch unit are the same doped region, and the second doped region of the j-1 th switch unit and the first doped region of the j-th switch unit are the same doped region; in the last switch unit, the fifth doped region is reused as a second source electrode, the first doped region is reused as a first source electrode, the second drain electrode is electrically connected with the second doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as a first drain electrode.

In some possible implementations, an orthographic projection of the first channel region on the substrate coincides with an orthographic projection of the second channel region on the substrate;

an orthographic projection of the first channel region on the substrate at least partially overlaps an orthographic projection of the first gate electrode on the substrate.

In some possible implementations, the display substrate further includes: a light-shielding layer;

the light shielding layer is located on one side, close to the substrate, of the first active layer, and an orthographic projection of the light shielding layer on the substrate covers an orthographic projection of the first channel region on the substrate.

In some possible implementations, the display substrate includes: the first metal layer, the first insulating layer, the first polysilicon layer, the second insulating layer, the second metal layer, the third insulating layer, the second polysilicon layer, the fourth insulating layer and the third metal layer are sequentially arranged along the direction vertical to the substrate;

the first metal layer includes: a light-shielding layer, the first polysilicon layer including: a first active layer, the second metal layer comprising: a first gate electrode and a scan signal line, the second polysilicon layer including: a second active layer, the third metal layer comprising: a second source electrode, a second drain electrode, and a data signal line.

In some possible implementations, the display substrate further includes: the flat layer, the first transparent conducting layer, the fifth insulating layer and the second transparent conducting layer;

the flat layer is positioned on one side of the third metal layer far away from the substrate, and a first through hole exposing the second drain electrode is formed in the flat layer;

the first transparent conducting layer is positioned on one side, away from the substrate, of the flat layer, and a second through hole exposing the first through hole is formed in the first transparent conducting layer; the orthographic projection of the second via hole on the substrate covers the orthographic projection of the first via hole on the substrate; the first transparent conductive layer includes: a common electrode;

the fifth insulating layer is positioned on one side, away from the substrate, of the first transparent conducting layer, and a third through hole exposing the second through hole is formed in the fifth insulating layer;

the second transparent conductive layer is located on one side, away from the substrate, of the fifth insulating layer, and the second transparent conductive layer includes: and the pixel electrode is connected with the second drain electrode through the first via hole, the second via hole and the third via hole.

In a second aspect, the present disclosure also provides a display device, including: the display substrate is provided.

In a third aspect, the present disclosure also provides a method for manufacturing a display substrate, configured to form the display substrate, the method including:

providing a substrate;

forming a switch structure on the substrate; the switch structure is respectively electrically connected with the control signal end, the signal input end and the signal output end and is arranged to provide the signal of the signal input end for the signal output end under the control of the control signal end; the switch structure includes: a switch unit; the switching unit includes: a first transistor and a second transistor; the first transistor and the second transistor are opposite in type; the first transistor includes: a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, the second transistor including: a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; the first gate electrode and the second gate electrode are respectively electrically connected with the control signal end, the first source electrode and the second source electrode are respectively electrically connected with the signal input end, and the first drain electrode and the second drain electrode are respectively electrically connected with the signal output end; the orthographic projection of the first active layer on the substrate is coincident with the orthographic projection of the second active layer on the substrate.

In some possible implementations, the forming a switching structure on the substrate includes:

sequentially forming a first metal layer and a first insulating layer on a substrate; the first metal layer includes: a light-shielding layer;

forming a first polysilicon layer on the first insulating layer; the first polysilicon layer includes: a first active layer;

sequentially forming a second insulating layer and a second metal layer on the first insulating layer on which the first polysilicon layer is formed; the second metal layer includes: a first gate electrode and a scanning signal line; the first gate electrode and the second gate electrode are the same electrode;

forming a third insulating layer on the second insulating layer on which the second metal layer is formed;

forming a second polysilicon layer on the third insulating layer, the second polysilicon layer comprising: a second active layer;

sequentially forming a fourth insulating layer and a third metal layer on the third insulating layer on which the second polysilicon layer is formed, the third metal layer including: a second source electrode, a second drain electrode, and a data signal line.

In some possible implementations, after sequentially forming a fourth insulating layer and a third metal layer on the third insulating layer on which the second polysilicon layer is formed, the method further includes:

forming a flat layer on the fourth insulating layer on which the third metal layer is formed;

forming a first transparent conductive layer on the planarization layer, the first transparent conductive layer comprising: a common electrode;

forming a fifth insulating layer on the first transparent conductive layer;

forming a second transparent conductive layer on the fifth insulating layer, the second transparent conductive layer including: and a pixel electrode.

In some possible implementations, when the first transistor is an N-type transistor, the second transistor is a P-type transistor,

the forming a first polysilicon layer on the first insulating layer includes:

depositing a first amorphous silicon film on the first insulating layer, crystallizing the first amorphous silicon film, and processing the crystallized first amorphous silicon film through a composition process to form a first polycrystalline silicon film; the first polysilicon film includes: the first region, the second region, the third region, the fourth region and the fifth region are arranged along a direction perpendicular to the arrangement direction of the first active layer and the second active layer, the second region and the third region are respectively positioned at two sides of the first region, the fourth region is positioned at one side of the second region far away from the first region, and the fifth region is positioned at one side of the third region far away from the first region;

carrying out threshold voltage doping treatment on the first polycrystalline silicon thin film;

carrying out N-type heavy doping treatment on the fourth region and the fifth region of the first polycrystalline silicon film;

carrying out N-type light doping treatment on the second region and the third region of the first polycrystalline silicon thin film to form a first polycrystalline silicon layer;

the forming a second polysilicon layer on the third insulating layer includes:

depositing a second amorphous silicon film on the third insulating layer, crystallizing the second amorphous silicon film, and processing the crystallized second amorphous silicon film through a composition process to form a second polycrystalline silicon film; the second polysilicon film includes: the first region, the second region and the third region are arranged along a direction vertical to the arrangement direction of the first active layer and the second active layer, and the second region and the third region are respectively positioned at two sides of the first region;

carrying out P-type doping treatment on the second region and the third region of the second polycrystalline silicon thin film to form a second polycrystalline silicon layer;

when the first transistor is a P-type transistor and the second transistor is an N-type transistor,

the forming a first polysilicon layer on the first insulating layer includes:

depositing a first amorphous silicon film on the first insulating layer, crystallizing the first amorphous silicon film, and processing the crystallized first amorphous silicon film through a composition process to form a first polycrystalline silicon film; the first polysilicon film includes: the first region, the second region and the third region are arranged along a direction vertical to the arrangement direction of the first active layer and the second active layer, and the second region and the third region are respectively positioned at two sides of the first region;

carrying out P-type doping treatment on the second region and the third region of the first polycrystalline silicon thin film to form a first polycrystalline silicon layer;

the forming a second polysilicon layer on the third insulating layer includes:

depositing a second amorphous silicon film on the third insulating layer, crystallizing the second amorphous silicon film, and processing the crystallized second amorphous silicon film through a composition process to form a second polycrystalline silicon film; the second polysilicon film includes: the first region, the second region, the third region, the fourth region and the fifth region are arranged along a direction perpendicular to the arrangement direction of the first active layer and the second active layer, the second region and the third region are respectively positioned at two sides of the first region, the fourth region is positioned at one side of the second region far away from the first region, and the fifth region is positioned at one side of the third region far away from the first region;

carrying out threshold voltage doping treatment on the second polycrystalline silicon thin film;

carrying out N-type heavy doping treatment on the fourth region and the fifth region of the second polycrystalline silicon film;

and carrying out N-type light doping treatment on the second region and the third region of the second polycrystalline silicon film to form a second polycrystalline silicon layer.

In a fourth aspect, the present disclosure further provides a driving method of a display substrate, for driving the display substrate, the method including:

the control signal terminal is provided with a control signal to provide the signal of the signal input terminal to the signal output terminal.

In some possible implementations, when the signal at the signal input terminal is a high-level signal, the providing the control signal to the control signal terminal includes:

providing a first control signal to a control signal end, wherein the first control signal is a low-level signal;

when the signal of the signal input end is a low level signal, the providing the control signal to the control signal end comprises:

and providing a second control signal to the control signal end, wherein the second control signal is a high-level signal.

The present disclosure provides a display substrate, a manufacturing method thereof, a driving method thereof, and a display device, wherein the display substrate includes: the switch structure is respectively electrically connected with the control signal end, the signal input end and the signal output end and is arranged to provide a signal of the signal input end for the signal output end under the control of the control signal end; the switch structure includes: a switch unit; the switch unit includes: a first transistor and a second transistor; the first transistor and the second transistor are opposite in type; the first transistor includes: a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor includes: a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; the first gate electrode and the second gate electrode are respectively and electrically connected with a control signal end, the first source electrode and the second source electrode are respectively and electrically connected with a signal input end, and the first drain electrode and the second drain electrode are respectively and electrically connected with a signal output end; the orthographic projection of the first active layer on the substrate is coincident with the orthographic projection of the second active layer on the substrate. This is disclosed through setting up including the type is opposite, and the parallelly connected switch structure of first transistor and the second transistor that sets up, improves the high frequency region of the charging rate in order to support the display product of display product effectively, has promoted the display effect.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. Other advantages of the disclosure may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1 is a schematic diagram of a switch structure provided by an embodiment of the present disclosure;

fig. 2 is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a switch architecture provided in an exemplary embodiment;

FIG. 4A is a cross-sectional view of a display substrate provided in accordance with an exemplary embodiment;

FIG. 4B is a cross-sectional view of a display substrate provided in accordance with another exemplary embodiment;

FIG. 5 is a top view of a display substrate provided in an exemplary embodiment;

fig. 6 is a cross-sectional view of forming a first insulating layer;

FIG. 7 is a top view of a first insulating layer;

fig. 8 is a cross-sectional view of a first polysilicon layer being formed;

FIG. 9 is a top view of a first polysilicon layer being formed;

FIG. 10 is a cross-sectional view of forming a second metal layer;

FIG. 11 is a top view of the formation of a second metal layer;

fig. 12 is a cross-sectional view of a second polysilicon layer being formed;

FIG. 13 is a top view of the formation of a second polysilicon layer;

fig. 14 is a cross-sectional view of forming a fourth insulating layer;

fig. 15 is a top view of forming a fourth insulating layer;

FIG. 16 is a cross-sectional view of the formation of a third metal layer;

FIG. 17 is a top view of the formation of a third metal layer;

FIG. 18 is a cross-sectional view of the formation of a planar layer;

fig. 19 is a cross-sectional view of forming a first transparent conductive layer.

Detailed Description

The present disclosure describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of the embodiments described in this disclosure. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure that have been disclosed may also be combined with any conventional features or elements to form a technical solution as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other aspects to form yet another aspect defined by the claims. Thus, it should be understood that any features shown and/or discussed in this disclosure may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Unless otherwise defined, technical or scientific terms used in the disclosure of the present disclosure should have the ordinary meaning as understood by those of ordinary skill in the art to which the disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "perpendicular" refers to a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which an angle is 85 ° or more and 95 ° or less.

Fig. 1 is a schematic diagram of a switch structure provided in an embodiment of the present disclosure, and fig. 2 is a cross-sectional view of a display substrate provided in an embodiment of the present disclosure. As shown in fig. 1 and 2, an embodiment of the present disclosure provides a display substrate including: a substrate 10 and a switching structure disposed on the substrate 10. And the switch structure is respectively electrically connected with the control signal terminal G, the signal input terminal IN and the signal output terminal OUT and is used for providing the signal of the signal input terminal IN for the signal output terminal OUT under the control of the control signal terminal G. The switch structure includes: switch unit 1, switch unit 1 includes: a first transistor T1 and a second transistor T2; the first transistor T1 and the second transistor T2 are of opposite type. Fig. 2 illustrates an example in which the switch structure includes one switch unit.

The first transistor T1 includes: the first active layer 11, the first gate electrode 12, the first source electrode 13, and the first drain electrode 14, and the second transistor T2 includes: a second active layer 21, a second gate electrode 22, a second source electrode 23, and a second drain electrode 24.

As shown IN fig. 1, the first gate electrode and the second gate electrode are electrically connected to the control signal terminal G, the first source electrode and the second source electrode are electrically connected to the signal input terminal IN, and the first drain electrode and the second drain electrode are electrically connected to the signal output terminal OUT.

As shown in fig. 2, an orthographic projection of the first active layer 11 on the substrate 10 coincides with an orthographic projection of the second active layer 21 on the substrate 10.

In one exemplary embodiment, the base 10 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass, metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

In one exemplary embodiment, the first and second transistors T1 and T2 may be P-type, or may be N-type. When the first transistor T1 is N-type, the second transistor T2 is P-type. When the first transistor T1 is P-type, the second transistor T2 is N-type.

In one exemplary embodiment, the first and second active layers 11 and 21 are made of a polysilicon material.

In the present embodiment, the types are opposite, and the first transistor T1 and the second transistor T2 arranged in parallel constitute a transmission gate.

In one exemplary embodiment, the switching structure is turned off when the voltage of the signal of the first gate electrode is 0V and the voltage of the signal of the second gate electrode is 0V. The switching structure is turned on when at least one of voltages of a signal of the first gate electrode and a signal of the second gate electrode is not 0.

In an exemplary embodiment, for example, when the first transistor T1 is N-type and the second transistor T2 is P-type, the switch structure may be turned on by providing a high level signal or a low level signal to the control signal terminal when the signal at the signal input terminal is a high level signal, so as to provide the signal at the signal input terminal to the signal output terminal. When the control signal terminal provides a high level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, and the absolute value of the gate-source voltage difference of the first transistor is a first difference. When the control signal terminal provides the low level signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and at this time, the absolute value of the gate-source voltage difference of the second transistor T2 is a second difference value, and the second difference value is greater than the first difference value because the voltage value of the low level signal is smaller than that of the high level signal. The voltage value of the signal provided by the signal input end is 8V, when the control signal end provides a high level signal, the voltage value of the signal of the control signal end is 6V, at the moment, the first difference value is 2V, when the control signal end provides a low level signal, the voltage value of the signal of the control signal end is-6V, at the moment, the second difference value is 14V. Because the second difference is greater than first difference, consequently, the resistance of switch structure when control signal end provides low level signal will be less than when control signal end provides high level signal switch structure's resistance, and at this moment, this disclosure can provide low level signal to control signal end and switch on switch structure, and then promotes switch structure's charging capacity. Similarly, when the signal provided by the signal input end is a low level signal, the second difference is smaller than the first difference. The voltage value of the signal provided by the signal input end is-8V, when the control signal end provides a high level signal, the voltage value of the signal of the control signal end is 6V, at the moment, the first difference value is 14V, when the control signal end provides a low level signal, the voltage value of the signal of the control signal end is-6V, at the moment, the second difference value is 2V. Because the second difference is less than first difference, consequently, the resistance of switch structure when control signal end provides high level signal will be less than when control signal end provides low level signal switch structure's resistance, and at this moment, this disclosure can provide high level signal to control signal end and switch on switch structure, and then promotes switch structure's charging capacity.

This embodiment can come the signal of control signal end according to signal input terminal's signal, when signal input terminal's signal is high level signal, can be through providing low level signal in order to switch on the switch structure to control signal end, when signal input terminal's signal is low level signal, can be through providing high level signal in order to switch on the switch structure to control signal end, the charging ability of switch structure has been improved, switch structure's flexibility has been increased, the problem that the charging ability that adopts single transistor to lead to is not enough has been avoided.

The display substrate includes: a plurality of sub-pixels disposed on the substrate. In an exemplary embodiment, the switching structure may be applied in a gate driving circuit, a sub-pixel, or a multiplexer.

When the switching structure is applied to the sub-pixel, the orthographic projection of the first active layer 11 on the substrate 10 is overlapped with the orthographic projection of the second active layer 21 on the substrate 10, which may affect the aperture ratio of the sub-pixel.

The display substrate provided by the embodiment of the disclosure includes: the switch structure is respectively electrically connected with the control signal end, the signal input end and the signal output end and is arranged to provide a signal of the signal input end for the signal output end under the control of the control signal end; the switch structure includes: a switch unit; the switch unit includes: a first transistor and a second transistor; the first transistor and the second transistor are opposite in type; the first transistor includes: a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor includes: a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; the first gate electrode and the second gate electrode are respectively and electrically connected with a control signal end, the first source electrode and the second source electrode are respectively and electrically connected with a signal input end, and the first drain electrode and the second drain electrode are respectively and electrically connected with a signal output end; the orthographic projection of the first active layer on the substrate is coincident with the orthographic projection of the second active layer on the substrate. This is disclosed through setting up the switch structure including first transistor and the second transistor of type opposite, can promote switch structure's the ability of charging, improves the high frequency drive that the charging rate of display product is in order to support the display product effectively, has promoted display effect.

Fig. 3 is a schematic diagram of a switch structure provided in an exemplary embodiment, fig. 4A is a cross-sectional view of a display substrate provided in an exemplary embodiment, and fig. 4B is a cross-sectional view of a display substrate provided in another exemplary embodiment. As shown in fig. 3 and 4, in one exemplary embodiment, the number of switching units is N. Fig. 3 and 4 illustrate an example in which the switch structure includes two switch units.

The first source electrode of the first switch unit is electrically connected with the signal input end IN, the first drain electrode of the jth switch unit is electrically connected with the first source electrode of the (j + 1) th switch unit, and the first drain electrode of the Nth switch unit is electrically connected with the signal output end OUT. The first gate electrode and the second gate electrode of all the switch units are respectively and electrically connected with a control signal end G, N is more than or equal to 1, and 1< j < N.

As shown in fig. 2 and 4, in an exemplary embodiment, the display substrate further includes: a scanning signal line (not shown in the figure), a data signal line (not shown in the figure), a common electrode 41, and a pixel electrode 42 provided on the substrate.

When the switch structure is applied to the sub-pixels, the scanning signal line is electrically connected with the control signal end and is set to provide signals for the control signal end; the data signal line is connected with the signal input end and is used for providing signals for the signal input end; the signal output end is connected with the pixel electrode and is used for providing signals for the pixel electrode; the common electrode 41 is located on a side of the pixel electrode 42 close to the substrate 10, and is configured to form an electric field with the pixel electrode.

In an exemplary embodiment, the common electrode 41 and the pixel electrode 42 are transparent electrodes, and the transparent electrodes may be made of zinc tin oxide or zinc tin oxide.

In one exemplary embodiment, as shown in fig. 2 and 4, the first gate electrode 12 and the second gate electrode 22 are the same electrode.

In one exemplary embodiment, as shown in fig. 2 and 4, the first active layer 11 is located at a side of the first gate electrode 12 close to the substrate 10; the second active layer 21 is positioned on one side of the first gate electrode 12 away from the substrate 10; the second active layer 21 is connected to the first active layer 11.

In one exemplary embodiment, when the first transistor is an N-type transistor and the second transistor is a P-type transistor; the first active layer 11 includes: a first channel region 111, a first doping region 112, a second doping region 113, a third doping region 114 and a fourth doping region 115 which are arranged along a direction perpendicular to the arrangement direction of the first active layer and the second active layer. The second active layer 21 includes: a second channel region 211, a fifth doped region 212 and a sixth doped region 213 arranged along a direction perpendicular to the arrangement direction of the first active layer and the second active layer.

The first, second, third, fourth, fifth and sixth doped regions 112, 113, 114, 115, 212 and 213 may be electrically conductive.

The first doping region 112 and the second doping region 113 have the same doping type and are respectively located at two sides of the first channel region 111; the doping types of the third doping region 114 and the fourth doping region 115 are the same, the third doping region 114 is located on the side of the first doping region 112 away from the first channel region 111, and the fourth doping region 115 is located on the side of the second doping region 113 away from the first channel region 111.

The fifth doping region 212 and the sixth doping region 213 have the same doping type and are respectively located at two sides of the second channel region 211.

In one exemplary embodiment, as shown in fig. 2, when the number of switching cells is one, in the switching cells, the second source electrode 23 and the second drain electrode 24 are disposed at a side of the second active layer 21 away from the substrate 10. The second source electrode 23 is electrically connected to the third doped region 114 through the fifth doped region 212, and the second source electrode 23 and the fifth doped region 212 are multiplexed as the first source electrode 13. The second drain electrode 24 is electrically connected to the fourth doped region 115 through the sixth doped region 213, and the second drain electrode 24 and the sixth doped region 213 are reused as the first drain electrode 14.

In one exemplary embodiment, when the number of the switching cells is at least two, the second source electrode 23 and the second drain electrode 24 are disposed at a side of the second active layer 21 away from the substrate 10 in each switching cell. The second source electrode 23 is electrically connected to the third doped region 114 through the fifth doped region 212, and the second source electrode 23 and the fifth doped region 212 are multiplexed as the first source electrode 13. The second drain electrode 24 is electrically connected to the fourth doped region 115 through the sixth doped region 213, and the second drain electrode 24 and the sixth doped region 213 are reused as the first drain electrode 14. The second drain electrode of the ith switch unit and the second source electrode of the (i + 1) th switch unit are the same electrode, and i is more than or equal to 1 and is less than N. Fig. 4A illustrates two switching units as an example, and as shown in fig. 4A, the second drain electrode of the first switching unit and the second source electrode of the second switching unit are the same electrode.

In an exemplary embodiment, when the number of the switching cells is at least two, the second source electrode of the first switching cell is disposed on a side of the second active layer of the first switching cell away from the substrate, and the second drain electrode of the last switching cell is disposed on a side of the second active layer of the last switching cell away from the substrate; in the first switch unit, the second source electrode is electrically connected with the third doped region through the fifth doped region, and the second source electrode and the fifth doped region are reused as the first source electrode; the sixth doped region is reused as a second drain electrode, and the fourth doped region is reused as a first drain electrode; in the jth switch unit, the fifth doped region is reused as the second source electrode, the third doped region is reused as the first source electrode, the sixth doped region is reused as the second drain electrode, the fourth doped region is reused as the first drain electrode, and j is more than 1 and less than N; the sixth doped region of the j-1 th switch unit and the fifth doped region of the j-1 th switch unit are the same doped region, and the fourth doped region of the j-1 th switch unit and the third doped region of the j-1 th switch unit are the same doped region; in the last switch unit, the fifth doped region is reused as the second source electrode, the third doped region is reused as the first source electrode, the second drain electrode is electrically connected with the fourth doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as the first drain electrode. Fig. 4B illustrates two switch units as an example, and as shown in fig. 4B, the sixth doped region of the first switch unit and the fifth doped region of the second switch unit are the same doped region, and the fourth doped region of the first switch unit and the third doped region of the second switch unit are the same doped region. At this time, when the switching transistor is turned on, the sixth doping region of the first switching unit, the fifth doping region of the second switching unit and the fourth doping region of the first switching unit are equivalent to resistors connected in parallel, so that the resistance of the switching structure can be reduced, and the charging rate of the switching structure is improved.

As shown in fig. 2 and 4, the first transistor is of a top-gate structure and the second transistor is of a bottom-gate structure.

In one exemplary embodiment, the doping concentrations of the first and second doping regions 112 and 113 may be equal.

In an exemplary embodiment, the doping concentrations of the third doped region 114 and the fourth doped region 115 may be equal.

In an exemplary embodiment, the doping concentrations of the fifth and sixth doping regions 212 and 213 may be equal

In one exemplary embodiment, the doping concentration of the third doping region 114 is greater than the doping concentration of the first doping region 112. The first doped region 112 and the second doped region 113 are lightly doped with N-type, and the third doped region 114 and the fourth doped region 115 are heavily doped with N-type. The first active layer is provided with the first doped region 112 and the second doped region 113 with high resistance values, so that the acceleration distance of electrons under the action of an electric field can be reduced, the heat generation of the first transistor can be effectively reduced, and the leakage current can be inhibited.

In an exemplary embodiment, the fifth and sixth doped regions 212 and 213 may be lightly doped P-type or heavily doped P-type.

In one exemplary embodiment, the control of the lengths of the first to sixth doped regions may be achieved by adjustment of the ion species of doping and the doping concentration.

In an exemplary embodiment, as shown in fig. 2 and 4, taking the first transistor as an N-type transistor and the second transistor as a P-type transistor as an example, when a high level signal is supplied to the first gate electrode, the first channel region 111 is in a conducting state and the second channel region 211 is in a high impedance state. The first channel region 111 is in a conducting state, a path is formed between the second source electrode 23, the fifth doping region 212, the third doping region 114, the first doping region 112, the first channel region 111, the second doping region 113, the fourth doping region 115, the sixth doping region 213 and the second drain electrode 24, since the second source electrode 23 and the fifth doping region 212 are multiplexed as the first source electrode 13, and the second drain electrode 24 and the sixth doping region 213 are multiplexed as the first drain electrode 14, the path is the first source electrode 13, the third doping region 114, the first doping region 112, the first channel region 111, the second doping region 113, the fourth doping region 115 and the first drain electrode 14, and a voltage signal of the first source electrode is transmitted to the first drain electrode through the path, at this time, the first transistor is in a conducting state. Since the second channel region 211 is in a high resistance state, a path cannot be formed between the second source electrode 23, the fifth doped region 212, the second channel region 211, the sixth doped region 213, and the second drain electrode 24, and at this time, the second transistor is in an off state. When a low-level signal is supplied to the first gate electrode, the first channel region 111 is in a high-resistance state, and the second channel region 211 is in an on state. The first channel region 111 is in a high resistance state, no path can be formed between the second source electrode 23, the fifth doping region 212, the third doping region 114, the first doping region 112, the first channel region 111, the second doping region 113, the fourth doping region 115, the sixth doping region 213 and the second drain electrode 24, that is, no path can be formed between the first source electrode 13, the third doping region 114, the first doping region 112, the first channel region 111, the second doping region 113, the fourth doping region 115 and the first drain electrode 14, and at this time, the first transistor is in an off state. The second channel region 211 is in a conducting state, a path is formed between the second source electrode 23, the fifth doped region 212, the second channel region 211, the sixth doped region 213 and the second drain electrode 24, a voltage signal of the second source electrode 23 is transmitted to the second drain electrode 24 through the path, and at this time, the second transistor is in a conducting state.

As can be seen from the above analysis, the first gate electrode 12 and the second gate electrode 22 are the same electrode, that is, the first transistor and the second transistor share the gate, which not only ensures the normal operation of the switch structure, but also simplifies the process and saves the cost.

Fig. 2 and 4 illustrate an example in which the first transistor is an N-type transistor and the second transistor is a P-type transistor.

In one exemplary embodiment, when the first transistor is a P-type transistor and the second transistor is an N-type transistor; the first active layer includes: the first channel region, the first doping region and the second doping region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer. The second active layer includes: and the second channel region, the third doped region, the fourth doped region, the fifth doped region and the sixth doped region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer.

The first doping region and the second doping region have the same doping type and are respectively positioned at two sides of the first channel region; the third doping region and the fourth doping region have the same doping type and are respectively positioned at two sides of the second channel region; the fifth doping region and the sixth doping region are the same in doping type, the fifth doping region is located on one side, away from the second channel region, of the third doping region, and the sixth doping region is located on one side, away from the second channel region, of the fourth doping region.

The second source electrode is connected with the first doped region through a fifth doped region, and the second source electrode and the fifth doped region are reused as the first source electrode; the second drain electrode is connected with the second doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as the first drain electrode.

In one exemplary embodiment, the doping concentrations of the first and second doping regions may be equal.

In one exemplary embodiment, the doping concentrations of the third and fourth doping regions may be equal.

In an exemplary embodiment, the doping concentrations of the fifth and sixth doping regions may be equal

In one exemplary embodiment, the doping concentration of the fifth doping region is greater than the doping concentration of the third doping region.

In one exemplary embodiment, when the number of the switching cells is one, in the switching cells, the second source electrode and the second drain electrode are disposed on a side of the second active layer away from the substrate; the second source electrode is electrically connected with the first doped region through the fifth doped region, and the second source electrode and the fifth doped region are reused as the first source electrode; the second drain electrode is electrically connected with the second doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as the first drain electrode.

In one exemplary embodiment, when the number of the switching cells is at least two, in each switching cell, the second source electrode and the second drain electrode are disposed on a side of the second active layer away from the substrate; the second source electrode is electrically connected with the first doped region through the fifth doped region, and the second source electrode and the fifth doped region are reused as the first source electrode; the second drain electrode is electrically connected with the second doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as the first drain electrode; the second drain electrode of the ith switch unit and the second source electrode of the (i + 1) th switch unit are the same electrode, and i is more than or equal to 1 and is less than N.

In an exemplary embodiment, when the number of the switching cells is at least two, the second source electrode of the first switching cell is disposed on a side of the second active layer of the first switching cell away from the substrate, and the second drain electrode of the last switching cell is disposed on a side of the second active layer of the last switching cell away from the substrate; in the first switch unit, the second source electrode is electrically connected with the first doped region through the fifth doped region, and the second source electrode and the fifth doped region are multiplexed into the first source electrode; the sixth doped region is reused as a second drain electrode, and the second doped region is reused as a first drain electrode; in the jth switch unit, the fifth doped region is reused as a second source electrode, the first doped region is reused as a first source electrode, the sixth doped region is reused as a second drain electrode, the second doped region is reused as a first drain electrode, and j is more than 1 and less than N; the sixth doped region of the j-1 th switch unit and the fifth doped region of the j-th switch unit are the same doped region, and the second doped region of the j-1 th switch unit and the first doped region of the j-th switch unit are the same doped region; in the last switch unit, the fifth doped region is reused as the second source electrode, the first doped region is reused as the first source electrode, the second drain electrode is electrically connected with the second doped region through the sixth doped region, and the second drain electrode and the sixth doped region are reused as the first drain electrode. At this time, when the switching transistor is turned on, the sixth doped region of the first switching unit, the fifth doped region of the second switching unit, and the second doped region of the first switching unit are equivalent to resistors connected in parallel, so that the resistance of the switching structure can be reduced, and the charging rate of the switching structure is improved.

As shown in fig. 2 and 4, in an exemplary embodiment, an orthographic projection of the first channel region 111 on the substrate 10 coincides with an orthographic projection of the second channel region 211 on the substrate 10; an orthogonal projection of the first channel region 111 on the substrate 10 at least partially overlaps an orthogonal projection of the first gate electrode 12 on the substrate 10.

Fig. 5 is a top view of a display substrate according to an exemplary embodiment. As shown in fig. 2, 4 and 5, an exemplary embodiment provides a display substrate further including: and a light-shielding layer 20.

The light shielding layer 20 is located on one side of the first active layer 11 close to the substrate 10, and an orthographic projection of the light shielding layer 20 on the substrate 10 covers an orthographic projection of the first channel region 111 on the substrate 10.

As shown in fig. 2, 4 and 5, an exemplary embodiment provides a display substrate including: a first metal layer, a first insulating layer 31, a first polysilicon layer, a second insulating layer 32, a second metal layer, a third insulating layer 33, a second polysilicon layer, a fourth insulating layer 34 and a third metal layer which are sequentially arranged along a direction perpendicular to the substrate.

The first metal layer includes: a light-shielding layer 20, the first polysilicon layer including: the first active layer 11, the second metal layer includes: a first gate electrode 11 and a scan signal line, and a second polysilicon layer including: the second active layer 21, the third metal layer includes: a second source electrode 23, a second drain electrode 24, and a data signal line.

As shown in fig. 2 and 4, an exemplary embodiment provides a display substrate further including: a planarization layer 35, a first transparent conductive layer, a fifth insulating layer 36 and a second transparent conductive layer.

The first transparent conductive layer includes: the common electrode 41, the second transparent conductive layer includes: and a pixel electrode 42.

The planarization layer 35 is located on a side of the third metal layer away from the substrate 10, the first transparent conductive layer is located on a side of the planarization layer 35 away from the substrate 10, the fifth insulating layer 36 is located on a side of the first transparent conductive layer away from the substrate 10, and the second transparent conductive layer is located on a side of the fifth insulating layer 36 away from the substrate 10.

The planarization layer 35 is provided with a first via hole exposing the second drain electrode, and the first transparent conductive layer is provided with a second via hole exposing the first via hole. The orthographic projection of the second via hole on the substrate covers the orthographic projection of the first via hole on the substrate. A third via hole exposing the second via hole is disposed on the fifth insulating layer 36. The pixel electrode 42 is connected to the second drain electrode 24 through the first, second, and third via holes.

In an exemplary embodiment, the first metal layer, the second metal layer, and the third metal layer may employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, and the like.

The first, second, third, fourth, and fifth insulating layers may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer is called a buffer layer and is configured to improve the water and oxygen resistance of the substrate, the second insulating layer is called a first gate insulating layer, the third insulating layer is called a second gate insulating layer, the fourth insulating layer is called an interlayer insulating layer, and the fifth insulating layer is called a passivation layer.

In an exemplary embodiment, the thickness of the second insulating layer may be smaller than that of the third insulating layer, and the thickness of the first insulating layer may be smaller than the sum of the thicknesses of the second insulating layer and the third insulating layer, so that the capacity of the storage capacitor may be increased while the insulating effect is ensured.

In one exemplary embodiment, the planarization layer may employ an organic material.

When the display substrate provided by the exemplary embodiment is driven at high frequency, the charging rate of the display substrate can reach 99.75%, the display effect of the display substrate is improved, and the display substrate is ensured to have no risk of poor display. The display failure refers to a failure phenomenon such as a vertical streak.

Taking the example that the switch structure includes one switch unit, and the first transistor is an N-type transistor and the second transistor is a P-type transistor, the structure of the display substrate provided by an exemplary embodiment is described below through a manufacturing process of the display substrate. The "patterning process" includes processes of depositing a film layer, coating a photoresist, mask exposure, developing, etching, and stripping a photoresist. The deposition may employ any one or more of sputtering, evaporation and chemical vapor deposition, the coating may employ any one or more of spray coating and spin coating, and the etching may employ any one or more of dry etching and wet etching. "thin film" refers to a layer of a material deposited or coated onto a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process.

(1) Forming a first metal layer and a first insulating layer on a substrate, including: a first metal thin film is deposited on a substrate, the first metal thin film is patterned through a patterning process to form a first metal layer, a first insulating thin film is deposited on the first insulating layer on which the first metal layer is formed, and the first insulating thin film is patterned through the patterning process to form a first insulating layer 31. The first metal layer includes: light-shielding layers, as shown in fig. 6 and 7.

(2) Forming a first polysilicon layer comprising: depositing a first amorphous silicon film on the first insulating layer, crystallizing the first amorphous silicon film, patterning the crystallized first amorphous silicon film by a patterning process to form a first polysilicon film, performing threshold voltage doping treatment on the first polysilicon film, performing N-type heavy doping on the first polysilicon film to form a third doped region 114 and a fourth doped region 115, and performing P-type light doping on the first polysilicon film to form a first doped region 112 and a second doped region 113, so as to form a first polysilicon layer. The first polysilicon layer includes: a first active layer 11, as shown in fig. 8 and 9.

(3) Forming the second insulating layer and the second metal layer includes: depositing a second insulating film on the first insulating layer on which the first polysilicon layer is formed, patterning the second insulating film through a patterning process to form a second insulating layer 32, depositing a second metal film on the second insulating layer 32, and patterning the second metal film through the patterning process to form a second metal layer. The second metal layer includes: the signal lines and the first gate electrode 11 are scanned as shown in fig. 10 and 11.

(4) Forming a third insulating layer and a second polysilicon layer, including: depositing a third insulating film on the second insulating layer on which the second metal layer is formed, patterning the third metal film through a patterning process to form a third insulating layer 33, depositing a second amorphous silicon film on the third insulating layer 33, crystallizing the second amorphous silicon film, patterning the crystallized second amorphous silicon film through the patterning process to form a second polysilicon film, P-doping the first polysilicon film to form a fifth doping region 212 and a sixth doping region 213, so as to form the second polysilicon layer. The second polysilicon layer includes: a second active layer 21, as shown in fig. 12 and 13.

The second insulating layer 32 and the third insulating layer 33 are provided thereon with a fourth via hole V4 exposing the third doped region 114 and a fifth via hole V5 exposing the fourth doped region 115. The fifth doped region 212 is electrically connected to the third doped region 114 through the fourth via V4, and the sixth doped region 213 is electrically connected to the third doped region 114 through the fifth via V5.

(5) Forming a fourth insulating layer including: a fourth insulating film is deposited on the third insulating layer on which the second polysilicon layer is formed, and the fourth insulating film is patterned through a patterning process to form a fourth insulating layer 34, as shown in fig. 14 and 15.

The fourth insulating layer 34 is provided with a sixth via V6 exposing the fifth doped region 212 and a seventh via V7 exposing the sixth doped region 213.

(6) Forming a third metal layer comprising: depositing a third metal film on the fourth insulating layer 34, and patterning the third metal film through a patterning process to form a third metal layer, wherein the third metal layer includes: a second source electrode 23, a second drain electrode 24, and a data signal line, as shown in fig. 16 and 17.

The fourth insulating layer 34 is provided with a sixth via hole exposing the fifth doped region 212 and a seventh via hole exposing the sixth doped region 213. The second source electrode 23 is electrically connected to the fifth doped region 212 through a sixth via hole, and the second drain electrode 24 is electrically connected to the sixth doped region 213 through a seventh via hole.

(6) Forming a planar layer comprising: on the fourth insulating layer on which the third metal layer is formed, a flat film is applied, and a flat layer 35 is formed by masking, exposure, and development of the flat film. The planarization layer has a first via V1 formed thereon, and the second drain electrode 24 is exposed by the first via V1, as shown in fig. 18.

(7) Forming a first transparent conductive layer comprising: and depositing a first transparent conductive film on the flat layer, and patterning the first transparent conductive film through a patterning process to form a first transparent conductive layer. The first transparent conductive layer includes a common electrode 41. A second via V2 exposing the first via V1 is disposed on the first transparent conductive layer, and an orthographic projection of the second via V2 on the substrate covers an orthographic projection of the first via V1 on the substrate, as shown in fig. 19.

(8) Forming a fifth insulating layer and a second transparent conductive layer, including: depositing a fifth insulating film on the first transparent conductive layer, patterning the fifth insulating film through a patterning process to form a fifth insulating layer 36, depositing a second transparent conductive film on the fifth insulating layer 36, and patterning the second transparent conductive film through the patterning process to form a second transparent conductive layer. The second transparent conductive layer includes a pixel electrode 42, as shown in fig. 2.

And a third via hole exposing the second via hole is formed in the fifth insulating layer, and the pixel electrode is connected with the second drain electrode through the first via hole, the second via hole and the third via hole.

The embodiment of the present disclosure further provides a method for manufacturing a display substrate, where the method for manufacturing a display substrate includes:

in step S1, a substrate is provided.

Step S2, forming a switch structure on the substrate.

The switch structure is respectively electrically connected with the control signal end, the signal input end and the signal output end and is arranged to provide the signal of the signal input end for the signal output end under the control of the control signal end; the switch structure includes: a switch unit; the switch unit includes: a first transistor and a second transistor; the first transistor and the second transistor are opposite in type; the first transistor includes: a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor includes: a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; the first gate electrode and the second gate electrode are respectively and electrically connected with a control signal end, the first source electrode and the second source electrode are respectively and electrically connected with a signal input end, and the first drain electrode and the second drain electrode are respectively and electrically connected with a signal output end; the orthographic projection of the first active layer on the substrate is coincident with the orthographic projection of the second active layer on the substrate.

The display substrate is the display substrate provided in any of the foregoing embodiments, and the implementation principle and the implementation effect are similar, and are not described herein again.

In an exemplary embodiment, the step S2 of forming the switch structure on the substrate includes:

step S21 is to sequentially form a first metal layer and a first insulating layer on the substrate.

The first metal layer includes: and a light shielding layer.

Step S22, a first polysilicon layer is formed on the first insulating layer.

The first polysilicon layer includes: a first active layer;

step S23 is to sequentially form a second insulating layer and a second metal layer on the first insulating layer on which the first polysilicon layer is formed.

The second metal layer includes: a first gate electrode and a scanning signal line; the first gate electrode and the second gate electrode are the same electrode;

step S24 is to form a third insulating layer on the second insulating layer on which the second metal layer is formed.

Step S25, a second polysilicon layer is formed on the third insulating layer.

The second polysilicon layer includes: a second active layer;

step S26, a fourth insulating layer and a third metal layer are sequentially formed on the third insulating layer on which the second polysilicon layer is formed.

The third metal layer includes: a second source electrode, a second drain electrode, and a data signal line.

After step S26, a method for manufacturing a display substrate according to an exemplary embodiment further includes:

step S27 is to form a planarization layer on the fourth insulating layer on which the third metal layer is formed.

Step S28 is to form a first transparent conductive layer on the planarization layer.

The first transparent conductive layer includes: a common electrode;

step S29 is to form a fifth insulating layer on the first transparent conductive layer, and form a second transparent conductive layer on the fifth insulating layer.

The second transparent conductive layer includes: and a pixel electrode.

In an exemplary embodiment, when the first transistor is an N-type transistor and the second transistor is a P-type transistor, the step S22 includes: depositing a first amorphous silicon film on the first insulating layer, crystallizing the first amorphous silicon film, and processing the crystallized first amorphous silicon film through a composition process to form a first polycrystalline silicon film, wherein the first polycrystalline silicon film comprises: the first region, the second region, the third region, the fourth region and the fifth region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer, the second region and the third region are respectively positioned at two sides of the first region, the fourth region is positioned at one side of the second region far away from the first region, and the fifth region is positioned at one side of the third region far away from the first region; carrying out threshold voltage doping treatment on the first polycrystalline silicon thin film; carrying out N-type heavy doping treatment on the fourth region and the fifth region of the first polycrystalline silicon film; and carrying out N-type light doping treatment on the second region and the third region of the first polycrystalline silicon film to form a first polycrystalline silicon layer.

In one exemplary embodiment, the heavily N-doping the fourth and fifth regions of the first polysilicon thin film includes: coating photoresist on the first polycrystalline silicon thin film, forming a first opening in the photoresist through a composition process, wherein the first opening is positioned above the fourth area and the fifth area, and performing ion implantation on the fourth area and the fifth area of the first polycrystalline silicon thin film through the first opening to form a third doped area and a fourth doped area;

in one exemplary embodiment, the N-type lightly doping process is performed on the second region and the third region of the first polysilicon thin film, and includes: and coating photoresist on the first polycrystalline silicon thin film, forming a second opening in the photoresist through a composition process, wherein the second opening is positioned above the second region and the third region, and performing ion implantation on the second region and the third region of the first polycrystalline silicon thin film through the second opening to form a third doped region and a fourth doped region.

In an exemplary embodiment, when the first transistor is an N-type transistor and the second transistor is a P-type transistor, the step S25 includes: depositing a second amorphous silicon film on the third insulating layer, crystallizing the second amorphous silicon film, and processing the crystallized second amorphous silicon film through a composition process to form a second polycrystalline silicon film; the second polysilicon film includes: the first region, the second region and the third region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer, and the second region and the third region are respectively positioned at two sides of the first region; and carrying out P-type doping treatment on the second region and the third region of the second polycrystalline silicon film to form a second polycrystalline silicon layer.

In one exemplary embodiment, the P-type doping process of the second region and the third region of the second polysilicon thin film includes: and coating photoresist on the second polycrystalline silicon film, forming an opening in the photoresist through a composition process, wherein the opening is positioned above the second region and the third region, and performing ion implantation on the second region and the third region of the second polycrystalline silicon film through the opening to form a fifth doped region and a sixth doped region.

In an exemplary embodiment, when the first transistor is a P-type transistor and the second transistor is an N-type transistor, the step S22 includes: depositing a first amorphous silicon film on the first insulating layer, crystallizing the first amorphous silicon film, and processing the crystallized first amorphous silicon film through a composition process to form a first polycrystalline silicon film; the first polysilicon film includes: the first region, the second region and the third region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer, and the second region and the third region are respectively positioned at two sides of the first region; and carrying out P-type doping treatment on the second region and the third region of the first polycrystalline silicon thin film to form a first polycrystalline silicon layer.

In one exemplary embodiment, the P-type doping process of the second and third regions of the first polysilicon thin film includes: coating photoresist on the first polycrystalline silicon thin film, forming an opening in the photoresist through a composition process, wherein the opening is positioned above the second area and the third area, and performing ion implantation on the second area and the third area of the first polycrystalline silicon thin film through the opening to form a first doped area and a second doped area;

in an exemplary embodiment, when the first transistor is a P-type transistor and the second transistor is an N-type transistor, the step S25 includes: the method comprises the following steps: depositing a second amorphous silicon film on the third insulating layer, crystallizing the second amorphous silicon film, and processing the crystallized second amorphous silicon film through a composition process to form a second polycrystalline silicon film; the second polysilicon film includes: the first region, the second region, the third region, the fourth region and the fifth region are arranged along the direction vertical to the arrangement direction of the first active layer and the second active layer, the second region and the third region are respectively positioned at two sides of the first region, the fourth region is positioned at one side of the second region far away from the first region, and the fifth region is positioned at one side of the third region far away from the first region; carrying out threshold voltage doping treatment on the second polycrystalline silicon film; carrying out N-type heavy doping treatment on a fourth region and a fifth region of the second polycrystalline silicon film; and carrying out N-type light doping treatment on the second region and the third region of the second polycrystalline silicon film to form a second polycrystalline silicon layer.

In one exemplary embodiment, the heavily N-doping the fourth and fifth regions of the second polysilicon thin film includes: and coating photoresist on the second polycrystalline silicon film, forming a first opening in the photoresist through a composition process, wherein the first opening is positioned above the positions of the fourth area and the fifth area, and performing ion implantation on the fourth area and the fifth area of the second polycrystalline silicon film through the first opening to form a fifth doped area and a sixth doped area.

In one exemplary embodiment, the N-type lightly doping the second and third regions of the second polysilicon thin film includes: and coating photoresist on the second polycrystalline silicon thin film, forming a second opening in the photoresist through a composition process, wherein the second opening is positioned above the second region and the third region, and performing ion implantation on the second region and the third region of the second polycrystalline silicon thin film through the second opening to form a third doped region and a fourth doped region.

The embodiment of the present disclosure further provides a driving method of a display substrate, which is used for driving the display substrate, and the driving method of the display substrate provided by the embodiment of the present disclosure includes: the control signal terminal is provided with a control signal to provide the signal of the signal input terminal to the signal output terminal.

The display substrate is provided by any one of the foregoing embodiments, and the implementation principle and the implementation effect are similar.

In an exemplary embodiment, when the signal at the signal input terminal is a high level signal, providing the control signal to the control signal terminal includes: providing a first control signal to a control signal end, wherein the first control signal is a low level signal;

in an exemplary embodiment, when the signal at the signal input terminal is a low level signal, providing the control signal to the control signal terminal includes: and providing a second control signal to the control signal end, wherein the second control signal is a high-level signal.

The embodiment of the present disclosure also provides a display device, including: a display substrate.

In an exemplary embodiment, the display device may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator.

The display substrate is provided by any one of the foregoing embodiments, and the implementation principle and the implementation effect are similar.

The drawings in this disclosure relate only to the structures to which the embodiments of the disclosure relate, and other structures may refer to general designs.

For clarity, the thickness and dimensions of layers or microstructures are exaggerated in the drawings that are used to describe embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the terms of the appended claims.