阅读说明：本技术 Oled显示面板及其制作方法 (OLED display panel and manufacturing method thereof ) 是由 刘杰 于 2020-06-19 设计创作，主要内容包括：本申请公开了一种OLED显示面板及其制作方法,所述OLED显示面板包括第一晶体管以及第二晶体管,其中所述第一晶体管的第一栅极与所述第二晶体管的第二栅极均位于第一金属层,所述第一晶体管的第一源极、第一漏极与位于所述第二晶体管上方的第一遮光层均位于第二金属层,且所述第二晶体管的第二有源层位于所述第二栅极与所述第一遮光层之间；相比于现有技术,本申请有效地防止了OLED显示面板内发出的光和热对第二有源层的稳定性造成影响,提高了第二有源层的稳定性,提高了第二晶体管的稳定性,进而提高了OLED显示面板的显示效果,且不需要增加额外的工艺工序,节省了工艺时间和工艺成本。(The application discloses an OLED display panel and a manufacturing method thereof, wherein the OLED display panel comprises a first transistor and a second transistor, wherein a first grid electrode of the first transistor and a second grid electrode of the second transistor are both positioned on a first metal layer, a first source electrode, a first drain electrode of the first transistor and a first shading layer positioned above the second transistor are all positioned on a second metal layer, and a second active layer of the second transistor is positioned between the second grid electrode and the first shading layer; compared with the prior art, the OLED display panel has the advantages that light and heat emitted in the OLED display panel are effectively prevented from influencing the stability of the second active layer, the stability of the second active layer is improved, the stability of the second transistor is improved, the display effect of the OLED display panel is further improved, extra process procedures do not need to be added, and process time and process cost are saved.)

1. An OLED display panel, comprising a plurality of pixel regions, wherein each of the pixel regions comprises a first transistor and a second transistor;

the OLED display panel further includes:

a substrate layer;

a first metal layer disposed on the substrate layer, the first metal layer including a first gate of the first transistor and a second gate of the second transistor;

the second metal layer is arranged above the first metal layer and comprises a first source electrode and a first drain electrode of the first transistor and a first shading layer positioned above the second transistor;

wherein the second active layer of the second transistor is located between the second gate and the first light-shielding layer.

2. The OLED display panel of claim 1, wherein a projected area of the second gate electrode on the substrate layer is greater than or equal to a projected area of the second active layer on the substrate layer.

3. The OLED display panel of claim 1, wherein a projected area of the first light shielding layer on the substrate layer is greater than or equal to a projected area of the second active layer on the substrate layer.

4. The OLED display panel of claim 1, further comprising an interlayer insulating layer and a third metal layer sequentially disposed on the second metal layer, wherein the interlayer insulating layer covers the second metal layer, and the third metal layer comprises a via electrically connected to the first drain electrode through a via penetrating through the interlayer insulating layer, and a second light shielding layer corresponding to the first light shielding layer and located above the first light shielding layer.

5. The OLED display panel of claim 4, further comprising a planarization layer and a pixel definition layer sequentially disposed on the third metal layer, wherein the planarization layer covers the third metal layer, the pixel definition layer comprises a plurality of pixel openings corresponding to the pixel regions one by one, each of the pixel openings has an anode and an organic light emitting layer sequentially disposed therein, and the anode is electrically connected to the conductive member through a via penetrating through the planarization layer.

6. The OLED display panel of claim 1, wherein the first transistor further comprises a first active layer disposed between the substrate layer and the first gate electrode, and wherein a material of the first active layer comprises low temperature polysilicon and a material of the second active layer comprises an oxide semiconductor.

7. The manufacturing method of the OLED display panel is characterized in that the OLED display panel comprises a plurality of pixel areas, and each pixel area comprises a first transistor and a second transistor;

the method comprises the following steps:

s10, preparing a first metal layer on the substrate layer, wherein the first metal layer comprises a first grid electrode of the first transistor and a second grid electrode of the second transistor;

s20, sequentially preparing a first insulating layer and a second active layer on the first metal layer, wherein the second active layer is located above the second gate; and

s30, sequentially preparing a second insulating layer and a second metal layer on the first insulating layer and the second active layer, wherein the second metal layer includes a first source and a first drain of the first transistor and a first light shielding layer above the second active layer.

8. The method for manufacturing the OLED display panel according to claim 7, wherein in the step S20, a projected area of the second gate electrode on the substrate layer is greater than or equal to a projected area of the second active layer on the substrate layer.

9. The method for manufacturing the OLED display panel according to claim 7, wherein in the step S30, a projected area of the first light shielding layer on the substrate layer is greater than or equal to a projected area of the second active layer on the substrate layer.

10. The method for manufacturing the OLED display panel according to claim 7, wherein the step S30 further includes: and preparing an interlayer insulating layer to cover the second metal layer, and preparing a third metal layer on the interlayer insulating layer, wherein the third metal layer comprises a conducting piece and a second shading layer, the conducting piece is electrically connected with the first drain electrode through a through hole penetrating through the interlayer insulating layer, and the second shading layer corresponds to the first shading layer and is positioned above the first shading layer.

Technical Field

The application relates to the technical field of display, in particular to an OLED display panel and a manufacturing method thereof.

Background

Display devices have also been developed to be products superior in portability and wearability. Due to the flexibility of the OLED display panel, the OLED display panel is increasingly sought after as a primary choice for flexible display. However, limited by the bottleneck of battery technology, reducing power consumption is the main direction.

Since the OLED display circuit is complex, and is usually a pixel circuit of 7T1C, the power consumption of the circuit is also high. Each pixel includes an organic light emitting diode constituted by an organic light emitting layer between an anode and a cathode, and a pixel circuit independently driving the organic light emitting diode. The pixel circuit is mainly composed of a switching transistor transmitting a data signal, a driving transistor driving the organic light emitting diode according to the data signal, and one capacitor holding a data voltage, the switching transistor charging the data voltage into the capacitor in response to a scan pulse, the driving transistor adjusting an amount of light emitted from the organic light emitting diode by controlling an amount of current supplied to the organic light emitting diode according to the data voltage charged in the capacitor.

However, the switching transistor is susceptible to light and heat generated in the OLED display panel due to the active layer made of the oxide semiconductor, which affects the stability of the switching transistor and the display effect.

Disclosure of Invention

The embodiment of the application provides an OLED display panel and a manufacturing method thereof, and the OLED display panel and the manufacturing method thereof can solve the technical problem that an active layer of the OLED display panel in the prior art is easily influenced by light and heat emitted in the OLED display panel due to the fact that the active layer is made of oxide semiconductor materials, so that the stability of a transistor device is influenced, and the display effect is further influenced.

In order to solve the above technical problem, an embodiment of the present invention provides an OLED display panel, including a plurality of pixel regions, each of the pixel regions including a first transistor and a second transistor;

the OLED display panel further includes:

a substrate layer;

a first metal layer disposed on the substrate layer, the first metal layer including a first gate of the first transistor and a second gate of the second transistor;

the second metal layer is arranged above the first metal layer and comprises a first source electrode and a first drain electrode of the first transistor and a first shading layer positioned above the second transistor;

wherein the second active layer of the second transistor is located between the second gate and the first light-shielding layer.

In an embodiment of the present application, a projected area of the second gate electrode on the substrate layer is greater than or equal to a projected area of the second active layer on the substrate layer.

In an embodiment of the application, a projected area of the first light shielding layer on the substrate layer is greater than or equal to a projected area of the second active layer on the substrate layer.

In an embodiment of the present application, the OLED display panel further includes an interlayer insulating layer and a third metal layer sequentially disposed on the second metal layer, the interlayer insulating layer covers the second metal layer, the third metal layer includes a via hole penetrating through the interlayer insulating layer, a conducting member electrically connected to the first drain, and a second light shielding layer corresponding to the first light shielding layer and located above the first light shielding layer.

In an embodiment of the present application, the OLED display panel further includes a flat layer and a pixel definition layer sequentially disposed on the third metal layer, the flat layer covers the third metal layer, the pixel definition layer includes a plurality of pixel openings corresponding to the plurality of pixel areas one to one, an anode and an organic light emitting layer are sequentially disposed in each of the plurality of pixel openings, and the anode is electrically connected to the conduction member through a via hole penetrating through the flat layer.

In one embodiment of the present application, the first transistor further includes a first active layer disposed between the substrate layer and the first gate electrode, and a material of the first active layer includes low temperature polysilicon, and a material of the second active layer includes an oxide semiconductor.

According to the above object of the present invention, a method for fabricating an OLED display panel is provided, the OLED display panel includes a plurality of pixel regions, and each of the pixel regions includes a first transistor and a second transistor;

the method comprises the following steps:

s10, preparing a first metal layer on the substrate layer, wherein the first metal layer comprises a first grid electrode of the first transistor and a second grid electrode of the second transistor;

s20, sequentially preparing a first insulating layer and a second active layer on the first metal layer, wherein the second active layer is located above the second gate; and

s30, sequentially preparing a second insulating layer and a second metal layer on the first insulating layer and the second active layer, wherein the second metal layer includes a first source and a first drain of the first transistor and a first light shielding layer above the second active layer.

In an embodiment of the application, in the step S20, a projected area of the second gate on the substrate layer is greater than or equal to a projected area of the second active layer on the substrate layer.

In an embodiment of the application, in the step S30, a projected area of the first light shielding layer on the substrate layer is greater than or equal to a projected area of the second active layer on the substrate layer.

In an embodiment of the present application, the step S30 further includes: and preparing an interlayer insulating layer to cover the second metal layer, and preparing a third metal layer on the interlayer insulating layer, wherein the third metal layer comprises a conducting piece and a second shading layer, the conducting piece is electrically connected with the first drain electrode through a through hole penetrating through the interlayer insulating layer, and the second shading layer corresponds to the first shading layer and is positioned above the first shading layer.

The beneficial effect of this application: the OLED display panel comprises a first grid electrode, a first source electrode, a first drain electrode, a second grid electrode, a first shading layer, a second active layer, a second shading layer and a second active layer, wherein the first grid electrode and the first source electrode are used for preparing the first transistor, the second grid electrode is used for preparing the second transistor, the first shading layer is used for being positioned above the second transistor, the second active layer of the second transistor is arranged between the second grid electrode and the first shading layer, the upper surface and the lower surface of the second active layer are protected, light and heat emitted in the OLED display panel are effectively blocked, the influence of the light and the heat on the stability of the second active layer is prevented, the stability of the second active layer is improved, the stability of the second transistor is improved, the display effect of the OLED display panel is improved, additional process procedures are not needed, and the process time and the process.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of an OLED display panel provided in an embodiment of the present application.

Fig. 2 is a flowchart of a method for manufacturing an OLED display panel according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

The embodiment of the application aims at the technical problems that the stability of a transistor device is influenced and the display effect is influenced because an active layer is made of an oxide semiconductor material and is easily influenced by light and heat emitted in an OLED display panel.

In order to solve the above technical problems, an embodiment of the present invention provides an OLED display panel, as shown in fig. 1, the OLED display panel includes a plurality of pixel regions, and each of the pixel regions includes a first transistor 101 and a second transistor 102; and the OLED display panel further includes: a substrate layer 109; a first metal layer 103 disposed on the substrate layer 109, the first metal layer 103 including a first gate 1031 of the first transistor 101 and a second gate 1032 of the second transistor 102; a second metal layer 104 disposed above the first metal layer 103, wherein the second metal layer 104 includes a first source 1041 and a first drain 1042 of the first transistor 101, and a first light-shielding layer 1043 located above the second transistor 102; the second active layer 105 of the second transistor 102 is located between the second gate 1032 and the first light shielding layer 1043.

In implementing the application, the existing OLED display panel adopts the LTPO technology for saving power consumption by providing a first transistor and a second transistor, and the second transistor charges a data voltage into a capacitor in response to a scan pulse, the first transistor adjusts a light emission amount of an organic light emitting diode by controlling a current amount supplied to the organic light emitting diode according to the data voltage charged in the capacitor, but the existing second transistor adopts an oxide semiconductor material as an active layer so that the active layer of the second transistor is highly susceptible to light and heat emitted within the OLED display panel, so that the second transistor is unstable, thereby affecting a display effect of the OLED display panel, whereas in the embodiment of the present application, by correspondingly preparing a second gate electrode and a first light shielding layer of the second transistor while preparing a first gate electrode and a first source electrode and a first drain electrode of the first transistor, and the second active layer of the second transistor is arranged between the second grid electrode and the first shading layer, so that the upper surface and the lower surface of the second active layer are protected, light and heat emitted in the OLED display panel are effectively blocked, the influence of the light and the heat on the stability of the second active layer is prevented, the stability of the second active layer is improved, the stability of the second transistor is improved, and the display effect of the OLED display panel is further improved.

Specifically, referring to fig. 1, the OLED display panel includes a substrate layer 109, and a first transistor 101 and a second transistor 102 disposed on the substrate layer 109.

Further, the substrate layer 109 includes a substrate 1091 and a buffer layer 1092, the substrate 1091 is not limited to a glass substrate or a flexible substrate, the material of the flexible substrate may include polyimide or polyethylene terephthalate, and the buffer layer 1092 may be a structural layer composed of one or more layers of silicon nitride (SiNx) or silicon oxide (SiO 2).

In the embodiment of the present application, the OLED display panel further includes a passivation layer 111, a first insulating layer 112, a second insulating layer 113, an interlayer insulating layer 114, a planarization layer 115, and a pixel defining layer 116 sequentially disposed on the substrate layer 109, where the passivation layer 111, the first insulating layer 112, the second insulating layer 113, and the interlayer insulating layer 114 may each be one or more layers of silicon nitride (SiNx) or silicon oxide (SiO2), the planarization layer 115 is not limited to an organic material layer or an inorganic material layer, and the pixel defining layer 116 may be an organic material layer and may include polyimide.

The first transistor 101 includes a first active layer 110 disposed on the substrate layer 109 and covered by the passivation layer 111, a first gate 1031 disposed on the passivation layer 111 and covered by the first insulating layer 112, a third gate 107 disposed on the first insulating layer 112 and covered by the second insulating layer 113, a first source 1041 and a first drain 1042 disposed on the second insulating layer 113 and covered by the interlayer insulating layer 114, wherein the first active layer 110 is disposed between the substrate layer 109 and the first gate 1031, the first gate 1031 is disposed on the first metal layer 103, the third gate 107 is disposed above the first gate 1031 to form a capacitor structure, so as to improve the operating efficiency of the first transistor 101, the first source 1041 and the first drain 1042 are disposed on the second metal layer 104, and the first source 1041 and the second source 1042 pass through the second insulating layer 113, The first insulating layer 112 and a portion of the via hole of the passivation layer 111 overlap both sides of the first active layer 110, respectively.

The second transistor 101 includes a second gate 1032 disposed on the passivation layer 111 and covered by the first insulating layer 112, a second active layer 105 disposed on the first insulating layer 112 and covered by the second insulating layer 113, and a second source 1081 and a second drain 1082 respectively disposed on two sides of the second active layer 105 and overlapping with two sides of the second active layer 105, it should be noted that the second metal layer 104 further includes a first light shielding layer 1043 disposed on the second insulating layer 113 and covered by the interlayer insulating layer 114, wherein the second gate 1032 is located in the first metal layer 103, and the second active layer 105 is located between the second gate 1032 and the first light shielding layer 1043 and located in the same structural layer as the third gate 107.

The OLED display panel further includes a third metal layer 106 disposed on the interlayer insulating layer 114 and covered by the planarization layer, the third metal layer 106 includes a conductive element 1061 corresponding to the first transistor 101 and a second light shielding layer 1062 corresponding to the second transistor 102, the conductive element 1061 is electrically connected to the first drain 1042 through a via hole penetrating through the interlayer insulating layer 114, and the second light shielding layer 1062 is located above the first light shielding layer 1043.

In the embodiment of the present invention, the material of the first active layer 110 includes low temperature polysilicon, the material of the second active layer 105 includes an oxide semiconductor, that is, the first transistor 101 may be a driving transistor of the OLED display panel, and the second transistor 102 may be a switching transistor of the OLED display panel, and in the embodiment of the present invention, the second gate 1032 and the first light shielding layer 1043 are disposed on the upper and lower surfaces of the second active layer 105 to block the influence of light and heat in the OLED display panel on the second active layer 105, so as to improve the stability of the second active layer 105, and further improve the stability of the second transistor 102, and improve the display effect of the OLED display panel, and meanwhile, the second gate 1032 and the first light shielding layer 1043 are disposed in the same process as the first gate 1031, the first source 1041, and the first drain 1042, respectively, no additional process is needed, the process time and the process cost are saved, the product yield is improved, furthermore, a third metal layer 106 is further arranged, namely, the conducting piece 1061 is arranged, and meanwhile, the second light shielding layer 1062 is prepared above the first light shielding layer 1043, so that the protection effect on the second active layer 105 is further enhanced, and the third metal layer 106 can be made of materials with better light reflection performance, such as metal Mo and the like, so that the blocking effect of the second light shielding layer 1062 on light and heat is improved.

It should be noted that a projection area of the second gate 1032 on the substrate layer 109 is greater than or equal to a projection area of the second active layer 105 on the substrate layer 109, and a projection area of the first light shielding layer 1043 on the substrate layer 109 is greater than or equal to a projection area of the second active layer 105 on the substrate layer 109, and in an implementation application process, the first light shielding layer 1043, the second source electrode 1081, and the second drain electrode 1082 should be arranged in a staggered manner as much as possible, so as to avoid an overlapping area to generate a parasitic capacitance.

The pixel defining layer 116 includes a plurality of pixel openings 119 corresponding to the plurality of pixel regions one to one, and an anode 117 and an organic light emitting layer 118 are sequentially disposed in each of the plurality of pixel openings 119, and the anode 117 is electrically connected to the conductive element 1061 through a via penetrating through the planar layer 115, and is electrically connected to the first drain 1042 through the conductive element 1061, so as to implement signal input.

In addition, an embodiment of the present invention further provides a method for manufacturing an OLED display panel according to the above embodiments, specifically, referring to fig. 1 and fig. 2, the OLED display panel includes a plurality of pixel regions, each of the pixel regions includes a first transistor 101 and a second transistor 102, and the method includes:

s10, preparing a first metal layer 103 on the substrate layer 109, where the first metal layer 103 includes the first gate 1031 of the first transistor 101 and the second gate 1032 of the second transistor 102.

Specifically, a substrate 1091 is provided, a buffer layer 1092 is formed on the substrate 1091, a first active layer 110 of the first transistor 101 is formed on the buffer layer 1092, a passivation layer 111 is formed on the buffer layer 1092 and covers the first active layer 110, a first metal layer 103 is formed on the passivation layer 111, the first metal layer 103 includes a first gate 1031 of the first transistor 101 and a second gate 1032 of the second transistor 102, and the first gate 1031 is located above the first active layer 110.

The substrate is not limited to a glass substrate or a flexible substrate, and the material of the flexible substrate includes polyimide or polyethylene terephthalate, the buffer layer 1092 and the passivation layer 111 may both be one or more layers of silicon nitride (SiNx) or silicon oxide (SiO2), and the material of the first active layer 110 includes low temperature polysilicon.

S20, sequentially preparing a first insulating layer 112 and a second active layer 105 on the first metal layer 103, wherein the second active layer 105 is located above the second gate 1032.

Specifically, a first insulating layer 112 is prepared to cover the first metal layer 103, the third gate 107 of the first transistor 101 and the second active layer 105 of the second transistor 102 are prepared on the first insulating layer 112, and the second source 1081 and the second drain 1082 of the second transistor 102 are prepared on two sides of the second active layer 105, and are respectively overlapped with two sides of the second active layer 105.

It should be noted that a projected area of the second gate 1032 on the substrate layer 109 is greater than or equal to a projected area of the second active layer 105 on the substrate layer 109.

The third gate 107 is located above the first gate 1031, and forms a capacitor structure with the first gate 1031 to improve the efficiency of the first transistor 101, and the second active layer 105 is located above the second gate 1032, so that the second gate 1032 can block light and heat conducted below the second active layer 105.

S30, sequentially preparing a second insulating layer 113 and a second metal layer 104 on the first insulating layer 112 and the second active layer 105, wherein the second metal layer 104 includes a first source 1041 and a first drain 1042 of the first transistor 101, and a first light shielding layer 1043 located above the second active layer 105.

Specifically, the second insulating layer 113 is formed on the first insulating layer 112 and covers the second active layer 105, the third gate 107, the second source 1081 and the second drain 1082, the second metal layer 104 is formed on the second insulating layer 113, the second metal layer 104 includes the first source 1041 and the first drain 1042 of the first transistor 101 and the first shielding layer 1043 of the second transistor 101, the first source 1041 and the first drain 1042 are respectively overlapped with two sides of the first active layer 110 by via holes penetrating through the second insulating layer 113, the first insulating layer 112 and a portion of the passivation layer 111, and the first shielding layer 1043 is located above the second active layer 105, so that the first shielding layer 1043 can block light and heat conducted above the second active layer 105.

It should be noted that a projection area of the first light shielding layer 1043 on the substrate layer 109 is greater than or equal to a projection area of the second active layer 105 on the substrate layer 109, and in an implementation application process, the first light shielding layer 1043, the second source electrode 1081, and the second drain electrode 1082 should be arranged in a staggered manner as much as possible to avoid an overlapping area to generate a parasitic capacitance.

Further, the step S30 further includes: an interlayer insulating layer 114 is prepared to cover the second metal layer 104, a third metal layer 106 is prepared on the interlayer insulating layer 114, the third metal layer 106 includes a conducting element 1061 electrically connected to the first drain electrode 1042 through a via hole penetrating through the interlayer insulating layer 114, and a second light shielding layer 1062 located above the first light shielding layer 1043, and the second metal layer 106 may be made of a material with better light reflectivity, such as Mo metal, so as to improve the light and heat shielding effect of the second light shielding layer 1062.

In addition, a planarization layer 115 is prepared on the interlayer insulating layer 114 and covers the third metal layer 106, an anode 117 is prepared on the planarization layer 115, the anode 117 is electrically connected to the via 1062 through a via hole penetrating through the planarization layer 115, a pixel definition layer 116 is prepared on the planarization layer 115, a plurality of pixel openings 119 corresponding to the pixel areas one by one are formed in the pixel definition layer 116, each pixel opening 119 correspondingly exposes an upper surface of one anode 117, an organic light emitting layer 118 is prepared on the anode 117, and the anode 117 is electrically connected to the via 1061 through a via hole penetrating through the planarization layer 115 and is electrically connected to the first drain 1042 through the via 1061, so as to implement signal input.

It should be noted that the subsequent processes further include processes such as packaging, and the preparation can be performed by referring to the existing processes, which are not described herein again.

To sum up, in the embodiment of the present application, when the first gate electrode, the first source electrode and the first drain electrode of the first transistor are prepared, the second gate electrode of the second transistor and the first light shielding layer located above the second transistor are respectively and correspondingly prepared, and the second active layer of the second transistor is disposed between the second gate electrode and the first light shielding layer, so that the upper and lower surfaces of the second active layer are protected, light and heat emitted in the OLED display panel are effectively blocked, the influence of the light and the heat on the stability of the second active layer is prevented, the stability of the second active layer is improved, the stability of the second transistor is improved, the display effect of the OLED display panel is improved, no additional process is required, and the process time and the process cost are saved.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The OLED display panel and the manufacturing method thereof provided in the embodiments of the present application are described in detail above, and specific examples are applied in the description to explain the principle and the implementation manner of the present application, and the description of the embodiments above is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.