阅读说明：本技术 半导体存储装置、半导体存储装置的制造方法及电子装置 (Semiconductor memory device, method of manufacturing semiconductor memory device, and electronic apparatus ) 是由 塚本雅则 于 2019-02-12 设计创作，主要内容包括：[问题]用于提供一种半导体存储装置和电子装置,半导体存储装置包括具有更优化的结构的铁电电容器作为存储器单元。[解决方案]一种半导体存储装置,包括：场效应晶体管,设置在半导体衬底的有源区域中；铁电电容器,具有将铁电膜保持在其间的第一电容器电极和第二电容器电极,所述第一电容器电极电连接到所述场效应晶体管的源极或漏极中的一个；源极线,电连接到所述铁电电容器的所述第二电容器电极；以及位线,电连接到所述场效应晶体管的源极或漏极中的另一个。所述场效应晶体管的栅极电极在第一方向上延伸超出所述有源区域,并且所述源极线和所述位线在与所述第一方向垂直的第二方向上延伸。([ problem ] to provide a semiconductor memory device including a ferroelectric capacitor having a more optimized structure as a memory cell, and an electronic device. [ solution ] A semiconductor storage device includes: a field effect transistor disposed in an active region of a semiconductor substrate; a ferroelectric capacitor having a first capacitor electrode and a second capacitor electrode holding a ferroelectric film therebetween, the first capacitor electrode being electrically connected to one of a source or a drain of the field effect transistor; a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor; and a bit line electrically connected to the other of the source or the drain of the field effect transistor. A gate electrode of the field effect transistor extends beyond the active region in a first direction, and the source line and the bit line extend in a second direction perpendicular to the first direction.)

1. A semiconductor memory device, comprising:

a field effect transistor disposed in an active region of a semiconductor substrate;

a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field effect transistor;

a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor; and

a bit line electrically connected to the other of the source or the drain of the field effect transistor,

wherein a gate electrode of the field effect transistor extends in a first direction across the active region, and the source line and the bit line extend in a second direction orthogonal to the first direction.

2. The semiconductor storage device according to claim 1, wherein the active region is provided in a stripe shape extending in a third direction obliquely crossing both the first direction and the second direction.

3. The semiconductor memory device according to claim 2, wherein the active regions are separated from each other by an element separation layer provided over the semiconductor substrate.

4. The semiconductor storage device of claim 1, wherein the gate is electrically connected to a word line.

5. The semiconductor memory device according to claim 1,

wherein a planarization film burying the field effect transistor is provided on the semiconductor substrate, an

The ferroelectric capacitor is disposed inside an opening provided in the planarization film.

6. The semiconductor memory device according to claim 5, wherein the ferroelectric capacitor includes the first capacitor electrode provided along a bottom surface and a side surface of the opening, the ferroelectric film provided on the first capacitor electrode along a shape of the opening, and the second capacitor electrode provided on the ferroelectric film to fill the opening.

7. The semiconductor storage device according to claim 6, wherein the first capacitor electrode is provided so as to be recessed from an opening surface of the opening in the planarization film.

8. The semiconductor memory device according to claim 5, wherein the ferroelectric capacitor is provided on the active region.

9. The semiconductor storage device according to claim 8, wherein the ferroelectric capacitor is provided on the active region corresponding to one of a source or a drain of the field effect transistor.

10. The semiconductor memory device according to claim 5, wherein the source line and the bit line are provided in the same layer.

11. The semiconductor memory device according to claim 5,

wherein the bit line is provided inside an interlayer insulating film provided on the planarization film, an

The opening is provided so as to penetrate from the interlayer insulating film up to the surface of the semiconductor substrate.

12. The semiconductor storage device according to claim 5, wherein the opening is provided so as to penetrate from the planarization film up to an inside of the semiconductor substrate.

13. A manufacturing method of a semiconductor memory device, the manufacturing method comprising:

forming a field effect transistor in an active region of a semiconductor substrate such that a gate electrode of the field effect transistor extends in a first direction across the active region;

forming a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field effect transistor; and

forming a source line electrically connected with the second capacitor electrode of the ferroelectric capacitor and a bit line electrically connected to the other of the source or the drain of the field effect transistor such that the source line and the bit line extend in a second direction orthogonal to the first direction.

14. An electronic device, comprising:

a semiconductor memory device comprising

A field effect transistor disposed in an active region of a semiconductor substrate,

a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field effect transistor,

a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor, an

A bit line electrically connected to the other of the source or the drain of the field effect transistor,

wherein, in the semiconductor memory apparatus, a gate electrode of the field effect transistor extends in a first direction crossing the active region, and the source line and the bit line extend in a second direction orthogonal to the first direction.

Technical Field

The present disclosure relates to a semiconductor memory device, a method of manufacturing the semiconductor memory device, and an electronic device.

Background

Complementary Metal Oxide Semiconductor (CMOS) circuits including an n-type metal oxide semiconductor field effect transistor (nMOSFET) and a p-type mosfet (pmosfet) provided on the same substrate are known as circuits having low power consumption, being operable at high speed, and being easily miniaturized and highly integrated.

Therefore, CMOS circuits are used in many Large Scale Integrated (LSI) devices. Note that such an LSI device has recently been commercialized as a system on chip (SoC) obtained by mounting an analog circuit, a memory, a logic circuit, and the like on one chip.

For example, a static random access memory (static RAM) (SRAM) or the like is used as a memory mounted on an LSI apparatus. In recent years, in order to reduce the cost and power consumption of LSI devices, it has been considered to use dynamic ram (dram), magnetic ram (mram), ferroelectric ram (feram), and the like instead of SRAM.

Here, the FeRAM refers to a semiconductor memory device that stores information using the direction of the remanent polarization of the ferroelectric member. For example, as an example of the structure of the FeRAM, a structure using a ferroelectric capacitor having a stacked cylindrical shape as a memory cell is proposed.

On the other hand, as a memory using a capacitor having a stacked cylindrical shape, as a memory cell, a DRAM using a paraelectric capacitor described in patent document 1 described below is known. For example, patent document 1 described below discloses a DRAM in which a paraelectric capacitor is provided in a contact hole provided on a drain region of a field effect transistor.

CITATION LIST

Patent document

Patent document 1: japanese unexamined patent application publication No.2007-

Disclosure of Invention

Problems to be solved by the invention

However, the structure disclosed in patent document 1 described above is a structure related to a DRAM using a paraelectric capacitor. Therefore, the structure disclosed in patent document 1 cannot be applied as it is to a FeRAM using a ferroelectric capacitor. Therefore, it is necessary to sufficiently optimize the structure of an FeRAM using a ferroelectric capacitor as a memory cell.

In view of the foregoing, the present disclosure proposes a semiconductor memory device, a method of manufacturing the semiconductor memory device, and an electronic device that are novel and improved and include a ferroelectric capacitor having a more optimized structure as a memory cell.

Solution to the problem

According to the present disclosure, there is provided a semiconductor memory device including: a field effect transistor disposed in an active region of a semiconductor substrate; a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field effect transistor; a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor; and a bit line electrically connected to the other of the source or the drain of the field effect transistor, wherein a gate electrode of the field effect transistor extends in a first direction across the active region, and the source line and the bit line extend in a second direction orthogonal to the first direction.

Further, according to the present disclosure, there is provided a manufacturing method of a semiconductor memory device, the manufacturing method including: forming a field effect transistor in an active region of a semiconductor substrate such that a gate electrode of the field effect transistor extends in a first direction across the active region; forming a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field effect transistor; and forming a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor and a bit line electrically connected to the other of the source or the drain of the field effect transistor such that the source line and the bit line extend in a second direction orthogonal to the first direction.

Further, according to the present disclosure, there is provided an electronic device including a semiconductor storage device including: a field effect transistor disposed in an active region of a semiconductor substrate; a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field effect transistor; a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor; and a bit line electrically connected to the other of the source or the drain of the field effect transistor; wherein, in the semiconductor memory apparatus, a gate electrode of the field effect transistor extends in a first direction crossing the active region, and the source line and the bit line extend in a second direction orthogonal to the first direction.

In the present disclosure, in a semiconductor memory apparatus including a capacitor and a transistor, an extending direction of a word line WL controlling selection or non-selection of the capacitor is orthogonal to an extending direction of a source line SL and a bit line BL driving the capacitor at the time of reading. Therefore, since the capacitor and the transistor can be efficiently arranged in the semiconductor memory device, an increase in the occupied area can be prevented.

ADVANTAGEOUS EFFECTS OF INVENTION

As described above, according to the present disclosure, a semiconductor memory device and an electronic device including a ferroelectric capacitor having a more optimized structure as a memory cell can be provided.

Note that the above-described effects are not always restrictive, and any of the effects described in this specification or other effects recognized from this specification may be caused in addition to or instead of the above-described effects.

Drawings

Fig. 1 is a circuit diagram showing an equivalent circuit of a semiconductor memory apparatus according to an embodiment of the present disclosure.

Fig. 2 is a schematic diagram showing a planar structure and a sectional structure of the semiconductor memory device.

Fig. 3 shows a plan view and a cross-sectional view describing one process of a first manufacturing method of a semiconductor memory device.

Fig. 4 shows a plan view and a cross-sectional view describing one process of a first manufacturing method of a semiconductor memory device.

Fig. 5 shows a plan view and a cross-sectional view describing one process of a first manufacturing method of a semiconductor memory device.

Fig. 6 shows a plan view and a cross-sectional view describing one process of a first manufacturing method of a semiconductor memory device.

Fig. 7 shows a plan view and a sectional view describing one process of a first manufacturing method of a semiconductor memory device.

Fig. 8 shows a plan view and a sectional view describing one process of a first manufacturing method of a semiconductor memory device.

Fig. 9 shows a plan view and a sectional view describing one process of a first manufacturing method of a semiconductor memory device.

Fig. 10 shows a plan view and a sectional view describing one process of a second manufacturing method of a semiconductor memory device.

Fig. 11 shows a plan view and a sectional view describing one process of a second manufacturing method of a semiconductor memory device.

Fig. 12 shows a plan view and a sectional view describing one process of a second manufacturing method of a semiconductor memory device.

Fig. 13 shows a plan view and a sectional view describing one process of a second manufacturing method of a semiconductor memory device.

Fig. 14 shows a plan view and a sectional view describing one process of a third manufacturing method of a semiconductor memory device.

Fig. 15 shows a plan view and a sectional view describing one process of a third manufacturing method of a semiconductor memory device.

Fig. 16 shows a plan view and a sectional view describing one process of a third manufacturing method of a semiconductor memory device.

Fig. 17 shows a plan view and a sectional view describing one process of a third manufacturing method of a semiconductor memory device.

Fig. 18 shows a plan view and a sectional view describing one process of a third manufacturing method of a semiconductor memory device.

Fig. 19 is a sectional view schematically showing a section taken along an active region of a semiconductor memory apparatus.

Fig. 20A is an external view illustrating an example of an electronic device according to an embodiment of the present disclosure.

Fig. 20B is an external view illustrating an example of an electronic device according to an embodiment of the present disclosure.

Fig. 20C is an external view illustrating an example of an electronic device according to an embodiment of the present disclosure.

Detailed Description

Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that in the present specification and the drawings, redundant description will be omitted by assigning the same reference numerals to components having substantially the same functional configuration.

Note that the description will be given in the following order.

1. Overview

2. Structural examples

3. Manufacturing method

3.1. First manufacturing method

3.2. Second manufacturing method

3.3. Third manufacturing method

4. Example of operation

5. Application example

<1. overview >

First, an outline of a semiconductor memory apparatus according to an embodiment of the present disclosure will be described with reference to fig. 1. Fig. 1 is a circuit diagram showing an equivalent circuit of the semiconductor storage device according to the present embodiment. Note that in the following description, "gate" indicates a gate electrode of a field effect transistor, "drain" indicates a drain electrode or a drain region of the field effect transistor, and "source" indicates a source electrode or a source region of the field effect transistor.

As shown in fig. 1, the semiconductor memory device 10 includes a capacitor 11 that stores information, and a transistor 21 that controls selection and non-selection of the capacitor 11. The semiconductor memory device 10 is a memory cell that stores one bit of information, for example, 0 or 1.

The capacitor 11 is a ferroelectric capacitor including a pair of electrodes sandwiching a ferroelectric film. The capacitor 11 can store information based on the direction of the residual polarization of the ferroelectric film sandwiched by the pair of electrodes. In the capacitor 11, one of the pair of electrodes is electrically connected to a source line SL, and the other of the pair of electrodes is electrically connected to a source or a drain of the transistor 21.

The transistor 21 is a field effect transistor that controls selection and non-selection of the capacitor 11. In the transistor 21, one of a source or a drain is electrically connected to the other electrode of the capacitor 11, and the other of the source or the drain is electrically connected to the bit line BL. Further, the gate of the transistor 21 is electrically connected to the word line WL, and the on/off state of the channel of the transistor 21 is controlled based on the applied voltage from the word line WL.

In the semiconductor memory device 10, when information is written into the capacitor 11, first, a voltage is applied to the word line WL, whereby the channel of the transistor 21 is turned on. After that, by applying a potential difference corresponding to information to be written between the source line SL and the bit line BL, an electric field is applied to the ferroelectric film of the capacitor 11. Accordingly, the semiconductor memory device 10 can control the direction of the remanent polarization of the ferroelectric film of the capacitor 11 based on the external electric field and write information into the capacitor 11.

On the other hand, in the semiconductor memory device 10, when reading information from the capacitor 11, first, a voltage is applied to the word line WL, whereby the channel of the transistor 21 is turned on. Thereafter, by applying a predetermined potential difference between the source line SL and the bit line BL, the polarization direction of the ferroelectric film of the capacitor 11 is changed to a predetermined direction. At this time, the magnitude of the current flowing in the capacitor 11 at the time of the transition changes depending on the polarization direction of the ferroelectric film before the transition. Therefore, in the semiconductor memory device 10, by measuring the magnitude of the current flowing into the capacitor 11, the information stored in the capacitor 11 can be read out.

With this arrangement, the semiconductor storage device 10 can operate as a ferroelectric random access memory (FeRAM) that stores information into the capacitor 11.

In the semiconductor memory device 10, the source lines SL and the bit lines BL extend in a direction orthogonal to the extending direction of the word lines WL. The reason for the extending direction of the source line SL, the bit line BL, and the word line WL will be described hereinafter.

In the semiconductor memory device 10 serving as an FeRAM using a ferroelectric capacitor, information is stored based on the polarization direction of the capacitor 11. Therefore, in order to read out information from the capacitor 11, a voltage is applied between the source line SL and the bit line BL, and the polarization of the capacitor 11 is converted into an electric charge amount and read out to the outside.

For example, when a voltage is applied to the word line WL, all the transistors 21 arranged in the extending direction of the word line WL become on state. Therefore, in the case where the extending direction of the word line WL is parallel to either one of the source line SL or the bit line BL, a potential is applied from the source line SL or the bit line BL to all the capacitors 11 arranged in the extending direction of the word line WL via the transistor 21 in an on state. In this case, a failure may occur in the unselected capacitor 11 to which a potential is applied from the source line SL or the bit line BL.

Further, in the semiconductor memory device 10, in order to write information into each capacitor 11 arranged in a matrix, the word line WL needs to be orthogonal to the source line SL and the bit line BL, and the intersection needs to be uniquely defined. Specifically, it is important that the extending direction of the selected or unselected word line WL of the control capacitor 11 is orthogonal to the extending direction of the source line SL and the bit line BL of the drive capacitor 11 at the time of writing.

Here, as other examples of the semiconductor memory device that stores information using a capacitor, a Dynamic Random Access Memory (DRAM) using a paraelectric capacitor is included.

In the DRAM, in order to increase the degree of integration, a method of fixing a source line connected to one of a pair of electrodes of a capacitor to a predetermined potential (this method will also be referred to as "Vcc/2 method") may be used. In this case, since the source line fixed to a predetermined potential is provided as a plate-like electrode scattered like a plate over the memory cell, the extending direction of the source line is not defined. Therefore, in the DRAM, the extending direction of the word line that controls the selection or non-selection of the capacitor and the extending direction of the source line and the bit line that drive the capacitor at the time of reading are not sufficiently considered.

As described above, since the semiconductor memory device 10 according to the present embodiment is provided as an FeRAM having a driving principle different from that of a DRAM, it becomes important to define the respective extending directions of the word lines WL, the source lines SL, and the bit lines BL. With this arrangement, since the semiconductor memory device 10 can form a memory cell using a simple configuration including the capacitor 11 and the transistor 21, integration and high density of the semiconductor memory device 10 can be more easily achieved. Further, in the semiconductor storage device 10, since selection and non-selection of the capacitor 11 can be controlled by the transistor 21, it is possible to prevent generation of a write interruption of rewriting information stored in the unselected capacitor 11 in writing of information.

<2. structural example >

Subsequently, a specific structure of the semiconductor memory device 10 according to the present embodiment will be described with reference to fig. 2. Fig. 2 is a schematic diagram showing a planar structure and a sectional structure of the semiconductor memory device 10 according to the present embodiment.

Note that, in order to clarify the arrangement of each configuration, the plan view in fig. 2 is described as a plan perspective view while omitting the planarization film 200 and the interlayer insulating film 300 formed over the entire surface of the semiconductor substrate 100. The sectional view in fig. 2 shows respective sections obtained by taking a plan view along the lines a-a, B-B and C-C.

Further, in the following description, "first conductivity type" indicates one of "p type" or "n type", and "second conductivity type" indicates the other of "p type" or "n type" different from the "first conductivity type".

As shown in fig. 2, the semiconductor memory device 10 is provided on a semiconductor substrate 100. By arranging a large number of semiconductor memory devices 10 in a matrix on a semiconductor substrate 100, a semiconductor memory 1 that can store a large amount of information is formed.

The capacitor 11 includes a first capacitor electrode 111 provided on the source or drain region 151 along the inside of an opening penetrating the planarization film 200, a ferroelectric film 113 provided on the first capacitor electrode 111 along the opening, and a second capacitor electrode 115 provided on the ferroelectric film 113 to fill the opening. The first capacitor electrode 111 is electrically connected to the source or drain region 151 of the transistor 21, and the second capacitor electrode 115 is electrically connected to the first wiring layer 311 serving as a source line SL.

The transistor 21 includes a gate insulating film 140 provided on the semiconductor substrate 100, a gate electrode 130 provided on the gate insulating film 140, and a source or drain region 151 provided in an active region 150 of the semiconductor substrate 100. By being connected to the first capacitor electrode 111, one of the source or drain regions 151 is electrically connected to the capacitor 11, and the other of the source or drain regions 151 is electrically connected to the second wiring layer 312 serving as the bit line BL via the contact 210. The gate electrode 130 functions as a word line WL by being provided over the plurality of active regions 150 across the element separation layer 105.

In the semiconductor memory device 10, the active region 150 is provided in a band shape extending in a third direction obliquely crossing both the first direction in which the gate electrode 130 extends and the second direction in which the first wiring layer 311 and the second wiring layer 312 extend. Therefore, the source or drain region 151 included in the same transistor 21 as the gate electrode 130 and the gate insulating film 140 shown in the line a-a sectional view is not shown in the line a-a sectional view, and one of the source or drain region 151 is shown in the line B-B sectional view. Note that a sectional view taken along the active region 150 will be described later with reference to fig. 19.

Here, as a structure in which a capacitor is formed by burying a dielectric member and an electrode in a recess or an opening provided in the planarization film 200, the semiconductor substrate 100, or the like, a Dynamic Random Access Memory (DRAM) having a stacked-type cylindrical shape can be given. However, in a DRAM that stores information based on charges accumulated in a capacitor, in order to read out the stored information with sufficient accuracy, for example, a capacitance of 100fF for a bit line, a capacitor capacitance of about 20fF is required.

For example, in the case where the relative dielectric constant of a dielectric member used in a capacitor is 25, when the width of the dielectric film is set to 60nm and the film thickness thereof is set to 5nm, the depth of the recess or opening for forming the capacitor having a capacitance of 20fF becomes about 8 μm. Since it is extremely difficult to process a recess or opening having such a depth, the recess or opening makes miniaturization and high integration of the DRAM difficult.

The semiconductor memory device 10 according to the present embodiment functions as an FeRAM that stores information based on the remanent polarization of the ferroelectric member. Since the operation principle of FeRAM is different from that of DRAM, for example, even if the capacitance of the bit line is 100fF, if the remanent polarization of the ferroelectric element is about 25 μ C/μm²The information readout can also be performed with sufficient accuracy. The capacitor 11 that realizes such residual polarization can be formed by using a recess or an opening having a depth of about 400 nm. Therefore, the semiconductor memory device 10 according to the present embodiment can be more easily miniaturized and highly integrated.

Hereinafter, each configuration of the semiconductor memory device 10 will be described in more detail.

The semiconductor substrate 100 includes a semiconductor material, and is a substrate over which the capacitor 11 and the transistor 21 are formed. The semiconductor substrate 100 may be a silicon substrate, or may be a silicon substrate such as SiO therein₂Such as a silicon-on-insulator (SOI) substrate in which an insulating film is buried in a silicon substrate. Alternatively, the semiconductor substrate 100 may be a substrate formed of another element semiconductor such as germanium, or may be a substrate formed of a compound semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), or silicon carbide (SiC).

The element separation layer 105 includes an insulating material, and the transistors 21 provided over the semiconductor substrate 100 are connected to each otherAnd (4) electrically separating. The element separation layer 105 may be provided so as to extend in a third direction (for example, a direction from the upper left toward the lower right when facing fig. 2) in band-like regions separated from each other. Note that the third direction is a direction obliquely intersecting both a first direction in which the gate electrode 130 extends (for example, the up-down direction when facing fig. 2) and a second direction in which the first wiring layer 311 and the second wiring layer 312 extend (for example, the left-right direction when facing fig. 2). For example, the element separation layer 105 may be formed of, for example, silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Or an insulating oxynitride such as silicon oxynitride (SiON).

For example, using a Shallow Trench Isolation (STI) method, a portion of the semiconductor substrate 100 in a predetermined region may be removed by etching or the like and then silicon oxide (SiO) may be used_x) The element separation layer 105 is formed by filling an opening formed by etching or the like. Further, using a local oxidation of silicon (LOCOS) method, the element separation layer 105 can be formed by thermally oxidizing the semiconductor substrate 100 in a predetermined region.

Regions having a band-like shape and separated from each other by the element separation layer 105 each serve as an active region 150 in which the transistor 21 is formed. In the semiconductor substrate 100 in the active region 150, for example, a first conductivity type impurity (e.g., a p-type impurity such as boron (B) or aluminum (Al)) may be introduced.

As shown in fig. 2, the element separation layer 105 and the active region 150 may be provided in a belt-like shape extending in a zigzag shape in the third direction. With this arrangement, since the capacitor 11 and the transistor 21 can be efficiently arranged in the semiconductor memory device 10, an increase in the footprint of the semiconductor memory device 10 can be prevented. However, it is to be appreciated that the element separation layer 105 and the active region 150 may be provided in a linear shape extending without being bent in the third direction.

The gate insulating film 140 includes an insulating material, and is disposed on the active region 150 of the semiconductor substrate 100. The gate insulating film 140 may be formed of an insulating material known as a gate insulating film of a field effect transistor. For example, the gate insulating film 140 may be formed of, for example, silicon oxide (SiO)_x) Silicon nitride(SiN_x) Or an insulating oxynitride such as silicon oxynitride (SiON).

The gate electrode 130 includes a conductive material, and is disposed on the gate insulating film 140. Specifically, the gate electrode 130 is provided to extend in a first direction obliquely crossing a third direction in which the element separation layer 105 extends. Further, the plurality of gate electrodes 130 are disposed at predetermined intervals in a second direction orthogonal to the first direction. The gate electrode 130 functions as a word line WL that electrically connects the gate electrodes of the transistors 21 of the respective memory cells by extending across the element separation layer 105 and being disposed over the plurality of active regions 150.

For example, the gate electrode 130 may be formed of polysilicon or the like, or may be formed of a metal, an alloy, a metal compound, or an alloy of a metal (Ni or the like) and polysilicon (so-called silicide). Specifically, the gate electrode 130 may be formed as a stacked structure of a metal layer and a polysilicon layer. For example, the gate electrode 130 may be formed as a stacked structure of a metal layer including TiN or TaN and a polysilicon layer disposed on the gate insulating film 140. According to such a stacked structure, the gate electrode 130 can reduce the interconnection resistance as compared with the case where the gate electrode 130 is formed of only a polysilicon layer.

The source or drain region 151 is a region of the second conductivity type formed in the semiconductor substrate 100. Specifically, the source or drain regions 151 may be respectively disposed in the active regions 150 extending in the third direction to sandwich the gate electrode 130. One of the source or drain regions 151 is electrically connected to the first capacitor electrode 111, and the other of the source or drain regions 151 is electrically connected to the second wiring layer 312 serving as the bit line BL via the contact 210.

For example, the source or drain region 151 may be formed by introducing a second conductive type impurity (e.g., an n-type impurity such As phosphorus (P) or arsenic (As)) into the semiconductor substrate 100 in the active region 150. Note that a Lightly Doped Drain (LDD) region having the same second conductivity type as the source or drain region 151 and having a lower conductive impurity density than the source or drain region 151 may be formed in the semiconductor substrate 100 between the source or drain region 151 and the gate electrode 130.

Note that any one of the source or drain regions 151 provided across the gate electrode 130 may function as a source region, and any one thereof may function as a drain region. The function can be arbitrarily changed depending on the polarity of the conductive impurities or the connection lines.

The sidewall insulating film 132 includes an insulating material, and is provided on the side face of the gate electrode 130 as a sidewall. Specifically, the sidewall insulating film 132 may be formed by uniformly forming an insulating film in a region including the gate electrode 130 and performing vertical anisotropic etching on the insulating film. For example, the sidewall insulating film 132 may be formed of, for example, silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Or an insulating oxynitride such as silicon oxynitride (SiON) is formed of a single layer or a plurality of layers.

When the second conductivity type impurity is introduced into the semiconductor substrate 100, the sidewall insulating film 132 controls the positional relationship between the gate electrode 130 and the source or drain region 151 in a self-aligned manner by shielding the second conductivity type impurity. Since the sidewall insulating film 132 can gradually control the introduction of the conductive impurities into the semiconductor substrate 100, it becomes possible to form the above-described LDD region between the source or drain region 151 and the gate electrode 130 in a self-aligned manner.

The conductive layer 131 is disposed on the gate electrode 130 and serves as a line electrically connecting the gate electrode 130. Specifically, the conductive layer 131 is disposed on an upper surface of the gate electrode 130 and functions as a word line WL. For example, the conductive layer 131 may be formed of a metal or a metal compound.

The contact region 152 is disposed on the surface of the semiconductor substrate 100 in the source or drain region 151, and reduces contact resistance between the source or drain region 151 and the first capacitor electrode 111 or the contact 210. Specifically, the contact region 152 may be formed of a metal such as Ni or an alloy with silicon (so-called silicide).

The planarization film 200 includes an insulating material, buries the transistor 21, and is disposed over the entire surface of the semiconductor substrate 100. The planarization film 200 is provided with a source or a drain for exposing the transistor 21An opening of one of the pole regions 151, and a capacitor 11 having a cylindrical structure is disposed within the opening. For example, the planarization film 200 may be made of, for example, silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Or an insulating oxynitride such as silicon oxynitride (SiON).

Note that a liner layer which is not shown in fig. 2 and includes an insulating material may be provided over the entire surface over the semiconductor substrate 100, the sidewall insulating film 132, and the conductive layer 131. In forming the opening for disposing the capacitor 11 or the contact 210 in the planarization film 200, the liner layer can provide high etching selectivity between the liner layer and the planarization film 200. Therefore, in this process, the liner layer can prevent the etching of the semiconductor substrate 100 from being performed. For example, the liner layer may be formed of a material such as silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Or an insulating oxynitride such as silicon oxynitride (SiON). Specifically, the planarizing film 200 is made of silicon oxide (SiO)_x) In the case of formation, the liner layer may be made of silicon nitride (SiN)_x) And (4) forming.

Further, the liner layer may be formed as a layer that adds compressive stress or tensile stress to the semiconductor substrate 100 under the gate insulating film 140. In this case, the liner layer can increase the carrier mobility of a channel formed in the semiconductor substrate 100 by the stress action.

The first capacitor electrode 111 includes a conductive material, and is provided along an inner side of an opening formed in the planarization film 200 to expose the active area 150. An opening formed in the planarization film 200 is provided to expose one of the source or drain regions 151, and the first capacitor electrode 111 is provided on the one of the source or drain regions 151 exposed through the opening. Accordingly, the first capacitor electrode 111 may be electrically connected with the source or drain region 151. Further, the first capacitor electrode 111 is provided so as to be recessed from an opening surface of the opening provided in the planarization film 200. With this arrangement, while ensuring the capacitance of the capacitor 11, the first capacitor electrode 111 can be prevented from being short-circuited with the second capacitor electrode 115 or the first wiring layer 311.

For example, the first capacitor electrode 111 may be formed ofA metal such as titanium (Ti) or tungsten (W), or a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN). In addition, the first capacitor electrode 111 may be made of ruthenium (Ru), ruthenium oxide (RuO)₂) And the like. The first capacitor electrode 111 may be formed using, for example, sputtering based on Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Ionized Metal Plasma (IMP).

The ferroelectric film 113 includes a ferroelectric material, and is provided on the first capacitor electrode 111 along the inside of the opening formed in the planarization film 200. The ferroelectric film 113 is formed of a ferroelectric material which is spontaneously polarized and can control the direction of remanent polarization based on an external electric field. For example, the ferroelectric film 113 may be made of, for example, piezoelectric lead zirconate titanate (Pb (Zr, Ti) O₃PZT or strontium bismuth tantalate (SrBi)₂Ta₂O₉SBT) or the like, having a perovskite structure. Further, the ferroelectric film 113 may be formed by heat treatment or the like to include, for example, HfO_x、ZrO_xOr HfZrO_xOr the like, or may be a ferroelectric film obtained by modifying the above-described film including a high dielectric material by introducing atoms such as lanthanum (La), silicon (Si), or gadolinium (Gd). Further, the ferroelectric film 113 may be formed of a single layer or may be formed of a plurality of layers. For example, ferroelectric film 113 may be a film including a material such as HfO_xSuch as a single layer film of ferroelectric material. The ferroelectric film 113 may be formed by using Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or the like.

The second capacitor electrode 115 includes a conductive material, and is provided on the ferroelectric film 113 to fill an opening formed in the planarization film 200. For example, the second capacitor electrode 115 may be formed of a metal such as titanium (Ti) or tungsten (W), or a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN). In addition, the second capacitor electrode 115 may be made of ruthenium (Ru), ruthenium oxide (RuO)₂) And the like. The second capacitor electrode 115 may be formed by using Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or the like.

The capacitor 11 is formed by sandwiching the ferroelectric film 113 described above between the first capacitor electrode 111 and the second capacitor electrode 115. Accordingly, the semiconductor memory device 10 can store information based on the polarization direction of the ferroelectric film 113 of the capacitor 11.

The contact 210 includes a conductive material, and is disposed to penetrate the planarization film 200. Specifically, the contact 210 is provided on the active region 150 corresponding to the other of the source or drain regions 151, and electrically connects the other of the source or drain regions 151 of the transistor 21 and the second wiring layer 312 serving as the bit line BL.

For example, the contact 210 may be formed of a metal such as titanium (Ti) or tungsten (W) or a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN). The contact 210 may be formed of a single layer, or may be formed of a stacked member including a plurality of layers. For example, the contact 210 may be formed of Ti or a stacked member of TiN and W.

The interlayer insulating film 300 buries the first wiring layer 311 and the second wiring layer 312, and is provided on the planarization film 200 over the entire surface of the semiconductor substrate 100. For example, the interlayer insulating film 300 may be formed of, for example, silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Or an insulating oxynitride such as silicon oxynitride (SiON).

The first wiring layer 311 includes a conductive material, and is disposed on the planarization film 200. Specifically, the first wiring layer 311 is provided on the capacitor 11 as a line extending in a second direction orthogonal to the first direction in which the word line WL extends. The first wiring layer 311 functions as a source line SL by being electrically connected to the second capacitor electrode 115. The first wiring layer 311 may be formed of, for example, a metal material such as copper (Cu) or aluminum (Al), or may be formed in a damascene structure of Cu or a dual damascene structure.

The second wiring layer 312 includes a conductive material, and is disposed on the planarization film 200. Specifically, the second wiring layer 312 is provided on the contact 210 as a line extending in a second direction orthogonal to the first direction in which the word line WL extends. The second wiring layer 312 functions as a bit line BL by being electrically connected to the other of the source or drain region 151 via the contact 210. The second wiring layer 312 may be formed of, for example, a metal material such as copper (Cu) or aluminum (Al), or may be formed in a damascene structure of Cu or a dual damascene structure.

According to the above structure, in the semiconductor storage device 10, since selection and non-selection of the capacitor 11 can be controlled by the transistor 21, it is possible to prevent generation of a write interruption in the unselected capacitor 11. Further, in the semiconductor memory device 10, by defining the respective extending directions of the active region 150, the word line WL, the source line SL, and the bit line BL, the transistor 21 and the capacitor 11 can be arranged efficiently. With this arrangement, in the semiconductor storage device 10, since an increase in the footprint of one memory cell can be suppressed, it becomes possible to further increase the storage density.

<3 > production method

(3.1. first production method)

Subsequently, a first manufacturing method of the semiconductor memory device 10 according to the present embodiment will be described with reference to fig. 3 to 9. Fig. 3 to 9 show plan and sectional views describing respective processes of a first manufacturing method of the semiconductor memory device 10.

Note that, also in fig. 3 to 9, similarly to fig. 2, illustration of layers formed over the entire surface of the semiconductor substrate 100 is omitted. Further, the sectional views show respective sections obtained by taking the plan views along the AA line, the BB line, and the CC line.

First, as shown in fig. 3, an element separation layer 105 is formed over a semiconductor substrate 100, and an active region 150 in which a transistor 21 is to be formed is formed.

Specifically, SiO is formed on the semiconductor substrate 100 including Si by dry oxidation or the like₂Film, and further forming Si by low pressure Chemical Vapor Deposition (CVD) or the like₃N₄And (3) a membrane. Subsequently, in Si₃N₄After forming a patterned resist layer on the film to protect the region where the active region 150 is formed, SiO is formed₂Film, Si₃N₄The film and the semiconductor substrate 100 are etched to a depth of 350nm to 400 nm. Next, by forming SiO with a film thickness of 650nm to 700nm₂The element separation layer 105 is formed by filling the opening formed by etching. For example, with good stepsCovering and forming dense SiO₂High density plasma CVD of films can be used to form SiO₂And (3) a membrane.

Subsequently, the excessively formed SiO is removed by using Chemical Mechanical Polishing (CMP) or the like₂Film, planarizing the surface of the semiconductor substrate 100. For example, only SiO using CMP needs to be performed₂Removal of the film until Si is exposed₃N₄And (4) preparing a film.

Further, Si is removed using hot phosphoric acid or the like₃N₄And (3) a membrane. Note that in order to make the element separation layer 105 SiO₂The film is referred to as a denser film or, to round the corners of the active region 150, the Si may be removed₃N₄Before the membrane is in N₂、O₂Or H₂/O₂The semiconductor substrate 100 is annealed in ambient. Next, an oxide film 100A is formed by oxidizing the surface of the region of the semiconductor substrate 100 corresponding to the active region 150 by about 10nm, and then, ion implantation of a first conductivity type impurity (e.g., boron (B) or the like) is performed to convert the semiconductor substrate 100 in the active region 150 into a well of the first conductivity type.

Next, as shown in fig. 4, after the gate insulating film 140 is formed, the gate electrode 130 is formed on the gate insulating film 140.

Specifically, first, the oxide film 100A covering the surface of the semiconductor substrate 100 is peeled off using a hydrofluoric acid solution or the like. Thereafter, by using O at 700 deg.C₂Forming a film thickness of 1.5nm to 10nm including SiO on the semiconductor substrate 100 by a dry oxidation or Rapid Thermal Annealing (RTA) process of₂The gate insulating film 140. Note that, as the gas used in the dry oxidation, other than O₂In addition, H may be used₂/O₂、N₂Mixed gas of O or NO. Further, when the gate insulating film 140 is formed, by using plasma nitridation, SiO can also be formed₂The film is nitrogen doped.

Next, use was made of the solution in which SiH was reacted₄Low-pressure CVD in which a gas is used as a source gas and a film formation temperature is set to 580 to 620 ℃, a polysilicon film with a film thickness of 50 to 150nm is formed. This is achieved byThereafter, anisotropic etching is performed on the formed polysilicon film by using the patterned resist as a mask, thereby forming the gate electrode 130. For example, HBr or Cl based gases may also be used for the anisotropic etch. For example, at the 40nm node, the gate electrode 130 may be formed by setting the gate width to about 40nm to 50 nm.

Note that the gate electrode 130 functions as a word line WL. Further, the gate electrode 130 may be formed simultaneously with or in a shared manner with the gate electrodes of the transistors provided in a logic region or the like other than the region where the semiconductor memory device 10 is formed.

Next, as shown in fig. 5, sidewall insulating films 132 are formed on both side surfaces of the gate electrode 130, and a source or drain region 151 is formed in the active region 150 of the semiconductor substrate 100.

In particular, by using a voltage of 5keV to 20keV and 5 to 20 × 10¹³/cm²Is performed to both sides of the gate electrode 130, ion implantation of arsenic (As) As a second conductive type impurity is performed to form LDD regions. Since the short channel effect can be suppressed by forming the LDD, the characteristic variation of the transistor 21 can be suppressed. Note that phosphorus (P) may also be used as the second conductivity type impurity.

Next, SiO with a film thickness of 10nm to 30nm is formed using plasma CVD₂After the film formation, Si with a film thickness of 30nm to 50nm is formed using plasma CVD₃N₄And forming an insulating film for the side wall. Thereafter, by performing anisotropic etching on the insulating film for the side wall, the side wall insulating film 132 is formed on both side faces of the gate electrode 130.

Thereafter, at 20keV to 50keV and at 1 to 2 × 10¹⁵/cm²Is performed as the second conductive type impurity, and the second conductive type impurity is introduced into both sides of the gate electrode 130. Accordingly, source or drain regions 151 are formed in the active region 150 at both sides of the gate electrode 130. Further, the ion-implanted impurity was activated by performing Rapid Thermal Annealing (RTA) at 1000 ℃ for five seconds. Thus, the transistor 21 is formed. Note that, in order to promote activation of the introduced impurity and suppress diffusion of the impurity,a spike RTA may also be used to activate the impurities.

Subsequently, after forming a Ni film with a film thickness of 6nm to 8nm over the entire surface of the semiconductor substrate 100 by sputtering or the like, Ni on Si is silicided (NiSi) by performing RTA at 300 ℃ to 450 ℃ for 10 seconds to 60 seconds. Because of SiO₂Ni above remains unreacted, so by using H₂SO₄/H₂O₂Unreacted Ni is removed, and a conductive layer 131 including NiSi and a contact region 152 are formed on the gate electrode 130 and in the source or drain region 151, respectively. Note that by forming a Co or NiPt film in place of Ni, CoSi can be used₂Or NiSi forms conductive layer 131 and contact region 152. The temperature of the RTA in the case of forming a Co or NiPt film only needs to be set appropriately.

Subsequently, as shown in fig. 6, a planarization film 200 is formed over the entire surface of the semiconductor substrate 100 to bury the transistors 21.

Specifically, SiO with a film thickness of 100nm to 500nm is formed on a semiconductor substrate 100 using CVD or the like₂After the film, planarization is performed by using a CMP method, thereby forming a planarization film 200.

Note that before the planarization film 200 is formed, a liner layer, which is not illustrated and includes SiN, may be formed on the semiconductor substrate 100 over the entire surface of the semiconductor substrate 100. For example, the liner layer can be formed by forming a SiN film with a film thickness of 10nm to 50nm using plasma CVD. The liner layer may also be formed as a layer that adds compressive stress or tensile stress to the semiconductor substrate 100. By forming the liner layer, in the subsequent process, the planarization film 200 can be etched under the condition that the etching selectivity between the planarization film 200 and the liner layer becomes high. Therefore, etching can be performed with higher controllability.

Subsequently, as shown in fig. 7, after an opening penetrating the planarization film 200 and exposing the active area 150 is formed, the first capacitor electrode 111 is formed within the opening.

Specifically, an opening is formed in the planarization film 200 on the other of the source or drain region 151 by anisotropic etching using a resist patterned by photolithography as a mask. The opening may be formed, for example, to have a width of 60nm and a depth of 200 nm. At this time, if the aspect ratio of the opening is about 20, etching for forming the opening and opening filling by film formation performed subsequently can be performed without any problem. The anisotropic etching may be performed, for example, by using a fluorocarbon-based gas. Further, by using the above-described liner layer, etching can be stopped with good controllability.

Next, using sputtering based on ALD, CVD, or IMP, a TiN film having a film thickness of 5nm to 20nm is formed on the source or drain region 151 along the inner shape of the opening formed in the planarization film 200. Note that TaN, Ru, RuO may be used₂And the like as a material for forming the first capacitor electrode 111 instead of TiN. Thereafter, after applying a resist on the formed first capacitor electrode 111, by performing etch back under a condition that the resist and the first capacitor electrode 111 become almost equal in selectivity, the first capacitor electrode 111 is recessed from the opening surface of the opening. Therefore, it is possible to recess the shoulder portion of the first capacitor electrode 111 and form a concave portion while leaving the first capacitor electrode 111 on the bottom and side surfaces of the opening.

Next, as shown in fig. 8, the capacitor 11 is formed in the opening by forming a ferroelectric film 113 on the first capacitor electrode 111 and further forming a second capacitor electrode 115 on the ferroelectric film 113.

Specifically, hafnium oxide (HfO) as a high dielectric material having a film thickness of 3 to 10nm is formed on the first capacitor electrode 111 using CVD or ALD along the inner shape of the opening provided in the planarization film 200_x) Thereby forming the ferroelectric film 113. Note that hafnium oxide (HfO) will be a high dielectric material by being subjected to annealing treatment in a subsequent process_x) Is converted into a ferroelectric material.

Note that, for example, zirconium oxide (ZrO) may also be used_x) Or hafnium zirconium oxide (HfZrO)_x) Such as a high dielectric material, instead of hafnium oxide. Further, these types of high dielectric materials can be doped with lanthanum (La), silicon (Si), gadolinium (Gd), or the likeIs converted into a ferroelectric material. In addition, a perovskite ferroelectric material such as piezoelectric lead zirconate titanate (PZT) or Strontium Bismuth Tantalate (SBT) may also be used as the ferroelectric film 113.

Thereafter, a TiN film having a film thickness of 5nm to 20nm is formed on the ferroelectric film 113 by using CVD, ALD, sputtering, or the like to fill the opening formed in the planarization film 200, thereby forming the second capacitor electrode 115. Note that TaN, Ru or RuO₂May also be used as a material for forming the second capacitor electrode 115. Subsequently, a process for forming HfO included in the ferroelectric film 113 is performed_xA crystallization anneal to convert to ferroelectric material. Note that for the use of HfO_xThe crystallization annealing for conversion into the ferroelectric material may be performed in this process, or may be performed in another process (for example, after CMP described later). For example, the conditions of the crystallization annealing may be arbitrarily changed without departing from the range of 400 ℃ to 700 ℃ and the heat-resistant range of another configuration such as the transistor 21 and NiSi. Thereafter, the ferroelectric film 113 and the second capacitor electrode 115 excessively formed on the planarization film 200 are removed by performing CMP or full-surface etch back. Thus, the capacitor 11 is formed.

Next, as shown in fig. 9, after forming the contact 210 electrically connected to the other of the source or drain region 151, an interlayer insulating film 300 is formed over the entire surface of the semiconductor substrate 100, and a first wiring layer 311 and a second wiring layer 312 are formed.

Specifically, by etching the planarization film 200, an opening is formed on the other of the source or drain region 151. Subsequently, after Ti and TiN films are formed in the opening in the planarization film 200 using CVD or the like and a W film is further formed, a contact 210 is formed on the other of the source or drain region 151 by performing planarization using a CMP method. Note that Ti and TiN films may be formed using a sputtering method using Ion Metal Plasma (IMP) or the like. In addition, planarization may be performed using a full-surface etch-back instead of the CMP method. Note that the contact 210 may be formed simultaneously with the contact of a transistor provided in a logic region or the like other than the region where the semiconductor memory device 10 is formed.

Thereafter, atForming a SiO film with a thickness of 100nm to 500nm by CVD or the like on the entire surface of the planarization film 200₂After the film is formed, planarization is performed by using a CMP method, thereby forming the interlayer insulating film 300. Subsequently, after an opening for electrical connection with the second capacitor electrode 115 or the contact 210 is formed by etching the interlayer insulating film 300, the first wiring layer 311 and the second wiring layer 312 are formed using Cu or the like as a wiring material by using a damascene structure or a dual damascene structure. Note that the first wiring layer 311 and the second wiring layer 312 may be formed of Al or the like. The first wiring layer 311 functions as a source line SL by extending in the second direction on the second capacitor electrode 115. Further, the second wiring layer 312 functions as a bit line BL by extending in the second direction on the contact 210.

According to the above-described procedure, the semiconductor memory device 10 according to the present embodiment can be formed.

(3.2. second production method)

Subsequently, a second manufacturing method of the semiconductor memory device 10 according to the present embodiment will be described with reference to fig. 10 to 13. Fig. 10 to 13 show plan and sectional views describing respective processes of a second manufacturing method of the semiconductor memory device 10.

Note that, also in fig. 10 to 13, similarly to fig. 2, illustration of layers formed over the entire surface of the semiconductor substrate 100 is omitted. Further, the sectional views show respective sections obtained by taking the plan views along the AA line, the BB line, and the CC line.

First, through a process similar to that described with reference to fig. 3 to 6, components up to the planarization film 200 are formed.

Subsequently, as shown in fig. 10, a contact 210 electrically connected to the other of the source or drain regions 151 is formed.

Specifically, by etching the planarization film 200, an opening is formed on the other of the source or drain region 151. Subsequently, after Ti and TiN films are formed in the opening in the planarization film 200 using CVD or the like and a W film is further formed, a contact 210 is formed on the other of the source or drain region 151 by performing planarization using a CMP method. Note that Ti and TiN films may be formed using a sputtering method using Ion Metal Plasma (IMP) or the like. In addition, planarization may be performed using a full-surface etch-back instead of the CMP method. Note that the contact 210 may be formed simultaneously with the contact of the transistor provided in the logic region other than the memory region.

Next, as shown in fig. 11, after forming the interlayer insulating film 300 over the entire surface of the semiconductor substrate 100, an opening that penetrates the planarization film 200 and the interlayer insulating film 300 and exposes the active region 150 is formed, and the first capacitor electrode 111 is formed within the opening.

Specifically, SiO with a film thickness of 100nm to 500nm is formed over the entire surface of the planarization film 200 using CVD or the like₂After the film formation, planarization is performed by using a CMP method, and the interlayer insulating film 300 is formed. Next, an opening is formed in the planarization film 200 and the interlayer insulating film 300 on the active region 150 corresponding to the other of the source or drain region 151 by anisotropic etching using a resist patterned by photolithography as a mask. For example, the opening may be formed to have a width of 60nm and a depth of 200 nm. At this time, if the aspect ratio of the opening is about 20, etching for forming the opening and opening filling by film formation performed subsequently can be performed without any problem. The anisotropic etching may be performed, for example, by using a fluorocarbon-based gas. Further, by using the above-described liner layer, etching can be stopped with good controllability.

Next, a TiN film having a film thickness of 5nm to 20nm is formed on the source or drain region 151 along the inner shape of the opening formed in the planarization film 200 and the interlayer insulating film 300 using sputtering based on ALD, CVD, or IMP. Note that TaN, Ru, RuO may be used₂And the like as a material for forming the first capacitor electrode 111 instead of TiN. Thereafter, after applying a resist on the formed first capacitor electrode 111, by performing etch back under a condition that the resist and the first capacitor electrode 111 become almost equal in selectivity, the first capacitor electrode 111 is recessed from the opening surface of the opening. Therefore, the shoulder portion of the first capacitor electrode 111 can be made concave and a concave portion can be formed while the same timeThe first capacitor electrode 111 on the bottom and the side of the opening remains.

Subsequently, as shown in fig. 12, the capacitor 11 is formed within the opening by forming the ferroelectric film 113 on the first capacitor electrode 111 and further forming the second capacitor electrode 115 on the ferroelectric film 113.

Specifically, hafnium oxide (HfO) as a high dielectric material having a film thickness of 3 to 10nm is formed on the first capacitor electrode 111 using CVD or ALD along the inner shape of the opening provided in the planarization film 200_x) Thereby forming the ferroelectric film 113. Note that hafnium oxide (HfO) will be a high dielectric material by being subjected to annealing treatment in a subsequent process_x) Is converted into a ferroelectric material.

Note that, for example, zirconium oxide (ZrO) may also be used_x) Or hafnium zirconium oxide (HfZrO)_x) Such as a high dielectric material, instead of hafnium oxide. Further, these types of high dielectric materials can be converted into ferroelectric materials by doping them with lanthanum (La), silicon (Si), gadolinium (Gd), or the like. In addition, a perovskite ferroelectric material such as piezoelectric lead zirconate titanate (PZT) or Strontium Bismuth Tantalate (SBT) may also be used as the ferroelectric film 113.

Thereafter, a TiN film having a film thickness of 5nm to 20nm is formed on the ferroelectric film 113 by using CVD, ALD, sputtering, or the like to fill the opening formed in the planarization film 200, thereby forming the second capacitor electrode 115. Note that TaN, Ru or RuO₂May also be used as a material for forming the second capacitor electrode 115. Subsequently, a process for forming HfO included in the ferroelectric film 113 is performed_xA crystallization anneal to convert to ferroelectric material. Note that for the use of HfO_xThe crystallization annealing for conversion into the ferroelectric material may be performed in this process, or may be performed in another process (for example, after CMP described later). For example, the conditions of the crystallization annealing may be arbitrarily changed without departing from the range of 400 ℃ to 700 ℃ and the heat-resistant range of another configuration such as the transistor 21 and NiSi. Thereafter, the ferroelectric film 113 and the second capacitor electrode 115 excessively formed on the planarization film 200 are removed by performing CMP or full-surface etch back. Thus, electricity is formedA container 11.

Thereafter, as illustrated in fig. 13, a second wiring layer 312 is formed.

Specifically, after an opening for electrical connection with the contact 210 is formed by etching the interlayer insulating film 300, the second wiring layer 312 is formed by using Cu or the like as a wiring material by using a damascene structure or a dual damascene structure. Note that the second wiring layer 312 may be formed of Al or the like. The second wiring layer 312 functions as a bit line BL by extending in the second direction on the contact 210.

Note that the first wiring layer 311 (not shown) may be formed in the interlayer insulating film on the second wiring layer 312 by repeating formation of an interlayer insulating film, formation of a contact penetrating the formed interlayer insulating film, formation of an interlayer insulating film filling the formed contact, and formation of a wiring layer having a damascene structure and connected to the contact.

According to the second manufacturing method, since the formation depth of the capacitor 11 can be increased by an amount corresponding to the thickness of the interlayer insulating film 300 as compared with the first manufacturing method, the capacitance of the capacitor 11 can be increased. Therefore, the semiconductor memory device 10 manufactured using the second manufacturing method can store information more stably.

(3.3. third production method)

Next, a third manufacturing method of the semiconductor memory device 10 according to the present embodiment will be described with reference to fig. 14 to 18. Fig. 14 to 18 show plan and sectional views describing respective processes of a third manufacturing method of the semiconductor memory device 10.

Note that, also in fig. 14 to 18, similarly to fig. 2, illustration of layers formed over the entire surface of the semiconductor substrate 100 is omitted. Further, the sectional views show respective sections obtained by taking the plan views along the AA line, the BB line, and the CC line.

First, components up to the gate electrode 130 are formed through a process similar to that described with reference to fig. 3 to 4.

Subsequently, as shown in fig. 14, sidewall insulating films 132 are formed on both side surfaces of the gate electrode 130, and a source or drain region 151 is formed in the active region 150 of the semiconductor substrate 100. However, in fig. 14, by further forming a silicide block layer 155 on a partial region of the semiconductor substrate 100, a region where the contact region 152 is not formed is provided in the semiconductor substrate 100.

Specifically, first, by using a voltage of 5keV to 20keV and 5 to 20 × 10¹³/cm²Is performed to both sides of the gate electrode 130, thereby forming LDD regions. Note that phosphorus (P) may also be used as the second conductivity type impurity.

Subsequently, SiO with a film thickness of 10nm to 30nm is formed using plasma CVD₂After the film formation, Si with a film thickness of 30nm to 50nm is formed using plasma CVD₃N₄And forming an insulating film for the side wall. Thereafter, by performing anisotropic etching on the insulating film for the side wall, the side wall insulating film 132 is formed on both side faces of the gate electrode 130. At this time, after patterning is performed by photolithography, the insulating film is etched so that only a region where the contact region 152 is formed is opened, and a silicide blocking layer 155 is formed on the semiconductor substrate 100 in a region where the contact region 152 is not formed. For example, the silicide block layer 155 may be formed in a region on the semiconductor substrate 100 other than the active region 150 where the contact 210 will be formed in a subsequent process.

Thereafter, at 20keV to 50keV and at 1 to 2 × 10¹⁵/cm²Performs ion implantation of arsenic (As) As a second conductive type impurity and introduces the second conductive type impurity to both sides of the gate electrode 130. Accordingly, source or drain regions 151 are formed in the active region 150 at both sides of the gate electrode 130. Further, the ion-implanted impurity was activated by performing Rapid Thermal Annealing (RTA) at 1000 ℃ for five seconds. Thus, the transistor 21 is formed. Note that in order to promote activation of the introduced impurity and suppress diffusion of the impurity, a spike RTA may also be used to activate the impurity.

Subsequently, after forming a Ni film with a film thickness of 6nm to 8nm over the entire surface of the semiconductor substrate 100 by sputtering or the like, N on Si by performing RTA at 300 ℃ to 450 ℃ for 10 to 60 secondsi is silicided (NiSi). Because of SiO₂Ni above remains unreacted, so by using H₂SO₄/H₂O₂Unreacted Ni is removed, and a conductive layer 131 including NiSi and a contact region 152 are formed on the gate electrode 130 and in the other of the source or drain regions 151, respectively. Note that by forming a Co or NiPt film instead of Ni, the conductive layer 131 and the contact region 152 may be formed of CoSi₂Or NiSi. The temperature of the RTA in the case of forming a Co or NiPt film only needs to be set appropriately.

At this time, in the region where the silicide block layer 155 is formed, unreacted Ni remains on the silicide block layer 155 serving as an insulating film. Accordingly, in the semiconductor substrate 100 in the region in which the silicide block layer 155 is formed, the silicide contact region 152 is not formed.

Subsequently, as shown in fig. 15, a planarization film 200 is formed over the entire surface of the semiconductor substrate 100 to bury the transistors 21.

Specifically, SiO with a film thickness of 100nm to 500nm is formed on the semiconductor substrate 100 and the silicide blocking layer 155 using CVD or the like₂After the film, the planarization film 200 is formed by performing planarization using a CMP method.

Note that before the planarization film 200 is formed, a liner layer, which is not illustrated and includes SiN, may be formed on the semiconductor substrate 100 over the entire surface of the semiconductor substrate 100. For example, the liner layer can be formed by forming a SiN film with a film thickness of 10nm to 50nm using plasma CVD. The liner layer may also be formed as a layer that adds compressive stress or tensile stress to the semiconductor substrate 100. By forming the liner layer, in the subsequent process, the planarization film 200 can be etched under the condition that the etching selectivity between the planarization film 200 and the liner layer becomes high. Therefore, etching can be performed with higher controllability.

Subsequently, as shown in fig. 16, after an opening penetrating the planarization film 200 and the silicide block layer 155 and reaching the inside of the semiconductor substrate 100 is formed, the first capacitor electrode 111 is formed within the opening.

Specifically, an opening reaching the inside of the semiconductor substrate 100 is formed from the planarization film 200 on the other of the source or drain region 151 by anisotropic etching using a resist patterned by photolithography as a mask. For example, the opening may be formed to have a width of 60nm and a depth of 200 nm. Note that if the aspect ratio of the opening is about 20, etching for forming the opening and opening filling by film formation performed subsequently can be performed without any problem. For example, the anisotropic etching may be performed by using a fluorocarbon-based gas.

Next, a TiN film having a film thickness of 5nm to 20nm is formed on the source or drain region 151 along the inner shape of the formed opening using sputtering based on ALD, CVD, or IMP. Note that TaN, Ru, RuO may be used₂And the like as a material for forming the first capacitor electrode 111 instead of TiN. Thereafter, after applying a resist on the formed first capacitor electrode 111, by performing etch back under a condition that the resist and the first capacitor electrode 111 become almost equal in selectivity, the first capacitor electrode 111 is recessed from the opening surface of the opening. Therefore, it is possible to recess the shoulder portion of the first capacitor electrode 111 and form a concave portion while leaving the first capacitor electrode 111 on the bottom and side surfaces of the opening.

At this time, an opening is provided to penetrate through the active region 150 including the planarization film 200 and the silicide block layer 155 up to within the semiconductor substrate 100. Accordingly, the first capacitor electrode 111 is electrically connected to the source or drain region 151 on the side and bottom surfaces of the opening. In the third manufacturing method, in the region where the capacitor 11 is formed, since the formation of the contact region 152 is prevented by the silicide block layer 155, it is possible to prevent an unexpected leak or short circuit from being generated between the first capacitor electrode 111 and the source or drain region 151.

Next, as shown in fig. 17, the capacitor 11 is formed in the opening by forming a ferroelectric film 113 on the first capacitor electrode 111 and further forming a second capacitor electrode 115 on the ferroelectric film 113.

Specifically, a film thickness of 3nm to ALD is formed on the first capacitor electrode 111 using CVD or ALD along the inner shape of the opening provided in the planarization film 20010nm hafnium oxide (HfO) as a high dielectric material_x) Thereby forming the ferroelectric film 113. Note that hafnium oxide (HfO) will be a high dielectric material by being subjected to annealing treatment in a subsequent process_x) Is converted into a ferroelectric material.

Note that, for example, zirconium oxide (ZrO) may also be used_x) Or hafnium zirconium oxide (HfZrO)_x) Such as a high dielectric material, instead of hafnium oxide. Further, these types of high dielectric materials can be converted into ferroelectric materials by doping them with lanthanum (La), silicon (Si), gadolinium (Gd), or the like. In addition, a perovskite ferroelectric material such as piezoelectric lead zirconate titanate (PZT) or Strontium Bismuth Tantalate (SBT) may also be used as the ferroelectric film 113.

Thereafter, the second capacitor electrode 115 is formed by forming a TiN film with a film thickness of 5nm to 20nm on the ferroelectric film 113 using CVD, ALD, sputtering, or the like to fill the opening formed in the planarization film 200. Note that TaN, Ru or RuO₂May also be used as a material for forming the second capacitor electrode 115. Subsequently, a process for forming HfO included in the ferroelectric film 113 is performed_xA crystallization anneal to convert to ferroelectric material. Note that for the use of HfO_xThe crystallization annealing for conversion into the ferroelectric material may be performed in this process, or may be performed in another process (for example, after CMP described later). For example, the conditions of the crystallization annealing may be arbitrarily changed without departing from the range of 400 ℃ to 700 ℃ and the heat-resistant range of another configuration such as the transistor 21 and NiSi. Thereafter, the ferroelectric film 113 and the second capacitor electrode 115 excessively formed on the planarization film 200 are removed by performing CMP or full-surface etch back. Thus, the capacitor 11 is formed.

Next, as shown in fig. 18, after forming the contact 210 electrically connected to the other of the source or drain region 151, an interlayer insulating film 300 is formed over the entire surface of the semiconductor substrate 100, and a first wiring layer 311 and a second wiring layer 312 are formed.

Specifically, by etching the planarization film 200, an opening is formed on the other of the source or drain region 151. Subsequently, after Ti and TiN films are formed in the opening in the planarization film 200 using CVD or the like and a W film is further formed, a contact 210 is formed on the other of the source or drain region 151 by performing planarization using a CMP method. Note that Ti and TiN films may be formed using a sputtering method using Ion Metal Plasma (IMP) or the like. In addition, planarization may be performed using a full-surface etch-back instead of the CMP method. Note that the contact 210 may be formed simultaneously with the contact of a transistor provided in a logic region or the like other than the region where the semiconductor memory device 10 is formed.

Thereafter, SiO with a film thickness of 100nm to 500nm is formed on the entire surface of the planarization film 200 using CVD or the like₂After the film formation, planarization is performed by using a CMP method, and the interlayer insulating film 300 is formed. Subsequently, after an opening for electrical connection with the second capacitor electrode 115 or the contact 210 is formed by etching the interlayer insulating film 300, the first wiring layer 311 and the second wiring layer 312 are formed using Cu or the like as a wiring material by using a damascene structure or a dual damascene structure. Note that the first wiring layer 311 and the second wiring layer 312 may be formed of Al or the like. The first wiring layer 311 functions as a source line SL by extending in the second direction on the second capacitor electrode 115. Further, the second wiring layer 312 functions as a bit line BL by extending in the second direction on the contact 210.

According to the third manufacturing method, since the formation depth of the capacitor 11 can be increased by the depth of digging into the semiconductor substrate 100 as compared with the first manufacturing method, the capacitance of the capacitor 11 can be increased. Therefore, the semiconductor memory device 10 manufactured using the third manufacturing method can store information more stably.

Note that the structure manufactured using the third manufacturing method may also be combined with the structure manufactured using the second manufacturing method. In this case, the capacitor 11 is disposed over the interlayer insulating film 300, the planarization film 200, and the semiconductor substrate 100. With this arrangement, since the formation depth of the capacitor 11 can be further increased, the semiconductor memory device 10 can increase the capacitance of the capacitor 11, and can store information more stably.

<4. working examples >

Subsequently, a writing operation and a reading operation of the above-described semiconductor memory device 10 will be described with reference to fig. 19. Fig. 19 is a sectional view schematically showing a section taken along the active region 150 of the semiconductor memory device 10.

As shown in fig. 19, the semiconductor memory device 10 includes a transistor 21 and a capacitor 11 connected to one of source or drain regions 151 of the transistor 21. The semiconductor memory device 10 is driven by a word line WL connected to the gate electrode 130 of the transistor 21, a bit line BL connected to the other of the source or drain region 151 of the transistor 21 via a contact 210, and a source line SL connected to the capacitor 11.

Table 1 given below is a table showing an example of voltages (unit: V) to be applied to each of SWL, SBL, SSL, Well, UWL, UBL, and USL shown in fig. 19 in the write operation and the read operation of the semiconductor memory apparatus 10.

Note that in table 1, Vth represents a threshold voltage for bringing the channel of the transistor 21 into an on state, and Vw represents a voltage at which the polarization state of the capacitor 11 can be reversed. Further, SWL, SBL, and SSL respectively denote a word line WL, a bit line BL, and a source line SL of a selected memory cell, and UWL, UBL, and USL respectively denote a word line WL, a bit line BL, and a source line SL of an unselected memory cell. Well denotes the potential of the active region 150 of the semiconductor substrate 100.

[ Table 1]

(Table 1)

	SWL	SBL	SSL	Well	UWL	UBL	USL
								Writing "1"	Vw+Vth	Vw	0	0	0	0	0
Write a "0"	Vw+Vth	0	Vw	0	0	0	0
								Read-out	Vw+Vth	Vw	0	0	0	0	0

For example, in the case of writing information indicating "1" into the semiconductor memory device 10, Vw + Vth is applied to the word line WL connected to the selected semiconductor memory device 10, Vw is applied to the bit line BL, the source line SL is set to 0V, and the active region 150 of the semiconductor substrate 100 is set to 0V. In addition, the word line WL, the bit line BL, and the source line SL of the unselected semiconductor memory device 10 are all set to 0V.

With this arrangement, since the potential of the other of the source or drain region 151 of the transistor 21 becomes Vw by applying Vw to the bit line BL, the potential of the first capacitor electrode 111 of the capacitor 11 becomes Vw. On the other hand, since the potential of the source line SL is 0V, the potential of the second capacitor electrode 115 becomes 0V. Therefore, since the potential difference of Vw, which becomes the higher potential on the first capacitor electrode 111 side, is applied to the ferroelectric film 113 of the capacitor 11, the polarization state of the ferroelectric film 113 is controlled. Through the above operation, for example, information indicating "1" is written into the semiconductor memory device 10.

At this time, the potential of the source or drain region 151 of the transistor 21 becomes Vw, but in the unselected transistor 21, since the word line WL and the gate electrode 130 are set to 0V in the adjacent unselected semiconductor memory device 10, no potential is applied to the first capacitor electrode 111. Therefore, according to the present embodiment, it is possible to prevent information stored in unselected semiconductor memory devices 10 from being written when information is written to a selected semiconductor memory device 10.

Further, in the case of writing information indicating "0" into the semiconductor memory device 10, Vw + Vth is applied to the word line WL connected to the selected semiconductor memory device 10, and Vw is applied to the source line SL. The bit line BL is set to 0V, and the active region 150 of the semiconductor substrate 100 is set to 0V. In addition, the word line WL, the bit line BL, and the source line SL of the unselected semiconductor memory device 10 are all set to 0V.

With this arrangement, since the bit line BL is set to 0V, the potential of the other of the source or drain region 151 of the transistor 21 becomes 0V, and the potential of the first capacitor electrode 111 of the capacitor 11 becomes 0V. On the other hand, since the potential of the source line SL is Vw, the potential of the second capacitor electrode 115 becomes Vw. Therefore, since the potential difference of Vw, which becomes the higher potential on the second capacitor electrode 115 side, is applied to the ferroelectric film 113 of the capacitor 11, the polarization state of the ferroelectric film 113 is controlled. Through the above operation, for example, information indicating "0" is written into the semiconductor memory device 10.

At this time, the potential of the source line SL becomes Vw, but in the unselected transistor 21, since the word line WL and the gate electrode 130 are set to 0V, in the adjacent unselected semiconductor memory device 10, the potential is not applied to the first capacitor electrode 111. Therefore, according to the present embodiment, it is possible to prevent information stored in unselected semiconductor memory devices 10 from being written when information is written in selected semiconductor memory devices 10.

Note that readout of information from the semiconductor memory device 10 is performed using a displacement current which is generated when "0" or "1" is written into the semiconductor memory device 10 and which changes depending on whether the information stored before writing indicates "0" or "1".

For example, in table 1, voltages to be applied to each of SWL, SBL, SSL, Well, UWL, UBL, and USL in the case where information is read out from the semiconductor memory apparatus 10 by writing information indicating "1" are shown. In this case, if the information stored in the semiconductor memory device 10 indicates "1", the change in the displacement current amount is small. On the other hand, if the information stored in the semiconductor memory device 10 indicates "0", the amount of displacement current is changed greatly. Accordingly, the semiconductor storage device 10 can determine which of "0" or "1" the stored information indicates.

However, in the case of reading out information from the semiconductor memory device 10 by such a reading operation, the information stored in the semiconductor memory device 10 is rewritten with "0" or "1" written at the time of reading out. In other words, information readout from the semiconductor memory device 10 becomes destructive readout. Therefore, in the semiconductor memory apparatus 10, after the read operation, the rewrite operation to restore the information destroyed by the read operation is performed.

<5. application example >

Subsequently, an electronic apparatus according to an embodiment of the present disclosure will be described. The electronic device according to the embodiment of the present disclosure corresponds to various types of electronic devices equipped with a circuit including the above-described semiconductor storage device 10. An example of such an electronic apparatus according to the present embodiment will be described with reference to fig. 20A to 20C. Fig. 20A to 20C are external view diagrams each showing an example of an electronic apparatus according to the present embodiment.

For example, the electronic apparatus according to the present embodiment may be an electronic apparatus such as a smartphone. Specifically, as shown in fig. 20A, the smartphone 900 includes a display unit 901 that displays various types of information, and an operation unit 903 that includes buttons and the like for receiving operation inputs from the user. Here, the circuit mounted on the smart phone 900 may be provided with the semiconductor memory device 10 described above.

For example, the electronic apparatus according to the present embodiment may be an electronic apparatus such as a digital camera. Specifically, as shown in fig. 20B and 20C, the digital camera 910 includes a main body portion (camera body) 911, an interchangeable lens unit 913, a grip portion 915 to be gripped by a user during image capturing, a monitor unit 917 that displays various types of information, and an Electronic Viewfinder (EVF)919 that displays a live view image viewed by the user during image capturing. Note that fig. 20B is a diagram showing the appearance of the digital camera 910 viewed from the front (i.e., the object side), and fig. 20C is a diagram showing the appearance of the digital camera 910 viewed from the back (i.e., the photographer side). Here, the circuit mounted on the digital camera 910 may be provided with the above-described semiconductor storage device 10.

Note that the electronic apparatus according to the present embodiment is not limited to the above-described example. The electronic device according to the present embodiment may be any field of electronic devices. Examples of such electronic devices include glasses-type wearable devices, Head Mounted Displays (HMDs), television devices, electronic books, Personal Digital Assistants (PDAs), laptop computers, cameras, gaming devices, and so forth.

Heretofore, the preferred embodiments of the present disclosure have been described in detail with reference to the drawings, but the technical scope of the present disclosure is not limited to this example. It should be appreciated that a person having ordinary knowledge in the technical field of the present disclosure can conceive various change examples and modification examples within the scope of the technical idea described in the appended claims, and these change examples and modification examples are interpreted as naturally falling within the technical scope of the present disclosure.

Further, the effects described in the present specification are provided only as illustrative or exemplary effects, and are not limited to these effects. That is, the technology according to the present disclosure may bring another effect, which is clear to those skilled in the art, from the description in the present specification in addition to or instead of the above effect.

Note that the following configuration also falls within the technical scope of the present disclosure.

(1) A semiconductor memory device, comprising:

a field effect transistor disposed in an active region of a semiconductor substrate;

a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field effect transistor;

a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor; and

a bit line electrically connected to the other of the source or the drain of the field effect transistor,

wherein a gate electrode of the field effect transistor extends in a first direction across the active region, and the source line and the bit line extend in a second direction orthogonal to the first direction.

(2) The semiconductor storage device according to the above (1), wherein the active region is provided in a stripe shape extending in a third direction obliquely crossing both the first direction and the second direction.

(3) The semiconductor memory device according to the above (2), wherein the active regions are separated from each other by an element separation layer provided on the semiconductor substrate.

(4) The semiconductor storage device according to any one of the above (1) to (3), wherein the gate is electrically connected to a word line.

(5) The semiconductor storage device according to any one of the above (1) to (4),

wherein a planarization film burying the field effect transistor is provided on the semiconductor substrate, an

The ferroelectric capacitor is disposed inside an opening provided in the planarization film.

(6) The semiconductor memory device according to the above (5), wherein the ferroelectric capacitor includes the first capacitor electrode provided along a bottom surface and a side surface of the opening, the ferroelectric film provided on the first capacitor electrode along a shape of the opening, and the second capacitor electrode provided on the ferroelectric film to fill the opening.

(7) The semiconductor storage device according to the above (6), wherein the first capacitor electrode is provided so as to be recessed from an opening surface of the opening in the planarization film.

(8) The semiconductor storage device according to any one of the above (5) to (7), wherein the ferroelectric capacitor is provided on the active region.

(9) The semiconductor storage device according to the above (8), wherein the ferroelectric capacitor is provided on the active region corresponding to one of a source or a drain of the field effect transistor.

(10) The semiconductor memory device according to any one of the above (5) to (9), wherein the source line and the bit line are provided in the same layer.

(11) The semiconductor storage device according to any one of the above (5) to (9),

wherein the bit line is provided inside an interlayer insulating film provided on the planarization film, an

The opening is provided so as to penetrate from the interlayer insulating film up to the surface of the semiconductor substrate.

(12) The semiconductor storage device according to any one of the above (5) to (11), wherein the opening is provided so as to penetrate from the planarization film up to an inside of the semiconductor substrate.

(13) A manufacturing method of a semiconductor memory device, the manufacturing method comprising:

forming a field effect transistor in an active region of a semiconductor substrate such that a gate electrode of the field effect transistor extends in a first direction across the active region;

forming a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field effect transistor; and

forming a source line electrically connected with the second capacitor electrode of the ferroelectric capacitor and a bit line electrically connected to the other of the source or the drain of the field effect transistor such that the source line and the bit line extend in a second direction orthogonal to the first direction.

(14) An electronic device, comprising:

a semiconductor memory device comprising

A field effect transistor disposed in an active region of a semiconductor substrate,

a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field effect transistor,

a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor, an

A bit line electrically connected to the other of the source or the drain of the field effect transistor,

wherein, in the semiconductor memory apparatus, a gate electrode of the field effect transistor extends in a first direction crossing the active region, and the source line and the bit line extend in a second direction orthogonal to the first direction.

List of reference numerals

10 semiconductor memory device

11 capacitor

21 transistor

100 semiconductor substrate

105 element separation layer

111 first capacitor electrode

113 ferroelectric film

115 second capacitor electrode

130 gate electrode

131 conductive layer

132 side wall insulating film

140 gate insulating film

150 active region

151 source or drain region

152 contact region

200 planarizing film

210 contact

300 interlayer insulating film

311 first wiring layer

312 second routing layer