Planar transistor with wrap-around gate and wrap-around source and drain contacts
阅读说明：本技术 具有环绕式栅极以及环绕式源极和漏极触点的平面晶体管 (Planar transistor with wrap-around gate and wrap-around source and drain contacts ) 是由 N.尼迪 R.拉马斯瓦米 邓汉威 M.拉多萨夫尔杰维奇 S.达斯古普塔 J.C.罗德 P 于 2020-02-03 设计创作，主要内容包括：本发明的主题是“具有环绕式栅极以及环绕式源极和漏极触点的平面晶体管”。本文中所公开的是IC结构、封装和装置,所述IC结构、封装和装置包含具有环绕式栅极和/或一个或多个环绕式源极/漏极(S/D)触点的平面III-N晶体管。一种示例IC结构包含支承结构(例如衬底)和平面III-N晶体管。晶体管包含：在支承结构之上提供的III-N半导体材料和极化材料的沟道堆叠；在沟道堆叠中提供的一对S/D区；以及在S/D区域之间的沟道堆叠的一部分之上提供的栅极介电材料和栅极电极材料的栅极堆叠,其中栅极堆叠至少部分地环绕沟道堆叠的上部。(The subject of the invention is a "planar transistor with a surrounding gate and surrounding source and drain contacts". Disclosed herein are IC structures, packages, and devices including planar III-N transistors with wrap-around gates and/or one or more wrap-around source/drain (S/D) contacts. An example IC structure includes a support structure (e.g., a substrate) and a planar III-N transistor. The transistor includes: a channel stack of III-N semiconductor material and polarization material provided over the support structure; a pair of S/D regions provided in the channel stack; and a gate stack of gate dielectric material and gate electrode material provided over a portion of the channel stack between the S/D regions, wherein the gate stack at least partially surrounds an upper portion of the channel stack.)
1. An Integrated Circuit (IC) structure, comprising:
a support structure; and
a III-N transistor, the III-N transistor comprising:
a channel stack over the support structure, the channel stack comprising a III-N semiconductor material and a polarized material over the III-N semiconductor material,
first and second source/drain (S/D) regions in the channel stack, and
a gate stack over a portion of the channel stack between the first and second S/D regions,
wherein the gate stack at least partially surrounds an upper portion of the channel stack.
2. The IC structure of claim 1, wherein the gate stack surrounding the upper portion of the channel stack includes the gate stack extending to a depth of between 2 nanometers and 100 nanometers over a top surface of the channel stack and along at least one sidewall of the channel stack.
3. The IC structure of claim 2, wherein the gate stack includes a gate dielectric material surrounding the upper portion of the channel stack and a gate electrode material surrounding the gate dielectric material.
4. The IC structure of claim 3, wherein a portion of the gate dielectric material is in contact with the III-N semiconductor material at the at least one sidewall of the channel stack.
5. The IC structure of any of claims 1-4, wherein a dimension of the channel stack in a direction perpendicular to a gate length of the III-N transistor is between 20 nanometers and 1 millimeter.
6. The IC structure of any of claims 1-4, wherein the polarization material comprises a material to induce tensile stress in the III-N semiconductor material.
7. The IC structure of any of claims 1-4, wherein a thickness of the polarization material between the gate stack and the III-N semiconductor material is between 0.1 nanometers and 50 nanometers.
8. The IC structure of any of claims 1-4, further comprising a buffer material between the III-N semiconductor material and the support structure, wherein a bandgap of the buffer material is greater than a bandgap of the III-N semiconductor material.
9. The IC structure of any of claims 1-4, further comprising S/D contact material at least partially surrounding an upper portion of the first S/D region.
10. The IC structure of claim 9, wherein the S/D contact material surrounding the upper portion of the first S/D region comprises the S/D contact material extending over a top surface of the first S/D region and along at least one sidewall of the channel stack to a depth between 2 nanometers and 150 nanometers.
11. The IC structure of claim 10, wherein a portion of the S/D contact material is in contact with the at least one sidewall of the first S/D region.
12. The IC structure of any of claims 1-4, wherein the III-N transistor is part of a radio frequency circuit or part of a power supply circuit.
13. An Integrated Circuit (IC) package, comprising:
an IC die comprising a planar transistor, the planar transistor comprising:
one or more channel stacks of semiconductor material, the channel stacks having a top surface and a pair of opposing sidewalls, wherein a distance between the pair of opposing sidewalls is greater than 100 nanometers, an
A gate stack, wherein the gate stack comprises:
a first portion in contact with a portion of the top surface of the channel stack, an
A second portion in contact with a portion of at least one sidewall of the pair of opposing sidewalls of the channel stack; and
a further IC component coupled to the IC die.
14. The IC package of claim 13, wherein the second portion of the gate stack is in contact with at least one of the one or more semiconductor materials of the channel stack at the at least one of the pair of opposing sidewalls of the channel stack.
15. The IC package of claim 13, wherein the first portion and the second portion are continuous.
16. The IC package of any of claims 13-15, wherein the further IC component comprises one of a package substrate, an interposer, or a further IC die.
17. The IC package of any of claims 13-15, wherein the IC package is included in one of a switch, a power amplifier, a low noise amplifier, a filter bank, a duplexer, an upconverter, a downconverter, or a logic circuit of an RF communication device.
18. A method of fabricating an Integrated Circuit (IC) structure, the method comprising:
forming a channel stack over a support structure, the channel stack comprising a III-N semiconductor material and a polarization material over the III-N semiconductor material;
forming a pair of source/drain (S/D) regions in the channel stack; and
providing a gate stack over a portion of the channel stack between the pair of S/D regions,
wherein the gate stack at least partially surrounds an upper portion of the channel stack.
19. The method of claim 18, wherein the gate stack surrounding the upper portion of the channel stack includes the gate stack extending to a depth of between 2 nanometers and 100 nanometers over a top surface of the channel stack and along at least one sidewall of the channel stack.
20. The method of claim 18, wherein the channel stack includes a top surface and a pair of opposing sidewalls, and wherein providing the gate stack includes:
forming a recess in a dielectric material surrounding the pair of opposing sidewalls of the channel stack to expose a portion of at least one of the pair of opposing sidewalls of the channel stack, wherein a height of the exposed portion of the at least one of the pair of opposing sidewalls of the channel stack is between 2 nanometers and 100 nanometers along the at least one sidewall of the channel stack,
depositing a gate dielectric material of the gate stack over the top surface of the channel stack and over the exposed portion of the at least one of the pair of opposing sidewalls of the channel stack, an
Depositing a gate electrode material of the gate stack over the gate dielectric material.
Background
Solid state devices that can be used in high frequency and/or high voltage applications are of great importance in modern semiconductor technology. For example, Radio Frequency (RF) integrated circuits (RFICs) and Power Management Integrated Circuits (PMICs) may be key functional blocks in a system-on-chip (SoC) implementation. Such SoC implementations may be found in mobile computing platforms (such as smartphones, tablets, laptops, netbooks, etc.). In such implementations, RFIC, as well as PMIC and RFIC, are important factors for power efficiency and form factor (formfactor), and may be as important or even more important than logic and memory circuits.
Due in part to their large bandgaps and high mobility, III-N material based transistors, such as gallium nitride (GaN) -based transistors, may be particularly advantageous for high frequency and high voltage applications.
Drawings
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. In the drawings of the accompanying drawings, embodiments are shown by way of example and not limitation.
Fig. 1A-1C provide various cross-sectional side views illustrating an Integrated Circuit (IC) structure including a planar III-N transistor with a wraparound gate and wraparound source/drain (S/D) contacts, according to some embodiments of the present disclosure.
Fig. 2A-2C provide various cross-sectional side views illustrating an IC structure including a planar III-N transistor with a wraparound gate, wraparound S/D contact, and a buffer layer, in accordance with some embodiments of the present disclosure.
Fig. 3 is a flow diagram of an example method of fabricating an IC structure including planar III-N transistors with wrap-around gates and/or wrap-around S/D contacts according to various embodiments of the present disclosure.
Fig. 4A-4E are various views illustrating different example stages in fabricating an IC structure using the method of fig. 3, according to some embodiments of the present disclosure.
Fig. 5A-5B are top views of a die and a wafer containing one or more IC structures having one or more planar III-N transistors with wrap-around gates and/or one or more wrap-around S/D contacts according to any of the embodiments of the present disclosure.
Fig. 6 is a cross-sectional side view of an IC package that may include one or more IC structures having one or more planar III-N transistors having a wraparound gate and/or one or more wraparound S/D contacts in accordance with any of the embodiments of the present disclosure.
Fig. 7 is a cross-sectional side view of an IC device assembly that may include one or more IC structures having one or more planar III-N transistors having a wraparound gate and/or one or more wraparound S/D contacts in accordance with any of the embodiments of the present disclosure.
Fig. 8 is a block diagram of an example computing device that may include one or more IC structures having one or more planar III-N transistors with a wraparound gate and/or one or more wraparound S/D contacts in accordance with any of the embodiments of the present disclosure.
Fig. 9 is a block diagram of an example RF device that may include one or more IC structures having one or more planar III-N transistors with a wrap-around gate and/or one or more wrap-around S/D contacts in accordance with any of the embodiments of the present disclosure.
Detailed Description
SUMMARY
As mentioned above, transistors based on III-N materials have properties that make them particularly advantageous for certain applications. For example, because GaN has a larger bandgap (about 3.4 eV) than silicon (Si, a bandgap of about 1.1 electron volts (eV)), GaN transistors are expected to withstand a larger electric field (e.g., resulting from applying a large voltage Vdd to the drain) before suffering breakdown compared to Si transistors of similar size. Furthermore, GaN transistors may advantageously employ a 2D electron gas (2 DEG), i.e., a set of electrons, electron gases, e.g., 2D sheet charges, that are free to move in two dimensions but are severely limited in the third dimension, as their transport channels, thereby achieving high mobility without the use of impurity dopants. For example, 2D surface charges may form at an abrupt heterojunction interface formed by depositing (e.g., epitaxially depositing) a charge-inducing film of a material having a more spontaneous and piezoelectric polarization than GaN on GaN (such a film is generally referred to as a "polarizing layer"). Providing a polarization layer on III-N materials, such as GaN, allows for the formation of very high charge densities without intentionally added impurity dopants, which in turn enables high mobility.
Despite these advantages, there are some challenges associated with III-N transistors that prevent their large scale implementation.
One such challenge is the gate control of III-N transistors. To achieve the required performance, the gate length of III-N transistors is greatly scaled (reduced). As a result, Short Channel Effects (SCE) come into play, significantly degrading transistor performance. This problem can be particularly acute for enhancement mode devices that require the gate voltage to be always positive. SCE causes a drain-induced barrier lowering (DIBL), which can cause the threshold voltage of the transistor to become negative at sufficiently high drain bias, resulting in leakage current at zero gate voltage.
Another challenge associated with III-N transistors is the contact resistance between the S/D contacts (i.e., the S/D electrode material) and the S/D regions (e.g., highly doped regions in the channel material of the transistor). Since the parasitic effect is very important for short channel transistors, any improvement in contact resistance is always desirable.
Disclosed herein are IC structures, packages, and device assemblies including planar III-N transistors with wrap-around gates and/or one or more wrap-around S/D contacts. An example IC structure includes a support structure/material (which may be, for example, a substrate, a die, or a chip) and further includes a planar III-N transistor. The III-N transistor includes: a channel stack of III-N semiconductor material and polarization material provided over the support structure; a pair of S/D regions provided in the channel stack; and a gate stack of gate dielectric material and gate electrode material provided over a portion of the channel stack between the S/D regions, wherein the gate stack at least partially surrounds an upper portion of the channel stack. Providing a gate stack at least partially surrounding the channel stack allows for increasing the contact area between the gate stack and the channel region of the channel stack (i.e. the region in the III-N semiconductor material of the channel stack where the conductive channel is formed during operation of the III-N transistor), which may advantageously improve gate control at the edge of the planar III-N transistor. Providing a wraparound gate (i.e., a gate stack that at least partially surrounds an upper portion of a channel stack of a transistor) for a planar transistor may achieve the required performance without resorting to the complex integration schemes associated with non-planar transistors. Furthermore, since the wraparound gate may be similar to a three-dimensional gate used with a non-planar transistor such as a FinFET (fin-based field effect transistor) but on a planar transistor, it may be possible to utilize the entire periphery of the III-N channel stack (which may be shaped as an island) to conduct current and control short channel losses at the edges of the channel stack. Providing a planar transistor with surrounding S/D contact material as one or two contacts to the S/D regions (e.g., S/D contact material at least partially surrounding an upper portion of one or two of the S/D regions of the transistor) allows for an increase in the contact area between the S/D contacts and the S/D regions, which may advantageously result in improved contact resistance.
While there may be advantages in implementing both a wrap-around gate and two wrap-around S/D contacts in a given planar III-N transistor, in various embodiments, a planar III-N transistor may implement: 1) a wrap-around gate as described herein, but without a wrap-around S/D contact; 2) one or more of the wrap-around S/D contacts as described herein, but without the wrap-around gate; or 3) a wrap-around gate as described herein and a wrap-around S/D contact as described herein, but implemented for only one of the S/D regions.
As used herein, the term "III-N semiconductor material" (hereinafter also simply referred to as "III-N material") refers to a compound semiconductor material having a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In) and a second sub-lattice of nitrogen (N). As used herein, the term "III-N transistor" means a device that includes a III-N material (which may include one or more different III-N materials, such as a plurality of different III-N materials stacked on top of one another) as an active material (active material) in which a conductive channel is formed during operation of the transistor.
Although various embodiments described herein may refer to the two-dimensional charge carrier layer as a "2 DEG" layer, embodiments described herein may also be applicable to systems and material combinations in which a 2D hole gas (2 DHG) may be formed instead of a 2 DEG. Accordingly, unless otherwise indicated, embodiments involving a 2DEG are equally applicable to, and implement, a 2DHG, and such embodiments are all within the scope of the present disclosure. Furthermore, although the various embodiments described herein relate to planar III-N transistors, they are equally applicable to transistors using semiconductor materials other than III-N materials as active materials.
Each of the structures, packages, methods, devices, and systems of the present disclosure may have several novel aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.
In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term "connected" means a direct electrical or magnetic connection between the things that are connected without any intermediate device, while the term "coupled" means a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediate devices. The term "circuit" means one or more passive and/or active components arranged to cooperate to provide a desired function. The terms "oxide", "carbide", "nitride" and the like, if used, refer to compounds containing oxygen, carbon, nitrogen, and the like, respectively. Similarly, the term designating various compounds refers to materials having any combination of individual elements within the compound (e.g., "gallium nitride" or "GaN" refers to materials comprising gallium and nitrogen, "aluminum indium gallium nitride" or "AlInGaN" refers to materials comprising aluminum, indium, gallium, and nitrogen, etc.). Furthermore, the term "high-k dielectric" refers to a material having a higher dielectric constant (k) than silicon oxide, while the term "low-k dielectric" refers to a material having a lower k than silicon oxide. The terms "substantially", "close", "approximately", "close" and "approximately" generally refer to being within +/-20% of a target value, preferably within +/-10% of the target value, based on the context of the particular value as described herein or as known in the art. Similarly, terms indicating the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, generally refer to being within +/-5-20% of a target value, based on the context of the particular value as described herein or as known in the art.
As used herein, terms such as "above," "below," "between," and "upper" refer to the relative position of one layer or component of material with respect to another layer or component. For example, one layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Further, one layer disposed between two layers may be in direct contact with one or both of the layers or may have one or more intervening layers. In contrast, a first layer described as "on" a second layer refers to the layer in direct contact with the second layer. Similarly, a feature disposed between two features may be in direct contact with adjacent features or may have one or more intervening layers, unless expressly stated otherwise.
For the purposes of this disclosure, the phrase "a and/or B" means (a), (B), or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" means (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C). The term "between" when used with reference to a measurement range encompasses the boundaries of the measurement range. As used herein, the label "A/B/C" means (A), (B) and/or (C).
The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The present disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "sides"; such descriptions are intended to facilitate the discussion and are not intended to limit the application of the disclosed embodiments. The drawings are not necessarily to scale. Unless otherwise specified, the use of the ordinal adjectives "first", "second", and "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration embodiments which may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense. For convenience, if a set of figures denoted with different letters exists (e.g., fig. 5A-5B), such a set may be referred to herein without the letters, e.g., as "fig. 5". In the drawings, the same reference numerals refer to the same or similar elements/materials as shown, so that unless otherwise specified, the description of an element/material having a given reference numeral provided in the context of one of the drawings may apply to other drawings in which the element/material having the same reference numeral may be shown.
In the drawings, some schematic representations of example structures of the various structures, devices, and assemblies described herein may be shown with precise right angles and straight lines, but it is understood that such schematic representations may not reflect practical process limitations that may make features appear not to be so "ideal" when examining any of the structures described herein using, for example, Scanning Electron Microscope (SEM) images or Transmission Electron Microscope (TEM) images. In such images of actual structures, possible process defects may also be visible, for example, imperfect straight edges of the material, tapered through-holes or other openings, unintentional rounding of corners or thickness variations of different material layers, sporadic spirals within the crystalline region(s), edge or combination dislocations, and/or sporadic dislocation defects of individual atoms or clusters of atoms. There may be other drawbacks not listed here but common in the field of device fabrication.
Various operations may be described as multiple discrete acts or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. The operations described may be performed in a different order than the described embodiments. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
Various IC structures including at least one planar III-N transistor with a wrap-around gate and/or one or more wrap-around S/D contacts as described herein can be implemented in one or more components associated with the IC and/or between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, transmitters, receivers, antennas, and so forth. Components associated with an IC may include those mounted on, provided as part of, or connected to the IC. The IC may be analog or digital, or may contain a combination of analog and digital circuits, and may be used in a variety of applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, and the like, depending on the components associated with the IC. In some embodiments, an IC structure as described herein may be included in an RFIC, which may be included in any component associated with the IC, for example, in an RF receiver, RF transmitter, or RF transceiver, or any other RF device, such as within a Base Station (BS) or User Equipment (UE) device, as used in telecommunications. Such components may include, but are not limited to, RF switches, power amplifiers, low noise amplifiers, RF filters (including arrays or banks of RF filters), up-converters, down-converters, and duplexers. In some embodiments, an IC structure as described herein may be used as part of a chipset for performing one or more related functions in a computer.
Wrap-around gate and S/D contact scheme for III-N transistors
Fig. 1A-1C provide different cross-sectional side views illustrating an
The
In some embodiments, the
In some embodiments,
In general, insulating materials, such as
The channel stack of III-
In some embodiments, III-
In general, III-
In some embodiments, III-
In some embodiments, the III-
In various embodiments, the thickness of III-
Turning now to the
As also shown in fig. 1, III-
The
Fig. 1 further illustrates a
The
Other layers may be included next to the
The III-
For such planar transistors, a wrap-around scheme for gate stacking and S/D contacts may be particularly beneficial, the details of which will now be described.
Fig. 1B illustrates that, in some embodiments of III-
Similarly, fig. 1C illustrates that, in some embodiments of III-
In various embodiments, the
Although not specifically shown in fig. 1C, in some embodiments, the S/D contact (S) 126 can extend down the sidewall (S) 164 of the S/
In some embodiments, only one of the S/
Although not specifically shown in fig. 1,
In some embodiments, the
Wrap-around gate and S/D contact scheme for non-III-N transistors
The wrap-around gate and S/D contact scheme described above can be particularly beneficial for planar III-N transistors because it can optimize the use of a 2DEG that is substantially two-dimensional (i.e., planar). In general, however, the wrap-around gate and S/D contact scheme as described herein may be applicable to non-III-N planar Field Effect Transistors (FETs), all of which are within the scope of the present disclosure. Thus, in some embodiments of the
In various embodiments, the non-III-N semiconductor material of the channel stack of
In some embodiments, the support structure over which such non-III-N semiconductor material may be provided may be any structure suitable for supporting non-III-N semiconductor material. In some embodiments, such support structures may comprise a semiconductor (such as silicon), and the non-III-N semiconductor material of the channel stack of
In some embodiments, the non-III-N semiconductor material of the channel stack of
In some embodiments, the non-III-N semiconductor material of the channel stack of
For the exemplary P-type transistor embodiment, the non-III-N semiconductor material of the channel stack of
For an exemplary N-type transistor embodiment, the non-III-N semiconductor material of the channel stack of
In some embodiments, the non-III-N semiconductor material of the channel stack of
Wrap-around gate and S/D contact scheme for III-N transistors with buffer layers
In some embodiments, current leakage may be further improved by providing a back barrier in the form of a buffer layer, as shown in fig. 2A-2C.
Fig. 2A-2C illustrate different cross-sectional side views of an IC structure 200, the IC structure 200 including a planar III-
In particular, fig. 2A-2C illustrate that, in some embodiments, the IC structure 200 may further include a buffer material 202 between the channel stack of the
Additional embodiments with wrap-around gate and S/D contact schemes
The
In addition, although some elements of the IC structure are shown in fig. 1-2 as planar rectangles or as being formed from cuboids, this is for ease of illustration only, and embodiments of various ones of these elements may be curved, rounded, or otherwise irregularly shaped, as dictated by, and sometimes unavoidable as a result of, the manufacturing process used to make the semiconductor device assembly. For example, although fig. 1-2 may show various elements (e.g., S/
Inspection of layout and mask data using, for example, optical microscopy, TEM or SEM, and reverse engineering portions of the device to reconstruct the circuit, and/or inspection of cross sections of the device using, for example, Physical Failure Analysis (PFA) to detect the shape and position of various device elements described herein, will allow for the determination of the integration of the wraparound gate with the planar III-N transistor as described herein.
Fabricating planar transistors with wrap-around gates and/or S/D contacts
IC structures implementing one or more planar transistors with wrap-around gates and/or one or more wrap-around S/D contacts as described herein may be fabricated using any suitable technique. Fig. 3 shows an example of such a method. However, other examples of making any of the IC structures described herein, as well as larger devices and assemblies (e.g., as shown in fig. 6-9) incorporating such structures, are also within the scope of the present disclosure.
Fig. 3 is a flow diagram of an example method 300 of fabricating an IC structure including a III-N transistor with a wraparound gate and/or one or more wraparound S/D contacts in accordance with various embodiments of the present disclosure.
Although the operations of method 300 are shown once per operation and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to substantially simultaneously fabricate a plurality of III-N transistors with wrap-around gates and/or one or more wrap-around S/D contacts as described herein. In another example, the operations may be performed in a different order to reflect the structure of a particular device assembly in which one or more planar III-N transistors with surrounding gates and/or one or more surrounding S/D contacts as described herein are to be included.
Additionally, the example method of manufacturing 300 may include other operations not specifically illustrated in fig. 3, such as various cleaning or planarization operations as are known in the art. For example, in some embodiments, the
Various operations of method 300 may be illustrated with reference to the example embodiments shown in fig. 4A-4E, illustrating fabrication of an IC structure as shown in fig. 1, but method 300 may be used to fabricate any suitable IC structure having one or more planar transistors with surrounding gates and/or one or more surrounding S/D contacts according to any other embodiment of the invention. Fig. 4A-4E illustrate cross-sectional side views, wherein each of fig. 4A-4E illustrate two views similar to the views illustrated in fig. 1A and 1B at various example stages in the fabrication of an IC structure using the method of fig. 3, according to some embodiments of the present disclosure.
The method 300 may begin by providing a channel stack over a support structure (process 302 shown in fig. 3, the result of which is shown as IC structure 402 shown in fig. 4A). IC structure 402 illustrates that the support structure provided in 302 may be
In some embodiments, process 302 may include epitaxially growing various transistor films, for example, for forming III-
In some embodiments, process 302 may include patterning to shape the channel stack in a desired geometry, for example, as an island (e.g., as shown in the right cross-section of fig. 4A) such that the channel stack is surrounded by an insulator (e.g., insulator 110). Any suitable deposition technique may be used to deposit
The method 300 may then proceed with providing S/D regions in the channel stack provided in 302 (process 304 shown in fig. 3, the result of which is shown as
Once the S/D regions have been formed, the method 300 may proceed with performing recessing of the dielectric material around upper portions of the sidewalls of the channel stack that are in opposing planes that are parallel to the planes of the first and second S/D regions formed in the connections 304 (the latter plane being a plane perpendicular to the support structure 108) (process 306 shown in fig. 3, the result of which is shown as IC structure 406 shown in fig. 4C). The IC structure 406 shows that the process 306 may expose a surface of the upper portion 454 of the
The method 300 may then proceed to define a region for forming a gate stack for a future transistor (process 308 shown in fig. 3, the result of which is shown as
The method 300 may then proceed with providing gate stacks in the regions defined in process 308 (process 310 shown in fig. 3, the result of which is shown as
Method 300 may also include providing S/D contacts to form electrical contacts to the S/D regions provided in process 304 (process 312 shown in fig. 3, the results of which are not shown in fig. 4A-4E, as the results may be an IC structure as shown in fig. 1). Examples of deposition techniques that may be used to provide the S/D contacts at process 312 include, but are not limited to, ALD, PVD, CVD, or electroplating.
Example structures and devices having planar transistors with wrap-around gates and/or S/D contacts
An IC structure including one or more planar transistors with a wraparound gate and/or one or more wraparound S/D contacts as disclosed herein may be included in any suitable electronic device. Fig. 5-9 illustrate various examples of devices and components that may include one or more planar transistors integrated with a wraparound gate and/or one or more wraparound S/D contacts as disclosed herein.
Fig. 5A-5B are top views of a
Fig. 6 is a cross-sectional side view of an example IC package 2200 that can include one or more IC structures having one or more planar transistors integrated with a wraparound gate and/or one or more wraparound S/D contacts in accordance with any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a system-in-package (SiP).
As shown in fig. 6, the IC package 2200 may include a package substrate 2252. The package substrate 2252 may be formed of a dielectric material (e.g., ceramic, glass, a combination of organic and inorganic materials, a laminate film, an epoxy film with filler particles therein, etc., and may have embedded portions of different materials) and may have conductive paths extending through the dielectric material between the face 2272 and the face 2274 or between different locations on the face 2272 and/or between different locations on the face 2274.
The package substrate 2252 may include conductive contacts 2263 coupled to conductive vias 2262 through the package substrate 2252, allowing circuits and/or interposer (interposer) 2257 within the die 2256 to be electrically coupled to respective ones of the conductive contacts 2264 (or other devices included in the package substrate 2252, not shown).
IC package 2200 may include an interposer 2257, the interposer 2257 being coupled to a package substrate 2252 via conductive contacts 2261 of interposer 2257, first level interconnects 2265, and conductive contacts 2263 of package substrate 2252. The first level interconnects 2265 shown in fig. 6 are solder bumps (solder bumps), but any suitable first level interconnects 2265 may be used. In some embodiments, the interposer 2257 may not be included in the IC package 2200; instead, die 2256 may be directly coupled to conductive contacts 2263 at face 2272 by first level interconnects 2265.
IC package 2200 may include one or more dies 2256, the one or more dies 2256 coupled to interposer 2257 via conductive contacts 2254 of die 2256, first level interconnects 2258, and conductive contacts 2260 of interposer 2257. Conductive contacts 2260 may be coupled to conductive vias (not shown) through interposer 2257, allowing circuitry within die 2256 to be electrically coupled to respective ones of conductive contacts 2261 (or other devices, not shown, contained in interposer 2257). The first level interconnects 2258 shown in fig. 6 are solder bumps, but any suitable first level interconnects 2258 may be used. As used herein, "conductive contact" may refer to a portion of a conductive material (e.g., metal) that serves as an interface between different components; the conductive contacts may be recessed into, flush with, or extend away from the surface of the component, and may take any suitable form (e.g., conductive pads or sockets).
In some embodiments, underfill material 2266 may be disposed around first level interconnects 2265 between the package substrate 2252 and the interposer 2257, and a mold compound (mold compound) 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, underfill 2266 may be the same as molding compound 2268. An example material that may be used for underfill 2266 and molding compound 2268 is a suitable epoxy molding material. Second level interconnect 2270 may be coupled to conductive contact 2264. The second level interconnects 2270 shown in fig. 6 are solder balls (e.g., for a ball grid array arrangement), although any suitable second level interconnects 2270 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array (land grid array) arrangement). As is known in the art and as discussed below with reference to fig. 7, the second level interconnect 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package.
Die 2256 may take the form of any of the embodiments of die 2002 discussed herein and may include any of the embodiments of IC structures described herein (e.g., any of
The IC package 2200 shown in fig. 6 may be a flip chip package, although other package architectures may be used. For example, the IC package 2200 may be a Ball Grid Array (BGA) package, such as an embedded wafer level ball grid array (eWLB) package. In another example, the IC package 2200 may be a Wafer Level Chip Scale Package (WLCSP) or a panel Fan Out (FO) package. Although two dies 2256 are shown in the IC package 2200 of fig. 6, the IC package 2200 may contain any desired number of dies 2256. The IC package 2200 may contain additional passive components such as surface mount resistors, capacitors, and inductors disposed on the first 2272 or second 2274 side of the package substrate 2252 or on any of the interposers 2257. More generally, the IC package 2200 may include any other active or passive component known in the art.
Fig. 7 is a cross-sectional side view of an
In some embodiments,
The
The package-on-
The
The
The
Fig. 8 is a block diagram of an example computing device 2400 that may include one or more components having one or more IC structures with one or more planar transistors integrated with a wraparound gate and/or one or more wraparound S/D contacts in accordance with any of the embodiments disclosed herein. For example, any suitable one of the components of computing device 2400 may include a die (e.g., die 2002 (fig. 5B)) including one or more planar transistors having a wraparound gate and/or one or more wraparound S/D contacts in accordance with any of the embodiments disclosed herein. Any of the components of computing device 2400 may include an IC device (e.g., any embodiment of the IC structure of fig. 1-2) and/or an IC package 2200 (fig. 6). Any of the components of the computing device 2400 may include an IC device assembly 2300 (fig. 7).
A number of components are shown in fig. 8 as being included in computing device 2400, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single SoC die.
Additionally, in various embodiments, the computing device 2400 may not include one or more of the components shown in fig. 8, but the computing device 2400 may include interface circuitry for coupling to one or more components. For example, computing device 2400 may not include display device 2406, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 2406 may be coupled. In another set of examples, the computing device 2400 may not include the audio input device 2418 or the audio output device 2408, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 2418 or the audio output device 2408 may be coupled.
Computing device 2400 may include processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Processing device 2402 may include one or more Digital Signal Processors (DSPs), application specific ics (asics), Central Processing Units (CPUs), Graphics Processing Units (GPUs), cryptographic processors (special purpose processors that perform cryptographic algorithms in hardware), server processors, or any other suitable processing device. The computing device 2400 may include memory 2404, which memory 2404 may itself include one or more memory devices, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., Read Only Memory (ROM)), flash memory, solid state memory, and/or a hard disk drive. In some embodiments, memory 2404 may include memory that shares a die with processing device 2402. The memory may be used as cache memory and may include, for example, eDRAM and/or spin-torque transfer magnetic random access memory (STT-MRAM).
In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured to manage wireless communications for communicating data to and from the computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not.
The communication chip 2412 may implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 modification), Long Term Evolution (LTE) project, along with any modifications, updates, and/or revisions (e.g., LTE-advanced project, Ultra Mobile Broadband (UMB) project (also referred to as "3 GPP 2"), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for worldwide interoperability for microwave access (worldwide interoperability for microwave access), which is a certification mark for products that pass conformance and interoperability tests of the IEEE 802.16 standard. The communication chip 2412 may operate in accordance with a global system for mobile communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), evolved HSPA (E-HSPA), or LTE network. Communication chip 2412 may operate in accordance with enhanced data rates for GSM evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), evolution-data optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols denoted as 3G, 4G, 5G, and above. In other embodiments, the communication chip 2412 may operate in accordance with other wireless protocols. Computing device 2400 may include an antenna 2422 to facilitate wireless communications and/or receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., ethernet). As described above, the communication chip 2412 may include multiple communication chips. For example, the first communication chip 2412 may be dedicated for short-range wireless communications (such as Wi-Fi or bluetooth, etc.), and the second communication chip 2412 may be dedicated for long-range wireless communications (such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others). In some embodiments, the first communication chip 2412 may be dedicated for wireless communication and the second communication chip 2412 may be dedicated for wired communication.
In various embodiments, an IC structure as described herein may be particularly advantageous for use within one or more of the communication chips 2412 described above. For example, such IC structures may be used to implement one or more of the following: power amplifiers implementing various transistors, low noise amplifiers, filters (including filter arrays and filter banks), switches, up-converters, down-converters, duplexers, and logic circuits (e.g., control logic), for example, as part of implementing an RF transmitter, RF receiver, or RF transceiver.
The computing device 2400 may include a battery/power circuit 2414. The battery/power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., an AC line power source).
Computing device 2400 may include display device 2406 (or corresponding interface circuitry, as discussed above). Display device 2406 may include any visual indicator, such as, for example, a heads-up display, a computer monitor, a projector, a touch screen display, a Liquid Crystal Display (LCD), a light emitting diode display, or a flat panel display.
Computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as discussed above). Audio output device 2408 may include any device that generates audible indications, such as a speaker, earphone, or earbud.
The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates signals representative of sound, such as a microphone, an array of microphones, or a digital instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output).
Computing device 2400 may include GPS device 2416 (or corresponding interface circuitry, as discussed above). As known in the art, GPS device 2416 may communicate with a satellite-based system and may receive the location of computing device 2400.
The computing device 2400 may include other output devices 2410 (or corresponding interface circuits, as discussed above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter to provide information to other devices, or an additional storage device.
Computing device 2400 may include other input devices 2420 (or corresponding interface circuitry, as discussed above). Examples of other input devices 2420 may include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices such as mice, styluses, touch pads, bar code readers, Quick Response (QR) code readers, any sensors, or Radio Frequency Identification (RFID) readers.
The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a Personal Digital Assistant (PDA), an ultra mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, computing device 2400 may be any other electronic device that processes data.
Fig. 9 is a block diagram of an example RF device 2500, the example RF device 2500 may include one or more components having one or more IC structures having one or more planar transistors having a wraparound gate and/or one or more wraparound S/D contacts, according to any of the embodiments disclosed herein. For example, any suitable one of the components of the RF device 2500 may include a die (e.g., the
In general, RF device 2500 may be any device or system that may support wireless transmission and/or reception of signals in the form of electromagnetic waves in the RF range of approximately 3 kilohertz (kHz) to 300 gigahertz (GHz). In some embodiments, the RF device 2500 may be used for wireless communication, for example, in a BS or UE device of any suitable cellular wireless communication technology, such as GSM, WCDMA, or LTE. In further examples, RF device 2500 may be used as or in, for example, a BS or UE device of millimeter wave wireless technology, such as fifth generation (5G) wireless (i.e., high frequency/short wavelength spectrum, e.g., having frequencies in a range between approximately 20 GHz and 60 GHz, corresponding to wavelengths in a range between approximately 5 millimeters and 15 millimeters). In yet another example, the RF device 2500 may be used, for example, in a Wi-Fi enabled device (e.g., a desktop computer, a laptop computer, a video game console, a smart phone, a tablet computer, a smart TV, a digital audio player, an automobile, a printer, etc.) for wireless communication using Wi-Fi technology (e.g., a 2.4 Ghz band, corresponding to a wavelength of approximately 12 cm, or a 5.8 Ghz band spectrum, corresponding to a wavelength of approximately 5 cm). In some implementations, the Wi-Fi enabled device may be, for example, a node (e.g., a smart sensor) in an intelligent system configured to communicate data with other nodes. In yet another example, the RF device 2500 may be used for wireless communication using bluetooth technology (e.g., a frequency band from about 2.4 Ghz to about 2.485 Ghz, corresponding to a wavelength of about 12 cm). In other embodiments, the RF device 2500 may be used to transmit and/or receive RF signals for purposes other than communication, for example, in automotive radar systems or in medical applications such as Magnetic Resonance Imaging (MRI).
In various embodiments, RF device 2500 may be included in a Frequency Domain Duplex (FDD) or Time Domain Duplex (TDD) variant that may be used for frequency allocation in a cellular network. In an FDD system, the uplink (i.e., RF signals transmitted from the UE device to the BS) and the downlink (i.e., RF signals transmitted from the BS to the UE device) may use separate frequency bands at the same time. In a TDD system, the uplink and downlink may use the same frequency, but at different times.
A number of components are shown in fig. 9 as being included in the RF device 2500, but any one or more of these components may be omitted or duplicated as appropriate for the application. For example, in some embodiments, RF device 2500 may be an RF device (e.g., an RF transceiver) that supports both wireless transmission and reception of RF signals, in which case it may include both components referred to herein as part of a Transmit (TX) path and components referred to herein as part of a Receive (RX) path. However, in other embodiments, RF device 2500 may be an RF device that supports only wireless reception (e.g., an RF receiver), in which case it may include components of the RX path, but not the TX path; or RF device 2500 may be an RF device (e.g., an RF transmitter) that supports only wireless transmissions, in which case it may contain components of the TX path, but not the RX path.
In some embodiments, some or all of the components included in the RF device 2500 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single die, for example, on a single SoC die.
Additionally, in various embodiments, the RF device 2500 may not include one or more of the components shown in fig. 9, but the RF device 2500 may include interface circuitry for coupling to one or more components. For example, the RF device 2500 may not include the antenna 2502, but may include antenna interface circuitry (e.g., matching circuitry, connectors, and driver circuitry) to which the antenna 2502 may be coupled. In another set of examples, the RF device 2500 may not include the digital processing unit 2508 or the local oscillator 2506, but may include device interface circuits (e.g., connectors and support circuits) to which the digital processing unit 2508 or the local oscillator 2506 may be coupled.
As shown in fig. 9, RF device 2500 may include an antenna 2502, a duplexer 2504, a local oscillator 2506, a digital processing unit 2508. As also shown in fig. 9, RF device 2500 may include an RX path, which may include an RX path amplifier 2512, an RX path pre-mix filter 2514, an RX path mixer 2516, an RX path post-mix filter 2518, and an analog-to-digital converter (ADC) 2520. As further shown in fig. 9, RF device 2500 may include a TX path, which may include a TX path amplifier 2522, a TX path post-mix filter 2524, a TX path mixer 2526, a TX path pre-mix filter 2528, and a digital-to-analog converter (DAC) 2530. Still further, the RF device 2500 may further include an impedance tuner 2532 and an RF switch 2534. In various embodiments, the RF device 2500 may include multiple instances of any of the components shown in fig. 9. In some embodiments, the RX path amplifier 2512, the TX path amplifier 2522, the duplexer 2504, and the RF switch 2534 may be considered to form or be part of the RF FE of the RF device 2500. In some embodiments, RX path mixer 2516 and TX path mixer 2526 (possibly along with their associated pre-and post-mixer filters shown in fig. 9) may be considered to form or be part of an RF transceiver (or RF receiver or RF transmitter, respectively, if only the RX path components or TX path components are included in RF device 2500) of RF device 2500. Although not specifically shown in fig. 9, the RF device 2500 may further include one or more control logic elements/circuits of the RF device (e.g., in an RF FR control interface), for example, to enhance control of complex RF system environments, support implementation of envelope tracking techniques, reduce dissipated power, and so forth. Various IC structures as described herein may be particularly advantageous for implementing at least portions of such control logic elements/circuits.
The antenna 2502 may be configured to wirelessly transmit and/or receive RF signals according to any wireless standard or protocol, such as Wi-Fi, LTE, or GSM, as well as any other wireless protocol denoted as 3G, 4G, 5G, and above. If the RF device 2500 is an FDD transceiver, the antenna 2502 may be configured for concurrent reception and transmission of communication signals in separate (i.e., non-overlapping and non-contiguous) frequency bands, e.g., in frequency bands having a separation of, for example, 20 MHz from one another. If RF device 2500 is a TDD transceiver, antenna 2502 may be configured for sequential reception and transmission of communication signals in frequency bands that may be the same or overlapping for TX and RX paths. In some embodiments, the RF device 2500 may be a multi-band RF device, in which case the antenna 2502 may be configured for concurrent reception and/or configured for concurrent transmission of signals having multiple RF components in separate frequency bands. In such embodiments, the antenna 2502 may be a single wideband antenna or a plurality of band-specific antennas (i.e., a plurality of antennas each configured to receive and/or transmit signals in a particular frequency band). In various embodiments, antenna 2502 may include multiple antenna elements, such as multiple antenna elements forming a phased antenna array (i.e., an array of antennas or a communication system that may transmit and receive RF signals using multiple antenna elements and phase shifting). Phased antenna arrays may provide advantages such as increased gain, directional steering (directional) capability, and simultaneous communication compared to single antenna systems. In some embodiments, RF device 2500 may include more than one antenna 2502 to achieve antenna diversity. In some such embodiments, RF switch 2534 may be deployed to switch between different antennas.
An output of the antenna 2502 may be coupled to an input of a duplexer 2504. The duplexer 2504 may be any suitable component configured to filter multiple signals to allow bi-directional communication through a single path between the duplexer 2504 and the antenna 2502. Duplexer 2504 may be configured to provide RX signals to an RX path of RF device 2500 and to receive TX signals from a TX path of RF device 2500.
The RF device 2500 may include one or more local oscillators 2506, the local oscillators 2506 configured to provide local oscillator signals that may be used for down-conversion of RF signals received by the antenna 2502 and/or up-conversion of signals to be transmitted by the antenna 2502.
The RF device 2500 may include a digital processing unit 2508, which digital processing unit 2508 may include one or more processing devices. In some embodiments, digital processing unit 2508 may be implemented as processing device 2402 shown in fig. 8, the description of which processing device 2402 is provided above (when used as digital processing unit 2508, processing device 2402 may, but need not, implement any of the IC structures as described herein, such as an IC structure having one or more planar transistors with a wraparound gate and/or one or more wraparound S/D contacts in accordance with any of the embodiments disclosed herein). Digital processing unit 2508 may be configured to perform various functions related to the digital processing of RX and/or TX signals. Examples of such functions include, but are not limited to, decimation/downsampling, error correction, digital down-or up-conversion, DC offset cancellation, automatic gain control, and the like. Although not shown in fig. 9, in some embodiments, the RF device 2500 may further include a memory device, e.g., memory device 2404 as described with reference to fig. 8, configured to cooperate with the digital processing unit 2508. When used within or coupled to the RF device 2500, the memory device 2404 may, but need not, implement any of the IC structures as described herein, such as an IC structure having one or more planar transistors with a wraparound gate and/or one or more wraparound S/D contacts in accordance with any of the embodiments disclosed herein.
Turning to the details of the RX path, which may be included in RF device 2500, RX path amplifier 2512 may include a Low Noise Amplifier (LNA). An input of the RX path amplifier 2512 may be coupled to an antenna port (not shown) of the antenna 2502, e.g., via a duplexer 2504. The RX path amplifier 2512 may amplify the RF signal received by the antenna 2502.
The output of the RX path amplifier 2512 may be coupled to an input of an RX path pre-mix filter 2514, which RX path pre-mix filter 2514 may be a harmonic or bandpass (e.g., low pass) filter configured to filter a received RF signal that has been amplified by the RX path amplifier 2512.
The output of the RX path mixing pre-filter 2514 may be coupled to an input of an RX path mixer 2516 (also referred to as a downconverter). The RX path mixer 2516 may include two inputs and one output. The first input may be configured to receive an RX signal, which may be a current signal, indicative of the signal received by the antenna 2502 (e.g., the first input may receive the output of the RX path pre-mixing filter 2514). The second input may be configured to receive a local oscillator signal from one of the local oscillators 2506. The RX path mixer 2516 may then mix the signals received at its two inputs to generate a downconverted RX signal provided at the output of the RX path mixer 2516. As used herein, down-conversion refers to the process of mixing a received RF signal with a local oscillator signal to generate a lower frequency signal. In particular, the down-conversion RX path mixer 2516 may be configured to generate a sum frequency and/or a difference frequency at the output port when two input frequencies are provided at the two input ports. In some embodiments, the RF device 2500 may implement a Direct Conversion Receiver (DCR), also referred to as a homodyne, synchronous, or zero-IF receiver, in which case the RX path mixer 2516 may be configured to demodulate an incoming radio signal using a local oscillator signal having a frequency that is the same as or very close to the carrier frequency of the radio signal. In other embodiments, RF device 2500 may utilize down conversion to an Intermediate Frequency (IF). IF may be used in a superheterodyne radio receiver, where a received RF signal is shifted to IF before final detection of information in the received signal is performed. Frequency conversion to IF may be useful for several reasons. For example, when several stages of filters are used, they can all be set to a fixed frequency, which makes them easier to build and tune. In some embodiments, RX path mixer 2516 may include several such stages of IF frequency conversion.
Although a single RX path mixer 2516 is shown in the RX path of fig. 9, in some embodiments, the RX path mixer 2516 may be implemented as a quadrature downconverter, in which case it would include a first RX path mixer and a second RX path mixer. The first RX path mixer may be configured to perform downconversion to generate an in-phase (I) downconverted RX signal by mixing the RX signal received by the antenna 2502 with the in-phase component of the local oscillator signal provided by the local oscillator 2506. The second RX path mixer may be configured to perform down-conversion by mixing an RX signal received by the antenna 2502 and a quadrature component of a local oscillator signal provided by the local oscillator 2506 (the quadrature component being a component offset in phase by 90 degrees from an in-phase component of the local oscillator signal) to generate a quadrature (Q) down-converted RX signal. The output of the first RX path mixer may be provided to the I signal path and the output of the second RX path mixer may be provided to the Q signal path, which may be substantially 90 degrees out of phase with the I signal path.
The output of RX path mixer 2516 may optionally be coupled to an RX path mixing post filter 2518, which RX path mixing post filter 2518 may be a low pass filter. Where RX path mixer 2516 is a quadrature mixer implementing first and second mixers as described above, the in-phase and quadrature components provided at the outputs of the first and second mixers, respectively, may be coupled to respective first and second RX path post-mixing filters included in filter 2518.
ADC 2520 may be configured to convert the mixed RX signal from RX path mixer 2516 from the analog domain to the digital domain. ADC 2520 may be a quadrature ADC, similar to RX path quadrature mixer 2516, may include two ADCs configured to digitize down-converted RX path signals separated in-phase and quadrature components. The output of the ADC 2520 may be provided to a digital processing unit 2508, which digital processing unit 2508 is configured to perform various functions related to the digital processing of the RX signal, enabling the extraction of information encoded in the RX signal.
Turning to the details of the TX path, which may be included in the RF device 2500, digital signals (TX signals), which are to be transmitted later by the antenna 2502, may be provided from the digital processing unit 2508 to the DAC 2530. Similar to ADC 2520, DAC2530 may include two DACs configured to convert the digital I and Q path TX signal components, respectively, to analog form.
Optionally, the output of DAC2530 may be coupled to a TX path pre-mix filter 2528, which TX path pre-mix filter 2528 may be a band pass (e.g., low pass) filter (or, in the case of quadrature processing, a pair of band pass (e.g., low pass) filters) configured to filter out signal components outside the desired frequency band from the analog TX signal output by DAC 2530. The digital TX signal may then be provided to a TX path mixer 2526, which TX path mixer 2526 may also be referred to as an upconverter. Similar to RX path mixer 2516, TX path mixer 2526 may include a pair of TX path mixers for mixing the in-phase and quadrature components. Similar to the first and second RX path mixers that may be included in the RX path, each of the TX path mixers of TX path mixer 2526 may include two inputs and one output. The first input may receive TX signal components that are converted to analog form by respective DACs 2530, which are to be upconverted to generate an RF signal to be transmitted. The first TX path mixer may generate an in-phase (I) upconverted signal by mixing the TX signal component converted to analog form by DAC2530 with an in-phase component of a TX path local oscillator signal provided from local oscillator 2506 (in various embodiments, local oscillator 2506 may comprise a plurality of different local oscillators, or be configured to provide different local oscillator frequencies for mixer 2516 in the RX path and mixer 2526 in the TX path). The second TX path mixer may generate a quadrature-phase (Q) upconverted signal by mixing the TX signal component converted to analog form by DAC2530 with the quadrature component of the TX path local oscillator signal. The output of the second TX path mixer may be added to the output of the first TX path mixer to create the actual RF signal. A second input of each of the TX path mixers may be coupled to a local oscillator 2506.
Alternatively, RF device 2500 may include a TX path post-mix filter 2524, the TX path post-mix filter 2524 configured to filter the output of TX path mixer 2526.
The TX path amplifier 2522 may be a Power Amplifier (PA) configured to amplify the upconverted RF signal before providing it to the antenna 2502 for transmission.
In various embodiments, any of RX path mixing pre-filter 2514, RX path mixing post-filter 2518, TX mixing post-filter 2524, and TX mixing pre-filter 2528 may be implemented as an RF filter. In some embodiments, each of such RF filters may include one or more (typically multiple) resonators (e.g., Film Bulk Acoustic Resonators (FBARs), lamb wave resonators, and/or contour wave resonators) arranged, for example, in a ladder configuration. The individual resonators of the RF filter may include a layer of piezoelectric material, such as aluminum nitride (AlN), enclosed between a bottom electrode and a top electrode, with a cavity provided around a portion of each electrode to allow a portion of the piezoelectric material to vibrate during operation of the filter. In some embodiments, the RF filter may be implemented as a plurality of RF filters or filter banks. The filter bank may include a plurality of RF resonators that may be coupled to a switch (e.g., RF switch 2534) configured to selectively turn any of the plurality of RF resonators on and off (i.e., activate any of the plurality of RF resonators) in order to achieve a desired filtering characteristic of the filter bank (i.e., in order to program the filter bank). Such a filter bank may be used to switch between different RF frequency ranges, for example, when the RF device 2500 is or is included in a BS or UE device. In another example, such a filter bank may be programmable to suppress TX leakage over different duplex distances.
The impedance tuner 2532 may include any suitable circuitry configured to match the input and output impedances of different RF circuits to minimize signal loss in the RF device 2500. For example, impedance tuner 2532 may comprise an antenna impedance tuner. Being able to tune the impedance of the antenna 2502 may be particularly advantageous because the impedance of the antenna is a function of the environment in which the RF device 2500 is located, e.g., the impedance of the antenna varies depending on, e.g., whether the antenna is held in the hand, placed on a vehicle roof, etc.
As described above, the RF switch 2534 may be used to selectively switch between multiple instances of any one of the components shown in fig. 9 in order to achieve the desired behavior and characteristics of the RF device 2500. For example, in some embodiments, an RF switch may be used to switch between different antennas 2502. In other embodiments, the RF switch may be used to switch between multiple RF resonators of any of the filters included in the RF device 2500 (e.g., by selectively turning on and off the RF resonators).
In various embodiments, one or more of the III-N transistors as described herein may be particularly advantageous when used in any of duplexer 2504, RX path amplifier 2512, RX path pre-mix filter 2514, RX path post-mix filter 2518, TX path amplifier 2522, TX path pre-mix filter 2528, TX path post-mix filter 2524, impedance tuner 2532, and/or RF switch 2534.
RF device 2500 provides a simplified version and, in further embodiments, may include other components not specifically shown in fig. 9. For example, the RX path of RF device 2500 may include a current-to-voltage amplifier between RX path mixer 2516 and ADC 2520 that may be configured to amplify and convert the downconverted signal to a voltage signal. In another example, the RX path of the RF device 2500 may include a balun (balun) for generating a balanced signal. In yet another example, the RF device 2500 may further include a clock generator, which may, for example, include a suitable phase-locked loop (PLL) configured to receive a reference clock signal and use it to generate a different clock signal, which may then be used to time the operation of the ADC 2520, DAC2530, and/or may also be used by the local oscillator 2506 to generate a local oscillator signal to be used in the RX path or TX path.
Selection example
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an IC structure comprising a support structure (e.g., a substrate, a die, or a chip) and a planar III-N transistor. The transistor includes: a channel stack provided over the support structure, the channel stack comprising a III-N semiconductor material provided over the support structure and a polarization material provided over the III-N semiconductor material; first and second source/drain (S/D) regions provided in the channel stack; and a gate stack provided over a portion of the channel stack between the first and second S/D regions, wherein the gate stack at least partially surrounds an upper portion of the channel stack.
Example 2 provides an IC structure according to example 1, wherein the gate stack surrounding the upper portion of the channel stack comprises a gate stack provided over a top surface of the channel stack (e.g., a face of the channel stack furthest from the support structure) and extending along at least one sidewall (preferably along both sidewalls) of the channel stack to a depth of between about 2 nanometers and 100 nanometers (including all values and ranges therein, e.g., between about 4 nanometers and 50 nanometers, or between about 5 nanometers and 30 nanometers).
Example 3 provides an IC structure according to example 2, wherein the gate stack includes a gate dielectric material surrounding an upper portion of the channel stack and a gate electrode material surrounding the gate dielectric material.
Example 4 provides the IC structure of example 3, wherein a portion of the gate dielectric material is in contact with the III-N semiconductor material at the at least one sidewall of the channel stack.
Example 5 provides an IC structure according to any of the above examples, wherein each of the first and second S/D regions extends into the channel stack to a depth of between about 8 nanometers and 200 nanometers, including all values and ranges therein, such as between about 10 nanometers and 150 nanometers, or between about 10 nanometers and 80 nanometers.
Example 6 provides an IC structure according to any of the above examples, wherein a width of the channel stack in a direction perpendicular to the gate length is between about 20 nanometers and 1 millimeter, including all values and ranges therein, such as between about 50 nanometers and 500 microns, or between about 100 nanometers and 50 microns.
Example 7 provides the IC structure according to any of the above examples, wherein the poled material comprises a material having a stronger piezoelectric poling behavior/property than the III-N semiconductor material and configured to induce a tensile stress in the III-N semiconductor material.
Example 8 provides the IC structure of example 7, wherein the polarization material comprises aluminum, indium, gallium, and nitrogen (e.g., Al)xInyGazN）。
Example 9 provides an IC structure according to any of the above examples, wherein a thickness of the polarization material between the gate stack and the III-N semiconductor material is between about 0.1 nanometers and 50 nanometers, such as between about 1 nanometer and 20 nanometers, or between about 1 nanometer and 10 nanometers.
Example 10 provides an IC structure according to any of the above examples, wherein the III-N semiconductor material includes nitrogen, and one or more of gallium and aluminum (e.g., GaN, AlN, or AlGaN).
Example 11 provides an IC structure according to any of the above examples, wherein the III-N semiconductor material has a thickness between approximately 5 nanometers and 1000 nanometers, such as between approximately 5 nanometers and 100 nanometers, or between approximately 10 nanometers and 50 nanometers.
Example 12 provides an IC structure according to any of the above examples, further comprising a buffer material between the III-N semiconductor material and the support structure, wherein a bandgap of the buffer material is greater than a bandgap of the III-N semiconductor material.
Example 13 provides the IC structure of example 12, wherein the buffer material comprises: a material containing aluminum, gallium, and nitrogen (e.g., AlGaN) or a material containing aluminum and nitrogen (e.g., AlN).
Example 14 provides the IC structure of example 12 or 13, wherein the buffer material is between about 100 nanometers and 5000 nanometers thick, e.g., between about 250 nanometers and 500 nanometers thick.
Example 15 provides an IC structure according to any of the above examples, further comprising S/D contact material (e.g.,
Example 16 provides the IC structure of example 15, wherein the S/D contact material surrounding the upper portion of the first S/D region comprises the S/D contact material provided over a top surface of the first S/D region (e.g., a surface of the S/D region furthest from the support structure) and extending along at least one sidewall (preferably along both sidewalls) of the channel stack to a depth of between about 2 nanometers and 150 nanometers (including all values and ranges therein, e.g., between about 4 nanometers and 75 nanometers or between about 5 nanometers and 45 nanometers).
Example 17 provides the IC structure of example 16, wherein a portion of the S/D contact material is in contact with at least one sidewall of the first S/D region.
Example 18 provides an IC structure according to any of the above examples, wherein the planar III-N transistor is part of an RF circuit, or the III-N transistor is part of a power supply circuit.
Example 19 provides an IC package including an IC die and a further IC assembly coupled to the IC die. The IC die includes a planar transistor having a channel stack and a gate stack. The channel stack includes one or more semiconductor materials (e.g., a III-N semiconductor material and a polarization material provided over the III-N semiconductor material). The channel stack has a top surface and a pair of opposing sidewalls, wherein a distance between the pair of opposing sidewalls is between about 20 nanometers and 1 millimeter, including all values and ranges therein, such as between about 50 nanometers and 500 micrometers, or above about 100 nanometers (e.g., between about 100 nanometers and 50 micrometers). The gate stack includes a first portion in contact with a portion of a top surface of the channel stack and a second portion in contact with a portion of at least one of a pair of opposing sidewalls of the channel stack.
Example 20 provides the IC package of example 19, wherein the second portion of the gate stack is in contact with at least one of the one or more semiconductor materials of the channel stack (e.g., in contact with III-N semiconductor material of the channel stack) at least one of a pair of opposing sidewalls of the channel stack.
Example 21 provides the IC package of example 19 or 20, wherein the first portion is continuous with the second portion (e.g., the gate stack surrounds at least one sidewall of a pair of opposing sidewalls of the channel stack).
Example 22 provides an IC package according to any of examples 19-21, wherein the further IC component comprises one of a package substrate, an interposer, or a further IC die.
Example 23 provides the IC package of any of examples 19-22, wherein the IC package is included in one of a switch, a power amplifier, a low noise amplifier, a filter bank, a duplexer, an upconverter, a downconverter, or a logic circuit of an RF communication device (e.g., an RF transceiver), and/or the IC package is included in a base station of a wireless communication system or a UE device (e.g., a mobile device) of the wireless communication system.
In various further examples, an IC die of an IC package according to any of the above examples may include an IC structure according to any of the above examples, such as an IC structure according to any of examples 1-18.
Example 24 provides a method of fabricating an IC structure. The method comprises the following steps: forming a channel stack over the support structure, the channel stack comprising a III-N semiconductor material and a polarization material over the III-N semiconductor material; forming a pair of source/drain (S/D) regions in the channel stack; and providing a gate stack over a portion of the channel stack between the pair of S/D regions, wherein the gate stack at least partially surrounds an upper portion of the channel stack.
Example 25 provides the method of example 24, wherein the gate stack surrounding the upper portion of the channel stack includes a gate stack provided over a top surface of the channel stack (e.g., a face of the channel stack furthest from the support structure) and extending along at least one sidewall of the channel stack (preferably along both sidewalls) to a depth of between about 2 nanometers and 100 nanometers (including all values and ranges therein, e.g., between about 4 nanometers and 50 nanometers, or between about 5 nanometers and 30 nanometers).
Example 26 provides the method of example 24, wherein the channel stack includes a top surface and a pair of opposing sidewalls, and wherein providing the gate stack includes: forming a recess in the dielectric material surrounding the pair of opposing sidewalls of the channel stack to expose a portion of at least one of the pair of opposing sidewalls of the channel stack, wherein the exposed portion of the at least one of the pair of opposing sidewalls of the channel stack has a height along the at least one sidewall (preferably along both sidewalls) of the channel stack of between about 2 nanometers and 100 nanometers, including all values and ranges therein, such as between about 4 nanometers and 50 nanometers, or between about 5 nanometers and 30 nanometers; depositing a gate dielectric material of the gate stack over a top surface of the channel stack and over an exposed portion of at least one of a pair of opposing sidewalls of the channel stack; and depositing a gate electrode material of the gate stack over the gate dielectric material.
In various further examples of the method according to any of examples 24-26, the IC structure is an IC structure according to any of examples 1-18, and the method includes corresponding further processes to fabricate any of the IC structures.
Example 27 provides an IC structure comprising a support structure (e.g., a substrate, a die, or a chip) and a planar transistor. The transistor includes: a channel stack provided over the support structure, the channel stack comprising one or more semiconductor materials (e.g., III-N semiconductor materials and a polarization material provided over the III-N semiconductor materials) provided over the support structure; first and second source/drain (S/D) regions provided in the channel stack; and an S/D contact material, wherein the S/D contact material at least partially surrounds an upper portion of at least one of the first and second S/D regions (e.g., the first S/D region). If the S/D contact material surrounds the upper portions of both S/D regions, it is a different instance of the material (e.g., discontinuous material) surrounding each respective S/D region.
Example 28 provides the IC structure of example 27, wherein the S/D contact material surrounding the upper portion of the first S/D region comprises the S/D contact material provided over a top surface of the first S/D region (e.g., a surface of the S/D region furthest from the support structure) and extending along at least one sidewall (preferably along both sidewalls) of the channel stack to a depth of between about 2 nanometers and 150 nanometers (including all values and ranges therein, e.g., between about 4 nanometers and 75 nanometers, or between about 5 nanometers and 45 nanometers).
Example 29 provides the IC structure of example 28, wherein a portion of the S/D contact material is in contact with at least one sidewall of the first S/D region.
Example 30 provides an electronic device, comprising: a carrier substrate; and an IC die coupled to the carrier substrate, wherein the IC die comprises a transistor arrangement according to any of examples 1-18 or 27-29, and/or is comprised in an IC package according to any of examples 19-23.
Example 31 provides the electronic device according to example 30, wherein the electronic device is a wearable or handheld electronic device.
Example 32 provides the electronic device of example 30 or 31, wherein the electronic device further comprises one or more communication chips and an antenna.
Example 33 provides the electronic device according to any one of examples 30-32, wherein the carrier substrate is a motherboard.
Example 34 provides the electronic device according to any one of examples 30-33, wherein the electronic device is an RF transceiver.
Example 35 provides an electronic device according to any of examples 30-34, wherein the electronic device is one of a switch, a power amplifier, a low noise amplifier, a filter bank, a duplexer, an upconverter, a downconverter, or logic circuitry (e.g., control logic) of an RF communication device (e.g., an RF transceiver).
Example 36 provides the electronic device according to any one of examples 30-35, wherein the electronic device is included in a base station of a wireless communication system.
Example 37 provides the electronic device according to any one of examples 30-35, wherein the electronic device is included in a UE device (e.g., a mobile device) of a wireless communication system.
The above description of illustrated implementations of the disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications can be made to the present disclosure in light of the above detailed description.
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