阅读说明：本技术 存储器装置 (Memory device ) 是由 叶腾豪 刘逸青 于 2019-02-22 设计创作，主要内容包括：本发明为一种存储器装置,包含：I个存储器区块、多个晶体管单元、I条全局电源线以及I个第一区域驱动模块。各个存储器区块包含：M条栅极控制线以及排列为M列的多个晶体管单元。其中,位于第m列的所述晶体管单元的栅极电连接于第m条栅极控制线。I条全局电源线分别电连接于I个预驱动电路与I个存储器区块。各第一区域驱动模块电连接于各全局电源线与各存储器区块。第一区域驱动模块包含M个第一区域驱动电路。第m个第一区域驱动电路电连接于第m条栅极控制线。(The invention is a memory device, comprising: the memory comprises I memory blocks, a plurality of transistor units, I global power lines and I first area driving modules. Each memory block includes: m gate control lines and a plurality of transistor cells arranged in M columns. And the grid electrode of the transistor unit positioned in the mth column is electrically connected with the mth grid electrode control line. The I global power lines are respectively and electrically connected with the I pre-drive circuits and the I memory blocks. Each first local driving module is electrically connected to each global power line and each memory block. The first area driving module comprises M first area driving circuits. The mth first area driving circuit is electrically connected to the mth gate control line.)

1. A memory device, comprising:

i memory blocks, wherein an ith memory block of the I memory blocks comprises:

m grid control lines; and

the transistor units are arranged in M rows, wherein the grid electrode of the transistor unit positioned in an M-th row is electrically connected with an M-th grid electrode control line in the grid electrode control lines;

i global power lines electrically connected to the I memory blocks respectively; and the number of the first and second groups,

i first local driving modules respectively electrically connected to each of the I global power lines and each of the I memory blocks, wherein an ith first local driving module of the I first local driving modules is electrically connected to an ith global power line of the I global power lines and the ith memory block, and the ith first local driving module includes:

the M first area driving circuits are commonly connected with the ith global power line, and an mth first area driving circuit in the M first area driving circuits is electrically connected with the mth gate control line, wherein M, M, I and I are positive integers, M is less than or equal to M, and I is less than or equal to I.

2. The memory device of claim 1, further comprising:

a de-multiplexing circuit having an input line and I block select lines, wherein each of the I block select lines corresponds to each of the I memory blocks, and the de-multiplexing circuit determines a logic level of the I block select lines according to an input signal received from the input line, wherein one of the I block select lines has a first logic level and (I-1) of the I block select lines has a second logic level; and the number of the first and second groups,

a pre-driver module electrically connected to the de-multiplexing circuit, comprising:

the I pre-driving circuits are respectively and electrically connected with each I block selection line and each I first area driving module, wherein each I pre-driving circuit generates I pre-driving voltages according to the logic level of each I block selection line, and each I pre-driving voltage is transmitted to each I first area driving module.

3. The memory device of claim 2,

when the input signal represents that the ith memory block is selected, an ith block selection line in the I block selection lines has the first logic level, and the ith global power line has a first power voltage; and

when the input signal indicates that the ith memory block is unselected, the ith block selection line has the second logic level, and the ith global power line has a second power voltage, wherein

The first power voltage is higher than a reading voltage, a writing voltage and an erasing voltage; and the second power voltage is lower than the read voltage, the write voltage and the erase voltage.

4. The memory device of claim 3, wherein an ith pre-driver circuit of the I pre-driver circuits comprises:

a first pre-driving transistor electrically connected to the ith block selection line;

a second pre-driver transistor electrically connected to the first pre-driver transistor and the ith global power line, wherein the second pre-driver transistor receives the first power voltage from a first voltage source; and

a third pre-driver transistor electrically connected to the first pre-driver transistor and the ith global power line, wherein the third pre-driver transistor receives the second power voltage from a second voltage source.

5. The memory device according to claim 4, wherein when the ith block select line has the first logic level, the first pre-driver transistor and the second pre-driver transistor are turned on, and the third pre-driver transistor is turned off, wherein the first power voltage is transmitted to the ith global power line through the second pre-driver transistor and the first pre-driver transistor; and

when the ith block selection line has the second logic level, the first pre-driving transistor and the second pre-driving transistor are turned off, and the third pre-driving transistor is turned on, wherein the second power voltage is transmitted to the ith global power line through the third pre-driving transistor.

6. The memory device of claim 1, wherein the transistor cells comprise J x K memory cell transistors, J series transistors, and J ground select transistors, wherein the memory cell transistors are arranged in J rows and K columns, and the gate control line comprises:

j serial selection lines respectively electrically connected to the gates of the J serial transistors;

k word lines, wherein a kth word line of the K word lines is electrically connected to gates of the J memory cell transistors on a kth column of the K columns; and

p ground select lines electrically connected to the gates of each of the J ground select transistors, where M ═ J + K + P, K is greater than J, and J is greater than or equal to P, where J, K and P are positive integers.

7. The memory device according to claim 1, wherein the mth first local driving module is a local transistor, a gate of the local transistor is electrically connected to the ith global power line, and a source of the local transistor is electrically connected to the mth gate control line.

8. The memory device of claim 1, wherein the memory device further comprises 2 x I floating lines, wherein each of the I memory blocks corresponds to two of the floating lines.

9. The memory device of claim 8, wherein two floating wires corresponding to the i-th memory block are disposed at both sides of the i-th global power line.

10. The memory device of claim 1, further comprising:

i second local driving modules respectively electrically connected to each of the I global power lines and each of the I memory blocks, wherein an ith second local driving module of the I second local driving modules is electrically connected to the ith global power line and the ith memory block, and the ith second local driving module includes:

m second local driving circuits electrically connected to the ith global power line, and an M-th one of the M second local driving circuits electrically connected to the M-th gate control line,

the ith first area driving circuit is located at one side of the ith memory block, and the ith second area driving module is located at the other side of the ith memory block.

Technical Field

The present invention relates to a memory device, and more particularly, to a memory device that provides a high voltage to a memory block using a global power line.

Background

Please refer to fig. 1, which is a schematic diagram of a three-dimensional memory structure. The three-dimensional memory has a plurality of layers of character pads WLPad stacked in a vertical direction (z direction). The character pads WLPad [ k-1], WLPak [ k ], and the ground selection layer GSL have a plurality of finger structures on both sides. In addition, parallel stripe-shaped serial selection lines SSL [ j-1], SSL [ j +1] are disposed above the corresponding positions of the word lines WL. The bit lines BL [ n ], BL [ n +1] extend in the z-direction parallel to the upper side and the lower side of the string select lines SSL [ j-1], SSL [ j +1 ]. The intersection of each bit line BL [ n ], BL [ n +1] and serial selection line SSL [ j-1], SSL [ j +1] is a serial selection transistor (SSM), and the intersection of the bit line BL [ n ], BL [ n +1] and word line WL is a memory cell transistor (MC); the intersections of the bit lines BL [ n ], BL [ n +1] and the Ground select layer GSL are Ground select transistors (GSM). Herein, a direction parallel to the serial select line SSL is defined as an x-direction; and, a direction parallel to the bit line BL is defined as a y direction.

Please refer to fig. 2, which is a schematic diagram of a global word line GWL and a word pad WLPad in a three-dimensional memory structure. In the three-dimensional memory structure, word lines WL may include Global Word Lines (GWL) GWL [ k-1], GWL [ k +1], and word pads WLPad [ k-1], WLPad [ k +1] disposed corresponding to memory blocks (Block, Blk). The word pads WLPad [ k-1], WLPad [ k +1] are overlapped with each other in a ladder structure (cascade), and global word lines GWL [ k-1], GWL [ k +1] are electrically connected to the multi-layer word pads WLPad [ k-1], WLPad [ k +1], respectively.

In these word lines WL, the resistances R and capacitances C of global word lines GWL [ k-1], GWL [ k ], and GWL [ k +1] using metal wires are very small, and the resistances R and capacitances C of word pads WLpad [ k-1], WLpad [ k ], and WLpad [ k +1] using polysilicon (poly-silicon) are large. Therefore, the RC delay (RC delay) of the word line WL is mainly determined by the areas of the word pads WLpad [ k-1], WLpad [ k +1 ].

In consideration of increasing the capacity of the memory device, it is often necessary to increase the number of layers of the word pads WLPad [ k-1], WLPad [ k +1 ]. Based on the process constraints, the size of the stair-step structure for connecting the word pads WLPad [ k-1], WLPad [ k +1] to the word line WL cannot be reduced as the number of layers of the word pads WLPad [ k-1], WLPad [ k +1] increases. In other words, as the number of layers of the character pads WLPad [ k-1], WLPad [ k +1] increases, the area required for the ladder structure increases, and the areas of the character pads WLPad [ k-1], WLPad [ k +1] also increase. However, the larger the area of the word pads WLpad [ k-1], WLpad [ k +1], the longer the RC delay of the word line WL. In fig. 2, the interdigitated portion of the character pad is defined as a segment (segment) 10. The main source of RC delay in charging up word line WL is the section 10 between every two word pads WLpad [ k-1], WLpad [ k +1 ]. In other words, the size of the sector 10 is left to right the rc delay of the word line WL.

Please refer to fig. 3A and 3B, which are schematic diagrams illustrating the increase of WLPad area of the word pad and the increase of capacitance C and resistance R of the word pad with the increase of memory capacity. Referring to fig. 3A and 3B, fig. 3A shows that when the number of character pad layers WLPad is small, the area of the character pad WLPad and the area occupied by the ladder structure STRl are small; fig. 3B shows that when the number of character pad layers WLPad is larger, the area of the character pad WLPad and the area occupied by the ladder STR2 are larger. From this, it can be seen that the increase in the area of the character pads WLPad [ k-1], WLPad [ k +1] corresponds to an increase in the capacitance C across the character pads WLPad [ k-1], WLPad [ k +1], and an increase in the resistance R of the respective character pads WLPad [ k-1], WLPad [ k +1 ].

For the NAND flash memory, a high voltage (e.g., 20V-25V) is required to be provided through the word line WL when the memory block Blk is programmed (erase operation or write operation). However, as the resistance R and the capacitance C of the word pad WLPad increase, the rc delay effect becomes more pronounced. In other words, it is less easy for the memory controller to pull up the word line WL to the required voltage quickly.

Disclosure of Invention

The invention relates to a memory device, which can quickly pull up the voltage of a word line WL by providing a high voltage for a selected memory block in a mode of correspondingly arranging a global power line on the memory block.

According to an aspect of the present invention, a memory device is provided. The memory device includes: the memory comprises I memory blocks, I global power lines and I first area driving modules. The ith memory block of the I memory blocks comprises: m gate control lines, and a plurality of transistor cells. The transistor units in the memory block are arranged in M columns, wherein the grid electrodes of the transistor units positioned in the mth column are electrically connected to the mth grid control line in the grid control lines. The I global power lines are respectively and electrically connected with the 1 pre-drive circuit and the I memory blocks. The I first region driving modules are respectively and electrically connected with the I global power lines and the I memory blocks. The ith first local drive module in the I first local drive modules is electrically connected with the ith global power line in the I global power lines and the ith memory block. The ith first area driving module comprises: m first area driving circuits. The M first area driving circuits are commonly connected with the ith global power line, and the mth first area driving circuit in the M first area driving circuits is electrically connected with the mth gate control line. Wherein M, M, I and I are positive integers, M is less than or equal to M, and I is less than or equal to I.

In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized below, may be had by reference to the appended drawings, in which:

drawings

FIG. 1 is a schematic diagram of a three-dimensional memory structure.

Fig. 2 is a schematic diagram of a global word line GWL and a word pad WLPad in a three-dimensional memory structure.

Fig. 3A and 3B are schematic diagrams illustrating increase of WLPad area of the word pad and further increase of capacitance C and resistance R of the word pad with increase of memory capacity.

FIG. 4 is a schematic diagram of a memory device according to an embodiment of the invention.

FIG. 5 is a schematic diagram illustrating a connection relationship between global power lines GPL arranged in a plurality of memory blocks according to the memory device of the embodiment of the invention.

Fig. 6 is a schematic diagram illustrating a connection relationship among the corresponding pre-driver circuits PC [ i ], the area driver modules a, and the area driver modules B, taking the memory block Blk [ i ] as an example.

Fig. 7A and 7B are schematic diagrams illustrating an operation mode of the pre-driver circuit.

Fig. 8 is a schematic diagram illustrating a global power line GPL provided in a three-dimensional memory structure, which shows an example of a gate control line GCL provided by a word line.

Fig. 9 is a schematic diagram illustrating how the global power line GPL is connected to the serial select transistor SSM and the memory cell transistor MC through the gate control line GCL.

FIG. 10A is a schematic diagram of a memory string with a bottom source string connection.

FIG. 10B is a schematic diagram of a memory structure when the memory strings are connected in a bottom source string manner.

FIG. 11 is a top view of a memory block with bottom source serial connections for an electrical memory string.

Fig. 12A is a schematic diagram of a plurality of gate control lines GCL provided in one memory block.

Fig. 12B is a schematic diagram of the global power line GPL and the floating lines disposed in one memory block.

Fig. 13 is a schematic diagram of the memory block shown in fig. 11, together with the gate control line GCL of fig. 12A, and the global power line GPL and the floating line of fig. 12B.

FIG. 14A is a schematic diagram of a memory chain connected in a U-shaped serial manner.

FIG. 14B is a schematic diagram of a memory structure when the memory serial adopts a U-type serial connection mode.

FIG. 15 is a top view of a memory block with a U-shaped serial connection for a memory chain.

Fig. 16 is a schematic diagram of the memory block shown in fig. 15, together with the gate control line GCL of fig. 12A, and the global power line GPL and the floating line of fig. 12B.

FIG. 17 is a diagram of a memory device according to an embodiment of the invention, with multiple memory blocks.

Fig. 18A is a top view of a plurality of memory blocks.

Fig. 18B is a schematic diagram of the memory block of fig. 18A, together with a gate control line GCL, a global power line GPL, and a floating line.

Reference numerals:

ground selection layer GSL

Serial selection lines SSL [ j-1], SSL [ j +1], SSL [ i ] [ j ]

Serial select transistor SSM

Bit lines BL [ n ], BL [ n +1]

Capacitor C, C1, C2

Character pads WLpad [ k-1], WLpad [ k +1], WL [2], WL [3], WL [4], WL [5]

Word lines WL [ K ], WL [1], WL [ K ], WL [2], WL [3], WL [4], WL [ j, 1], WL [ j, K ], WL [ j +1, 1], WL [ j +1, K ], WL [ K/2+1], WL [ K-1]

Global word lines GWL [ k-1], GWL [ k +1]

Segment 10, seg [ i ] [1], seg [ i ] [2], seg [1] [1], seg [ i ] [2], seg [ i ] [3], seg [ i ] [4]

Stepped structure STR1 and STR2

Memory device 20

De-multiplexing circuit 21

Pre-drive module 23

Area drive group a 25a

Area drive group B25B

Memory array 27

Page buffer circuit 29

Zone drive modules LMa [1], LMa [ I ], LMa [ I-1]

Zone drive modules LMb [1], LMb [ I ], LMa [ I ], LMb [ I-1]

Input line (signal) Sin

Memory blocks BLK [1], BLK [ I ], BLK [ I ], BLK [2]

Global power lines GPL [1] -GPL [ I ], GPL [ I ]

Block select lines (signals) Ssel [1], Ssel [2], Ssel [ I ]

Floating connection lines Sfla [1], Sflb [1], Sfla [ I ], Sflb [ I ], Sfla [ I ] and Sflb [ I ]

Gate control lines GCL [1] [1] GCL [1] [ M ], GCL [ I ] [1] GCL [ I ] [ M ], GCL [ I ] [1] GCL [ I ] [ M ], GCL [ I-1] [1], GCL [ I-1] [ M ]

The area driving circuits LCa [ i ] [1], LCa [ i ] [2], LCa [ i ] [3], LCa [ i ] [ M-1], LCa [ i ] [ M ], LCb [ i ] [1], LCb [ i ] [2], LCb [ i ] [3], LCb [ i ] [ M-1], and LCb [ i ] [ M ]

Memory serials ST [ i ] [ j-1], ST [ i ] [ j ], ST [ j +1]

Ground selection lines GSL [ i ] [ p ], GSL [ j, p ], GSL [ j +1, p ], GSL

Predrive transistors M1, M2, M3

Predrive circuits PC [ i ], PC [ i-1]

Predrive voltage Spre [ i ]

A first power supply voltage Vpp

Second power supply voltage Vss

Currents i1, i2

Ground-character pads GSL _ WLPad [ i ] [1], GSL _ WLPad [ i ] [2], GSL _ WLPad [1] [1], GSL _ WLPad [1] [2], GSL _ WLPad [1] [3]

Serial-character pads SSL _ WLPad [ i ] [1], SSL _ WLPad [1] [2], SSL _ WLPad [1] [3]

Detailed Description

Please refer to fig. 4, which is a schematic diagram of a memory device according to an embodiment of the invention. The memory device 20 includes: a de-multiplexing circuit 21, a pre-driver module 23, a region driver group A25 a, a region driver group B25B, a page buffer circuit 29, I global power lines GPL [1] GPL [ I ], and a memory array 27. For ease of illustration, it is assumed herein that the memory array 27 includes memory blocks Blk [1] -Blk [ I ], and that each memory block Blk includes one or more memory pages (pages). Each of the memory blocks Blk [1] to Blk [ I ] corresponds to a global power line GPL [1] to GPL [ I ], respectively. For example, the memory block Blk [ i ] corresponds to the global power line GPL [ i ].

The de-multiplexing circuit 21 is electrically connected to the pre-driving module 23, and the pre-driving module 23 is electrically connected to the local driving group a 25a and the local driving group B25B through I global power lines GPL. The page buffer circuit 29 is electrically connected to the memory array 27. For convenience of explanation, the respective wirings and signals on the wirings are denoted by the same reference numerals in the following. For example, Ssel is used to indicate the block select line and the block select signal, and the rest signals and the wiring are labeled in the same way.

Referring to fig. 5, a schematic diagram of a memory device according to an embodiment of the invention is shown in which a global power line GPL is disposed between a local driving module and a memory block. The de-multiplexing circuit 21 has an input line Sin and I block selection lines Ssel [1] to Ssel [ I ]. The de-multiplexing circuit 21 receives an input signal Sin from the memory controller for determining which of the memory blocks Blk [1] Blk [ I ] is used for access. Therefore, the block selection signals Ssel [1] to Ssel [ I ] generated by the de-multiplexing circuit 21 correspond to the memory blocks Blk [1] to Blk [ I ], respectively.

When the block selection signal Ssel [ i ] represents that the memory block Blk [ i ] is selected, the ith selection line Ssel [ i ] has a first logic level (e.g., a logic low level L). When the block select signal Ssel [ i ] represents that the memory block Blk [ i ] is unselected, the block select line Ssel [ i ] has a second logic level (e.g., a logic high level H).

The pre-driving module 23 includes pre-driving circuits PC [1] to PC [ I ] for receiving block selection signals Ssel [1] to Ssel [ I ] corresponding to the memory blocks Blk [1] to Blk [ I ], respectively. The pre-driving circuits PC [1] to PC [ I ] receive block selection signals Ssel [1] to Ssel [ I ] and respectively output pre-driving voltages Spre [1] to Spre [ I ] correspondingly.

According to the idea of the present invention, global power lines GPL [1] GPL [ I ] are provided for each memory block Blk [1] Blk [ J ], respectively. These global power supply lines GPL [1] to GPL [ I ] are used to transmit pre-drive voltages Spre [1] to Spre [ I ]. In addition, floating lines Sfla and Sflb are respectively arranged on two sides of each global power line GPL [1] -GPL [ I ]. For example, floating connection lines Sfla [1] and Sflb [1] are arranged on two sides of a global power line GPL [1 ]; and floating lines Sfla [ I ] and Sflb [ I ] are arranged on two sides of the global power line GPL [ I ]. In addition, each of the memory blocks Blk [1] -Blk [ J ] includes M gate control lines GCL. For example, the memory block Blk [1] includes gate control lines GCL [1] [1] to GCL [1] [ M ]; the memory block Blk [ I ] includes gate control lines GCL [ I ] [1] to GCL [ I ] [ M ].

The region drive group A25 a includes region drive modules LMa [1] to LMa [ I ] corresponding to the memory blocks Blk [1] to Blk [ I ]; the region driving module B25B includes region driving modules LMb [1] to LMb [ I ] corresponding to the memory blocks Blk [1] to Blk [ I ]. The area driving modules LMa [1] to LMa [ I ] receive pre-driving voltages Spre [1] to Spre [ I ] generated by the pre-driving circuits PC [1] to PC [ I ] through global power lines GPL [1] to GPL [ I ] respectively, and the area driving modules LMb [1] to LMb [ I ] receive the pre-driving voltages Spre [1] to Spre [ I ] generated by the pre-driving circuits PC [1] to PC [ I ] through global power lines GPL [1] to GPL [ I ] respectively.

Please refer to fig. 6, which is a schematic diagram illustrating a connection relationship among the pre-driver circuits PC [ i ], the local driver modules LMa [ i ], and the local driver modules LMb [ i ] corresponding to the memory blocks Blk [ i ], as an example. The memory block Blk [ i ] is electrically connected to the pre-driver circuit PC [ i ] via the global power line GPL [ i ]. In addition, floating connection lines Sfla [ i ] and Sflb [ i ] are arranged on two sides of the global power line GPL [ i ].

The area driving module LMa [ i ] comprises M area driving circuits LCa [ i ] [1] to LCa [ i ] [ M ]; the area driving module LMb [ i ] includes M area driving circuits LCb [ i ] [1] to LCb [ i ] [ M ]. The area driving circuits LCa [ i ] [1] to LCa [ i ] [ M ] are connected to the global power line GPL [ i ] through a common wiring; and the area driving circuits LCb [ i ] [1] to LCb [ i ] [ M ] are connected to the global power supply line GPL [ i ] through another common wiring.

The memory block Blk [ i ] includes: and gate control lines GCL [ i ] [1] to GCL [ i ] [ M ]. Among them, some of the grid control lines GCL [ i ] [1] GCL [ i ] [ M ] are serial selection lines SSL [ i ] [1] SSL [ i ] [ J ], some are word lines WL [1] WL [ K ], and some are ground selection lines GSL [ i ] [1] GSL [ i ] [ P ] (only GSL [ i ] [ P ] is shown in FIG. 6). The area driving circuits LCa [ i ] [1] to LCa [ i ] [ M ] are electrically connected to the gate control lines GCL [ i ] [1] to GCL [ i ] [ M ] respectively; the area driving circuits LCb [ i ] [1] to LCb [ i ] [ M ] are also electrically connected to the gate control lines GCL [ i ] [1] to GCL [ i ] [ M ], respectively.

The pre-driver circuits PC [1] to PC [ I ] have similar structures to each other, and only the pre-driver circuit PC [ I ] is taken as an example here. The pre-drive circuit PC [ i ] includes: pre-drive transistors M1, M2, M3. The pre-driving transistors M1, M2, and M3 are all high voltage tolerant transistors. The pre-driving transistor M1 is a PMOS transistor, the pre-driving transistors M2 and M3 are NMOS transistors, and the pre-driving transistor M2 is a depletion mode transistor. The pre-drive transistor M3 may be a normal NMOS transistor or a triple-well NMOS transistor.

The pre-driver transistor M1 is electrically connected to the block select line Ssel [ i ]; the pre-driving transistor M2 is electrically connected to the pre-driving transistor M1 and the global power line GPL [ i ]. The pre-driving transistor M2 receives the first power supply voltage Vpp from the first voltage source Vpp. The pre-driving transistor M3 is electrically connected to the pre-driving transistor M1 and the global power line GPL [ i ]. The pre-drive transistor M3 receives the second power supply voltage Vss from the second voltage source Vss. The source terminal and the body terminal (body) of the pre-driving transistor M1 are electrically connected to each other, and the drain terminal of the pre-driving transistor M1 and the gate terminal of the pre-driving transistor M2 are electrically connected to the global power line GPL [ i ] in common.

In the embodiment of the invention, the first power supply voltage Vpp is higher than the read voltage Vrd of the memory, the write voltage Vwr of the memory and the erase voltage Vers of the memory. The second power supply voltage Vss is lower than the read voltage Vrd of the memory, the write voltage Vwr of the memory, and the erase voltage Vers of the memory. In some applications, the read voltage Vrd and the erase voltage Vers may be lower than the ground voltage (0V). Meanwhile, the second power voltage Vss is a negative voltage. Due to the fact that the second power supply voltage Vss is still maintained at the lowest potential, abnormal forward-on (forward-on) of the transistor can be avoided. In addition, all NMOS transistors with their bases connected to the negative voltage Vss need to use triple-well NMOS transistors, such as the local driving circuits LCa and LCb and the pre-driving transistor M3. Accordingly, other NMOS transistors of the same memory device can be prevented from being affected.

Before the memory controller selects any one of the memory blocks Blk [1] to Blk [ I ], the block selection lines Ssel [1] to Ssel [ I ] output by the de-multiplexing circuit 21 all have a logic high level H. Assuming that the memory controller selects the memory block Blk [ I ], the block selection line Ssel [ I ] output by the de-multiplexing circuit 21 is at a logic low level L, and the block selection lines Ssel [1] -Ssel [ I-1], Ssel [ I +1] -Ssel [ I ] are at a logic high level H. The logic high level H may be 4V and the logic low level L may be 0V.

Please refer to fig. 7A and 7B, which are schematic diagrams illustrating operation modes of the pre-driver circuit PC [ i ] corresponding to the memory block Blk [ i ]. FIG. 7A shows a case where the memory block Blk [ i ] is unselected; FIG. 7B shows the selected memory block Blk [ i ]. As can be seen from fig. 7A and 7B, the pre-driving transistor M1 receives the first power voltage Vpp (e.g., 30V) and the pre-driving transistor M3 receives the second power voltage Vss regardless of whether the memory block Blk [ i ] is selected.

In fig. 7A, the pre-drive transistor M3 receives the second power supply voltage Vss for pre-charging; the pre-driving transistor M1 receives the first power voltage Vpp, and the voltage of the pre-charging node Npre is the second power voltage Vss. Since the block select line Ssel [ i ] has a logic high level H, the pre-drive transistor M1 remains off, and the pre-drive transistor M2 also remains off. At this time, only the pre-driving transistor M3 is turned on.

Therefore, when the memory block Blk [ i ] is not selected, the pre-driving circuit PC [ i ] generates a displacement current (displacement current) i1 due to the internal charge imbalance. Therefore, the voltage (pre-drive voltage) Spre [ i ] on the pre-drive signal line connected to the pre-charge node Npre is the second power supply voltage Vss transferred to the global power supply line GPL [ i ] via the pre-drive transistor M3. In conjunction, both of the region driving modules LMa [ i ], LMb [ i ] corresponding to the memory blocks Blk [ i ] receive the second power supply voltage Vss from the global power supply line GPL [ i ]. Therefore, the memory block Blk [ i ] does not perform various memory operations. Incidentally, the displacement current i1 does not continue to be generated. Once the potential reaches equilibrium (Spre ═ Vss), the displacement current disappears.

In fig. 7B, the pre-drive transistor M3 receives the second power supply voltage Vss for pre-charging; the pre-driving transistor M1 receives the first power supply voltage Vpp, and the voltage of the pre-charging node Npre is the second power supply voltage Vss at the very beginning. When the block select line Ssel [ i ] has a logic low level L, the threshold voltage Vth of the pre-driving transistor M2 is less than 0V because it is a depletion transistor, so that the pre-driving transistor M2 is partially turned on.

For the pre-drive transistor M1, the pre-drive transistor M1 will start to form a weak conduction (weak turn-on) because the gate receives the voltage of the low logic level L and the source gradually receives the first power supply voltage Vpp through the pre-drive transistor M2. When the pre-driving transistor M1 is turned on, the source voltage of the pre-driving transistor M1 is transmitted to the drain of the pre-driving transistor M1, i.e., the pre-charge node Npre. The voltage at the pre-charge node Npre will drive the gate voltage of the pre-driving transistor M2 to make the pre-driving transistor M2 turn on more completely, so as to form a positive feedback effect of conducting current between the pre-driving transistors M1 and M2.

At this time, the pre-driving transistors M1 and M2 are turned on, and the voltage of the pre-charge node Npre is raised to the first power supply voltage Vpp. At the same time, the pre-drive transistor M3 is off. In this case, the gate of the pre-driving transistor M1 is connected to 0V, and the source and N-well (well) of the pre-driving transistor M1 are connected to the first power voltage Vpp. Therefore, the pre-driving transistor M1 needs to use a transistor with a higher breakdown voltage. For example, the gate oxide (oxide) of the pre-driver transistor M1 needs to be thicker than that of a general PMOS transistor.

The pre-driver circuit PC [ i ] generates a displacement current i2 when the memory block Blk [ i ] is selected. Therefore, the voltage (pre-driving voltage) Spre [ i ] on the pre-driving signal line connected to the pre-charge node Npre is the first power supply voltage Vpp. Since the pre-driving voltage Spre [ i ] is connected to the global power line GPL [ i ], both the region driving blocks LMa [ i ], LMb [ i ] corresponding to the memory block Blk [ i ] will receive the first power voltage Vpp from the global power line GPL [ i ]. Therefore, the memory controller can control the selected memory block Blk [ i ] to perform various memory operations.

As mentioned above, when the block select line Ssel [ i ] output by the de-multiplexing circuit 21 has a logic low level L, the representative memory block Blk [ i ] is selected. At this time, the pre-driving circuit PC [ i ] outputs the first power voltage Vpp to the global power line GPL [ i ] corresponding to the memory block Blk [ i ]. When the block select line Ssel [ i ] output by the de-multiplexing circuit 21 has a logic high level H, it represents that the memory block Blk [ i ] is unselected. At this time, the pre-driving circuit PC [ i ] outputs the second power supply voltage Vss to the global power supply line GPL [ i ] corresponding to the memory block Blk [ i ].

Since the first power voltage Vpp is the highest voltage provided by the memory device, in order to prevent the high voltage of the global power line GPL [ i ] corresponding to the selected memory block Blk [ i ] from forming an excessive voltage difference with the peripheral signal lines, and thus damaging the memory structure, the embodiments of the present invention further provide floating lines Sfla [ i ], Sflb [ i ] on both sides of the global power line GPL [ i ]. The floating lines Sfla [ i ], Sflb [ i ] are arranged to slightly alleviate the influence of the global power line GPL [ i ] with high voltage on other peripheral signal lines.

Please refer to fig. 8, which illustrates a schematic diagram of a global power line GPL in a three-dimensional memory, illustrating a step structure of a drawing type word pad WLPad. The de-multiplexing circuit 21 is electrically connected to the pre-driving circuit PC [ i ] through a block selection line Ssel [ i ], and the pre-driving circuit PC [ i ] is electrically connected to the local driving module LMa [ i ] and the local driving module LMb [ i ] through a global power line GPL [ i ]. The pre-driving circuit PC [ i ] outputs a pre-driving voltage Spre [ i ] having a level of the first power supply voltage Vpp or the second power supply voltage Vss to the global power supply line GPL [ i ]. It is assumed here that the area driver module LMa [ i ] includes the area driver circuits LCa [ i ] [1] to LCa [ i ] [5] and the area driver module LMb [ i ] includes the area driver circuits LCb [ i ] [1] to LCb [ i ] [5 ]. The area driving circuit LCa [ i ] [1] and the area driving circuit LCb [ i ] [1] are electrically connected to a character pad WLPad [ i ] [1] in a ladder structure; the area driving circuit LCa [ i ] [2] and the area driving circuit LCb [ i ] [2] are electrically connected to the character pad WLPad [ i ] [2] in the ladder structure; and the rest is analogized.

As described above, in addition to the word lines WL [1] -WL [ K ], some of the gate control lines GCL [1] -GCL [ M ] may be the serial select lines SSL [1] -SSL [ J ] and the ground select lines GSL [ i ] [1] -GSL [ i ] [ P ]. The jth memory string ST [ i ] [ j ] of the memory block Blk [ i ] includes a string selection transistor SSM [ i ] [ j ], K memory cell transistors MC [ i ] [ j ] [1] to MC [ i ] [ j ] [ K ], and a ground selection transistor GSM [ i ] [ j ]. The memory cell transistors MC [ i ] [ j ] [1] to MC [ i ] [ j ] [ K ] may be nonvolatile memories such as floating gate transistors or charge trapping devices. In actual use, the types of the memory cell transistors MC [ i ] [ j ] [1] to MC [ i ] [ j ] [ K ] are not necessarily limited.

Please refer to fig. 9, which is a schematic diagram illustrating how the global power line GPL [ i ] is connected to the serial select transistor SSM and the memory cell transistor MC via the gate control line GCL. This figure schematically illustrates the relationship between the transistor cells and the various types of wiring in the memory block Blk [ i ].

The memory block Blk [ i ] includes memory strings ST [ i ] [1] to ST [ i ] [ J ], and here, only the memory string ST [ i ] [ J-1] and the memory string ST [ i ] [ J ] in the memory block Blk [ i ] are taken as an example. The memory series ST [ i ] [ j-1] includes: a serial selection transistor SSM [ i ] [ j-1], K memory cell transistors MC [ i ] [ j-1] [1] to MC [ i ] [ j-1] [ K ] connected to word lines WL [1] to WL [ K ], and a ground selection transistor GSM [ i ] [ j-1 ]. The memory series ST [ i ] [ j ] includes: a serial selection transistor SSM [ i ] [ j ], K memory cell transistors MC [ i ] [ j ] [1] MC [ i ] [ j ] [ K ] connected to word lines WL [1] WL [ K ], and a ground selection transistor GSM [ i ] [ j ].

Accordingly, the memory strings ST [ i ] [ J ] (where J is 1 to J) in the memory block Blk [ i ] correspond to one string selection transistor SSM [ i ] [ J ], K memory cell transistors MC [ i ] [ J ] [1] to MC [ i ] [ J ] [ K ], and one ground selection transistor GSM [ i ] [ J ]. The gates of the ground select transistors GSM [ i ] [ j-1], GSM [ i ] [ j ] in different strings of the memory block Blk [ i ] are commonly connected to P ground select lines GSL [ i ] [1] -GSL [ i ] [ P ]. For convenience of explanation, P is assumed to be 1. In addition, the ground select transistors GSM [ i ] [ j-1], GSM [ i ] [ j ] in different strings of the memory block Blk [ i ] are all electrically connected to the same common source line (CSL [ i ]).

On the other hand, if P ≠ 1, then J memory strings can be divided into P string groups, where J may be greater than or equal to P. The gates of the ground select transistors GSM [ i ] [ j ] in the memory strings belonging to the same serial group are commonly connected to the same ground select line GSL [ i ] [ p ]. For example, assuming that J is an even number and P is 2, J memories may be serially divided into 2 serial groups. Wherein the first serial group includes memory serial ST [ i ] [1] to ST [ i ] [ J/2 ]; the second serial group includes memory serials ST [ i ] [ J/2+1] to ST [ i ] [ J ]. Accordingly, the gates of the ground selection transistors GSM [ i ] [1] to GSM [ i ] [ J/2] belonging to the memory strings ST [ i ] [1] to ST [ i ] [ J/2] are commonly connected to the ground selection line GSL [ i ] [1 ]; the gates of ground selection transistors GSM [ i ] [ J/2+1] to GSM [ i ] [ J ] belonging to the memory strings ST [ i ] [ J/2+1] to ST [ i ] [ J ] are commonly connected to a ground selection line GSL [ i ] [2].

It should be noted that, for the convenience of describing the connection relationship between the transistor units and the local driving circuits LCa, LCb, the heights of the string selection transistors SSM of the memory strings ST [ j-1], ST [ j ] are not the same. However, in the memory process, the actual heights of the string select transistors SSM of the memory strings ST [ j-1], ST [ j ] are equal to each other.

According to the connection mode of the memory serial ST, the flash memory can be divided into two connection modes: the bottom source (bottom) serial connection mode and the U-turn serial connection mode. The embodiment of the invention can be arbitrarily matched with the flash memories adopting the two serial connection modes for use. As mentioned above, the memory block Blk [ i ] may include J memory ranks divided into P groups. For the bottom source serial connection, the ground select line GSL is located at the bottom of the memory structure, so the memory serial is usually divided into two groups in the memory process, i.e. P is 2. On the other hand, for the U-type serial connection, the ground selection line GSL may be cut into any different equal parts (P may be any positive integer) by using a shallow etching method, and the memory serial of the U-type serial connection may be freely grouped in the process.

Please refer to fig. 10A, which is a schematic diagram of a transistor with a bottom source serial connection. When the memory serial ST adopts a bottom source serial connection mode, each row of transistors form one memory serial ST. This figure contains two memory strings ST [ j ], ST [ j +1 ]. The memory serial ST [ j ] comprises a serial selection transistor SSM electrically connected with a serial selection line SSL [ j ], K memory cell transistors MC respectively electrically connected with word lines WL [ j, 1] -WL [ j, K ], and a grounding selection transistor GSM [ j ] electrically connected with a grounding selection line GSL [ j, p ]; the memory string ST [ j +1] includes a string select transistor SSM electrically connected to a string select line SSL [ j +1], K memory cell transistors MC electrically connected to word lines WL [ j +1, 1] -WL [ j +1, K ], respectively, and a ground select transistor GSM [ j +1] electrically connected to a ground select line GSL [ j +1, p ]. In this figure, word lines WL [ j, 1] -WL [ j, K ] corresponding to a memory string ST [ j ] and word lines WL [ j +1, 1] -WL [ j +1, K ] corresponding to a memory string ST [ j +1] belong to two different groups of word pads WLpad. Similarly, the ground selection lines GSL [ j, p ] corresponding to the memory series ST [ j ], and the ground selection lines GSL [ j +1, p ] corresponding to the memory series ST [ j +1] are divided into two independent ground selection layers GSL.

Please refer to fig. 10B, which is a schematic diagram of a memory structure when the memory string adopts the bottom source string connection mode. The character pad WLpad and the grounding selection layer GSL are arranged in parallel, and the serial selection lines SSL [ j ], SSL [ j +1], SSL [ j +2] and SSL [ j +3] are arranged above the character pad WLpad and the grounding selection layer GSL in a strip-shaped staggered mode.

Please refer to fig. 11, which is a top view of a memory block when the memory string adopts the bottom source string connection mode. The memory block Blk [ i ] may include a plurality of serial select-word pads esl _ WLPad, oSSL _ WLPad. Wherein the serial select-character pad eSSL _ WLPad is used to form a serial at an even row; the serial select-character pad oSSL WLPad is used to form the serial at odd rows. The serial select-word pad eSSL _ WLPad and the serial select-word pad oSSL _ WLPad are interleaved with each other in a finger-like structure. The staggered arrangement of the serial select-word pad eSSL _ WLPad and the serial select-word pad oSSL _ WLPad is the sections seg [1], seg [2] in the bottom source serial connection mode. In addition, above and below the memory block Blk [ i ], there is a common source plate (CSL plate) for connecting the source of the ground selection transistor GSM.

Please refer to fig. 12A, which is a schematic diagram of a plurality of gate control lines GCL disposed in the memory block Blk [ i ]. As previously described, the gate control lines GCL [ i ] [1] -GCL [ i ] [ M ] may be the serial select line SSL, the word line WL, or the ground select line GSL.

Please refer to fig. 12B, which is a diagram illustrating a global power line GPL and a floating line disposed in a memory block Blk [ i ]. The global power line GPL [ i ] and the floating lines Sfla [ i ], Sflb [ i ] are arranged in parallel, and the floating lines Sfla [ i ], Sflb [ i ] are respectively positioned at two sides of the global power line GPL [ i ].

The memory block Blk [ i ] of FIG. 11, the gate control lines GCL [ i ] [1] to GCL [ i ] [ M ] of FIG. 12A, and the global power supply line GPL [ i ] of FIG. 12B are combined with the floating lines Sfla [ i ], Sflb [ i ], and a top view corresponding to the memory block Blk [ i ] shown in FIG. 13 can be obtained.

Please refer to fig. 14A, which is a schematic diagram illustrating a U-type serial connection mode for a memory serial. When the memory serial adopts a U-shaped serial connection mode, the transistors in every two rows form a memory serial together. This figure contains a memory serial ST. The memory cell comprises a serial selection transistor SSM electrically connected with a serial selection line SSL, K memory cell transistors MC respectively electrically connected with word lines WL [1] to WL [ K ], and a grounding selection transistor GSM electrically connected with a grounding selection line GSL; and two pass transistors (pass transistors) IWLS, IWLG. The pass transistors IWLS, IWLG are not used for storing data, but are used only for transferring potentials between the memory cell transistors MC. The transfer transistors IWLS, IWLG may be referred to as Inversion Gate (IG) or Inversion Word Line (IWL) alternatively.

The control terminal of the serial select transistor SSM is electrically connected to a serial select line SSL, one terminal is electrically connected to a memory cell transistor MC controlled by a word line WL [1], and the other terminal is electrically connected to a bit line BL. The control terminal of the ground select transistor GSM is electrically connected to the ground select line GSL, one terminal is electrically connected to the memory cell transistor MC controlled by the word line WL [ K ], and the other terminal is electrically connected to the common source line CSL.

Please refer to fig. 14B, which is a schematic diagram of a memory structure when the memory serial adopts a U-type serial connection mode. The word pad WLpad is parallel to the inverted gate layer IG, and the serial select lines SSL [ j ], SSL [ j +1], SSL [ j +2], SSL [ j +3], and the ground select line GSL are arranged above the word pad WLpad in a stripe-like staggered manner. Here, the ground selection lines GSL are connected to each other in the y direction on one side thereof, in addition to being disposed parallel to the x direction.

Please refer to fig. 15, which is a top view of a memory block when the memory chain adopts the U-type serial connection mode. The memory block Blk [ i ] may include a plurality of ground-word pads GSL _ WLPad [ i ] [1], GSL _ WLPad [ i ] [2], and serial-word pads SSL _ WLPad [ i ] [1 ]. The sectors seg [ i ] [1] and seg [ i ] [2] in the U-shaped serial connection mode are formed at the positions where the ground-character pads GSL _ WLPad [ i ] [1], GSL _ WLPad [ i ] [2] and the serial-character pads SSL _ WLPad [ i ] [1] are arranged in a finger-shaped structure in a staggered mode.

After the memory block Blk [ i ] shown in FIG. 15 is combined with the gate control lines GCL [ i ] [1] to GCL [ i ] [ M ] shown in FIG. 12A and the global power line GPL [ i ] shown in FIG. 12B and the floating lines Sfla [ i ] and Sflb [ i ], a top view corresponding to the memory block Blk [ i ] shown in FIG. 16 can be obtained.

Next, the application of the concept of the present invention to multiple memory blocks is further described. According to the embodiment of the present invention, a plurality of sets of global power lines GPL [ I ] may be provided in a plurality of memory blocks Blk [1] Blk [ I ] of the memory device in correspondence with the floating lines Sfla [ I ], Sflb [ I ].

Please refer to fig. 17, which is a schematic diagram illustrating a memory device according to an embodiment of the invention, configured with a plurality of memory blocks. This figure shows the relationship between the arrangement of the global power supply line GPL and the floating lines Sfla, Sflb and the memory block Blk.

For the memory block Blk [ i-1], the de-multiplexing circuit 21 outputs a block selection signal Ssel [ i-1] to the pre-driver circuit PC [ i-1], and the pre-driver circuit PC [ i-1] is electrically connected to the global power line GPL [ i-1 ]. The global power line GPL [ i-1] is further connected to the region driving module A LMa [ i-1] and the region driving module B LMb [ i-1 ]. The area driving circuits LCa [ i-1] [1] to LCa [ i-1] [ M ] included in the area driving module ALMa [ i ] and the area driving circuits LCb [ i-1] [1] to LCb [ i-1] [ M ] included in the area driving module B LMb [ i-1] supply voltages to the gates of the transistor cells through the gate control lines GCL [ i-1] [1] to GCL [ i-1] [ M ], respectively.

For the memory block Blk [ i ], the de-multiplexing circuit 21 outputs a block selection signal Ssel [ i ] to the pre-driving circuit PC [ i ], which is electrically connected to the global power line GPL [ i ]. The global power line GPL [ i ] is further connected to the local driving module A LMa [ i ] and the local driving module B LMb [ i ]. The area driving circuits LCa [ i ] [1] to LCa [ i ] [ M ] included in the area driving module A LMa [ i ] and the area driving circuits LCb [ i ] [1] to LCb [ i ] [ M ] included in the area driving module B LMb [ i ] supply voltages to the gates of the transistor cells through the gate control lines GCL [ i ] [1] to GCL [ i ] [ M ], respectively.

In addition, the sources of the area driving circuits LCa [ i-1] [1] to LCa [ i-1] [ M ] in the area driving module A LMa [ i-1] are electrically connected to the global source lines Sgps [1] to Sgps [ M ], respectively; the sources of the area driving circuits LCa [ i ] [1] to LCa [ i ] [ M ] in the area driving module A LMa [ i ] are electrically connected to the global source lines Sgps [1] to Sgps [ M ], respectively. On the other hand, the sources of the area drive circuits LCb [ i-1] [1] to LCb [ i-1] [ M ] in the area drive module B LMb [ i-1] are electrically connected to the global source lines Sgps [1] to Sgps [ M ], respectively; the sources of the local drive circuits LCb [ i ] [1] to LCb [ i ] [ M ] in the local drive module B LMb [ i ] are electrically connected to the global source lines Sgps [1] to Sgps [ M ], respectively. According to the embodiment of the present invention, the drains of the local driving circuits LCa, LCb in the local driving module A, B are all floating, and their potentials will be equal to the source at last.

Next, fig. 18A and 18B are top views of the memory blocks according to the embodiment of the present invention. As can be seen from fig. 12 to 13 and 15 to 16, when the memory block adopts the bottom source serial connection mode or the U-type serial connection mode, although the positions and the connection relations of the serial select line SSL, the shared source line CSL and the ground select line GSL are slightly different, the positions and the relative relations of the word pad and the serial select line SSL are similar. Therefore, the plurality of memory blocks Blk using the U-type serial connection is only taken as an example here.

Please refer to fig. 18A, which is a top view of a plurality of memory blocks adopting a U-type serial connection. The memory blocks Blk [1] -Blk [ I ] of this figure each have multiple sectors and word pads. For example, the memory block Blk [1] includes ground-word pads GSL _ WLPad [1] [1], GSL _ WLPad [1] [2], GSL _ WLPad [1] [3], and serial-word pads SSL _ WLPad [1] [1], SSL _ WLPad [1] [2]. If the transistor cells belonging to the same memory string are arranged in a U-string connection, the ground-word pads GSL-WLPad and the string-word pads SSL-WLPad are staggered with each other. A segment seg is formed between these ground-word pads GSL _ WLpad [ i ] [1], GSL _ WLpad [ i ] [2] and the serial-word pad SSL _ WLpad [ i ] [1 ]. For example, the memory block Blk [1] includes segments seg [1] [1], seg [1] [2], seg [1] [3], and seg [1] [4 ].

Referring to fig. 18B, the memory block of fig. 18A is shown with a control line GCL, a global power line GPL, and floating lines Sfla and Sflb. This figure illustrates the correspondence between the global power line GPL [ I ] and the floating lines Sfla [ I ], Sflb [ I ] and the memory blocks Blk [ I ], I being 1 to I. For example, global power line GPL [1] and floating lines Sfla [1], Sflb [1] are set for memory block BLK [1 ]; setting global power line GPL [2] and floating lines Sfla [2] and Sflb [2] for memory block BLK [2 ]; a global power line GPL [ I ] and floating lines Sfla [ I ], Sflb [ I ] are provided for a memory block BLK [ I ].

According to the idea of the present invention, one global power line GPL [ i ] and two floating lines Sfla [ i ], Sflab [ i ] are provided for the gate control lines GCL [ i ] [1] to GCL [ i ] [ M ] in the same memory block BLK [ i ]. The gate control lines GCL [ i ] [1] GCL [ i ] [ M ] may be serial select lines SSL [ i ] [1] SSL [ i ] [ J ], word lines WL [ i ] [1] WL [ i ] [ K ], or ground select lines GSL [ i ] [1] GSL [ i ] [ P ]. The number of the transistor cells connected to the gate control lines GCL [ i ] [1] to GCL [ i ] [ M ] in each column varies depending on the gate control lines GCL [ i ] [1] to GCL [ i ] [ M ]. When the grid control line GCL [ i ] [ m ] is the serial selection line SSL, the number of the serial selection transistors SSM connected with the grid control line GCL [ i ] [ m ] is 1; when the gate control lines GCL [ i ] [ m ] are the ground selection lines GSL [ i ] [1] to GSL [ i ] [ P ], the number of ground selection transistors GSM connected to the P ground selection lines is "J/P". When the number of bit lines BL in the memory block Blk [ i ] is represented by N, the number of memory cell transistors MC connected to the gate control line GCL [ i ] [ m ] is "N" when it is the word line WL [ i ] [ k ].

In summary, the present invention can achieve the effect of rapidly increasing the voltage of the gate control line GCL of the selected memory block by providing the global power lines GPL [1], GPL [ 2.. GPL [ I ]. In other words, the RC delay caused by the increase of the pad area can be compensated to reduce the effect.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.