阅读说明：本技术 半导体元件及其制作方法 (Semiconductor element and manufacturing method thereof ) 是由 王慧琳 刘盈成 施易安 李怡慧 翁宸毅 谢晋阳 曾奕铭 张境尹 王裕平 于 2019-02-14 设计创作，主要内容包括：本发明公开一种半导体元件及其制作方法,其中该半导体元件包含一金属氧化物半导体晶体管设于一基底上,一层间介电层设于该金属氧化物半导体晶体管上,以及一磁性隧穿结(magnetic tunneling junction,MTJ)设于该层间介电层上,其中MTJ上表面包含一倒V形且MTJ上表面是电连接至金属氧化物半导体晶体管的一源极/漏极区域。(The invention discloses a semiconductor element and a manufacturing method thereof, wherein the semiconductor element comprises a metal oxide semiconductor transistor arranged on a substrate, an interlayer dielectric layer arranged on the metal oxide semiconductor transistor, and a Magnetic Tunneling Junction (MTJ) arranged on the interlayer dielectric layer, wherein the upper surface of the MTJ comprises an inverted V-shaped MTJ and is electrically connected to a source/drain region of the metal oxide semiconductor transistor.)

1. A semiconductor device, comprising:

a metal oxide semiconductor transistor disposed on the substrate;

an interlayer dielectric layer arranged on the metal oxide semiconductor transistor; and

a Magnetic Tunneling Junction (MTJ) disposed on the interlayer dielectric layer, wherein an upper surface of the MTJ is electrically connected to the source/drain region of the mos transistor.

2. The semiconductor device of claim 1, further comprising:

a first metal interconnection connecting the bottom of the magnetic tunnel junction;

a first inter-metal dielectric layer disposed on the interlayer dielectric layer and surrounding the first metal interconnection;

a second metal interconnection disposed beside the magnetic tunneling junction;

a second inter-metal dielectric layer disposed on the first inter-metal dielectric layer and surrounding the magnetic tunnel junction and the second metal interconnection;

a third metal interconnection connecting the bottom of the first metal interconnection;

a fourth metal interconnection connecting the bottom of the second metal interconnection and the source/drain region of the MOS transistor;

a fifth metal interconnection connecting the top of the MTJ and the second metal interconnection; and

a third IMD layer surrounding the fifth IMD layer.

3. The semiconductor device of claim 2, wherein said second metal interconnect comprises:

a first trench conductor; and

a first contact hole conductor is connected to the bottom of the first trench conductor.

4. The semiconductor device as defined in claim 3, wherein the upper surface of the first trench conductor is flush with the upper surface of the second IMD layer.

5. The semiconductor device of claim 3, wherein said fifth metal interconnect comprises:

a second trench conductor; and

a second contact hole conductor and a third contact hole conductor disposed at the bottom of the second trench conductor, wherein the second contact hole conductor is connected to the first trench conductor and the third contact hole conductor is connected to the magnetic tunneling junction.

6. The semiconductor device as defined in claim 5, wherein the upper surface of the second trench conductor is flush with the upper surface of the third IMD layer.

7. The semiconductor device of claim 5, wherein said second contact hole conductor bottom portion comprises a planar surface.

8. The semiconductor device of claim 5, wherein said third contact hole conductor bottom portion comprises an inverted V-shape.

9. The semiconductor device as defined in claim 1, wherein the upper surface of the magnetic tunnel junction comprises an inverted V-shape.

10. A semiconductor device, comprising:

a Magnetic Tunneling Junction (MTJ) disposed on the substrate, wherein an upper surface of the MTJ comprises an inverted V-shape;

the first gap wall is arranged on the first side wall of the magnetic tunneling junction; and

and the second gap wall is arranged on the second side wall of the magnetic tunneling junction, wherein the first gap wall and the second gap wall are not symmetrical with each other.

11. The semiconductor device of claim 10, further comprising:

a first inter-metal dielectric layer disposed on the substrate; and

the first metal interconnection line is connected with the bottom of the first metal interconnection line and arranged in the first inter-metal dielectric layer.

12. The semiconductor device of claim 11, wherein the magnetic tunneling junction comprises:

a lower electrode disposed on the first metal interconnection line;

a free layer disposed on the lower electrode; and

and an upper electrode disposed on the free layer.

13. The semiconductor device as claimed in claim 12, further comprising a second inter-metal dielectric layer disposed on the first inter-metal dielectric layer and surrounding the magnetic tunnel junction.

14. The semiconductor device of claim 13, further comprising a second metal interconnect disposed over said mtj and said second ild, wherein said second metal interconnect comprises a protrusion contacting a sidewall of said top electrode.

15. The semiconductor device as defined in claim 14, wherein the protrusion contacts the top electrode, the second spacer and the second IMD layer.

16. The semiconductor device as defined in claim 14, wherein the lower surface of the protrusion is higher than the upper surface of the free layer.

17. The semiconductor device of claim 13, further comprising a second metal interconnect disposed over said mtj and said second ild, wherein said second metal interconnect comprises a first protrusion and a second protrusion.

18. The semiconductor device as defined in claim 17, wherein the first protrusion contacts one sidewall of the top electrode and the second protrusion contacts the other sidewall of the top electrode.

19. The semiconductor device as defined in claim 17, wherein the lower surface of the first and second protrusions is higher than the upper surface of the free layer.

20. The semiconductor device as defined in claim 10, wherein the first spacer and the second spacer comprise different heights.

Technical Field

The present invention relates to semiconductor devices and methods for fabricating the same, and more particularly, to a Magnetoresistive Random Access Memory (MRAM) and a method for fabricating the same.

Background

It is known that the Magnetoresistance (MR) effect is an effect of changing the resistance of a material with a change in an applied magnetic field, and the physical quantity is defined as the difference in resistance in the presence or absence of a magnetic field divided by the original resistance to represent the rate of change in resistance. At present, the magnetoresistance effect has been successfully applied to the production of hard disks, and has important commercial application value. In addition, by utilizing the characteristic that giant magnetoresistance materials have different resistance values in different magnetization states, a Magnetic Random Access Memory (MRAM) can be manufactured, which has the advantage that stored data can be continuously reserved under the condition of no power supply.

The magneto-resistive effect is also applied in the field of magnetic field sensor, such as the electronic compass (electronic compass) component of mobile phone with Global Positioning System (GPS) for providing the user with information of moving direction. Currently, various magnetic field sensing technologies are available in the market, such as Anisotropic Magnetoresistive (AMR) sensing elements, Giant Magnetoresistive (GMR) sensing elements, Magnetic Tunneling Junction (MTJ) sensing elements, and so on. However, the disadvantages of the prior art described above generally include: the chip area, the manufacturing process are expensive, power consumption is high, the sensitivity is not sufficient, and the device is susceptible to temperature variation.

Disclosure of Invention

An embodiment of the invention discloses a semiconductor device, which includes a metal oxide semiconductor transistor disposed on a substrate, an interlayer dielectric layer disposed on the metal oxide semiconductor transistor, and a Magnetic Tunneling Junction (MTJ) disposed on the interlayer dielectric layer, wherein the MTJ upper surface includes an inverted V-shape and is electrically connected to a source/drain region of the metal oxide semiconductor transistor.

In another embodiment of the present invention, a semiconductor device includes a Magnetic Tunneling Junction (MTJ) disposed on a substrate, wherein an upper surface of the MTJ includes an inverted V-shape, a first spacer disposed on a first sidewall of the MTJ and a second spacer disposed on a second sidewall of the MTJ, and wherein the first and second spacers are asymmetric with respect to each other.

Drawings

FIGS. 1-6 illustrate a method of fabricating an MRAM cell according to an embodiment of the invention;

FIG. 7 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a semiconductor device according to an embodiment of the invention.

Description of the main elements

12 substrate 14 MTJ region

16 logic region 18 interlayer dielectric layer

20 metal interconnect structure 22 metal interconnect structure

24 intermetal dielectric layer 26 metal interconnect

28 stop layer 30 intermetal dielectric layer

32 metal interconnect 34 barrier layer

36 metal layer 38 MTJ stack structure

40 cover layer 42 cover layer

44 first electrode layer 46 anchor layer

48 free layer 50 barrier layer

52 second electrode layer 54 patterning mask

56 organic dielectric layer 58 silicon-containing hard mask and antireflective layer

60 patterned photoresist 62 MTJ

64 first angled sidewall 66 second angled sidewall

68 liner layer 70 first spacer

72 intermetal dielectric layer 74 metal interconnect

76 bottom electrode 78 top electrode

80 stop layer 82 second spacer

86 intermetal dielectric layer 88 metal interconnect

90 metal interconnect 92 barrier layer

94 metal layer 96 stop layer

98 projection

102 mos transistor 104 gate structure

106 spacer 108 source/drain region

110 contact plug 114 metal interconnect

116 metal interconnect 118 metal interconnect

120 trench conductor 122 contact hole conductor

124 trench conductor 126 contact hole conductor

128 contact hole conductor 130 first projection

132 second projection

Detailed Description

Referring to fig. 1 to 7, fig. 1 to 7 are schematic views illustrating a method of fabricating a semiconductor device, or more specifically, an MRAM cell, according to an embodiment of the present invention. As shown in fig. 1-5, a substrate 12, such as a substrate 12 made of a semiconductor material selected from the group consisting of silicon, germanium, silicon germanium composite (sige), silicon carbide (silicon carbide), gallium arsenide (gaas), etc., is provided, and a Magnetic Tunneling Junction (MTJ) region 14 and a logic region 16 are preferably defined on the substrate 12.

The substrate 12 may include active (active) devices such as metal-oxide semiconductor (MOS) transistors 102, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 18 overlying the active (active) devices, the passive (passive) devices, and the conductive layers. More specifically, the substrate 12 may include MOS transistor devices, such as planar or non-planar MOS transistor devices (e.g., fin-shaped transistors), wherein the MOS transistor 102 may include transistor devices, such as a gate structure 104 (e.g., a metal gate), spacers 106, source/drain regions 108, an epitaxial layer, a contact hole etch stop layer, etc., the interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistor 102, and the interlayer dielectric layer 18 may have at least one contact plug 110 electrically connected to the source/drain regions 108 of the MOS transistor 102. Since the related fabrication processes of planar or non-planar transistors and interlayer dielectrics are well known in the art, further description is omitted here.

Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric 18 in the MTJ region 14 and the logic region 16 to electrically connect the contact plugs, wherein the metal interconnect structure 20 includes an inter-metal dielectric 24 and metal interconnects 26, 114 and 116 are embedded in the inter-metal dielectric 24, and the metal interconnect structure 22 includes a stop layer 28, an inter-metal dielectric 30 and a plurality of metal interconnects 32 are embedded in the stop layer 28 and the inter-metal dielectric 30.

In the present embodiment, each of the metal interconnects 26, 114, 116 in the metal interconnect structure 20 preferably includes a trench conductor (trench conductor), and the metal interconnect 32 in the metal interconnect structure 22 disposed in the MTJ region 14 includes a via conductor (via conductor). In addition, each of the metal interconnects 26, 32, 114, 116 in each of the metal interconnect structures 20, 22 may be embedded in the intermetal dielectric layers 24, 30 and/or the stop layer 28 and electrically connected to each other according to a single damascene process or a dual damascene process. For example, each of the metal interconnects 26, 32, 114, 116 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN), and the metal layer 36 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), and the like, but is not limited thereto. Since the single damascene or dual damascene process is well known in the art, it is not further described herein. In addition, in the present embodiment, the metal layer 36 preferably includes copper, the intermetal dielectric layers 24 and 30 preferably include silicon oxide, and the stop layer 28 includes a Nitrogen Doped Carbide (NDC) layer, silicon nitride, or silicon carbide nitride (SiCN), but is not limited thereto.

Next, an MTJ stack 38 is formed on the metal interconnect structure 22, a cap layer 40 is formed on the MTJ stack 38, and another cap layer 42 is formed on the liner layer 40. In the present embodiment, the MTJ stack structure 38 is formed by sequentially forming a first electrode layer 44, a fixed layer (fixed layer)46, a free layer (free layer)48, a capping layer (capping layer)50, and a second electrode layer 52. In the present embodiment, the first electrode layer 44 and the second electrode layer 52 preferably comprise a conductive material, such as, but not limited to, tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer 46 may be made of an Antiferromagnetic (AFM) material, such as FeMn (FeMn), PtMn (PtMn), IrMn (IrMn), nickel oxide (NiO), etc., for pinning or confining the magnetic moment direction of adjacent layers. The free layer 48 may be made of a ferromagnetic material, such as iron, cobalt, nickel, or alloys thereof, such as cobalt-iron-boron (CoFeB), but is not limited thereto. Wherein the magnetization direction of the free layer 48 is "free" to change by an external magnetic field. The capping layer 50 may be formed of an insulating material including an oxide, such as aluminum oxide (AlO)_x) Or magnesium oxide (MgO), but is not limited thereto. In addition, the cap layer 40 and the cap layer 42 preferably comprise different materials, for example, the cap layer 40 of the present embodiment preferably comprises silicon nitride and the cap layer 42 preferably comprises silicon oxide, but not limited thereto.

A patterned mask 54 is then formed over the masking layer 42. In the present embodiment, the patterned mask 54 may comprise an Organic Dielectric Layer (ODL) 56, a silicon-containing hard mask and antireflective (SHB) layer 58, and a patterned photoresist 60.

As shown in FIG. 2, the patterned mask 54 is used as a mask to perform one or more etching processes to remove portions of the capping layers 40, 42, a portion of the MTJ stack 38, and a portion of the IMD 30 to form the MTJ62 in the MTJ region 14, wherein the first electrode layer 44 preferably becomes the lower electrode 76 of the MTJ62 and the second electrode layer 52 becomes the upper electrode 78 of the MTJ62 at this stage, and the capping layers 40, 42 can be removed together during the etching process. It is noted that, in the present embodiment, a Reactive Ion Etching (RIE) process is performed to remove portions of the capping layers 40 and 42 and a portion of the MTJ stack structure 38 by using the patterned mask 54, then the patterned mask 54 is removed, and then the patterned capping layer 42 is used as a mask to remove a portion of the MTJ stack structure 38 and a portion of the inter-metal dielectric layer 30 by using an Ion Beam Etching (IBE) process to form the MTJ 62. Due to the characteristics of the ion beam etching process, the top surface of the remaining IMD 30 is preferably slightly lower than the top surface of the metal interconnect 32 and the top surface of the IMD 30 preferably exhibits an arc or curved surface.

It should be noted that in the present embodiment, it is preferable to remove a portion of the intermetal dielectric layer 30 by ion beam etching, so that the metal interconnect 32 forms a first inclined sidewall 64 and a second inclined sidewall 66 near the junction of the MTJ 62. In addition, the second electrode layer 52 on the top is preferably removed when the MTJ stack structure 38 is patterned by the ion beam etching process at this stage, so that the patterned MTJ62 forms an inclined surface. For details, the top or upper surface of MTJ62, or more specifically upper electrode 78, formed at this stage preferably comprises an inverted V-shape, while the left and right sidewalls of MTJ62 are preferably sloped sidewalls.

Then, as shown in FIG. 3, a liner layer 68 is formed on the MTJ62 and covers the surface of the IMD 30. In the present embodiment, the liner layer 68 preferably comprises silicon oxide, but other dielectric materials may be selected according to the manufacturing process requirements, such as silicon oxide, silicon oxynitride or silicon oxycarbide.

As shown in fig. 4, an etching process is then performed to remove a portion of the liner layer 68 to form a first spacer 70 and a second spacer 82 on the sidewalls of the MTJ62, wherein the first spacer 70 and the second spacer 82 are preferably disposed on the sidewalls of the MTJ62 and cover and contact the first sloped sidewall 64 and the second sloped sidewall 66 of the metal interconnect 32.

Then, as shown in fig. 5, another inter-metal dielectric layer 72 is formed in the MTJ region 14 and the logic region 16, and a planarization process, such as a Chemical Mechanical Polishing (CMP) process, is used to remove a portion of the inter-metal dielectric layer 72, so that the upper surface of the inter-metal dielectric layer 72 is slightly higher than the upper surface of the MTJ 62. A pattern transfer process is then performed, such as by removing a portion of the intermetal dielectric layer 72 beside the MTJ62 in the MTJ region 14 and a portion of the intermetal dielectric layer 72, a portion of the intermetal dielectric layer 30, and a portion of the stop layer 28 in the logic region 16 using a patterned mask to form contact holes (not shown) exposing the underlying metal interconnects 26, 114, 116. The contact hole is then filled with the desired metal material and another planarization process is performed to form metal interconnects 74 and 118 or contact plugs in the contact hole, wherein metal interconnect 118 next to MTJ62 is preferably connected to underlying metal interconnect 114 and metal interconnect 74 of logic region 16 is connected to the underlying metal interconnect.

In the present embodiment, each metal interconnect 74, 118 preferably includes a trench conductor 120 and a contact hole conductor 122, wherein each metal interconnect 74, 118 may be embedded in the intermetal dielectric layers 30, 72 and/or the stop layer 28 according to a single damascene process or a dual damascene process. For example, each of the metal interconnects 74 and 118 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), and the like, but is not limited thereto. Since the single damascene or dual damascene process is well known in the art, it is not further described herein. Furthermore, in the present example, metal layer 36 preferably comprises copper and inter-metal dielectric layer 72 preferably comprises silicon oxide.

Subsequently, as shown in FIG. 6, a stop layer 80 and another IMD layer 86 are sequentially formed on the MTJ62 and cover the surface of the IMD layer 72, and one or more photolithography and etching processes are performed to remove a portion of the IMD layer 86 and a portion of the stop layer 80 in the MTJ region 14 and the logic region 16. Conductive material is then filled into each contact hole and a planarization process such as CMP is used to form metal interconnects 88, 90 in the MTJ area 14 and the logic area 16, respectively, to connect the underlying metal interconnect 118, MTJ62, and metal interconnect 74, wherein the metal interconnect 88 in the MTJ area 14 preferably directly contacts the underlying metal interconnect 118 and MTJ62 and the metal interconnect 90 in the logic area 16 contacts the underlying metal interconnect 74. Another stop layer 96 is then formed on the intermetal dielectric layer 86 and covers the metal interconnects 88 and 90.

In the present embodiment, the stop layer 80 may comprise the same or different material as the stop layer 28, for example, both may be selected from the group consisting of Nitrogen Doped Carbide (NDC), silicon nitride (SiN), and silicon carbide nitride (SiCN). As with the previously described metal interconnects, each metal interconnect 88, 90 disposed within the intermetal dielectric layer 86 may be embedded within the intermetal dielectric layer according to a single damascene process or a dual damascene process. For example, the metal interconnect 88 in the MTJ region 14 preferably includes a trench conductor 124 and two contact hole conductors 126, 128 disposed at the bottom of the trench conductor 124, wherein the two contact hole conductors 126, 128 are connected to the trench conductor 124 and the MTJ62, respectively. As mentioned above, each of the metal interconnects 88, 90 may further include a barrier layer 92 and a metal layer 94, wherein the barrier layer 92 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN), and the metal layer 36 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), and the like, but is not limited thereto. Since the single damascene or dual damascene process is well known in the art, it is not further described herein. Thus, the fabrication of the semiconductor device according to an embodiment of the present invention is completed.

Referring to fig. 6 again, fig. 6 further discloses a structural schematic diagram of a semiconductor device according to an embodiment of the invention. As shown in fig. 6, the semiconductor device mainly includes at least one mos transistor 102 disposed on the substrate 12, an interlayer dielectric layer 18 disposed on the mos transistor 102 and an MTJ62 disposed on the interlayer dielectric layer 18, wherein the upper surface of the MTJ62 is electrically connected to a source/drain region 108 of the mos transistor 102.

In more detail, the semiconductor device further includes a metal interconnect 32 connected to the bottom of the MTJ62, an intermetal dielectric layer 30 on the ild layer 18 and surrounding the metal interconnect 32, a metal interconnect 118 beside the MTJ62, an intermetal dielectric layer 72 on the ild layer 30 and surrounding the MTJ62 and the metal interconnect 118, a metal interconnect 26 connected to the bottom of the metal interconnect 32, a metal interconnect 114 connected to the bottom of the metal interconnect 118 and the source/drain region 108 of the mos transistor 102 and the source/drain region 108 preferably does not overlap the MTJ62, a metal interconnect 88 connected to the top of the MTJ62 and the metal interconnect 118, and an intermetal dielectric layer 86 on the ild layer 72 and surrounding the metal interconnect 88.

In addition, metal interconnect 88 includes trench conductor 124 and contact hole conductors 126, 128 disposed at the bottom of trench conductor 124, wherein the top surface of trench conductor 124 is aligned with the top surface of IMD 86, contact hole conductor 126 is preferably connected to trench conductor 120 beside MTJ62, contact hole conductor 128 is preferably connected to MTJ62, and the top surface of trench conductor 120 is aligned with the top surface of IMD 72. It is noted that the bottom of contact hole conductor 126 comprises a flat surface and the bottom of contact hole conductor 128 comprises an inverted V-shape that directly contacts the upper surface of MTJ 62. As a whole, the MTJ62 of the present embodiment is preferably configured with a reversed cell (reverse cell) in which the top side is electrically connected to the metal interconnect 118 on the left side of the MTJ62 through the upper metal interconnect 88 and to the source/drain region 108 of the MOS transistor 102 through the contact plug 110.

Referring to fig. 7, fig. 7 further discloses a structural diagram of a semiconductor device according to an embodiment of the invention. As shown in FIG. 7, the mask position may be selectively adjusted in FIG. 6 by photolithography and etching processes to form metal interconnect 88 in MTJ region 14, so that the etching process removes a portion of IMD 72 and even a portion of second spacer 82 beside MTJ62 in addition to removing stop layer 80 and IMD 86 directly above MTJ62, thereby misaligning the formed metal interconnect 88 with the underlying MTJ 62. In other words, at least a portion of metal interconnect 88 contacts a portion of the sidewall of MTJ62 in addition to a portion of metal interconnect 88 directly contacting the top of MTJ62 at the bottom.

In general terms, the semiconductor device disclosed in fig. 7 mainly includes an MTJ62 disposed in the MTJ region 14 of the substrate 12, a metal interconnect 74 disposed in the logic region 16 beside the MTJ62, an inter-metal dielectric layer 72 surrounding the MTJ62 and the metal interconnect 74, a metal interconnect 32 connected to and contacting the bottom of the MTJ62, a metal interconnect 88 connected to and contacting the top and a portion of the sidewall of the MTJ62, another metal interconnect 90 connected to and contacting the metal interconnect 74, an inter-metal dielectric layer 86 surrounding the metal interconnect 88 and the metal interconnect 90, a stop layer 80 disposed between the inter-metal dielectric layer 72 and the inter-metal dielectric layer 86, and a stop layer 96 overlying the MTJ62, the metal interconnect 90, and the inter-metal dielectric layer 86.

In the present embodiment, MTJ62 preferably includes a lower electrode 76, a pinned layer 46, a free layer 48, a barrier layer 50, and an upper electrode 78, and MTJ62 has a first spacer 70 on one side and a second spacer 82 on the other side, wherein first spacer 70 and second spacer 82 are preferably asymmetric structures. In detail, the bottom of first spacer 70 directly contacts first sloped sidewall 64, the bottom of second spacer 82 directly contacts second sloped sidewall 66, the top surface of first spacer 70 preferably is flush with the inverted V-shaped top surface of top electrode 78 of MTJ62, and the top surface of second spacer 82 preferably is lower than the inverted V-shaped top surface of top electrode 78 but higher than the top surface of barrier layer 50 or free layer 48. In other words, the first spacer 70 and the second spacer 82 preferably comprise different heights.

Metal interconnect 88, disposed directly above MTJ62 in more detail, preferably includes a protrusion 98 disposed directly below contact hole conductor 128 and contacting an angled sidewall of top electrode 78. Since the second spacer 82 does not completely shield the sidewall of MTJ62 to expose part of the sidewall of MTJ62, the protrusion 98 preferably contacts the top electrode 78, the second spacer 82 and the inter-metal dielectric layer 72 at the same time and the bottom surface or bottom-most portion of the protrusion 98 is preferably higher than the top surface of the barrier layer 50 or the free layer 48. It is noted that the top or upper surface of MTJ62 of the present embodiment has an inverted V-shape and the sidewalls on both sides are preferably sloped sidewalls, so the bottom of contact hole conductor 128 disposed directly above MTJ62 preferably directly contacts the inverted V-shape on the top of MTJ62 and protrusion 98 preferably contacts the sloped sidewalls on one side of MTJ62 or upper electrode 78, wherein contact hole conductor 128 can contact only one of the sloped sides of the inverted V-shape or both sloped sides depending on the manufacturing process requirements.

It should be noted that although the embodiment is shown with the metal interconnect 88 biased toward the right side of the MTJ62 and the protrusion 98 contacting the right side wall of the MTJ62, the invention is not limited to this design, and the metal interconnect 88 biased toward the left side of the MTJ62 and the protrusion 98 contacting the left side wall of the MTJ62 according to other embodiments of the invention, and even as shown in fig. 8, both sides of the bottom of the contact hole conductor 128 may extend downward to form the first protrusion 130 and the second protrusion 132 contacting both side walls of the MTJ62, respectively, for example, the first protrusion 130 contacting the left side wall of the upper electrode 78 and the second protrusion 132 contacting the right side wall of the upper electrode 78, which also falls within the scope of the invention.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.