阅读说明：本技术 显示装置及半导体器件 (Display device and semiconductor device ) 是由 神内纪秀 渡壁创 花田明纮 小野寺凉 铃村功 于 2020-02-05 设计创作，主要内容包括：本发明涉及显示装置及半导体器件。能在同一基板内形成LTPS TFT和氧化物半导体TFT。显示装置,其特征在于,具有形成有使用氧化物半导体(109)的第一TFT和使用多晶硅半导体的第二TFT的基板,上述第一TFT中,覆盖上述氧化物半导体而形成第一绝缘膜(112),第一漏电极(110)介由上述第一绝缘膜中形成的第一通孔(132)连接于上述氧化物半导体,第一源电极(111)介由第二通孔(133)连接于上述氧化物半导体,覆盖上述第一漏电极及上述第一源电极而形成第二绝缘膜(115),漏极布线(120)介由上述第二绝缘膜中形成的第三通孔(130)连接于上述第一漏电极,源极布线(122)介由上述第二绝缘膜中形成的第四通孔(131)连接于上述第一源电极。(The invention relates to a display device and a semiconductor device. The LTPS TFT and the oxide semiconductor TFT can be formed in the same substrate. A display device is characterized by comprising a substrate on which a first TFT using an oxide semiconductor (109) and a second TFT using a polysilicon semiconductor are formed, wherein the first TFT is formed so as to cover the oxide semiconductor to form a first insulating film (112), a first drain electrode (110) is connected to the oxide semiconductor via a first through hole (132) formed in the first insulating film, a first source electrode (111) is connected to the oxide semiconductor via a second through hole (133), a second insulating film (115) is formed so as to cover the first drain electrode and the first source electrode, a drain wiring (120) is connected to the first drain electrode via a third through hole (130) formed in the second insulating film, and a source wiring (122) is connected to the first source electrode via a fourth through hole (131) formed in the second insulating film.)

1. A display device having a substrate on which a first TFT using an oxide semiconductor and a second TFT using a polysilicon semiconductor are formed,

a first TFT in which a first insulating film is formed so as to cover the oxide semiconductor, a first drain electrode is connected to the oxide semiconductor via a first via hole formed in the first insulating film, a first source electrode is connected to the oxide semiconductor via a second via hole formed in the first insulating film,

and a second insulating film formed so as to cover the first drain electrode and the first source electrode, wherein a drain wiring is connected to the first drain electrode through a third via hole formed in the second insulating film, and a source wiring is connected to the first source electrode through a fourth via hole formed in the second insulating film.

2. The display device according to claim 1, wherein the first drain wiring is a video signal line.

3. The display device according to claim 1, wherein the first source wiring is connected to a pixel electrode.

4. The display device according to claim 1, wherein the first through hole and the third through hole are formed at different positions in a plan view, and wherein the second through hole and the fourth through hole are formed at different positions in a plan view.

5. The display device according to claim 1, wherein the first drain electrode and the first source electrode of the first TFT are formed over the first insulating film.

6. The display device according to claim 1, wherein the first gate wiring of the first TFT is formed in the same layer as the scan line.

7. The display device according to claim 1, wherein the second TFT is formed in the vicinity of the substrate closer than the first TFT.

8. The display device according to claim 1, wherein the second TFT has a second drain electrode and a second source electrode,

the first drain wiring and the first source wiring of the first TFT, and the second drain electrode and the second source electrode of the second TFT are formed in the same layer.

9. The display device according to claim 1, wherein the second TFT has a second drain electrode and a second source electrode,

the first drain wiring and the first source wiring of the first TFT, and the second drain electrode and the second source electrode of the second TFT are formed over the second insulating film.

10. The display device according to claim 1, wherein the display device is a liquid crystal display device.

11. The display device according to claim 1, wherein the display device is an organic EL display device.

12. A semiconductor device having a substrate on which a first TFT using an oxide semiconductor and a second TFT using a polysilicon semiconductor are formed,

a first TFT in which a first insulating film is formed so as to cover the oxide semiconductor, a first drain electrode is connected to the oxide semiconductor via a first via hole formed in the first insulating film, a first source electrode is connected to the oxide semiconductor via a second via hole formed in the first insulating film,

and a second insulating film formed so as to cover the first drain electrode and the first source electrode, wherein a drain wiring is connected to the first drain electrode through a third via hole formed in the second insulating film, and a source wiring is connected to the first source electrode through a fourth via hole formed in the second insulating film.

13. The semiconductor device according to claim 12, wherein the first via hole and the third via hole are formed at different positions in a plan view, and wherein the second via hole and the fourth via hole are formed at different positions in a plan view.

14. The semiconductor device according to claim 12, wherein the drain electrode and the source electrode of the first TFT are formed over the first insulating film.

15. The semiconductor device according to claim 12, wherein the second TFT is formed in a vicinity closer to the substrate than the first TFT.

16. The semiconductor device according to claim 12, wherein the second TFT has a second drain electrode and a second source electrode,

the first drain wiring and the first source wiring of the first TFT, and the second drain electrode and the second source electrode of the second TFT are formed in the same layer.

17. The semiconductor device according to claim 12, wherein the second TFT has a second drain electrode and a second source electrode,

the first drain wiring and the first source wiring of the first TFT, and the second drain electrode and the second source electrode of the second TFT are formed over the second insulating film.

Technical Field

The present invention relates to a display device and a semiconductor device using a hybrid structure based on both a TFT using a polycrystalline silicon semiconductor and a TFT using an oxide semiconductor.

Background

In a liquid crystal display device, the following configuration is formed: the liquid crystal display device includes a TFT substrate in which pixels including pixel electrodes, Thin Film Transistors (TFTs), and the like are formed in a matrix, and a counter substrate disposed to face the TFT substrate, and liquid crystal is sandwiched between the TFT substrate and the counter substrate. Then, the transmittance of light by the liquid crystal molecules is controlled for each pixel, thereby forming an image. On the other hand, the organic EL display device forms a color image by disposing an organic EL layer and a TFT which are self-luminous in each pixel. The organic EL display device is advantageous for thinning because it does not require a backlight.

The polycrystalline silicon semiconductor has high mobility and is therefore suitable as a TFT for a driver circuit. On the other hand, the oxide semiconductor has high OFF resistance, and when it is used as a switching TFT in a pixel, OFF current can be reduced.

Patent document 1, patent document 2, patent document 3, patent document 4, and patent document 5 describe a TFT using an oxide semiconductor and a display device using a polysilicon semiconductor.

Disclosure of Invention

Problems to be solved by the invention

A TFT used as a switch of a pixel needs to have a small leakage current. The TFT using an oxide semiconductor can reduce leakage current. However, since the oxide semiconductor has a low carrier mobility, it is sometimes difficult to form a driver circuit built in a display device using a TFT using an oxide semiconductor.

On the other hand, since TFTs formed of a polycrystalline silicon semiconductor have high mobility, a driver circuit can be formed of TFTs using a polycrystalline silicon semiconductor. However, when a polycrystalline silicon semiconductor is used as a switching TFT in a pixel, a leakage current of the polycrystalline silicon semiconductor is large, and therefore, two polycrystalline silicon semiconductor TFTs are generally used in series.

Therefore, it is reasonable to use an oxide semiconductor for the switching TFT which is a pixel in the display region and a polysilicon semiconductor for the TFT of the peripheral driver circuit. However, a TFT using a polysilicon semiconductor and a TFT using an oxide semiconductor need to be formed in different layers. In general, a TFT using a polycrystalline silicon semiconductor is formed first (i.e., at a lower layer) and then a TFT using an oxide semiconductor is formed (i.e., at an upper layer) according to process temperature conditions.

However, since the surface of the polycrystalline silicon semiconductor is oxidized, after a via hole is formed in an insulating film stacked over the polycrystalline silicon semiconductor, the via hole is cleaned with hydrofluoric acid (HF). At this time, hydrofluoric acid (HF) also enters the through hole formed on the oxide semiconductor side. In this case, the oxide semiconductor disappears due to hydrofluoric acid (HF).

To prevent this, the following operations are performed: forming a drain metal or a source metal and connecting the via to the drain metal or the source metal without directly connecting the via to the oxide semiconductor. Patent documents 1 to 5 show examples of such a configuration.

Patent documents 1 to 4 are examples in which a drain metal and a source metal are stacked on an upper side of an oxide semiconductor. In this structure, the surface of the oxide semiconductor is contaminated when the drain metal and the source metal are formed, and the characteristics of the TFT using the oxide semiconductor become unstable. Patent document 5 describes an example in which an oxide semiconductor is stacked over a drain metal and a source metal, but in this case, the drain metal and the source metal are patterned before the oxide semiconductor is formed, and therefore there is a risk that the surface on which the oxide semiconductor is formed is contaminated. Further, since the oxide semiconductor having a small film thickness is also formed on the drain metal or the source metal, there is a risk of disconnection.

In view of the above problems, the present invention provides a TFT using an oxide semiconductor with stable characteristics. Further, a highly reliable display device or semiconductor device using both a TFT using an oxide semiconductor and a TFT using a polysilicon semiconductor is realized.

Means for solving the problems

The present invention overcomes the above problems, and representative specific means are as follows. That is, the display device includes a substrate on which a first TFT using an oxide semiconductor and a second TFT using a polysilicon semiconductor are formed, wherein the first TFT is formed to cover the oxide semiconductor to form a first insulating film, a first drain electrode is connected to the oxide semiconductor through a first via hole formed in the first insulating film, a first source electrode is connected to the oxide semiconductor through a second via hole formed in the first insulating film, a second insulating film is formed to cover the first drain electrode and the first source electrode, a drain wiring is connected to the first drain electrode through a third via hole formed in the second insulating film, and a source wiring is connected to the first source electrode through a fourth via hole formed in the second insulating film.

Drawings

FIG. 1 is a plan view of a liquid crystal display device.

FIG. 2 is a cross-sectional view of a display region of a liquid crystal display device.

Fig. 3 is a plan view showing a pixel configuration of a display region in a case where the present invention is not used.

FIG. 4 is a sectional view taken along line A-A of FIG. 3.

FIG. 5 is a cross-sectional view of a display region of a liquid crystal display device according to the present invention.

Fig. 6 is a plan view showing a pixel configuration of a display region according to the present invention.

FIG. 7 is a sectional view taken along line B-B of FIG. 6.

FIG. 8 is a cross-sectional view showing a mixed structure of an oxide semiconductor TFT and a polysilicon semiconductor TFT.

FIG. 9 is a cross-sectional view showing a mixed structure of an oxide semiconductor TFT and a polysilicon semiconductor TFT according to the present invention.

Fig. 10 is a cross-sectional view of a display region of an organic EL display device.

FIG. 11 is a cross-sectional view of a photosensor.

FIG. 12 is a plan view of a photosensor.

Description of the reference numerals

11.. scanning lines, 12.. video signal lines, 13.. pixels, 14.. display regions, 15.. terminal regions, 16.. sealing materials, 17.. flexible wiring substrates, 118.. scanning line driving circuits, 90.. detection regions, 91.. scanning lines, 92.. signal lines, 93.. power supply lines, 94.. sensor elements, 95.. scanning circuits, 96.. signal circuits, 97.. power supply circuits, 99.. 1, 100.. TFT substrates, 101.. 1. light shielding films, 102.. light shielding films, 103.. polysilicon semiconductors, 104.. 1. gate insulating films, 105.. 1. gate electrodes, 106.. 2 light shielding films, 107.. connecting electrodes, 108.. insulating films, 103.. interlayer oxide semiconductors, 110.. drain electrodes, 78.. interlayer oxide semiconductors, 110 … 111 … source electrode, 112.. 2 gate insulating film, 113.. AlO film, 114.. 2 gate electrode, 115.. inorganic passivation film, 116.. 1 shield wiring, 117.. 1 drain wiring electrode, 118.. 1 gate wiring, 119.. 1 source wiring, 121.. 2 gate wiring, 122.. 2 source wiring, 123.. 2 shield wiring, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139.. via hole, 140.. organic passivation film, 141.. common electrode, 142.. capacitor insulating film, 143.. pixel electrode, 144.. orientation film, 150.. lower electrode, 151.. organic EL layer, 152.. cathode, 154.. protective layer, 153.. dam material, 160.. dam material, 160.. 160 172. 172, 174.. via hole, 200.. opposed substrate, 201.. color filter, 202.. black matrix, 203.. cover film, 204.. alignment film, 300.. liquid crystal layer, 301.. liquid crystal molecule, 400.. window, 500.. light receiving element, 600.. panel, 601.. adhesive material, 700.. measured object

Detailed Description

The Oxide semiconductor includes IGZO (Indium Gallium Zinc Oxide ), ITZO (Indium Tin Zinc Oxide, Indium Tin Zinc Oxide), ZnON (Zinc oxynitride, Zinc Oxide Nitride), IGO (Indium Gallium Oxide ), and the like. In the present invention, a case where IGZO is used as an example of the oxide semiconductor will be described. Hereinafter, a TFT using an oxide semiconductor is referred to as an oxide semiconductor TFT.

In a display device, a so-called LTPS (low temperature polysilicon) is generally used as a polycrystalline semiconductor, which is formed by annealing an a-Si (amorphous silicon) semiconductor formed by CVD (Chemical vapor deposition) using an excimer laser. Hereinafter, a TFT using a polycrystalline silicon semiconductor is referred to as a polycrystalline silicon semiconductor TFT.

In this specification, a structure using both an oxide semiconductor TFT and a polysilicon semiconductor TFT may be referred to as a hybrid (hybrid) system. The present invention will be described in detail below with reference to examples.

[ example 1]

Fig. 1 is a top view of a liquid crystal display device to which the present invention can be applied. In fig. 1, the TFT substrate 100 and the counter substrate 200 are bonded together with a sealing material 16, and a liquid crystal layer is interposed between the TFT substrate 100 and the counter substrate 200. The display region 14 is formed in a portion where the TFT substrate 100 and the counter substrate 200 overlap each other.

In the display region 14 of the TFT substrate 100, the scanning lines 11 extend in the lateral direction (x direction) and are arranged in the longitudinal direction (y direction). In addition, the video signal lines 12 extend in the longitudinal direction and are arranged in the lateral direction. A region surrounded by the scanning line 11 and the video signal line 12 becomes a pixel 13.

The TFT substrate 100 is formed larger than the counter substrate 200, and a portion of the TFT substrate 100 not overlapping with the counter substrate 200 serves as the terminal region 15. A flexible wiring board 17 is connected to the terminal region 15. A driver IC for driving the liquid crystal display device is mounted on the flexible wiring board 17.

Since the liquid crystal itself does not emit light, a backlight is disposed on the rear surface of the TFT substrate 100. The liquid crystal display panel forms an image by controlling light from a backlight for each pixel. By bending the flexible wiring substrate 17 toward the back surface of the backlight, the overall external shape of the liquid crystal display device is reduced.

In the liquid crystal display device of the present invention, an oxide semiconductor TFT having a small leak current is used as a TFT used in the display region 14. In addition, for example, a scanning line driving circuit 18 is formed in the frame portion near the sealing material, and a polysilicon semiconductor TFT having a high mobility is used for the scanning line driving circuit 18.

Fig. 2 is a cross-sectional view of a display region where a pixel exists. Fig. 2 shows a liquid crystal display device of an IPS (In plane switching) system called FFS (Fringe field switching) system. In fig. 2, a TFT using an oxide semiconductor 109 is used. The TFT using the oxide semiconductor 109 has a small leak current and is therefore suitable as a switching TFT.

In the present invention, as described later, since the peripheral circuit is formed by the TFT using a polycrystalline silicon semiconductor, an insulating layer or the like used for this is also formed in the display region. The polysilicon semiconductor TFT is formed closer to the substrate 100 than the oxide semiconductor TFT. The gate insulating film 104 of the polysilicon semiconductor TFT extends in the display region.

In fig. 2, a base film 102 is formed over a TFT substrate 100 formed of glass, polyimide, or other resin. The base film 102 prevents a polycrystalline silicon semiconductor or an oxide semiconductor formed thereon from being contaminated with impurities from a glass substrate or the like. The base film 102 is often formed of a stacked film of a silicon oxide film (hereinafter referred to as SiO) and a silicon nitride film (hereinafter referred to as SiN). An aluminum oxide film (hereinafter, referred to as AlO) may be further laminated.

A gate insulating film 104 for a polysilicon semiconductor TFT is formed over the base film 102. Over this, a light shielding film 106 is formed of a metal. The metal may be the same as a gate electrode or the like described later. The light shielding film 106 is used to shield light from the backlight so that light from the backlight is not applied to a channel portion of a TFT to be formed later.

By applying a predetermined potential to the light-shielding film 106, the light-shielding film 106 can be used as a shield electrode. When the substrate 100 is formed of a resin such as polyimide, the substrate 100 is easily charged, which affects the characteristics of the TFT. By using the light shielding film 106 as a shield electrode, it is possible to prevent the electric charge on the substrate 100 from affecting the TFT.

An interlayer insulating film 108 is formed to cover the light-shielding film 106. The interlayer insulating film 108 is formed of an SiO film or a laminated film of an SiO film and an SiN film. An oxide semiconductor 109 constituting a TFT is formed over the interlayer insulating film 108. The thickness of the oxide semiconductor 109 is 10nm to 100 nm. In the source and drain regions of the oxide semiconductor 108, a drain electrode 110 and a source electrode 111 are formed in portions connected to the via holes 130 and 131. This is to prevent hydrofluoric acid (HF) from entering the through holes 130 and 131 and causing the oxide semiconductor 109 to disappear when the through holes are cleaned with the HF. In an actual device, as shown in fig. 2 and 3, the drain electrode 110 and the source electrode 111 are formed to extend on the interlayer insulating film 108.

The 2 nd gate insulating film 112 is formed of SiO covering the oxide semiconductor 109. The 2 nd gate insulating film 112 formed of SiO supplies oxygen to the oxide semiconductor 109 to stabilize channel characteristics. A 2 nd gate electrode 114 is formed over the 2 nd gate insulating film 112, and an AlO film 113 is formed between the 2 nd gate electrode 114 and the 2 nd gate insulating film 112 with a thickness of about 10 nm. For assisting the supply of oxygen from the 2 nd gate insulating film 112 to the oxide semiconductor 109.

An inorganic passivation film 115 is formed of SiO or SiN covering the 2 nd gate electrode 114. The thickness of the inorganic passivation film 115 is, for example, 150nm to 300 nm. The inorganic passivation film 115 may have a two-layer structure of an SiO film and an SiN film.

Through holes 130 and 131 are formed through the inorganic passivation film 115 and the 2 nd gate insulating film 112. This is used to connect the oxide semiconductor 109 and the video signal line 12 (in fig. 2 and the like, the video signal line is a drain wiring) or to connect the oxide semiconductor 109 and the source wiring 122. The source wiring 122 is connected to the pixel electrode 143 through the via holes 135 and 136.

In fig. 2, an organic passivation film 140 is formed to cover the video signal line 12 and the source wiring 122. The organic passivation film 140 is formed of, for example, acrylic resin or the like. The organic passivation film 140 is formed to be thick about 2 to 4 μm in order to function as a planarization film and to reduce parasitic capacitance between the video signal line 12 and the common electrode 141. A through hole 135 is formed in the organic passivation film 140 to connect the source line 122 to the pixel electrode 143.

A common electrode 141 is formed of a transparent conductive film such as ito (indium Tin oxide) on the organic passivation film 140. The common electrode 141 is formed in a planar shape in common to a plurality of pixels. The capacitor insulating film 142 is formed of SiN so as to cover the common electrode 141. The pixel electrode 143 is formed of a transparent conductive film such as ito (indium Tin oxide) so as to cover the capacitor insulating film 142. The pixel electrode 143 is formed in a comb-tooth shape. Fig. 3 shows an example of the planar shape of the pixel electrode 143. The capacitor insulating film 142 forms a pixel capacitor between the common electrode 141 and the pixel electrode 143.

An alignment film 144 is formed to cover the pixel electrode 143. The alignment film 144 defines an initial alignment direction of the liquid crystal molecules 301. The alignment treatment of the alignment film 144 is alignment treatment by rubbing or photo-alignment treatment using polarized ultraviolet rays. No pretilt angle is required in IPS, so photo-alignment treatment is advantageous.

In fig. 2, the counter substrate 200 is disposed with the liquid crystal layer 300 interposed therebetween. A color filter 201 and a black matrix 202 are formed on the counter substrate 200, and an overcoat film (overcoat film)203 is formed thereon. An alignment film 204 is formed over the cover film 203. The alignment film 204 functions and alignment treatment in the same manner as the alignment film 144 on the TFT substrate 100 side.

In fig. 2, when a voltage is applied between the common electrode 141 and the pixel electrode 143, electric lines of force such as those indicated by arrows in fig. 2 are generated, and the liquid crystal molecules 301 are rotated to control the transmittance of the liquid crystal layer 300 with respect to light from the backlight. An image is formed by controlling the transmittance of light for each pixel.

Fig. 3 is a plan view of a pixel in the display region of the liquid crystal display device corresponding to fig. 2. In fig. 3, the scanning lines 11 extend in the lateral direction (x direction) and are arranged in the longitudinal direction (y direction). In addition, the video signal lines 12 extend in the longitudinal direction and are arranged in the lateral direction. The pixel electrode 143 is formed in a region surrounded by the scanning line 11 and the video signal line 12. An oxide semiconductor TFT is formed between the video signal line 12 and the pixel electrode 143. In fig. 3, the light shielding film is omitted.

In fig. 3, the drain electrode 110 is connected to the video signal line 12 via a via hole 130, passes under the video signal line 12, and extends in the direction of the oxide semiconductor TFT formed in the pixel adjacent to the pixel. The oxide semiconductor 109 is formed in an L shape, and one end thereof is stacked and connected to the drain electrode 110.

The oxide semiconductor 109 passes under the scanning line 11, and at this time, a channel of the TFT is formed. In fig. 3, the scanning line 11 also functions as the gate electrode 114 in fig. 2. The oxide semiconductor 109 (except for the channel portion directly below the gate electrode 114, i.e., the scan line 11) is doped with ions such as phosphorus (P) or boron (B) by ion implantation to provide conduction. The other end of the oxide semiconductor 109 is connected to the source electrode 111 in a stacked state. The source electrode 111 extends toward the pixel electrode 143 and is connected to the source wiring 122 via the via hole 131.

The source wiring 122 is connected to the pixel electrode 143 through a via hole 135 formed in the organic passivation film 140 and a via hole 136 formed in the capacitor insulating film. The pixel electrode 143 is formed in a comb-tooth shape. Below the pixel electrode 143, the common electrode 141 is formed in a planar shape. When a voltage is applied to the pixel electrode 143, electric lines of force are generated between the common electrode 141 and the pixel electrode 143, and liquid crystal molecules are rotated to control the transmittance of liquid crystal in the pixel, as described with reference to fig. 2.

In this manner, the drain region of the oxide semiconductor 109 is connected to the video signal line 12 via the via hole 130 by the drain electrode 110. The source region of the oxide semiconductor 109 is connected to the source wiring 122 through the via 131 by the source electrode 111. Therefore, even if hydrofluoric acid (HF) enters the through holes 130 and 131, the hydrofluoric acid (HF) does not contact the oxide semiconductor 109, and thus the oxide semiconductor 109 does not disappear.

However, this structure has the following problems. Fig. 4 is a sectional view a-a of fig. 3. In fig. 4, an oxide semiconductor 109 is formed over the interlayer insulating film 108. A drain electrode 110 is stacked on the drain region of the oxide semiconductor 109, and a source electrode 111 is stacked on the source region. A 2 nd gate insulating film 112 is formed to cover the oxide semiconductor 109, the drain electrode 110, and the source electrode 111.

A 2 nd gate electrode 114 is formed on the 2 nd gate insulating film 112 with an AlO film 113 interposed therebetween, and an inorganic passivation film 115 is formed so as to cover the 2 nd gate electrode. On one side of the oxide semiconductor 109, the video signal line 12 extends over the inorganic passivation film 115, and on the other side of the oxide semiconductor 109, the source wiring 122 extends over the inorganic passivation film 115. The video signal line 12 and the drain electrode 110 are connected via a via hole 130. The source electrode 111 and the source wiring 122 are connected through a via 131.

In fig. 4, first, the oxide semiconductor 109 is deposited over the interlayer insulating film 108 by sputtering or the like, and then, patterning of the oxide semiconductor 109 is performed. Then, a metal such as Ti as the drain electrode 110 and the source electrode 111 is deposited by sputtering or the like. At this time, Ti is also sputtered on the channel surface of the oxide semiconductor 109, and thus the surface of the oxide semiconductor 109 is contaminated with Ti.

Then, Ti is patterned. Ti is patterned by chlorine dry etching, and at this time, the oxide semiconductor 109 is also damaged by the dry etching. That is, since the oxide semiconductor 109 is etched by chlorine dry etching, irregularities are easily formed on the surface of the oxide semiconductor 109.

Such damage to the oxide semiconductor causes variation in characteristics of the oxide semiconductor TFT. This variation is manifested in particular as a variation in the threshold voltage Vt; and so on. The same applies to the case where MoW is used for the drain electrode 110 or the source electrode 111.

The present invention can form an oxide semiconductor TFT with stable characteristics by suppressing such variations in characteristics of the oxide semiconductor 109. Fig. 5 is a diagram showing the configuration of the present invention. Fig. 5 is a cross-sectional view of a display region of a liquid crystal display device according to the present invention. Fig. 5 is a portion of the oxide semiconductor TFT in a different point from fig. 2, and the other points are the same as fig. 2, and only the portion of the oxide semiconductor TFT will be described.

In fig. 5, an oxide semiconductor 109 is formed over the interlayer insulating film 108. The oxide semiconductor 109 is patterned. A 2 nd gate insulating film 112 is formed to cover the oxide semiconductor 109. In the 2 nd gate insulating film 112, a via hole 132 is formed corresponding to the drain region of the oxide semiconductor 109, and a via hole 133 is formed corresponding to the source region. Then, the drain electrode 110 is formed in the via hole 132, and the source electrode 111 is formed in the via hole 133. On the 2 nd gate insulating film 112, a 2 nd gate electrode 114 is formed with an AlO film 113 interposed therebetween. Accordingly, the drain electrode 110, the source electrode 111, and the 2 nd gate electrode 114 are formed on the 2 nd gate insulating film 112. The drain electrode 110, the source electrode 111, and the 2 nd gate electrode 114 may be formed of the same material. An inorganic passivation film 115 is formed to cover these electrodes.

In the inorganic passivation film 115, a via hole 130 is formed to connect the drain electrode 110 to the video signal line 12 functioning as a drain wiring. In the inorganic passivation film 115, a via hole 131 is formed to connect the source electrode 111 and the source wiring 122.

The drain electrode 110 is connected to the oxide semiconductor 109 through a via hole 132 formed in the 2 nd gate insulating film 112, and the source electrode 111 is connected to the oxide semiconductor 109 through a via hole 133 formed in the 2 nd gate insulating film 112. Thus, fig. 5 is largely different from fig. 2 in that: the drain electrode 110 and the source electrode 111 are not formed in the same layer as the oxide semiconductor 109, and are connected to the oxide semiconductor 109 through the vias 132 and 133.

Fig. 6 is a plan view of a pixel in the display region of the liquid crystal display device corresponding to fig. 5. Fig. 6 differs from fig. 3 in that: the drain electrode 110 and the oxide semiconductor 109 are connected via a via 132, and the source electrode 111 and the source wiring 122 are connected via a via 133. The other points are the same as in fig. 3.

Fig. 7 is a sectional view B-B of fig. 6. Fig. 7 differs from fig. 4 in that: the drain electrode 110 is formed on a layer different from the oxide semiconductor 109, that is, the 2 nd gate insulating film 112, and is connected to the oxide semiconductor 109 through a via hole 132. The source electrode 111 is formed on the 2 nd gate insulating film 112, which is a layer different from the oxide semiconductor 109, and is connected to the oxide semiconductor 109 through the via hole 133.

In the structure of fig. 7, the oxide semiconductor 109 and the drain electrode 110 or the oxide semiconductor 109 and the source electrode 111 are not stacked. Therefore, the following damage is not present: damage to the oxide semiconductor 109 when the drain electrode 110 or the source electrode 111 is deposited, and damage to the oxide semiconductor 109 when the drain electrode 110 or the source electrode 111 is patterned.

In fig. 7, the via hole 132 for connecting the drain electrode 110 and the oxide semiconductor 109 or the via hole 133 for connecting the source electrode 111 and the oxide semiconductor 109 is not exposed to hydrofluoric acid (HF) when cleaning the via hole for the polysilicon semiconductor TFT, and therefore the oxide semiconductor is not lost by hydrofluoric acid (HF). Therefore, the oxide semiconductor is not damaged by the formation of the drain electrode and the source electrode, and thus an oxide semiconductor TFT having stable characteristics can be manufactured.

Fig. 8 and 9 are cross-sectional views of the case where an oxide semiconductor TFT and a polysilicon semiconductor TFT are formed on the same substrate 100. In an actual product, since the oxide semiconductor TFT is formed in the display region and the polysilicon semiconductor TFT is formed in the peripheral circuit, the oxide semiconductor TFT and the polysilicon semiconductor TFT are formed in separate portions, and fig. 8 and 9 show the two adjacent to each other for easy understanding of the drawings.

Fig. 8 shows a mixed structure in a case where the present invention is not used in the oxide semiconductor TFT, and fig. 9 shows a mixed structure in a case where the present invention is used in the oxide semiconductor TFT. In any case, the polysilicon semiconductor TFT is formed before the oxide semiconductor TFT, that is, closer to the substrate 100. The reason for this is that the polycrystalline silicon semiconductor 103 uses a higher temperature process than the oxide semiconductor 109.

First, description is made with reference to fig. 8. In fig. 8, a 1 st light-shielding film 101 is formed on a TFT substrate 100 formed of a resin such as glass or polyimide. The material of the 1 st light-shielding film 101 may be the same material as the gate electrode or the like. For example, a laminated structure of MoW or Ti-Al-Ti. The 1 st light shielding film 101 shields the polycrystalline silicon semiconductor 103 formed thereon from light from a backlight, preventing generation of photocurrent in the polycrystalline silicon semiconductor 103.

Another important function of the 1 st light shielding film 101 is to shield the polycrystalline silicon semiconductor 103 from the electric charges charged in the TFT substrate 100. In particular, when the substrate 100 is made of resin such as polyimide, the resin is easily charged, and therefore, it is necessary to shield the substrate with the 1 st light-shielding film 101. For this reason, a predetermined potential, for example, a common voltage is applied to the 1 st light-shielding film 101.

A base film 102 is formed by CVD or the like so as to cover the 1 st light-shielding film 101. The base film 102 is formed of two layers of, for example, an SiO film and an SiN film. A polysilicon semiconductor 103 is formed over the base film 102. In the polycrystalline silicon semiconductor 103, an a-Si film is first formed by CVD or the like, and then converted into the polycrystalline silicon semiconductor 103 by irradiating the film with excimer laser light. Then, the polycrystalline silicon semiconductor 103 is patterned.

The 1 st gate insulating film 104 is formed of a SiN film or the like so as to cover the polycrystalline silicon semiconductor 103. A 1 st gate electrode 105 is formed over the 1 st gate insulating film 104. The material of the 1 st gate electrode 105 is, for example, a stacked structure of MoW or Ti-Al-Ti. Simultaneously with the formation of the 1 st gate electrode 105, a 2 nd light-shielding film 106 for the oxide semiconductor 109 is formed. That is, the 1 st gate electrode 105 and the 2 nd light shielding film 106 are formed of the same material. The composition and the action of the 2 nd light shielding film 106 are as illustrated in fig. 2.

An interlayer insulating film 108 is formed to cover the 1 st gate electrode 105 and the 2 nd light-shielding film 106. The interlayer insulating film 108 has, for example, a two-layer structure, and has a SiN film on the lower side and a SiO film on the upper side. In this case, hydrogen is supplied from the lower SiN film to the polycrystalline silicon semiconductor 103, and oxygen is supplied from the upper SiO film to the oxide semiconductor 109.

An oxide semiconductor 109 is formed over the interlayer insulating film 108, and a drain electrode 110 and a source electrode 111 are stacked and formed at an end portion of the oxide semiconductor 109. The oxide semiconductor 109, the drain electrode 110, and the source electrode 111 are formed as described with reference to fig. 2 to 4. A 2 nd gate insulating film 112 is formed so as to cover the oxide semiconductor 109, the drain electrode 110, and the source electrode 111, and a 2 nd gate electrode 114 is formed thereon with an AlO film 113 interposed therebetween. An inorganic passivation film 115 is formed to cover the 2 nd gate electrode 114. The structure from the oxide semiconductor 109 to the formation of the inorganic passivation film 115 and the functions of these films are as described in fig. 2.

Then, through holes 171, 172, 173, 174, 130, 131, 134, 137, and the like are formed in the inorganic passivation film 115, the 2 nd gate insulating film 112, the interlayer insulating film 108, and the like, and the 1 st shield wiring 116, the 1 st drain electrode 117, the 1 st gate wiring 118, the 1 st source electrode 119, the 2 nd drain electrode 120, the 2 nd gate wiring 121, the 2 nd source wiring 122, the 2 nd shield wiring 123, and the like are formed in each through hole.

In the through-holes 172 and 174, hydrofluoric acid (HF) is used to remove the oxide on the surface of the polycrystalline silicon semiconductor 103, and the hydrofluoric acid (HF) also penetrates into the other through-holes. In the structure of fig. 8, hydrofluoric acid (HF) is in contact with the drain electrode 110 and the source electrode 111 in the through holes 130 and 131, but not in contact with the oxide semiconductor 109, and therefore the oxide semiconductor 109 can be prevented from being lost by hydrofluoric acid (HF).

However, in this configuration, when the drain electrode 110 and the source electrode 111 are formed on both sides of the oxide semiconductor 109, the oxide semiconductor 109 is contaminated when metal for forming the drain electrode 110 and the source electrode 111 is sputtered or when the drain electrode 110 and the source electrode 111 are patterned, and the characteristics of the oxide semiconductor 109 become unstable.

Fig. 9 is a cross-sectional view of the hybrid structure in the present invention to address this problem. In fig. 9, the steps up to formation of the oxide semiconductor 109 are the same as those in fig. 8. Fig. 9 differs from fig. 8 in that: the 2 nd gate insulating film 112 is formed after the oxide semiconductor 109 is patterned. Therefore, the oxide semiconductor 109 is not contaminated by deposition of a metal film for forming the drain electrode 110 and the source electrode 111 and patterning of the metal film.

In fig. 9, through holes 132 and 133 for forming the drain electrode 110 and the source electrode 111 are formed in the 2 nd gate insulating film 112. Then, a drain electrode 110, a 2 nd gate electrode 114, and a source electrode 111 are formed on the 2 nd gate insulating film 112.

Then, an inorganic passivation film 115 is formed to cover the drain electrode 110, the 2 nd gate electrode 114, and the drain electrode 111. Then, through holes 171, 172, 173, 174, 130, 131, 134, 137 are formed in the inorganic passivation film 115, the 2 nd gate insulating film 112, the interlayer insulating film 108, the 1 st gate insulating film, and the like, and then the 1 st shield wiring 116, the 1 st drain electrode 117, the 1 st gate electrode 118, the 1 st source electrode 119, the video signal line 12, the 2 nd gate wiring 121, the 2 nd source wiring 122, the 2 nd shield wiring 123, and the like are formed in the respective through holes.

In the through-holes 172 and 174, hydrofluoric acid (HF) is used to remove the oxide on the surface of the polycrystalline silicon semiconductor, and in the structure of fig. 9, hydrofluoric acid (HF) is in contact with the drain electrode 110 and the source electrode 111 but not in contact with the oxide semiconductor 109 in the through-holes 130 and 131, and therefore, the oxide semiconductor 109 can be prevented from being lost due to hydrofluoric acid (HF). Further, since the drain electrode 110 and the source electrode 111 are formed on the 2 nd gate insulating film 112, the oxide semiconductor can be prevented from being contaminated when the drain electrode 110 and the source electrode 111 are formed. Therefore, an oxide semiconductor TFT with stable characteristics can be formed.

Thus, according to embodiment 1, an oxide semiconductor TFT with stable characteristics can be formed. Further, a liquid crystal display device having a mixed structure of a polysilicon semiconductor TFT and an oxide semiconductor TFT with stable characteristics can be realized.

[ example 2]