阅读说明：本技术 半导体器件及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 申宇哲 姜明吉 益冈完明 李相勋 黄成万 于 2019-08-12 设计创作，主要内容包括：提供了一种半导体器件及其制造方法,该半导体器件包括：第一半导体层,具有第一区域和第二区域；多个第一沟道层,在第一半导体层的第一区域上沿垂直方向彼此隔开；第一栅电极,围绕所述多个第一沟道层；多个第二沟道层,在第一半导体层的第二区域上沿垂直方向彼此隔开；以及第二栅电极,围绕所述多个第二沟道层,其中,所述多个第一沟道层中的每个具有第一晶向,并且所述多个第二沟道层中的每个具有不同于第一晶向的第二晶向,其中,所述多个第一沟道层中的每个的厚度不同于所述多个第二沟道层中的每个的厚度。(Provided are a semiconductor device and a method of manufacturing the same, the semiconductor device including: a first semiconductor layer having a first region and a second region; a plurality of first channel layers spaced apart from each other in a vertical direction on a first region of the first semiconductor layer; a first gate electrode surrounding the plurality of first channel layers; a plurality of second channel layers spaced apart from each other in a vertical direction on a second region of the first semiconductor layer; and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystal orientation and each of the plurality of second channel layers has a second crystal orientation different from the first crystal orientation, wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.)

1. A semiconductor device, the semiconductor device comprising:

a first semiconductor layer including a first region and a second region;

a plurality of first channel layers spaced apart from each other in a vertical direction in the first region and on the first semiconductor layer;

a first gate electrode surrounding the plurality of first channel layers;

a plurality of second channel layers spaced apart from each other in a vertical direction in the second region and on the first semiconductor layer; and

a second gate electrode surrounding the plurality of second channel layers,

wherein each of the plurality of first channel layers has a first crystal orientation and each of the plurality of second channel layers has a second crystal orientation different from the first crystal orientation, wherein a thickness of at least one of the plurality of first channel layers is greater than a thickness of at least one of the plurality of second channel layers.

2. The semiconductor device of claim 1, wherein the first crystal orientation is a (100) orientation and the second crystal orientation is a (110) orientation.

3. The semiconductor device of claim 1, wherein each of the plurality of second channel layers has a same thickness.

4. The semiconductor device of claim 1, wherein a thickness of each of the plurality of second channel layers is less than a thickness of each of the plurality of first channel layers.

5. The semiconductor device of claim 1, wherein the plurality of second channel layers have different thicknesses.

6. The semiconductor device according to claim 5, wherein the plurality of second channel layers include a first sub-channel layer, a second sub-channel layer, and a third sub-channel layer in this order below the second gate electrode, and a thickness of the third sub-channel layer is larger than thicknesses of the first sub-channel layer and the second sub-channel layer, and the first sub-channel layer is closer to the first semiconductor layer than the third sub-channel layer.

7. The semiconductor device of claim 1, wherein a number of the plurality of first channel layers is different from a number of the plurality of second channel layers.

8. The semiconductor device of claim 7, wherein each of the plurality of second channel layers has a same thickness, and the thickness of each of the plurality of second channel layers is less than the thickness of each of the plurality of first channel layers.

9. The semiconductor device of claim 1, further comprising:

a buried insulating layer in the first region and between the first semiconductor layer and the first gate electrode;

and a second semiconductor layer extending in one direction on the buried insulating layer.

10. The semiconductor device of claim 9, wherein the second semiconductor layer has a first crystal orientation.

11. The semiconductor device of claim 10, further comprising:

and a body layer in the second region and between the second gate electrode and the first semiconductor layer, wherein the body layer has a second crystal orientation.

12. The semiconductor device of claim 11, wherein the first semiconductor layer has a second crystal orientation.

13. The semiconductor device of claim 11, further comprising: and a device isolation layer covering the upper surface of the first semiconductor layer and the side surface of the base layer in the second region.

14. A semiconductor device, the semiconductor device comprising:

a first semiconductor layer including an n-type metal oxide semiconductor region and a p-type metal oxide semiconductor region;

a buried insulating layer located in the n-type metal oxide semiconductor region and on the first semiconductor layer;

a second semiconductor layer on the buried insulating layer;

a base layer located in the p-type metal oxide semiconductor region and on the first semiconductor layer;

a plurality of first channel layers including silicon and spaced apart from each other in a vertical direction on the second semiconductor layer;

a first gate electrode surrounding the plurality of first channel layers;

a plurality of second channel layers including silicon and spaced apart from each other in a vertical direction on the base layer; and

a second gate electrode surrounding the plurality of second channel layers,

wherein each of the plurality of first channel layers has a first crystal orientation and each of the plurality of second channel layers has a second crystal orientation different from the first crystal orientation, an

Wherein the substrate layer has a second crystal orientation.

15. The semiconductor device of claim 14, wherein the first crystal orientation is a (100) orientation and the second crystal orientation is a (110) orientation.

16. The semiconductor device of claim 14, wherein a gap between the plurality of first channel layers is different from a gap between the plurality of second channel layers.

17. The semiconductor device of claim 14, wherein:

the first semiconductor layer and the second semiconductor layer comprise silicon;

the first semiconductor layer has a (110) crystal orientation; and is

The second semiconductor layer has a (100) crystal orientation.

18. The semiconductor device of claim 17, further comprising:

source/drain regions on both sides of each of the plurality of first channel layers; and

and an interlayer insulating layer covering the upper surface of the buried insulating layer, the side surface of the second semiconductor layer, and the source/drain regions.

19. The semiconductor device of claim 18, wherein the lattice constant of the source/drain regions is less than the lattice constant of silicon.

20. The semiconductor device of claim 18, further comprising:

an inner spacer between the plurality of first channel layers and between one of the plurality of first channel layers and the second semiconductor layer, wherein an outer surface of the inner spacer is in contact with the source/drain region.

Technical Field

Devices and methods consistent with example embodiments relate to a semiconductor device having a plurality of channel layers and a method of manufacturing the semiconductor device.

Background

With the demand for high integration and miniaturization of semiconductor devices, the size of transistors of the semiconductor devices is also being miniaturized. In order to prevent short channel effects due to size miniaturization of transistors, transistors having multiple channels have been proposed. Further, there is a problem of a method of improving the performance of a semiconductor device by optimizing the mobility of carriers in a channel.

Disclosure of Invention

According to an example embodiment, there is provided a semiconductor device including: a first semiconductor layer including a first region and a second region; a plurality of first channel layers disposed to be spaced apart from each other in a vertical direction on a first region of the first semiconductor layer; a first gate electrode configured to surround the plurality of first channel layers; a plurality of second channel layers disposed to be spaced apart from each other in a vertical direction on a second region of the first semiconductor layer; and a second gate electrode configured to surround the plurality of second channel layers. The plurality of first channel layers may have a first crystal orientation, and the plurality of second channel layers may have a second crystal orientation different from the first crystal orientation. A thickness of each of the plurality of first channel layers may be different from a thickness of each of the plurality of second channel layers.

According to an example embodiment, there is provided a semiconductor device including: a first semiconductor layer including an n-type metal oxide semiconductor (NMOS) region and a p-type metal oxide semiconductor (PMOS) region; a buried insulating layer disposed in the NMOS region of the first semiconductor layer; a second semiconductor layer disposed on the buried insulating layer; a body layer disposed in the PMOS region of the first semiconductor layer; a plurality of first channel layers including silicon and disposed to be spaced apart from each other in a vertical direction on the second semiconductor layer; a first gate electrode configured to surround the plurality of first channel layers; a plurality of second channel layers including silicon and disposed to be spaced apart from each other in a vertical direction on the base layer; and a second gate electrode configured to surround the plurality of second channel layers. The plurality of first channel layers may have a first crystal orientation, the plurality of second channel layers may have a second crystal orientation different from the first crystal orientation, and a thickness of each of the plurality of second channel layers may be less than a thickness of each of the plurality of first channel layers.

According to an example embodiment, there is provided a method of manufacturing a semiconductor device, the method including: providing a first semiconductor layer having a first region and a second region, a buried insulating layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the buried insulating layer; forming a first stack in which a plurality of first sacrificial layers and a plurality of first channel layers are alternately stacked on the second semiconductor layer; removing the buried insulating layer, the second semiconductor layer, and a portion of the first stack on the second region using the mask pattern to expose the first semiconductor layer; forming a base layer on the exposed second region and forming a second stack in which a plurality of second sacrificial layers and a plurality of second channel layers are alternately stacked on the base layer; and patterning the first stack and the second stack into a fin shape. The first channel layer may have a first crystal orientation, and the second channel layer may have a second crystal orientation different from the first crystal orientation.

Drawings

Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the attached drawings, wherein:

fig. 1 shows a perspective view of a semiconductor device according to an example embodiment;

fig. 2 shows a vertical cross-sectional view along lines a-a 'and B-B' of the semiconductor device in fig. 1;

fig. 3 shows a vertical cross-sectional view taken along lines C-C 'and D-D' of the semiconductor device in fig. 1;

FIGS. 4 and 5 show vertical cross-sectional views taken along lines A-A 'and B-B' and lines C-C 'and D-D', respectively, according to an example embodiment;

FIGS. 6 and 7 show vertical cross-sectional views taken along lines A-A 'and B-B' and lines C-C 'and D-D', respectively, according to an example embodiment;

FIGS. 8 and 9 show vertical cross-sectional views taken along lines A-A 'and B-B' and lines C-C 'and D-D', respectively, according to an example embodiment;

FIGS. 10 and 11 show vertical cross-sectional views taken along lines A-A 'and B-B' and lines C-C 'and D-D', respectively, according to an example embodiment;

FIGS. 12 and 13 show vertical cross-sectional views taken along lines A-A 'and B-B' and lines C-C 'and D-D', respectively, according to an example embodiment;

figures 14-20 show cross-sectional views of stages in a method of manufacturing a first stack and a second stack according to an example embodiment; and

fig. 21 to 31 show perspective and cross-sectional views of stages in a method of manufacturing a semiconductor device according to an example embodiment.

Detailed Description

Fig. 1 illustrates a perspective view showing a semiconductor device according to an example embodiment. Fig. 2 shows vertical cross-sectional views taken along line a-a 'of the first transistor and line B-B' of the second transistor shown in fig. 1, respectively. Fig. 3 shows vertical cross-sectional views taken along line C-C 'of the first transistor and line D-D' of the second transistor shown in fig. 1, respectively.

The semiconductor device according to example embodiments may include a first transistor 100 disposed in a first region I and a second transistor 200 disposed in a second region II. The semiconductor device may be a Complementary Metal Oxide Semiconductor (CMOS) device. The first region I may be an n-type metal oxide semiconductor (NMOS) region and the second region II may be a p-type metal oxide semiconductor (PMOS) region. The first transistor 100 and the second transistor 200 may be a gate-all-around field effect transistor (GAAFET).

Referring to fig. 1 to 3, the first transistor 100 may include a first semiconductor layer 102, a buried insulating layer 103, a second semiconductor layer 104, first channel layers 112, 114, and 116, a gate spacer 135, a source/drain region 150, an interlayer insulating layer 160, and a gate electrode 170. The first transistor 100 may further include an inner spacer 140 and a gate dielectric layer 172.

The first semiconductor layer 102 may include, for example, silicon. The buried insulating layer 103 and the second semiconductor layer 104 may be sequentially disposed on the first semiconductor layer 102. The first semiconductor layer 102 and the buried insulating layer 103 may be disposed on the entire surface of the lower portion of the first region I, and the second semiconductor layer 104 may be disposed to have a predetermined width in the second direction D2 and to extend in the first direction D1.

The buried insulating layer 103 may comprise, for example, silicon oxide. The buried insulating layer 103 may electrically insulate the first semiconductor layer 102 from the second semiconductor layer 104. In an example embodiment, the second semiconductor layer 104 may include, for example, silicon. The first semiconductor layer 102 and the second semiconductor layer 104 may have different crystal orientations. For example, the upper surface of the first semiconductor layer 102 (i.e., the surface of the first semiconductor layer 102 facing the buried insulating layer 103) may have a (110) orientation, and the upper and lower surfaces of the second semiconductor layer 104 may each have a (100) orientation. In example embodiments, the second semiconductor layer 104 may include a group IV semiconductor (e.g., Ge, SiGe, etc.) or a group III-V compound (e.g., InGaAs, InAs, GaSb, InSb, etc.).

The plurality of first channel layers 112, 114, and 116 may be disposed on the second semiconductor layer 104 to be spaced apart from each other, for example, along the third direction D3. Each of the plurality of first channel layers 112, 114, and 116 may have a predetermined length in the first direction D1 and a predetermined width in the second direction D2. Each of the plurality of first channel layers 112, 114, and 116 may be rectangular in shape when viewed in a cross-sectional view, and an upper surface and a lower surface of each of them may be larger than a side surface of each of them. In an example embodiment, each of the plurality of first channel layers 112, 114, and 116 may include, for example, silicon. The plurality of first channel layers 112, 114, and 116 may each have the same crystal orientation as that of the second semiconductor layer 104. For example, an upper surface and a lower surface of each of the plurality of first channel layers 112, 114, and 116 may each have a (100) orientation. In example embodiments, each of the plurality of first channel layers 112, 114, and 116 may include a group IV semiconductor (e.g., Ge, SiGe, etc.) or a group III-V compound (e.g., InGaAs, InAs, GaSb, InSb, etc.). For example, each of the plurality of first channel layers 112, 114, and 116 may be composed of multiple layers of a III-V compound (e.g., InP/InGaAs/InAs, GaAs/InP/InAs, GaAs/InGaAs/InAs, GaAs/InAlAs/InAs, InP/InGaAs/InP, GaAs/InAs, GaAs/InGaAs, or InP/InGaAs).

The source/drain regions 150 may be disposed on both sides (e.g., opposite sides) of each of the plurality of first channel layers 112, 114, and 116 in the first direction D1. The width of the source/drain region 150 in the second direction D2 may be formed to be greater than the width of the second semiconductor layer 104 in the second direction D2, and the source/drain region 150 may have a pentagonal cross-section. The source/drain region 150 may be electrically connected to the plurality of first channel layers 112, 114, and 116. The source/drain region 150 may be formed by Selective Epitaxial Growth (SEG), and may be doped with impurities.

For example, when the first transistor 100 is an NMOS transistor, the source/drain region 150 may include silicon doped with n-type impurities, and may have a lattice constant smaller than that of silicon. The source/drain regions 150 may improve the mobility of carriers by applying tensile stress to the first channel layers 112, 114, and 116, which are channel regions.

An interlayer insulating layer 160 may be disposed on the source/drain regions 150 and on the outer side of the gate electrode 170. The interlayer insulating layer 160 may completely cover the upper surface of the buried insulating layer 103, the side surface of the second semiconductor layer 104, and the source/drain region 150. The interlayer insulating layer 160 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material, and may be composed of one or more layers. For example, the low-k dielectric material may include undoped silicon dioxide glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Plasma Enhanced Tetraethylorthosilicate (PETEOS), Fluoride Silicate Glass (FSG), High Density Plasma (HDP) oxide, or a combination thereof.

The gate structure may be disposed to extend in the second direction D2 and to surround the plurality of first channel layers 112, 114, and 116. The gate dielectric layer 172 may be conformally disposed along the surfaces of the buried insulating layer 103, the second semiconductor layer 104, the plurality of first channel layers 112, 114, and 116, the gate spacer 135, and the inter-spacer 140. Gate dielectric layer 172 may comprise, for example, a high-k dielectric material.

For example, the high-k dielectric material may include hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium silicate, tantalum oxide, Barium Strontium Titanate (BST), barium titanate, strontium titanate, yttrium oxide, aluminum oxide, or combinations thereof. In example embodiments, the gate dielectric layer 172 may include hafnium oxide (HfO)₂)。

Gate electrode 170 may be disposed on gate dielectric layer 172. As shown in fig. 3, in the cross-sectional view in the second direction D2, the gate electrode 170 may completely cover the plurality of first channel layers 112, 114, and 116. Gate electrode 170 can include, for example, aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, or combinations thereof. In an example embodiment, gate electrode 170 may include tungsten.

An oxide layer may be disposed on surfaces of the plurality of first channel layers 112, 114, and 116. In addition, a work function adjusting layer may be included on the gate dielectric layer 172.

Gate spacers 135 may be disposed on two sides (e.g., opposite sides) of gate electrode 170 in first direction D1. Gate spacers 135 may be disposed to face each other on both sides of gate electrode 170. The gate spacer 135 may protect the gate electrode 170. The gate spacer 135 may be comprised of one or more layers. The first transistor 100 may further include a cap layer. A capping layer may be disposed on the gate spacer 135, the interlayer insulating layer 160, and the gate electrode 170.

The inner spacers 140 may be disposed on both sides (e.g., opposite sides) of the gate electrode 170 in the first direction D1. The inter-spacers 140 may be disposed between the first channel layers 112, 114, and 116 and between the first channel layer 112 and the second semiconductor layer 104. An outer surface of the inner spacer 140 contacting the source/drain region 150 may be coplanar with outer surfaces of the first channel layers 112, 114, and 116. The width of the inner spacers 140 in the first direction D1 may be substantially equal to the width of the gate spacers 135 in the first direction D1. The interior spacers 140 may comprise, for example, silicon oxide, silicon nitride, a low-k dielectric material, or a combination thereof.

The second transistor 200 in the second region II may include a configuration similar to that of the first transistor 100. In detail, the second transistor 200 may include a first semiconductor layer 102, a device isolation layer 203, a body layer 204, second channel layers 212, 214, and 216, a gate spacer 235, source/drain regions 250, an interlayer insulating layer 260, and a gate electrode 270. The second transistor 200 may further include an inner spacer 240 and a gate dielectric layer 272.

The device isolation layer 203 may cover a portion of the first semiconductor layer 102, the base layer 204 may be disposed on a portion of the first semiconductor layer 102 that is not covered by the device isolation layer 203, the base layer 204 may protrude from the first semiconductor layer 102 in a third direction D3, e.g., through the device isolation layer 203, the base layer 204 may be disposed to extend in a first direction D1, a lower surface of the device isolation layer 203 may be coplanar with a lower surface of the base layer 204, an upper surface of the device isolation layer 203 may be located at a lower level than an upper surface of the base layer 204, the device isolation layer 203 may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material, the device isolation layer 203 may be formed by, e.g., an atomic layer deposition (A L D) method, a Chemical Vapor Deposition (CVD) method, or the like.

The plurality of second channel layers 212, 214, and 216 may be disposed on the body layer 204 to be spaced apart from each other, for example, along the third direction D3. Each of the plurality of second channel layers 212, 214, and 216 may have a rectangular shape when viewed in a cross-sectional view, and an upper surface and a lower surface of each of them may be larger than a side surface of each of them. The plurality of second channel layers 212, 214, and 216 may include, for example, silicon, and may each have the same crystal orientation as that of the first semiconductor layer 102. For example, upper and lower surfaces of the plurality of second channel layers 212, 214, and 216 may each have a (110) orientation.

The first channel layers 112, 114, and 116 may each have a thickness T in the third direction d 3. The second channel layers 212, 214, and 216 may each have a thickness T' in the third direction D3. The thickness T may be formed to be substantially equal to the thickness T'.

As shown in fig. 2 and 3, the first channel layers 112, 114, and 116 and the second channel layers 212, 214, and 216 may each have a cross-section in the form of a rectangular sheet, but the embodiment is not limited thereto, and for example, the layers may each have a cross-section in the form of a line. For example, in a vertical cross-section taken along the line C-C 'or D-D', the first channel layers 112, 114, and 116 and/or the second channel layers 212, 214, and 216 may each have a cross-section in the form of a circle or an ellipse. In example embodiments, the plurality of first channel layers 112, 114, and 116 and the plurality of second channel layers 212, 214, and 216 may each have a cross-section in the form of, for example, a trapezoid, a triangle, or a diamond whose lower surface is greater than the upper surface.

Electrons may be used as carriers in NMOS transistors and holes may be used as carriers in PMOS transistors. Electron mobility is high in silicon with a (100) orientation, while hole mobility is high in silicon with a (110) orientation. In the semiconductor device according to example embodiments, the first channel layers 112, 114, and 116 and the second channel layers 212, 214, and 216 may each include silicon, upper surfaces of the first channel layers 112, 114, and 116 may each have a (100) orientation, and upper surfaces of the second channel layers 212, 214, and 216 may each have a (110) orientation. As described above, the crystal orientation of the first channel layers 112, 114, and 116 is made different from the crystal orientation of the second channel layers 212, 214, and 216, so that mobility in the NMOS transistor and the PMOS transistor can be optimized. Therefore, a semiconductor device having a high operation speed can be realized.

In example embodiments, the first region I may correspond to a PMOS region, the second region II may correspond to an NMOS region, upper surfaces of the plurality of first channel layers 112, 114, and 116 may each have a (110) orientation, and upper surfaces of the plurality of second channel layers 212, 214, and 216 may each have a (100) orientation. In this case, the upper surface of the second semiconductor layer 104 has a (110) orientation, and the base layer 204 has a (100) orientation.

The source/drain regions 250 may be disposed on both sides of each of the plurality of second channel layers 212, 214, and 216. When the second transistor 200 is a PMOS transistor, the source/drain region 250 may include SiGe doped with p-type impurities and may have a lattice constant greater than that of silicon. The source/drain region 250 may improve the mobility of carriers by applying a compressive stress to the second channel layers 212, 214, and 216.

The gate structure may include a gate electrode 270 and a gate dielectric layer 272. The gate dielectric layer 272 may be conformally disposed along the surfaces of the device isolation layer 203, the body layer 204, the plurality of second channel layers 212, 214, and 216, the gate spacer 235, and the inter-spacer 240. A gate electrode 270 may be disposed on the gate dielectric layer 272.

Fig. 4 and 5 show cross-sectional views of a semiconductor device according to example embodiments. Fig. 4 shows a vertical cross-sectional view taken along line a-a 'of the first transistor and line B-B' of the second transistor, respectively, corresponding to the vertical cross-sectional view of fig. 2, according to an example embodiment. Fig. 5 shows a vertical cross-sectional view taken along line C-C 'of the first transistor and line D-D' of the second transistor, respectively, corresponding to the vertical cross-sectional view of fig. 3, according to an example embodiment.

Referring to fig. 4 and 5, the second transistor 200a may include a plurality of second channel layers 212a, 214a, and 216 a. The second channel layers 212a, 214a, and 216a may each have a thickness T' a in the third direction D3. As described below, the first channel layers 112, 114, and 116 and the second channel layers 212a, 214a, and 216a are formed through different processes, and thus may be formed to have different thicknesses. For example, the thickness T' a of each of the second channel layers 212a, 214a, and 216a may be formed to be smaller than the thickness T of each of the first channel layers 112, 114, and 116. A gap between the second channel layers 212a, 214a, and 216a may be formed to be larger than a gap between the first channel layers 112, 114, and 116.

In general, when the channel layer is short, a leakage current between source/drain regions may occur even when a voltage is not applied to the metal gate. As shown in fig. 4 and 5, the second transistor 200a includes second channel layers 212a, 214a, and 216a, each having a relatively small thickness T' a, so that a problem of leakage current occurring between the source/drain regions 250 may be prevented.

Fig. 6 and 7 show cross-sectional views of a semiconductor device according to example embodiments. Fig. 6 shows a vertical cross-sectional view taken along line a-a 'of the first transistor and line B-B' of the second transistor, respectively, corresponding to the vertical cross-sectional view of fig. 2, according to an example embodiment. Fig. 7 shows a vertical cross-sectional view taken along the line C-C 'of the first transistor and the line D-D' of the second transistor, respectively, corresponding to the vertical cross-sectional view of fig. 3, according to an example embodiment.

Referring to fig. 6 and 7, the second transistor 200b may include a plurality of second channel layers 212b, 214b, and 216 b. The second channel layer 212b may have a thickness T ' b3, the second channel layer 214b may have a thickness T ' b2, and the second channel layer 216b may have a thickness T ' b 1. The thicknesses T ' b3, T ' b2, and T ' b1 of the second channel layers 212b, 214b, and 216b may be formed to be different from each other and at least one of them is smaller than the thickness T of the first channel layers 112, 114, and 116. For example, the second channel layer 214b may be formed thinner than the second channel layer 216b and formed thicker than the second channel layer 212 b.

Fig. 8 and 9 show cross-sectional views of semiconductor devices according to example embodiments. Fig. 8 shows a vertical cross-sectional view taken along line a-a 'of the first transistor and line B-B' of the second transistor, respectively, corresponding to the vertical cross-sectional view of fig. 2, according to an example embodiment. Fig. 9 shows a vertical cross-sectional view taken along line C-C 'of the first transistor and line D-D' of the second transistor, respectively, corresponding to the vertical cross-sectional view of fig. 3, according to an example embodiment.

Referring to fig. 8 and 9, the first transistor 100 and the second transistor 200c may have different numbers of channels. In an example embodiment, the first transistor 100 may include three first channel layers 112, 114, and 116, and the second transistor 200c may include four second channel layers 212c, 214c, 216c, and 218 c. A thickness T' c of each of the second channel layers 212c, 214c, 216c, and 218c may be formed to be less than the thickness T of each of the first channel layers 112, 114, and 116. The second channel layers 212c, 214c, 216c, and 218c may have the same thickness T' c, but the embodiment is not limited thereto. Referring to fig. 8 and 9, the second transistor 200c includes second channel layers 212c, 214c, 216c, and 218c, each having a relatively small thickness T' c, so that a short channel effect and a channel resistance may be complementary.

Fig. 10 and 11 illustrate cross-sectional views of semiconductor devices according to example embodiments. Fig. 10 shows a vertical cross-sectional view taken along line a-a 'of the first transistor and line B-B' of the second transistor, respectively, corresponding to the vertical cross-sectional view of fig. 2, according to an example embodiment. Fig. 11 shows a vertical cross-sectional view taken along line C-C 'of the first transistor and line D-D' of the second transistor, respectively, corresponding to the vertical cross-sectional view of fig. 3, according to an example embodiment.

Referring to fig. 10 and 11, an upper surface of the first semiconductor layer 102 at a lower portion of the first transistor 100 may be located at a level different from that of an upper surface of the first semiconductor layer 102d at a lower portion of the second transistor 200 d. For example, the upper surface of the first semiconductor layer 102d may be located at a level lower than that of the upper surface of the first semiconductor layer 102. In a process to be described below, the second region II of the first semiconductor layer 102 may be partially etched to form a first semiconductor layer 102 d. The thickness T may be formed substantially the same as the thickness T', but the embodiment is not limited thereto.

Fig. 12 and 13 show cross-sectional views of semiconductor devices according to example embodiments. Fig. 12 shows a vertical cross-sectional view taken along line a-a 'of the first transistor and line B-B' of the second transistor, respectively, corresponding to the vertical cross-sectional view of fig. 2, according to an example embodiment. Fig. 13 shows a vertical cross-sectional view taken along line C-C 'of the first transistor and line D-D' of the second transistor, respectively, corresponding to the vertical cross-sectional view of fig. 3, according to an example embodiment.

Referring to fig. 12 and 13, the upper surface of the second semiconductor layer 104 may be located at a level different from that of the upper surface of the base layer 204e of the second transistor 200 e. For example, the upper surface of the base layer 204e may be located at a lower level than the level of the upper surface of the second semiconductor layer 104. In an example embodiment, the upper surface of the base layer 204e may be located at a higher level than the level of the upper surface of the second semiconductor layer 104. The thickness T may be formed substantially the same as the thickness T', but the embodiment is not limited thereto.

Fig. 14 to 20 are cross-sectional views for describing a method of manufacturing the first stack 110 and the second stack 210 according to example embodiments and are shown according to a process sequence.

Referring to fig. 14, a first semiconductor layer 102, a buried insulating layer 103, and a second semiconductor layer 104 may be provided. For example, the first semiconductor layer 102, the buried insulating layer 103, and the second semiconductor layer 104 may be a silicon-on-insulator (SOI) substrate. For example, an SOI substrate may be formed by bonding a substrate (e.g., the first semiconductor layer 102) to another substrate having an oxide film thereon (e.g., the second semiconductor layer 104 having the buried insulating layer 103 thereon), so that a structure in which the buried insulating layer 103 is sandwiched between the first semiconductor layer 102 and the second semiconductor layer 104 can be formed. In example embodiments, the first and second semiconductor layers 102 and 104 may include silicon, and the silicon in the first and second semiconductor layers 102 and 104 may have different crystal orientations. For example, the upper surface of the first semiconductor layer 102 may have a (110) orientation and the upper surface of the second semiconductor layer 104 may have a (100) orientation. In example embodiments, the first semiconductor layer 102 and/or the second semiconductor layer 104 may include a group IV semiconductor (e.g., Ge, SiGe, etc.) or a group III-V compound (e.g., InGaAs, InAs, GaSb, InSb, etc.).

Referring to fig. 15, a first stack 110 may be formed on the second semiconductor layer 104. The first stack 110 may have a structure in which a plurality of sacrificial layers 111, 113, and 115 and a plurality of first channel layers 112, 114, and 116 are alternately stacked. The plurality of sacrificial layers 111, 113, and 115 and the plurality of first channel layers 112, 114, and 116 may be formed by epitaxial growth with the second semiconductor layer 104 as a seed layer. The plurality of sacrificial layers 111, 113, and 115 may include a material having an etch selectivity with respect to the plurality of first channel layers 112, 114, and 116. In example embodiments, the plurality of sacrificial layers 111, 113, and 115 may include, for example, SiGe, and the plurality of first channel layers 112, 114, and 116 may include Si. For example, since the plurality of first channel layers 112, 114, and 116 are grown from the second semiconductor layer 104, the plurality of first channel layers 112, 114, and 116 may each have the same crystal orientation as that of the second semiconductor layer 104. For example, an upper surface and a lower surface of each of the plurality of first channel layers 112, 114, and 116 may each have a (100) orientation. In example embodiments, the plurality of sacrificial layers 111, 113, and 115 and/or the plurality of first channel layers 112, 114, and 116 may include a group IV semiconductor (e.g., Si, Ge, SiGe, etc.) or a III-V compound.

Referring to fig. 16, a mask pattern M1 may be disposed on the first stack 110. For example, the mask pattern M1 may be disposed in the first region I, and the mask pattern M1 may not be disposed in the second region II.

Referring to fig. 17, a portion of the first stack 110 exposed by the mask pattern M1 and in the second region II may be removed. The buried insulating layer 103 and the second semiconductor layer 104 in the second region II may be etched to expose the first semiconductor layer 102. In fig. 18, the upper surface of the first semiconductor layer 102 in the first region I and the upper surface of the first semiconductor layer 102 in the second region II have been shown to be located at the same level, but the embodiment is not limited thereto. In example embodiments, the first semiconductor layer 102 in the second region II may be over-etched, and thus an upper surface of the first semiconductor layer 102 in the second region II may be located at a lower level than that of the upper surface of the first semiconductor layer 102 in the first region I.

Referring to fig. 18, the pad 120 may be formed on a side surface of the first stack 110 in the first direction D1 the pad 120 may be disposed at a boundary between the first region I and the second region II the pad 120 may be formed by forming an insulating layer on the resultant structure of fig. 18 by CVD or a L D and then, when performing anisotropic etching, leaving the insulating layer only on the side surface of the first stack 110.

Referring to fig. 19, a base layer 204 and a second stack 210 disposed on the base layer 204 may be formed on a portion of the exposed first semiconductor layer 102. A base layer 204 and a second stack 210 may be provided in the second zone II. The second stack 210 may have a structure in which a plurality of sacrificial layers 211, 213, and 215 and a plurality of second channel layers 212, 214, and 216 are alternately stacked. The base layer 204, the plurality of sacrificial layers 211, 213, and 215, and the plurality of second channel layers 212, 214, and 216 may be formed by epitaxial growth with the first semiconductor layer 102 as a seed layer. The plurality of sacrificial layers 211, 213, and 215 may include a material having an etch selectivity with respect to the plurality of second channel layers 212, 214, and 216. In an example embodiment, the plurality of sacrificial layers 211, 213, and 215 may include SiGe, and the body layer 204 and the plurality of second channel layers 212, 214, and 216 may include Si. For example, since the body layer 204 and the plurality of second channel layers 212, 214, and 216 are grown from the first semiconductor layer 102, the body layer 204 and the plurality of second channel layers 212, 214, and 216 may have the same crystal orientation as that of the first semiconductor layer 102. For example, an upper surface and a lower surface of each of the plurality of second channel layers 212, 214, and 216 may each have a (110) orientation. In example embodiments, the body layer 204 and/or the plurality of second channel layers 212, 214, and 216 may include a group IV semiconductor (e.g., Si, Ge, SiGe, etc.) or a group III-V compound. Each of the plurality of second channel layers 212, 214, and 216 may be composed of multiple layers.

Referring to fig. 20, the mask pattern M1 may be removed, and the pad 120 may be partially etched. The first channel layers 112, 114, and 116 and the second channel layers 212, 214, and 216 may also be partially etched.

As shown in fig. 14 to 20, the first stack 110 and the second stack 210 may be formed through separate processes. In example embodiments, the first stack 110 may be formed first, and then, the second stack 210 may be formed on the first semiconductor layer 102 exposed by removing a portion of the first stack 110. The upper surfaces of the first channel layers 112, 114, and 116 and the upper surfaces of the second channel layers 212, 214, and 216 may be located at the same level.

In fig. 20, the plurality of sacrificial layers 111, 113, 115, 211, 213, and 215, the first channel layers 112, 114, and 116, and the second channel layers 212, 214, and 216 have been illustrated to have the same thickness, but the embodiment is not limited thereto. In example embodiments, the plurality of sacrificial layers 111, 113, and 115 may be formed thicker than the plurality of first channel layers 112, 114, and 116. The plurality of sacrificial layers 211, 213, and 215 may be formed thicker than the plurality of second channel layers 212, 214, and 216.

Fig. 14-20 show that the first semiconductor layer 102 comprising silicon has a (110) orientation, while the second semiconductor layer 104 has a (100) orientation. However, the embodiments are not limited thereto. In an example embodiment, the first semiconductor layer 102 including silicon may have a (100) orientation, and the second semiconductor layer 104 may have a (110) orientation. In this case, each of the first channel layers 112, 114, and 116 may have the same (110) orientation as that of the second semiconductor layer 104, and the second channel layers 212, 214, and 216 may each have the same (100) orientation as that of the first semiconductor layer 102.

Since the first stack 110 and the second stack 210 are formed through separate processes, the first stack 110 and the second stack 210 may have different structures. In example embodiments, the plurality of second channel layers 212, 214, and 216 may be formed thinner than the plurality of first channel layers 112, 114, and 116. The thickness of each of the plurality of sacrificial layers 211, 213, and 215 may be formed to be greater than the thickness of each of the plurality of sacrificial layers 111, 113, and 115. In example embodiments, the plurality of second channel layers 212, 214, and 216 may have different thicknesses. Alternatively, the plurality of first channel layers 112, 114, and 116 may have different thicknesses. The thicknesses of the plurality of first channel layers 112, 114, and 116, the second channel layers 212, 214, and 216, and the sacrificial layers 111, 113, 115, 211, 213, and 215 may be adjusted in the third direction D3, which is a vertical direction, so that transistors having various characteristics can be formed without changing existing design rules.

Fig. 21 to 23, 24A, 25A, 26A, 27A, 28A, 29A, 30A and 31 illustrate perspective and cross-sectional views for describing a method of manufacturing a semiconductor device according to an example embodiment and according to a process sequence. Fig. 24B, 25B, 26B, 27B, 28B, 29B, and 30B are vertical sectional views taken along lines a-a 'and B-B' in fig. 24A, 25A, 26A, 27A, 28A, 29A, and 30A.

Referring to fig. 21, the first stack 110 and the second stack 210 may be patterned in a fin shape. The buried insulating layer 103 of the first region I and the first semiconductor layer 102 of the second region II may be exposed. The first semiconductor layer 102 and the buried insulating layer 103 may not be etched. Base layer 204 may have the same pattern as the pattern of second stack 210.

The patterned first stack 110, the second semiconductor layer 104, the base layer 204, and the second stack 210 may have a shape protruding from the first semiconductor layer 102 in the third direction D3. The patterned first stack 110, second semiconductor layer 104, base layer 204, and second stack 210 may extend in a first direction D1. In fig. 21, the widths of the patterned first stack 110, the second semiconductor layer 104, the base layer 204, and the second stack 210 have been illustrated as being constant in the second direction D2, but the embodiment is not limited thereto. In an example embodiment, the patterned first stack 110 and the patterned base layer 204 may have a shape in which a width in the second direction D2 increases downward. The patterned second stack 210 may also have a shape in which the width in the second direction D2 increases downward.

Referring to fig. 22, a device isolation layer 203 may be formed in the second region II and on the first semiconductor layer 102. The device isolation layer 203 may partially cover the upper surface of the first semiconductor layer 102 and the side surface of the base layer 204 in the second region II. Device isolation layer 203 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material.

Referring to fig. 23, a dummy gate structure may be formed on each of the first stack 110 and the second stack 210. The dummy gate structure may include dummy gate insulation layers 130 and 230, dummy gate electrodes 132 and 232, and dummy capping layers 134 and 234. The dummy gate structure may be disposed to cross each of the first and second stacks 110 and 210, and may also extend in the second direction D2. The dummy gate structure may cover a side surface and an upper surface of each of the first and second stacks 110 and 210.

The dummy gate insulating layers 130 and 230, the dummy gate electrodes 132 and 232, and the dummy caps 134 and 234 may be sequentially stacked, the dummy gate insulating layers 130 and 230 may include silicon oxide, and may be formed by, for example, a CVD method, an a L D method, etc., the dummy gate electrodes 132 and 232 may include, for example, polysilicon, the dummy caps 134 and 234 may be formed of, for example, silicon nitride, silicon oxynitride, or a combination thereof.

Referring to fig. 24A and 24B, gate spacers 135 or 235 may be formed on side surfaces of the dummy gate structure. The gate spacers 135 or 235 may be disposed to face each other on both sides of the dummy gate electrode 132 or 232 in the first direction D1. The gate spacers 135 and 235 may not be removed during a subsequent etching process to protect the gate electrodes 170 and 270.

Each of the gate spacers 135 and 235 may be comprised of one or more layers and may include, for example, silicon nitride, silicon oxynitride, or a combination thereof. The gate spacers 135 and 235 may not cover the upper surfaces of the dummy caps 134 and 234.

Referring to fig. 25A and 25B, a portion of the first stack 110 not covered by the dummy gate electrode 132 and a portion of the second stack 210 not covered by the dummy gate electrode 232 may be etched. For example, exposed portions of first stack 110 and second stack 210 may be partially removed to form recesses 110R and 210R. Side surfaces of the sacrificial layers 111, 113, 115, 211, 213, and 215, the first channel layers 112, 114, and 116, and the second channel layers 212, 214, and 216 may be exposed through the recesses 110R and 210R. In an example embodiment, portions of the second semiconductor layer 104 and the base layer 204 may not be etched. In example embodiments, portions of second semiconductor layer 104 outside of gate spacer 135 and portions of body layer 204 outside of gate spacer 235 may be partially or fully removed.

Referring to fig. 26A and 26B, the outer sides of the sacrificial layers 111, 113, 115, 211, 213, and 215 exposed by the recesses 110R and 210R may be partially etched to form a plurality of recesses 140R and 240R. The plurality of recesses 140R and 240R may have a trench or recess shape, and the sacrificial layers 111, 113, 115, 211, 213, and 215 may not be completely removed. The width of the recess 140R or 240R may be substantially equal to the width of the gate spacer 135 or 235. The first channel layers 112, 114, and 116 and the second channel layers 212, 214, and 216 having an etch selectivity with respect to the plurality of sacrificial layers 111, 113, 115, 211, 213, and 215 may not be etched.

Referring to fig. 27A and 27B, a plurality of the internal spacers 140 and 240 may be formed such that a plurality of recesses 140R and 240R may be filled with the plurality of internal spacers 140 and 240.

The internal spacers 140 and 240 may be formed of a material having excellent gap filling capability. The inner spacer 140 may also be formed on the second semiconductor layer 104 and the gate spacer 135. An inner spacer 240 may also be formed on the base layer 204 and the gate spacer 235.

A plurality of interior spacers 140 and 240 may be disposed between the first channel layers 112, 114, and 116 and between the second channel layers 212, 214, and 216. The inter-spacer 140 may be disposed between the second semiconductor layer 104 and the first channel layer 112, and the inter-spacer 240 may also be disposed between the base layer 204 and the second channel layer 212. The outer surfaces of the inner spacers 140 and 240 may be positioned to be coplanar with the outer surfaces of the first channel layers 112, 114, and 116 and the outer surfaces of the second channel layers 212, 214, and 216, respectively.

Referring to fig. 28A and 28B, source/drain regions 150 and 250 may be formed on the second semiconductor layer 104 and an upper portion of the base layer 204. Source/drain regions 150 or 250 may be formed on both sides of the dummy gate structure. For example, the source/drain regions 150 or 250 may be located on the outer surface of the gate spacers 135 or 235. The source/drain regions 150 and 250 may be formed by SEG. The source/drain regions 150 and 250 may be doped with suitable ions according to the type of transistor.

For example, the fin serving as the source/drain region 250 of the PMOS transistor may be doped with a p-type impurity. Boron (B), gallium (Ga), or the like may be used as the p-type impurity. The fin serving as the source/drain region 150 of the NMOS transistor may be doped with n-type impurities. Phosphorus (P), arsenic (As), or the like may be used As the n-type impurity.

The source/drain regions 150 and 250 may have different growths according to crystal orientations, and may have a pentagonal cross-section. However, the embodiment is not limited thereto, and the source/drain regions 150 and 250 may have, for example, a diamond shape, a circular shape, a rectangular shape, a hexagonal shape, or the like.

Referring to fig. 29A and 29B, interlayer insulating layers 160 and 260 may be formed on the source/drain regions 150 and 250, the interlayer insulating layers 160 and 260 may entirely cover the gate spacers 135 and 235 and side surfaces of the source/drain regions 150 and 250, the interlayer insulating layers 160 and 260 may each include, for example, one of silicon oxide, silicon nitride, silicon oxynitride, PSG, BPSG, a low-k dielectric material, and/or a different applicable dielectric material, or may be a multi-layer made of a plurality of layers, in an example embodiment, the interlayer insulating layers 160 and 260 may include silicon oxide, the interlayer insulating layers 160 and 260 may be formed by CVD, Physical Vapor Deposition (PVD), a L D, spin coating, or the like, after the interlayer insulating layers 160 and 260 are formed, upper portions of the interlayer insulating layers 160 and 260 may be partially removed together with the dummy capping layers 134 and 234, and the dummy gate electrodes 132 and 232 may be exposed.

Referring to fig. 30A and 30B, the dummy gate electrodes 132 and 232 may be removed to form recesses 132R and 232R. For example, the dummy gate electrodes 132 and 232 may be removed by dry etching. For example Cl₂、HBr、SF₆Or CF₄May be used for etching.

Referring to fig. 31, the dummy gate insulating layers 130 and 230, the sacrificial layers 111, 113, and 115 of the first stack 110, and the sacrificial layers 211, 213, and 215 of the second stack 210 may be removed to form openings OP1 and OP 2. The sacrificial layers 111, 113, 115, 211, 213, and 215 having etch selectivity with respect to the first channel layers 112, 114, and 116 and the second channel layers 212, 214, and 216 may be removed by selective etching. The inner spacers 140 and 240 may prevent the source/drain regions 150 and 250 from being etched.

Referring to fig. 1 to 3, a gate electrode 170 and a gate dielectric layer 172 may be formed in the recess 132R and the opening OP1 of the first region I. The gate dielectric layer 172 may be conformally formed along the surfaces of the buried insulating layer 103, the second semiconductor layer 104, the first channel layers 112, 114, and 116, the gate spacer 135, and the inner spacer 140. A gate electrode 170 may be formed on the gate dielectric layer 172.

A gate electrode 270 and a gate dielectric layer 272 may be formed in the recess 232R and the opening OP2 of the second region II. A gate dielectric layer 272 may be conformally formed along the surfaces of the device isolation layer 203, the body layer 204, the second channel layers 212, 214, and 216, the gate spacer 235, and the inter-spacer 240. A gate electrode 270 may be formed on the gate dielectric layer 272.

By way of summary and review, example embodiments are directed to a semiconductor device including first and second channel layers having different crystal orientations. In addition, example embodiments are also directed to a method of manufacturing a semiconductor device including first and second channel layers having different crystal orientations.

That is, according to example embodiments, since the first channel layer and the second channel layer have different crystal orientations (e.g., silicon having a (100) orientation and silicon having a (110) orientation), a semiconductor device having a fast operation speed may be realized by optimizing carrier (e.g., electron and hole) mobility in respective NMOS and PMOS transistors according to the crystal orientations. To form a semiconductor device having a hybrid crystal orientation, a silicon-on-insulator (SOI) substrate having a hybrid crystal orientation may be used.

Example embodiments have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless specifically stated otherwise, as will be apparent to one of ordinary skill in the art at the time of filing the present application. It will, therefore, be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as set forth in the appended claims.