阅读说明：本技术 阵列基板及其制作方法、显示器件 (Array substrate, manufacturing method thereof and display device ) 是由 李松举 宋晶尧 付东 于 2018-12-29 设计创作，主要内容包括：本发明涉及一种阵列基板及其制作方法、显示器件,该阵列基板包括衬底、有源层、栅极绝缘层、栅极层、中间介电层、半导体层、漏电极以及源电极；有源层设置在衬底上,栅极绝缘层设置在有源层上,栅极层设置在栅极绝缘层上,中间介电层设置在栅极层以及栅极绝缘层上,半导体层经由第一孔洞中与第二电极连接区形成PN结,漏电极设置在半导体层上,源电极经由第二孔洞与第一电极连接区电性连接。本发明通过设置半导体层与有源层的第二电极连接区形成PN结,形成二极管结构,使阵列基板的电流只能往一个方向流动,从而减小了可能产生的漏电流。(The invention relates to an array substrate, a manufacturing method thereof and a display device, wherein the array substrate comprises a substrate, an active layer, a grid electrode insulating layer, a grid electrode layer, an intermediate dielectric layer, a semiconductor layer, a drain electrode and a source electrode; the active layer is arranged on the substrate, the grid insulating layer is arranged on the active layer, the grid layer is arranged on the grid insulating layer, the intermediate dielectric layer is arranged on the grid layer and the grid insulating layer, the semiconductor layer forms a PN junction with the second electrode connecting region through the first hole, the drain electrode is arranged on the semiconductor layer, and the source electrode is electrically connected with the first electrode connecting region through the second hole. According to the invention, the semiconductor layer and the second electrode connecting region of the active layer are arranged to form a PN junction to form a diode structure, so that the current of the array substrate can only flow in one direction, and the possible leakage current is reduced.)

1. An array substrate, comprising:

a substrate;

an active layer disposed on the substrate, the active layer having a first electrode connection region and a second electrode connection region;

a gate insulating layer disposed on the active layer;

a gate electrode layer disposed on the gate insulating layer;

an intermediate dielectric layer disposed on the gate electrode layer and the gate insulating layer, the intermediate dielectric layer having a first hole penetrating through the intermediate dielectric layer and the gate insulating layer to the second electrode connection region, the intermediate dielectric layer having a second hole penetrating through the intermediate dielectric layer and the gate insulating layer to the first electrode connection region;

the semiconductor layer is positioned in the first hole and forms a PN junction with the second electrode connecting region;

a drain electrode disposed on the semiconductor layer; and

and the source electrode is electrically connected with the first electrode connecting area through the second hole.

2. The array substrate of claim 1, wherein the intermediate dielectric layer comprises a first intermediate dielectric layer disposed on the gate layer and the gate insulating layer and a second intermediate dielectric layer disposed on the first intermediate dielectric layer, wherein a first capacitive electrode disposed between the gate insulating layer and the first intermediate dielectric layer and a second capacitive electrode disposed between the first intermediate dielectric layer and the second intermediate dielectric layer are deposited on the array substrate, and wherein an orthographic projection of the first capacitive electrode on the substrate at least partially overlaps an orthographic projection of the second capacitive electrode on the substrate.

3. The array substrate of claim 1, wherein the second electrode connection region is made of an N-type semiconductor, and the semiconductor layer is made of a P-type semiconductor; alternatively, the first and second electrodes may be,

the second electrode connecting region is made of a P-type semiconductor, and the semiconductor layer is made of an N-type semiconductor.

4. The array substrate according to claim 1, wherein the intermediate dielectric layer is provided with a third hole penetrating through the intermediate dielectric layer and the gate insulating layer up to the second electrode connection region and a fourth hole penetrating through the intermediate dielectric layer to the gate layer, the drain electrode comprises a first drain electrode and a second drain electrode, the first drain electrode is electrically connected to the second electrode connection region through the third hole, the second drain electrode is provided on the semiconductor layer, and the second drain electrode is further electrically connected to the gate layer through the fourth hole.

5. The array substrate of claim 4, wherein the second electrode connection region is made of an N-type semiconductor, and the semiconductor layer is made of a P-type semiconductor; alternatively, the first and second electrodes may be,

the second electrode connecting region is made of a P-type semiconductor, and the semiconductor layer is made of an N-type semiconductor.

6. The array substrate of any one of claims 1 to 5, further comprising a passivation layer disposed on the drain electrode, the source electrode, and the intermediate dielectric layer.

7. The array substrate of claim 6, further comprising a planarization layer disposed on the passivation layer.

8. The manufacturing method of the array substrate is characterized by comprising the following steps:

manufacturing an active layer on a substrate;

manufacturing a grid electrode insulating layer on the active layer;

manufacturing a grid electrode layer on the grid electrode insulating layer;

manufacturing an intermediate dielectric layer on the grid electrode layer and the grid electrode insulating layer;

making a first hole penetrating through the intermediate dielectric layer and the gate insulating layer to a second electrode connection region of the active layer;

manufacturing a semiconductor layer in the first hole and on the second electrode connecting region, so that the semiconductor layer and the second electrode connecting region form a PN junction;

making a second hole penetrating through the intermediate dielectric layer and the gate insulating layer to the first electrode connection region of the active layer;

manufacturing a drain electrode on the semiconductor layer;

and manufacturing a source electrode which is electrically connected with the first electrode connecting area through the second hole.

9. The method of claim 8, wherein the step of forming an interlayer dielectric layer on the gate layer and the gate insulating layer comprises:

and manufacturing a first capacitor electrode on the gate insulating layer, manufacturing a first intermediate dielectric layer on the gate layer, the gate insulating layer and the first capacitor electrode, manufacturing a second capacitor electrode on the first intermediate dielectric layer, enabling the orthographic projection of the first capacitor electrode on the substrate to at least partially overlap with the orthographic projection of the second capacitor electrode on the substrate, and manufacturing a second intermediate dielectric layer on the first intermediate dielectric layer and the second capacitor electrode.

10. The method for manufacturing the array substrate according to claim 8 or 9, further comprising the steps of:

forming a third hole through the intermediate dielectric layer and the gate insulating layer to the second electrode connecting region and a fourth hole through the intermediate dielectric layer to the gate layer;

and manufacturing a drain electrode, wherein the drain electrode comprises a first drain electrode and a second drain electrode, the first drain electrode is electrically connected with the second electrode connecting area through the third hole, the second drain electrode is electrically connected with the semiconductor layer, and the second drain electrode is also electrically connected with the gate layer through the fourth hole.

11. A display device, comprising the array substrate according to any one of claims 1 to 7, and a light-emitting functional layer disposed on the array substrate, wherein the light-emitting functional layer is driven by the array substrate to emit light.

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display device.

Background

In the current flat panel display, an array substrate is widely used as a basis for active driving display to achieve high resolution, so as to obtain high-speed image conversion and higher resolution display effect. The array substrate is used as an important component of active driving, and currently, mainstream driving devices are amorphous silicon, polycrystalline silicon and oxide array substrates. Among them, the low temperature polysilicon technology is currently recognized as the most suitable array substrate manufacturing technology for high-definition display of mobile phone flat panel terminals. The low-temperature polycrystalline silicon array substrate has the advantages of high mobility, low starting voltage, high reliability, stability and the like, and compared with an amorphous silicon array substrate, the leakage current (Ioff) of the polycrystalline silicon array substrate is smaller. However, compared with an oxide array substrate, the leakage current of the low-temperature polysilicon array substrate is higher by 1-2 orders of magnitude, and although the leakage current of the low-temperature polysilicon array substrate at present can basically meet the requirements, the leakage current of the low-temperature polysilicon array substrate actually increases the power consumption of a display and reduces a process window in the manufacturing process. Therefore, there is still a need to reduce the leakage current of the low temperature polysilicon array substrate.

Disclosure of Invention

Accordingly, there is a need for an array substrate, a method of fabricating the same, and a display device capable of reducing leakage current.

An array substrate, comprising:

a substrate;

an active layer disposed on the substrate, the active layer having a first electrode connection region and a second electrode connection region;

a gate insulating layer disposed on the active layer;

a gate electrode layer disposed on the gate insulating layer;

an intermediate dielectric layer disposed on the gate electrode layer and the gate insulating layer, the intermediate dielectric layer having a first hole penetrating through the intermediate dielectric layer and the gate insulating layer to the second electrode connection region, the intermediate dielectric layer having a second hole penetrating through the intermediate dielectric layer and the gate insulating layer to the first electrode connection region;

the semiconductor layer is positioned in the first hole and forms a PN junction with the second electrode connecting region;

a drain electrode disposed on the semiconductor layer; and

and the source electrode is electrically connected with the first electrode connecting area through the second hole.

In one embodiment, the intermediate dielectric layer includes a first intermediate dielectric layer disposed on the gate electrode layer and the gate insulating layer and a second intermediate dielectric layer disposed on the first intermediate dielectric layer, the array substrate has a first capacitor electrode and a second capacitor electrode deposited thereon, the first capacitor electrode is disposed between the gate insulating layer and the first intermediate dielectric layer, the second capacitor electrode is disposed between the first intermediate dielectric layer and the second intermediate dielectric layer, and an orthographic projection of the first capacitor electrode on the substrate at least partially overlaps an orthographic projection of the second capacitor electrode on the substrate.

In one embodiment, the second electrode connecting region is made of an N-type semiconductor, and the semiconductor layer is made of a P-type semiconductor.

In one embodiment, the second electrode connecting region is made of a P-type semiconductor, and the semiconductor layer is made of an N-type semiconductor.

In one embodiment, the intermediate dielectric layer is provided with a third hole penetrating through the intermediate dielectric layer and the gate insulating layer to the second electrode connection region and a fourth hole penetrating through the intermediate dielectric layer to the gate layer, the drain electrode includes a first drain electrode and a second drain electrode, the first drain electrode is electrically connected to the second electrode connection region through the third hole, the second drain electrode is disposed on the semiconductor layer, and the second drain electrode is further electrically connected to the gate layer through the fourth hole.

In one embodiment, the second electrode connecting region is made of an N-type semiconductor, and the semiconductor layer is made of a P-type semiconductor.

In one embodiment, the second electrode connecting region is made of a P-type semiconductor, and the semiconductor layer is made of an N-type semiconductor.

In one embodiment, the array substrate further includes a passivation layer disposed on the drain electrode, the source electrode, and the intermediate dielectric layer.

In one embodiment, the array substrate further comprises a planarization layer disposed on the passivation layer.

A manufacturing method of an array substrate comprises the following steps:

manufacturing an active layer on a substrate;

manufacturing a grid electrode insulating layer on the active layer;

manufacturing a grid electrode layer on the grid electrode insulating layer;

manufacturing an intermediate dielectric layer on the grid electrode layer and the grid electrode insulating layer;

making a first hole penetrating through the intermediate dielectric layer and the gate insulating layer to a second electrode connection region of the active layer;

manufacturing a semiconductor layer in the first hole and on the second electrode connecting region, so that the semiconductor layer and the second electrode connecting region form a PN junction;

making a second hole penetrating through the intermediate dielectric layer and the gate insulating layer to the first electrode connection region of the active layer;

manufacturing a drain electrode on the semiconductor layer;

and manufacturing a source electrode which is electrically connected with the first electrode connecting area through the second hole.

In one embodiment, the step of forming an intermediate dielectric layer on the gate electrode layer and the gate insulating layer comprises:

and manufacturing a first capacitor electrode on the gate insulating layer, manufacturing a first intermediate dielectric layer on the gate layer, the gate insulating layer and the first capacitor electrode, manufacturing a second capacitor electrode on the first intermediate dielectric layer, enabling the orthographic projection of the first capacitor electrode on the substrate to at least partially overlap with the orthographic projection of the second capacitor electrode on the substrate, and manufacturing a second intermediate dielectric layer on the first intermediate dielectric layer and the second capacitor electrode.

In one embodiment, the method further comprises the following steps:

forming a third hole through the intermediate dielectric layer and the gate insulating layer to the second electrode connecting region and a fourth hole through the intermediate dielectric layer to the gate layer;

and manufacturing a drain electrode, wherein the drain electrode comprises a first drain electrode and a second drain electrode, the first drain electrode is electrically connected with the second electrode connecting area through the third hole, the second drain electrode is electrically connected with the semiconductor layer, and the second drain electrode is also electrically connected with the gate layer through the fourth hole.

A display device includes the array substrate of any of the above embodiments and a light-emitting functional layer disposed on the array substrate, the light-emitting functional layer being driven by the array substrate to emit light.

Compared with the prior art, the invention has the following beneficial effects:

according to the array substrate, the manufacturing method of the array substrate and the display device, the PN junction is formed by arranging the semiconductor layer and the second electrode connecting area of the active layer, the diode structure is formed, the current of the array substrate can only flow in one direction, and therefore the leakage current which is possibly generated is reduced.

Drawings

Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment;

fig. 2 is a schematic structural diagram of an array substrate according to another embodiment;

FIG. 3 is a schematic view of a manufacturing process of the array substrate shown in FIG. 1, wherein a-i are intermediate products obtained in each manufacturing step;

FIG. 4 is a driving circuit diagram including the array substrate shown in FIG. 1;

FIG. 5 is a diagram of another driving circuit including the array substrate shown in FIG. 1;

fig. 6 is a driving circuit diagram including the array substrate shown in fig. 2.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1, an array substrate 100 according to an embodiment of the present invention includes a substrate 110, an active layer, a gate insulating layer 130, a gate layer 140, an interlayer dielectric layer, a semiconductor layer 180, a drain electrode 190b, and a source electrode 190 a.

An active layer is disposed on the substrate 110, the active layer having a first electrode connection region 120a and a second electrode connection region 120 c. The gate insulating layer 130 is disposed on the active layer. The gate layer 140 is disposed on the gate insulating layer 130, and the gate layer 140 and the active layer are insulated and separated by the gate insulating layer 130. The interlayer dielectric layer is disposed on the gate electrode layer 140 and the gate insulating layer 130. The intermediate dielectric layer has a first hole through the intermediate dielectric layer and the gate insulating layer 130 to the second electrode connecting region 120c, and the intermediate dielectric layer has a second hole through the intermediate dielectric layer and the gate insulating layer 130 to the first electrode connecting region 120 a. The semiconductor layer 180 is disposed in the first hole and on the second electrode connection region 120 c. The drain electrode 190b is disposed on the semiconductor layer 180, and the source electrode 190a is electrically connected to the first electrode connection region 120a through the second hole.

Wherein the semiconductor layer 180 is of a semiconductor type opposite to that of the second electrode connecting region 120c, that is, if the second electrode connecting region 120c of the active layer is a P-type semiconductor, the semiconductor layer 180 is an N-type semiconductor; if the second electrode connecting region 120c of the active layer is an N-type semiconductor, the semiconductor layer 180 is a P-type semiconductor. With this arrangement, the second electrode connection region 120c of the active layer forms a PN junction, i.e., a diode structure, with the semiconductor layer 180.

As shown in fig. 1, with the above arrangement, the diode structure is connected in series to one side of the drain electrode 190b, so that the current of the array substrate 100 can flow only in one direction, thereby reducing the leakage current that may be generated.

It is understood that the above-described effects can also be obtained by disposing the semiconductor layer 180 on the side of the first electrode connecting region 120a of the active layer to form a PN junction with the first electrode connecting region 120a, disposing the source electrode 190a on the semiconductor layer 180, and electrically connecting the drain electrode 190b with the second electrode connecting region 120 c. It should be noted that, in the present invention, the first electrode connection region and the second electrode connection region, and the source electrode and the drain electrode are relative concepts, and both of the above cases are within the scope of the present invention.

The substrate 110 is used to support other layers of the array substrate 100, and may also be used to support O L ED, Q L ED, liquid crystal devices, and the like, the substrate 110 may be a rigid substrate 110 or a flexible substrate 110, the rigid substrate 110 may be a ceramic material, various glass materials, and the like, and the flexible substrate 110 may be PI (polyimide) and its derivatives, PEN (polyethylene naphthalate), PEP (phosphoenolpyruvate), diphenylene ether resin, and the like.

The active layer is made of semiconductor material, and generally, if a voltage is applied across the first electrode connecting region 120a and the second electrode connecting region 120c of the semiconductor, no current flows inside the semiconductor (but a very small leakage current flows; when the gate voltage drops with respect to the first electrode connecting region 120a and the second electrode connecting region 120c and reaches a threshold voltage (Vth), the resistivity of the inside of the semiconductor is reduced by the influence of the gate, and thus 10 s may occur⁴The change of the current amount more than twice, i.e., the conduction of the source/drain, plays a role of controlling whether the first electrode connection region 120a and the second electrode connection region 120c are conducted or not through the gateCan be used.

The material of the active layer may be amorphous silicon, polycrystalline silicon, an oxide semiconductor, an organic semiconductor, a molybdenum sulfide semiconductor, or the like. Preferably, the active layer is made of polysilicon, has high mobility and better controllability of semiconductor characteristics than amorphous silicon and oxide semiconductor materials, and can be controlled to be a P-type semiconductor or an N-type semiconductor by methods such as ion doping and metal induced doping.

As shown in fig. 1, the active layer includes a channel portion 120b and a first electrode connection region 120a and a second electrode connection region 120c connected to the channel portion 120b, respectively, wherein the first electrode connection region 120a and the second electrode connection region 120c are made of a semiconductor material and the channel portion 120b maintains the characteristics of the semiconductor and is the most important component of the array substrate 100.

The gate insulating layer 130 is an important structure of the organic array substrate 100. On one hand, the gate insulating layer 130 functions to insulate the active layer and the gate electrode layer 140 so that the active layer and the gate electrode layer 140 can interact only by electric field induction; on the other hand, the thickness, film properties, and the like of the gate insulating layer 130 greatly affect the electrical properties of the array substrate 100, such as mobility, leakage current, threshold voltage, and the like of the array substrate 100. The material of the gate insulating layer 130 may be an organic insulating material or an inorganic insulating material, wherein the inorganic insulating material may be silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, aluminum oxide, or the like.

The gate layer 140 is a conductive electrode. When a threshold voltage (Vth) is applied to the gate layer 140, the active layer changes its conductive properties due to the voltage, which can function to control the current in the active layer. The material of the gate layer 140 may be inorganic, organic, or nanowire, wherein the inorganic may be conductive metal such as aluminum, molybdenum, titanium, copper, silver, or gold, or alloy, combination stack thereof.

The intermediate dielectric layer is an insulating material, and may be an organic insulating material or an inorganic insulating material, where the inorganic insulating material may be silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, aluminum oxide, or the like.

The semiconductor layer 180 may be amorphous silicon, polycrystalline silicon, an oxide semiconductor, an organic semiconductor, a molybdenum sulfide semiconductor, or the like. If the second electrode connection region 120c of the active layer is a P-type semiconductor, the semiconductor layer 180 is an N-type semiconductor; if the second electrode connecting region 120c of the active layer is an N-type semiconductor, the semiconductor layer 180 is a P-type semiconductor. With this arrangement, the second electrode connection region 120c of the active layer forms a PN junction, i.e., a diode structure, with the semiconductor layer 180. Depending on the structure and the conductive properties of the diode, macroscopic currents can only flow from the P-type semiconductor side to the N-type semiconductor side, i.e. the unidirectional conductivity of the diode. The direction of the diode in the thin film circuit may be determined according to the conductive characteristics of the second electrode connection region 120c of the active layer and the semiconductor layer 180. Also, by controlling the doping concentration of the second electrode connection region 120c of the active layer and the doping concentration of the semiconductor layer 180, it is possible to control characteristic variations of the diode, such as a turn-on voltage, a maximum forward average current, and the like of the diode.

The drain electrode 190b and the source electrode 190a are conductive electrodes, and generally take roles of inputting a data voltage, a peripheral current path of the display screen, and the like. The drain electrode 190b and the source electrode 190a are generally thin conductive layers with low resistance and good conductive properties, and may be conductive metals such as aluminum, molybdenum, titanium, copper, silver, gold, and alloys and composite laminates thereof. As shown in fig. 1, the drain electrode 190b is electrically connected to the second electrode connection region 120c of the active layer, the source electrode 190a is electrically connected to the first electrode connection region 120a of the active layer, and after a voltage is applied between the drain electrode 190 b/the second electrode connection region 120c and the source electrode 190 a/the first electrode connection region 120a to form a loop, the voltage of the gate is controlled to control whether a current flows between the drain electrode 190 b/the second electrode connection region 120c and the source electrode 190 a/the first electrode connection region 120a, so as to achieve the switching function.

As shown in fig. 1, in one example, the intermediate dielectric layers include a first intermediate dielectric layer 150a and a second intermediate dielectric layer 150 b. The first interlayer dielectric layer 150a is disposed on the gate electrode layer 140 and the gate insulating layer 130. The second intermediate dielectric layer 150b is disposed on the first intermediate dielectric layer 150 a. In this example, the array substrate 100 has a first capacitive electrode 160 and a second capacitive electrode 170 deposited thereon. The first capacitor electrode 160 is disposed between the gate insulating layer 130 and the first intermediate dielectric layer 150 a. The second capacitor electrode 170 is disposed between the first and second intermediate dielectric layers 150a and 150 b. And, the orthographic projection of the first capacitive electrode 160 on the substrate 110 at least partially overlaps the orthographic projection of the second capacitive electrode 170 on the substrate 110. In the example shown in fig. 1, the first capacitance electrode 160 is disposed on a region of the gate insulating layer 130 extending outside the active layer.

The first capacitor electrode 160, the second capacitor electrode 170 and the first intermediate dielectric layer 150a together form a capacitor structure in the thin film circuit, and the size of the capacitor can be designed by controlling the thickness of the first intermediate dielectric layer 150a and the overlapping area of the first capacitor electrode 160 and the second capacitor electrode 170.

The first capacitor electrode 160 and the second capacitor electrode 170 are both made of conductive materials, such as conductive metals, such as aluminum, molybdenum, titanium, copper, silver, or gold, or alloys and composite laminates thereof.

In this example, one function of the first interlayer dielectric layer 150a is to isolate the gate layer 140 from electrical connection with other conductive electrodes on its surface; it also functions as a dielectric material part of the capacitor in the driving circuit, and is an indispensable part for forming the capacitor. In one example, the material of the first intermediate dielectric layer 150a is silicon nitride, which is easy to prepare and has a high dielectric constant.

The second interlayer dielectric layer 150b has a structure and a function similar to those of the first interlayer dielectric layer 150a, and mainly plays a role in isolating the gate layer 140 and the second capacitor electrode 170 from the other conductive electrodes thereon and reducing parasitic capacitance. In one example, the second intermediate dielectric layer 150b is a stacked film of silicon nitride and silicon oxide, and since the film formation rate of silicon oxide can be high, the stacked structure can increase the breakdown voltage between the upper and lower electrodes, thereby preventing the breakdown phenomenon when the voltage is applied too high.

As shown in fig. 2, in one example, the intermediate dielectric layer is provided with a third hole penetrating through the intermediate dielectric layer and the gate insulating layer 130 to the second electrode connecting region 120c and a fourth hole penetrating through the intermediate dielectric layer to the gate layer 140, the drain electrode includes a first drain electrode 190b 'and a second drain electrode 190b ", the first drain electrode 190 b' is electrically connected to the second electrode connecting region 120c through the third hole, the second drain electrode 190 b" is disposed on the semiconductor layer 180, and the second drain electrode 190b "is also electrically connected to the gate layer 140 through the fourth hole. In the example shown in fig. 2, the third via hole penetrates the second intermediate dielectric layer 150b, the first intermediate dielectric layer 150a, and the gate insulating layer 130 up to the second electrode connection region 120c, and the first drain electrode 190 b' extends from the second electrode connection region 120c toward the second intermediate dielectric layer 150 b; the fourth hole penetrates the second intermediate dielectric layer 150b, the first intermediate dielectric layer 150a and the gate layer 140, and the second drain electrode 190b ″ extends from the gate layer 140 toward the second intermediate dielectric layer 150b and is connected to the semiconductor layer 180. In this example, the gate layer 140, the second drain electrode 190b ", the semiconductor layer 180, and the second electrode connection region 120c constitute a structure in which a diode is connected in parallel to the gate and the source and drain electrodes.

In one example, the array substrate 100 further includes a passivation layer (not shown) disposed on the drain electrode 190b, the source electrode 190a, and the second intermediate dielectric layer 150 b. The passivation layer mainly plays a role in protecting the electrode material below the passivation layer from external pollution. The passivation layer is an insulating material such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, aluminum oxide, and the like.

In one example, the array substrate 100 further includes a planarization layer 1100, and the planarization layer 1100 is disposed on the passivation layer. The flat layer 1100 mainly plays a role in protection, and meanwhile, the material characteristics of the flat layer enable the flat layer to be better spread on the uneven surface to form a relatively flat membrane surface, so that the material on the flat layer can be formed into a membrane on the relatively flat surface, the stability of the material on the flat layer is ensured, and the risk of short circuit and open circuit is reduced. The material of the planarization layer 1100 may be an organic photoresist such as Polyimide (PI), and may be a film layer patterned by coating, exposure, and development.

In one example, the array substrate 100 further includes an anode layer 1110, the anode layer 1110 is disposed on the flat layer 1100 and electrically connected to the drain electrode 190b, in the above parallel connection scheme, the anode layer 1110 is electrically connected to the first drain electrode 190 b', the anode layer 1110 is a conductive electrode, in the liquid crystal display, the anode layer 1110 is a portion of an upper electrode and a lower electrode for driving liquid crystal to move, in the O L ED display, the anode layer 1110 is a portion of an O L ED light emitting device structure and plays a role of injecting holes or electrons, the material of the anode layer 1110 may be a metal oxide conductive material such as ITO (indium tin oxide), IZO (indium zinc oxide), organic conductive material such as PEDOT (3, 4-ethylenedioxythiophene monomer), conductive metal such as aluminum, titanium, copper, silver, gold, etc., and alloys thereof, a composite laminate, and the anode layer 1110 is an ITO/Ag/ITO laminate.

In one example, the array substrate 100 further includes a pixel defining layer 1120, the pixel defining layer 1120 is disposed on the planarization layer 1100 and the anode layer 1110. the pixel defining layer 1120 is an insulating film layer formed after patterning to fill some regions, and serves to form a pixel structure by filling the regions with a material such as O L ED, and at the same time, serves to protect the material and reduce the risk of short/open circuit of the O L ED device.

In one example, the array substrate 100 further includes a support post layer 1130, the support post layer 1130 is disposed on the pixel defining layer 1120. the support post layer 1130 is patterned to form a plurality of higher post-like insulating layers, which are distributed in a large number in the display, and serve to support the pressure generated when two glass substrates are assembled together during the packaging process of the liquid crystal and O L ED, thereby protecting the functional layers/devices underneath.

Further, the present invention also provides a display device, including the array substrate 100 of any of the above examples and a light emitting function layer disposed on the array substrate 100, the light emitting function layer being driven by the array substrate 100 to emit light.

In the array substrate 100 and the display device, the semiconductor layer 180 and the second electrode connecting region 120c of the active layer are arranged to form a PN junction to form a diode structure, so that the current of the array substrate 100 can flow only in one direction, thereby reducing the leakage current which may be generated.

The array substrate 100 and the display device can be applied to the fields of flat panel display, television display, electronic paper, logic and memory circuit, flexible display, and the like, such as mobile phones, televisions, tablet computers, displays, VR/AR devices, computers, vehicle-mounted displays, or any other products or components with display functions.

Further, as shown in fig. 3, the present invention further provides a method for manufacturing an array substrate 100, including the following steps:

fabricating an active layer 120 on the substrate 110;

forming a gate insulating layer 130 on the active layer 120;

forming a gate electrode layer 140 on the gate insulating layer 130;

forming an interlayer dielectric layer on the gate electrode layer 140 and the gate insulating layer 130;

forming a first hole penetrating the interlayer dielectric layer and the gate insulating layer 130 to the second electrode connecting region 120c of the active layer;

manufacturing a semiconductor layer 180 in the first hole and on the second electrode connection region 120c, so that the semiconductor layer 180 and the second electrode connection region 120c form a PN junction;

forming a second hole penetrating the interlayer dielectric layer and the gate insulating layer 130 to the first electrode connecting region 120c of the active layer;

fabricating a drain electrode 190b on the semiconductor layer 180;

a source electrode 190a electrically connected to the first electrode connection region 120a through the second hole is fabricated.

In one example, the step of forming the interlayer dielectric layer on the gate electrode layer 140 and the gate insulating layer 130 includes:

a first capacitor electrode 160 is formed on the gate insulating layer 130. A first interlayer dielectric layer 150a is formed on the gate electrode layer 140, the gate insulating layer 130 and the first capacitor electrode 160. The second capacitive electrode 170 is formed on the first intermediate dielectric layer 150a such that an orthographic projection of the first capacitive electrode 160 on the substrate 110 at least partially overlaps an orthographic projection of the second capacitive electrode 170 on the substrate 110. A second intermediate dielectric layer 150b is formed over the first intermediate dielectric layer 150a and the second capacitor electrode 170.

In one example, the method for manufacturing the array substrate 100 further includes the following steps:

drain electrodes are formed, wherein the drain electrodes include a first drain electrode 190b 'and a second drain electrode 190b ", the first drain electrode 190 b' is electrically connected to the second electrode connection region 120c through the third hole, the second drain electrode 190 b" is electrically connected to the semiconductor layer 180, and the second drain electrode 190b "is further electrically connected to the gate layer 140 through the fourth hole. Specifically, as shown in fig. 3, the manufacturing method includes the following steps:

s1: a patterned active layer 120 is fabricated on the substrate 110.

As shown in a of fig. 3, a patterned active layer 120 is formed on a substrate 110. In one example, a low temperature polysilicon process is used, comprising: the method comprises the steps of carrying out plasma chemical vapor deposition on an amorphous silicon film layer, forming a polycrystalline silicon film layer after excimer laser annealing, patterning by utilizing a photoetching process, and carrying out semiconductor characteristic adjustment on the polycrystalline silicon film layer by utilizing ion implantation doped B/P ions.

S2: a gate insulating layer 130 is formed on the active layer 120, and a patterned gate layer 140 is formed on the gate insulating layer 130.

As shown in b of fig. 3, the gate insulating layer 130 and the gate electrode layer 140 may be coated by chemical vapor deposition, magnetron sputtering, evaporation, or the like, and the gate electrode layer may be patterned by photolithography. In one embodiment, the gate insulating layer 130 is formed by a slow deposition process using plasma chemical vapor deposition, and has a thickness of 110 nm.

S3: the active layer 120 is doped with B (boron) ions at a high concentration.

As shown in c in fig. 3, the doping method may be ion implantation, that is, ions generated by ionizing gas are accelerated and then scanned across the entire surface of the substrate, and the ionized ions are driven into the thin film. If the B ions are doped into a semiconductor film, such as a polysilicon film, and the concentration is high (e.g., 10)¹⁰～10¹⁶Per cm2) in the region, the polycrystalline silicon film layer is made conductive, the resistivity is obviously reduced, and the conductivity can be improvedOhmic contact is formed when the integrated semiconductor is contacted with metal, so that the contact resistance between the semiconductor and the metal is reduced, the energy consumption is reduced, and the on-state current of the array substrate 100 is improved. Meanwhile, the doping of the B ions causes the semiconductor conduction characteristic of the region to be represented as a P-type semiconductor, and the conduction is mainly carried out by holes.

Since the implantation of the ions is performed while the metal film layer is encountered, the implantation cannot be continued, so that the gate layer 140 serves as a mask, the ions cannot be implanted into the active layer covered by the gate layer 140, i.e., the channel portion 120b of the active layer is formed, and the ion-implanted region forms the first electrode connection region (source region) 120a and the second electrode connection region (drain region) 120c of the active layer.

S4: a patterned first capacitor electrode 160 is formed on the gate insulating layer 130, a first intermediate dielectric layer 150a is formed on the gate insulating layer 140, the gate insulating layer 130 and the first capacitor electrode 160, and a second capacitor electrode 170 is formed on the first intermediate dielectric layer 150 a.

As shown in d of fig. 3, the first intermediate dielectric layer 150a, the first capacitor electrode 160 and the second capacitor electrode 170 may be coated by chemical vapor deposition, magnetron sputtering, evaporation, etc., and the first capacitor electrode 160 and the second capacitor electrode 170 may be patterned by photolithography. Wherein an orthographic projection of the first capacitive electrode 160 on the substrate 110 at least partially overlaps an orthographic projection of the second capacitive electrode 170 on the substrate 110.

S5: a second interlayer dielectric layer 150b is formed on the second capacitor electrode 170 and a first hole is formed through the first interlayer dielectric layer 150a, the second interlayer dielectric layer 150b to the second electrode connection region (drain region) 120c of the active layer.

As shown in e of fig. 3, the second intermediate dielectric layer 150b may be coated by chemical vapor deposition, magnetron sputtering, evaporation, etc. to form a first hole penetrating through the first intermediate dielectric layer 150a, the second intermediate dielectric layer 150b and reaching the second electrode connection region (drain region) 120c of the active layer.

S6: a semiconductor layer 180 is formed in the first hole and on the second electrode contact region (drain region) 120c, such that the semiconductor layer 180 and the second electrode contact region (drain region) 120c form a PN junction.

As shown in f in fig. 3, the coating of the semiconductor can be completed by chemical vapor deposition, magnetron sputtering, evaporation, and the like. In one specific example, semiconductor layer 180 is an N-type semiconductor, such as a phosphorus doped microcrystalline silicon film. Intermittent coating process by chemical vapor deposition using SiH₄、PH₃And H₂As a main film forming gas source, in the whole film coating process, 30 percent of the time is in normal film coating, and 70 percent of the time is in H₂Plasma surface treatment by continuously performing coating and H₂Plasma processing makes the coating film denser, and generally can form a microcrystalline structure, and the microcrystalline structure has better stability and can better reflect the conductive characteristic of a semiconductor, so that a more reliable diode structure can be formed.

S7: the semiconductor layer 180 is etched.

As shown in g of fig. 3, the etching area can be controlled to be performed on the surface of the film layer by using an isotropic etching manner, including wet etching, ECP plasma etching, etc., and finally the illustrated structure is formed, and the height of the semiconductor layer 180 in the hole can be controlled by the etching time.

S8: a second hole is formed through the first and second interlayer dielectric layers 150a and 150b to the first electrode connection region (source region) 120a of the active layer.

As shown in h of fig. 3, a semiconductor lithography technique is employed, wherein the etching process uses a plasma physical etching method to form a second hole penetrating through the first intermediate dielectric layer 150a, the second intermediate dielectric layer 150b and reaching the first electrode connection region (source region) 120a of the active layer.

S9: a drain electrode 190b is formed on the semiconductor layer 180, and a source electrode 190a electrically connected to the first electrode connection region (source region) 120a through the second hole is formed.

As shown in i in fig. 3, the source electrode 190a and the drain electrode 190b are coated by chemical vapor deposition, magnetron sputtering, evaporation, and the like, and the source electrode 190a and the drain electrode 190b are patterned by photolithography. The source electrode 190a forms an ohmic connection with the first electrode connection region (source region) 120a, the drain electrode 190b forms an ohmic connection with the second electrode connection region (drain region) 120c, and there is no electrical connection between the source electrode 190a and the drain electrode 190 b.

S10: a passivation layer is formed on the drain electrode 190b, the source electrode 190a, and the intermediate dielectric layer.

And completing the film coating of the passivation layer by using methods such as chemical vapor deposition, magnetron sputtering, evaporation and the like, and patterning the passivation layer by using a photoetching technology.

S11: a planarization layer 1100 is fabricated on the passivation layer.

The planarization layer 1100 is formed by a photoresist process in a photolithography process, and is patterned by exposure and development.

S12: an anode layer 1110 is formed on the planarization layer 1100 and electrically connected to the drain electrode 190 b.

The anode layer 1110 is coated by chemical vapor deposition, magnetron sputtering, or evaporation, and the anode layer 1110 is patterned by photolithography.

S13: a pixel definition layer 1120 is fabricated on the planarization layer 1100 and the anode layer 1110.

The pixel defining layer 1120 is formed by a photoresist process in a photolithography process, and is patterned by exposure and development.

S14: a support post layer 1130 is fabricated on the pixel definition layer 1120.

The support post layer 1130 is formed by a photoresist coating process in a photolithography process, and is patterned by exposure and development to obtain the film array substrate and the associated auxiliary structures shown in fig. 1, not shown in detail, in particular, the processes of S10-S14.

The fabrication of the light emitting device on the array substrate 100 can be completed subsequently.

In the array substrate 100, as shown in fig. 4, the second electrode connection region (drain region) 120C corresponds to the drain of the transistor T1 and is also the P-type semiconductor portion of the diode D1, the semiconductor layer 180 corresponds to the N-type semiconductor portion of the diode D1, 190b can be electrically configured such that one electrode of the capacitor C1 is electrically connected (the capacitor C1 corresponds to the capacitor formed by the first capacitor electrode 160, the second capacitor electrode 170 and the dielectric therein in fig. 1, which can serve as a storage capacitor on the array substrate), wherein T2 serves as a transistor for driving the O L ED in the fig. 1 to emit light, and T2 and O L in fig. 4 are not shown in the array substrate of the present embodiment, which can be applied to a driving circuit of an AMO L ED display, and by such a design, current can only flow from the data tube 1 and the diode D56 to the C1 and then flow through the capacitor C1, even if the leakage current of the AMO circuit is reduced to a large extent that leakage current can actually flow through the AMO 1 or the AMO 1.

In another example, the first electrode connection region (source region) 120a and the second electrode connection region (drain region) 120C are both N-type semiconductors, and correspondingly, the semiconductor layer 180 is a P-type semiconductor connected to the first electrode connection region (source region) 120a (the design of the array substrate with this structure is specifically illustrated), and the application circuit thereof is as shown in fig. 5, where the first electrode connection region (source region) 120a corresponds to the N-type semiconductor portion of the diode D1, the semiconductor layer 180 corresponds to the P-type semiconductor portion of the diode D1, the storage capacitor in fig. 5 is C1 in fig. 4, the liquid crystal capacitor is not illustrated, and 190b (it should be noted that the 190b electrode is electrically connected to the second electrode connection region (drain region) 120C) can be electrically connected to one electrode of the capacitor C1, and by such design, the data current can only be charged to the capacitor C1 after passing through the T1 tube and the diode D1, the reverse flow is prevented, and even if the D1 diode actually has a leakage current, the leakage current of the whole circuit or device can be reduced to a great extent. The circuit can be applied to a simple driving circuit of a liquid crystal display, and can reduce electric quantity leakage of a storage capacitor in the driving circuit.

In another exemplary method for manufacturing an array substrate, step S9 is as follows:

forming third holes through the second interlayer dielectric layer 150b, the first interlayer dielectric layer 150a, and the gate insulating layer 130 to the second electrode connecting region 120c, and forming first drain electrodes 190 b' in the third holes; a fourth hole is formed through the second intermediate dielectric layer 150b, the first intermediate dielectric layer 150a and the gate layer 140, and a second drain electrode 190b ″ is formed in the fourth hole and connected to the semiconductor layer 180.

Step S12 is as follows:

an anode layer 1110 is formed on the planarization layer 1100 and electrically connected to the first drain electrode 190 b'.

The other steps are the same as the above steps.

As shown in fig. 6 and fig. 2, the second electrode connecting region (drain region) 120C is equivalent to the drain of the transistor T1 and is also the P-type semiconductor portion of the diode D1, the semiconductor layer 180 is the N-type semiconductor portion of the diode D1, 190 b' may be electrically connected to one electrode of the capacitor C1 (the C1 is equivalent to the capacitor formed by the first capacitor electrode 160, the second capacitor electrode 170 and the dielectric therein in fig. 1, the capacitor may serve as a storage capacitor on the array substrate), wherein T2 serves as a transistor for driving the O L ED to emit light in the pixel, 190b "is connected to the N-type semiconductor portion of the diode D1 and the gate electrode of the T1, the T2 and the O L ED in fig. 6 are not shown in the array substrate according to the embodiment of the present invention, the diode structure in the array substrate 100 is a diode connected in parallel to the gate electrode and the source-drain electrode, and the diode structure in the circuit is applicable to the driving circuit of the AMO 7 ED display panel, the diode D1 and the transistor T2 serve as a voltage-gate-on switch, thereby enabling the voltage of the voltage switch to be more uniformly applied to the whole voltage of the display panel without causing the voltage drop of the voltage drop.

By adding diodes in the thin film array driving circuit, the circuit design scheme can be enriched, more functional circuits can be obtained, and the possibility of insufficient compensation process of the circuit is improved.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.