阅读说明：本技术 包括不同类型的薄膜晶体管的显示装置及其制造方法 (Display device including different types of thin film transistors and method of manufacturing the same ) 是由 张宰满 朴世熙 金大焕 尹弼相 于 2019-12-17 设计创作，主要内容包括：包括不同类型的薄膜晶体管的显示装置及其制造方法。一种显示装置包括基板、基板上的像素驱动电路和与像素驱动电路连接的显示单元,其中,像素驱动电路包括第一薄膜晶体管和第二薄膜晶体管,其中,第一薄膜晶体管包括：基板上的第一栅极；与第一栅极间隔开并与第一栅极的至少一部分交叠的第一有源层；与第一有源层连接的第一源极；以及与第一源极间隔开并与第一有源层连接的第一漏极,并且第二薄膜晶体管包括：基板上的第二有源层；以及与第二有源层间隔开并与第二有源层的至少一部分部分交叠的第二栅极,其中,第一栅极设置在基板和第一有源层之间,第二有源层设置在基板和第二栅极之间,并且第一栅极和第二栅极相对于第二有源层设置在相反的侧。(A display device including different types of thin film transistors and a method of manufacturing the same. A display device includes a substrate, a pixel driving circuit on the substrate, and a display unit connected to the pixel driving circuit, wherein the pixel driving circuit includes a first thin film transistor and a second thin film transistor, wherein the first thin film transistor includes: a first gate electrode on the substrate; a first active layer spaced apart from the first gate electrode and overlapping at least a portion of the first gate electrode; a first source connected to the first active layer; and a first drain electrode spaced apart from the first source electrode and connected to the first active layer, and the second thin film transistor includes: a second active layer on the substrate; and a second gate electrode spaced apart from the second active layer and partially overlapping at least a portion of the second active layer, wherein the first gate electrode is disposed between the substrate and the first active layer, the second active layer is disposed between the substrate and the second gate electrode, and the first gate electrode and the second gate electrode are disposed on opposite sides with respect to the second active layer.)

1. A display device, comprising:

a substrate;

a pixel driving circuit on the substrate; and

a display unit connected with the pixel driving circuit,

wherein the pixel driving circuit includes a first thin film transistor and a second thin film transistor,

wherein the first thin film transistor includes:

a first gate on the substrate;

a first active layer spaced apart from the first gate electrode and overlapping at least a portion of the first gate electrode;

a first source connected to the first active layer; and

a first drain electrode spaced apart from and connected to the first source electrode and

wherein the second thin film transistor includes:

a second active layer over the substrate; and

a second gate electrode spaced apart from the second active layer and partially overlapping at least a portion of the second active layer,

wherein the first gate electrode is disposed between the substrate and the first active layer, the second active layer is disposed between the substrate and the second gate electrode, and the first gate electrode and the second gate electrode are disposed on opposite sides with respect to the second active layer.

2. The display device according to claim 1, wherein the second active layer is provided on the same layer as the first source electrode and the first drain electrode.

3. The display device according to claim 1, further comprising a first interlayer insulating layer on the first active layer, wherein the first source electrode and the first drain electrode are provided on the first interlayer insulating layer and connected to the first active layer through a contact hole.

4. The display device according to claim 3, wherein each of the first source electrode and the first drain electrode has a recess in the contact hole.

5. The display device according to claim 3, wherein each of the first source electrode and the first drain electrode directly contacts the first active layer through the contact hole.

6. The display device according to claim 3, further comprising an etch stopper layer on the first active layer, wherein the etch stopper layer is provided at the same layer as the first interlayer insulating layer and is formed of the same material as the first interlayer insulating layer.

7. The display device according to claim 3, wherein the second active layer is provided on the first interlayer insulating layer.

8. The display device according to claim 1, wherein the second active layer, the first source electrode, and the first drain electrode are formed of an oxide semiconductor material.

9. The display device of claim 1, wherein at least one of the first active layer and the second active layer comprises:

a first oxide semiconductor layer; and

a second oxide semiconductor layer disposed on the first oxide semiconductor layer.

10. The display device according to claim 9, wherein the first oxide semiconductor layer comprises Ga.

11. The display device according to claim 1, further comprising a data line and a driving voltage line, wherein the data line and the driving voltage line are provided at the same layer as the first gate electrode.

12. The display device according to claim 3, further comprising:

a second interlayer insulating layer on the first source electrode and the first drain electrode; and

a planarization layer on the second interlayer insulating layer,

wherein the display unit is disposed on the planarization layer.

13. The display device according to claim 12, further comprising a storage capacitor connected to the first thin film transistor,

wherein the storage capacitor includes:

a first capacitor electrode formed integrally with the first source electrode; and

a second capacitor electrode formed integrally with the first gate electrode.

14. The display device according to claim 13, wherein the storage capacitor further comprises a third capacitor electrode spaced apart from the first capacitor electrode and provided on the second interlayer insulating layer.

15. The display device according to claim 14, wherein the third capacitor electrode overlaps the first capacitor electrode and is connected to the first gate electrode through a contact hole.

16. The display device according to claim 1, wherein the first thin film transistor serves as a driving transistor configured to drive the display unit.

17. The display device according to claim 1, wherein the second thin film transistor functions as a switching transistor.

18. A method of manufacturing a display device, the method comprising the steps of:

sequentially depositing a first conductive material layer, a first insulating material layer and a first active material layer on a substrate;

forming a first gate electrode from the first conductive material layer, a first gate insulating film from the first insulating material layer, and a first active layer from the first active material layer by a selective etching process;

forming a first interlayer insulating layer on the first active layer;

forming a second active material layer including a plurality of patterns on the first interlayer insulating layer;

forming a second gate insulating film and a second gate electrode on at least a portion of the second active material layer; and

the second active material layer in a region not overlapping the second gate electrode is made conductive to form a first source electrode and a first drain electrode spaced apart from each other and connected to the first active material layer.

19. The method of claim 18, wherein the step of rendering the second active material layer conductive is performed by using the second gate as a mask.

20. The method of claim 18, wherein the second active material is an oxide semiconductor material and the step of making the second active material layer conductive is performed by plasma treatment or hydrogen treatment.

21. The method of claim 18, further comprising the steps of: an etch barrier layer is formed between the first source electrode and the first drain electrode.

22. The method of claim 21, wherein the etch stop layer is formed of the same material as the first interlayer insulating layer.

23. The method of claim 18, wherein a portion of the first source and a portion of the first gate overlap each other in a vertical direction and form a storage capacitor.

24. The method of claim 23, further comprising the steps of:

forming a second interlayer insulating layer on the first source electrode; and

forming a third capacitor electrode overlapping at least a portion of the first source electrode on the second interlayer insulating layer.

Technical Field

The present disclosure relates to a display device, and more particularly, to a display device including different types of thin film transistors and a method of manufacturing the same. Although the present disclosure is suitable for a wide scope of applications, it is particularly suitable for ensuring a sufficient capacitor area when a plurality of thin film transistors need to be arranged in a display device, and a method of manufacturing the display device.

Background

A thin film transistor can be manufactured on a glass substrate or a plastic substrate, and thus the thin film transistor has been widely used as a switching device or a driving device in a display device such as a liquid crystal display device or an organic light emitting device.

The thin film transistor may be roughly classified into an amorphous silicon thin film transistor having an active layer of amorphous silicon, a polycrystalline silicon thin film transistor having an active layer of polycrystalline silicon, and an oxide semiconductor thin film transistor having an active layer of an oxide semiconductor, depending on the material for the active layer.

In addition, the amorphous silicon thin film transistor has disadvantages of low current driving efficiency and variation in threshold voltage due to low mobility.

A polycrystalline silicon thin film transistor (poly-Si TFT) may be obtained by depositing amorphous silicon and crystallizing the deposited amorphous silicon, the polycrystalline silicon thin film transistor having advantages of high electron mobility and good stability, achieving a thin shape and high resolution, and high power efficiency.

An oxide semiconductor thin film transistor (oxide semiconductor TFT) has high mobility and large resistance variation according to oxygen content, which is advantageous in that desired performance can be easily obtained. In addition, an active layer of oxide is formed at a relatively low temperature for a process of manufacturing an oxide semiconductor thin film transistor, so that manufacturing costs can be reduced. In addition, the oxide semiconductor is transparent due to the nature of the oxide, contributing to the realization of a transparent display device. However, the oxide semiconductor thin film transistor has relatively low stability and electron mobility compared to the polycrystalline silicon thin film transistor.

Recently, with the progress of high quality and high resolution in display apparatuses, thin film transistors are integrated in a display device at high density. As a result, a large number of thin film transistors are arranged in a limited area, and a large number of contact holes are formed, so that it is difficult to secure a sufficient capacitor area. Therefore, a method for securing a capacitor region in a display device including a large number of thin film transistors is required.

Disclosure of Invention

The present disclosure has been made in view of the above problems, and it is an object of the present disclosure to provide a display device which helps to secure a sufficient capacitor region even in a case where a plurality of thin film transistors are arranged, and a method of manufacturing the same.

Further, the present disclosure provides a display device that helps ensure a sufficient capacitor area by reducing the number of contact holes for electrical connection of thin film transistors even in a case where a plurality of thin film transistors are arranged, and a method of manufacturing the display device.

In addition, the present disclosure provides a method of manufacturing a display device that helps reduce the number of patterning processes and a display device manufactured by the method.

In accordance with one aspect of the present disclosure, the above and other aspects can be achieved by providing a display device including: a substrate; a pixel driving circuit on the substrate; and a display unit connected with the pixel driving circuit, wherein the pixel driving circuit includes a first thin film transistor and a second thin film transistor, wherein the first thin film transistor includes: a first gate electrode on the substrate, a first active layer configured to be spaced apart from the first gate electrode and to overlap at least a portion of the first gate electrode, a first source electrode connected to the first active layer; and a first drain electrode configured to be spaced apart from the first source electrode and connected to the first active layer, and wherein the second thin film transistor includes: the semiconductor device includes a substrate, a first active layer over the substrate, and a second gate electrode configured to be spaced apart from the second active layer and to partially overlap at least a portion of the second active layer, the first gate electrode being disposed between the substrate and the first active layer, and the second active layer being disposed between the substrate and the second gate electrode.

The first gate electrode and the second gate electrode are disposed at opposite layers with respect to the second active layer.

The second active layer is disposed on the same layer as the first source electrode and the first drain electrode.

The display device further includes a first interlayer insulating layer on the first active layer, wherein the first source electrode and the first drain electrode are disposed on the first interlayer insulating layer and connected to the first active layer through the contact hole.

The display device further includes an etch barrier layer on the first active layer.

The etch stopper layer is disposed on the same layer as the first interlayer insulating layer.

The etch stopper layer is formed of the same material as that of the first interlayer insulating layer.

The second active layer is disposed on the first interlayer insulating layer.

The second active layer is formed of an oxide semiconductor material, and the first source electrode and the first drain electrode are formed of the same oxide semiconductor material as the oxide semiconductor material of the second active layer.

At least one of the first active layer and the second active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

The display device further includes a data line and a driving voltage line, wherein the data line and the driving voltage line are disposed on the same layer as the first gate electrode.

The display device further includes: a second interlayer insulating layer on the first source electrode and the first drain electrode; and a planarization layer on the second interlayer insulating layer, wherein the display unit is disposed on the planarization layer.

The display unit includes a first electrode on the planarization layer, wherein the first electrode is connected to any one of the first source electrode and the first drain electrode through a contact hole provided in the second insulating layer and the planarization layer.

The display device further includes a storage capacitor connected to the first thin film transistor, wherein the storage capacitor includes: a first capacitor electrode formed integrally with the first source electrode; and a second capacitor electrode formed integrally with the first gate electrode.

The storage capacitor further includes a third capacitor electrode configured to be spaced apart from the first capacitor electrode and disposed on the second interlayer insulating layer.

The first thin film transistor may function as a driving transistor that drives the display unit. The second thin film transistor may function as a switching transistor.

According to another aspect of the present disclosure, there is provided a method of manufacturing a display device, the method including: sequentially depositing a first conductive material layer, a first insulating material layer and a first active material layer on a substrate; forming a first gate electrode from the first conductive material layer, a first gate insulating film from the first insulating material layer, and a first active layer from the first active material layer by a selective etching process; forming a first interlayer insulating layer on the first active layer; forming a second active material layer including a plurality of patterns on the first interlayer insulating layer; forming a second gate insulating film and a second gate electrode on at least a portion of the second active material layer; and making the second active material layer in a region not overlapping with the second gate electrode conductive.

According to still another aspect of the present invention, there is provided a pixel driving circuit for a display device, the pixel driving circuit including: a first gate on the substrate; a first active layer spaced apart from the first gate electrode and overlapping at least a portion of the first gate electrode; a first source connected to the first active layer; a first drain spaced apart from the first source and connected to the first active layer; a second active layer over the substrate; and a second gate electrode spaced apart from and overlapping at least a portion of the second active layer, wherein the first gate electrode, the first active layer, and the first source/drain electrodes constitute a driving transistor of the pixel driving circuit, and the second gate electrode, the second active layer, and the second source/drain electrodes constitute a switching transistor of the pixel driving circuit, and wherein the first gate electrode is disposed between the substrate and the first active layer, the second active layer is disposed between the substrate and the second gate electrode, and the first gate electrode and the second gate electrode are disposed on opposite sides with respect to the second active layer.

The first source electrode and the first drain electrode are formed to be spaced apart from each other and connected to the first active layer in the conductive process.

The etch stopper is disposed between the first source electrode and the first drain electrode.

The etch stopper layer is formed of the same material as that of the first interlayer insulating layer.

A portion of the first source electrode and a portion of the first gate electrode overlapping each other form a storage capacitor.

The method further comprises the following steps: forming a second interlayer insulating layer on the first source electrode; and forming a third capacitor electrode overlapping at least a portion of the first source electrode on the second interlayer insulating layer.

According to an aspect of the present disclosure, a bottom gate type thin film transistor is used together with a top gate type thin film transistor in a display device, so that a capacitor region in the display device can be sufficiently secured.

According to another aspect of the present disclosure, a bottom gate type thin film transistor is used together with a top gate type thin film transistor in a display device, so that the number of contact holes for electrical connection of the thin film transistor can be reduced. As a result, the capacitor region in the display device can be sufficiently secured.

According to another aspect of the present invention, a bottom gate type thin film transistor is used together with a top gate type thin film transistor in a display device, so that the number of patterning processes is reduced, and thus it is possible to simplify a manufacturing process and reduce manufacturing costs.

In addition to the effects of the present disclosure mentioned above, other advantages and features of the present disclosure will be clearly understood from the description of the present disclosure by those skilled in the art.

Drawings

The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram illustrating a display device according to one aspect of the present disclosure;

fig. 2 is a plan view illustrating a pixel unit included in the display device of fig. 1;

fig. 3 is a plan view showing any one of the pixels of fig. 1;

FIG. 4 is a circuit diagram of the pixel of FIG. 3;

FIG. 5 is a cross-sectional view taken along line I-I' of FIG. 3;

fig. 6A is a plan view showing any one pixel unit in a display device according to the related art;

fig. 6B is a sectional view showing a storage capacitor, a driving transistor, and a switching transistor included in a display device according to the related art;

fig. 7 is a cross-sectional view illustrating a pixel of a display device according to another aspect of the present disclosure;

fig. 8 is a circuit diagram illustrating a pixel of a display device according to another aspect of the present disclosure;

fig. 9A, 9B, 9C, 9D, 9E, 9F, 9G, 9H, and 9I are sectional views illustrating a method of manufacturing a display device according to an aspect of the present disclosure;

fig. 10A, 10B, 10C, and 10D are plan views illustrating a method of manufacturing a display device according to an aspect of the present disclosure; and

fig. 11 is a diagram comparing a process of manufacturing a display device according to an aspect of the present disclosure with a process of manufacturing a display device according to the related art.

Detailed Description

Advantages and features of the present disclosure and methods of accomplishing the same will be set forth in the following aspects, which are described with reference to the accompanying drawings. This disclosure may, however, be embodied in different forms and should not be construed as limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Furthermore, the present disclosure is to be limited only by the scope of the claims.

The shapes, sizes, ratios, angles, and numbers disclosed in the drawings for describing aspects of the present disclosure are merely examples, and thus the present disclosure is not limited to the details shown. Like reference numerals refer to like elements throughout. In the following description, when it is determined that a detailed description of related known functions or configurations unnecessarily obscures the focus of the present disclosure, the detailed description will be omitted.

In the case of using "including", "having", and "including" described in this specification, another component may also be present unless "only" is used. Unless otherwise indicated, terms in the singular may include the plural.

In explaining an element, although not explicitly described, the element is to be interpreted as including an error range.

In describing the positional relationship, for example, when the positional order is described as "on …", "above …", "below …", "below …" and "close", a case where there is no contact therebetween may be included unless "right" or "direct" is used. If a first element is referred to as being "on" a second element, that does not mean that the first element is substantially above the second element in the figures. The upper and lower portions of the object may be changed according to the orientation of the object concerned. Thus, the case where a first element is located "on" a second element includes the case where the first element is located "below" the second element in the drawings or actual configuration and the case where the first element is located "above" the second element.

In describing temporal relationships, for example, when temporal order is described as "after …", "subsequently", "immediately" and "before …", it may include instances of discontinuity, unless "exactly" or "directly" is used.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

The terms "first horizontal axis direction", "second horizontal axis direction", and "vertical axis direction" should not be construed based only on a geometric relationship in which the respective directions are perpendicular to each other, but may denote directions having wider directivity in a range in which the assembly of the present disclosure can be functionally operated.

It is to be understood that the term "at least one" includes all combinations that relate to any one item. For example, the "at least one of the first element, the second element, and the third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element and each of the first element, the second element, and the third element.

The features of the various aspects of the present disclosure may be partially or wholly coupled or combined with each other, and may interoperate differently from each other and be technically driven, as may be well understood by those skilled in the art. Aspects of the present disclosure may be implemented independently of each other or may be implemented together in an interdependent relationship.

In the drawings, the same or similar elements are denoted by the same reference numerals even though they are shown in different drawings.

In aspects of the present disclosure, the source and the drain are distinguished from each other for convenience of explanation. However, the source and drain may be used interchangeably. Thus, the source may be the drain, and the drain may be the source. Further, the source in any aspect of the present disclosure may be the drain in another aspect of the present disclosure, and the drain in any aspect of the present disclosure may be the source in another aspect of the present disclosure.

In one or more aspects of the present disclosure, for convenience of explanation, the source region is distinguished from the source, and the drain region is distinguished from the drain. However, aspects of the present disclosure are not limited to this structure. For example, the source region may be a source, and the drain region may be a drain. Further, the source region may be a drain, and the drain region may be a source.

Hereinafter, a display device 100 according to an aspect of the present disclosure will be described in detail with reference to fig. 1 to 5.

The display device 100 according to an aspect of the present disclosure includes a substrate 110, a Pixel Driving Circuit (PDC) on the substrate 110, and a display unit 710 connected to the Pixel Driving Circuit (PDC). The Pixel Driving Circuit (PDC) includes thin film transistors (TR1, TR 2).

Fig. 1 is a schematic diagram illustrating a display device 100 according to an aspect of the present disclosure.

As shown in fig. 1, a display device 100 according to an aspect of the present disclosure includes a pixel (P) on a substrate 110, a gate driver 220, a data driver 230, and a controller 240.

On the substrate 110, there are gate lines (G L) and data lines (D L), and pixels (P) are arranged at crossing portions of the gate lines (G L) and the data lines (D L), the pixels (P) include a display unit 710 and a Pixel Driving Circuit (PDC) for driving the display unit 710, an image is displayed by driving the pixels (P), and a plurality of pixels (P) may constitute one pixel unit (PG).

The controller 240 controls the gate driver 220 and the data driver 230.

The controller 240 outputs a Gate Control Signal (GCS) for controlling the gate driver 220 and a Data Control Signal (DCS) for controlling the data driver 230 by using vertical/horizontal synchronization signals and clock signals supplied from an external system (not shown). In addition, the controller 240 samples input video data provided from an external system, then realigns the sampled video data, and provides the realigned digital video data (RGB) to the data driver 230.

The Gate Control Signal (GCS) includes a Gate Start Pulse (GSP), a Gate Shift Clock (GSC), a gate output enable signal (GOE), a start signal (Vst), and a gate clock (GC L K).

The Data Control Signal (DCS) includes a Source Start Pulse (SSP), a source shift clock signal (SSC), a source output enable Signal (SOE), and a polarity control signal (PO L).

The data driver 230 supplies the data voltages to the data lines (D L) on the substrate 110. in particular, the data driver 230 converts the video data (RGB) supplied from the controller 240 into analog data voltages and supplies the analog data voltages to the data lines (D L).

The gate driver 220 sequentially supplies the Gate Pulse (GP) to the gate lines (G L) in 1 frame period, here, "1 frame" represents a period in which one image is output through the display panel, and furthermore, the gate driver 220 supplies the gate off signal for turning off the switching devices to the gate lines (G L) in the remaining period of 1 frame in which the Gate Pulse (GP) is not supplied.

According to an aspect of the present disclosure, the gate driver 220 may be disposed on the substrate 110. A structure in which the gate driver 220 is directly disposed on the substrate 110 may be referred to as a gate-in-panel (GIP) structure.

Fig. 2 is a plan view illustrating a pixel cell (PG) included in the display device 100 of fig. 1.

Referring to fig. 1 and 2, the pixel unit (PG) may include three pixels (P). Each of the pixels (P) included in one pixel cell (PG) may emit red, green, or blue light, respectively. The pixel cell (PG) can represent various colors by using the pixels (P) emitting red, green and blue light.

Fig. 3 is a plan view illustrating any one of the pixels (P) of fig. 1, fig. 4 is a circuit diagram of the pixel (P) of fig. 3, and fig. 5 is a sectional view taken along I-I' of fig. 3.

The circuit diagram of fig. 4 corresponds to an equivalent circuit diagram of one pixel (P) in an organic light emitting display device including an organic light emitting diode (O L ED) as the display unit 710.

The pixel (P) of the display device 100 shown in fig. 4 includes an organic light emitting diode (O L ED) corresponding to the display unit 710 and a Pixel Driving Circuit (PDC) for driving the display unit 710.

On the substrate 110, there are signal lines (D L, E L, G L, P L, SC L, R L) for supplying driving signals to a Pixel Driving Circuit (PDC) including thin film transistors (TR1, TR2, TR3, TR 4).

The Pixel Driving Circuit (PDC) of fig. 4 further includes a first thin film transistor (TR1) corresponding to the driving transistor, a second thin film transistor (TR2) corresponding to the switching transistor, a third thin film transistor (TR3) corresponding to the reference transistor, and a fourth thin film transistor (TR4) corresponding to the light emission controlling transistor.

Specifically, the first thin film transistor (TR1) corresponds to a driving transistor configured to control a level of current output to the display unit 710 according to the data voltage (Vdata) transmitted through the second thin film transistor (TR2), the second thin film transistor (TR2) corresponds to a switching transistor connected to the gate line (G L) and the data line (D L), the third thin film transistor (TR3) corresponds to a reference transistor configured to sense a characteristic of the first thin film transistor (TR1), and the fourth thin film transistor (TR4) corresponds to a light emission control transistor configured to control a light emission time by controlling the first thin film transistor (TR 1).

A data voltage (Vdata) is supplied to the data line (D L), a Scan Signal (SS) is supplied to the gate line (G L), a driving Voltage (VDD) for driving the pixel is supplied to the driving voltage line (P L), a reference voltage (Vref) is supplied to the reference line (R L), a light emission control signal (EM) is supplied to the light emission control line (E L), and a Sensing Control Signal (SCS) is supplied to the sensing control line (SC L).

Referring to fig. 4, when the gate line of the nth pixel (P) is referred to as "G L n", the gate line of the adjacent (n-1) th pixel (P) is "G L n-1", and the gate line of the (n-1) th pixel (P) serves as the sensing control line (SC L) of the nth pixel (P).

The storage capacitor (Cst) is positioned between the display unit 710 and the gate electrode (G1) of the first thin film transistor (TR 1). Specifically, the storage capacitor (Cst) is formed between a first node (n1) connected to the display unit 710 and a second node (n2) connected to the gate electrode (G1) of the first thin film transistor (TR 1).

The second thin film transistor (TR2) is turned on by a Scan Signal (SS) supplied to the gate line (G L), and the second thin film transistor (TR2) transmits a data voltage (Vdata) supplied to the data line (D L) to the gate electrode (G1) of the first thin film transistor (TR 1).

Specifically, when the second thin film transistor (TR2) is turned on, the data voltage (Vdata) supplied through the data line (D L) is supplied to the gate electrode (G1) of the first thin film transistor (TR 1).

When the first thin film transistor (TR1) is turned on, light is emitted from the display unit 710 because a driving voltage (Vdd) for driving the pixel supplies a current to the display unit 710 through the first thin film transistor (TR 1).

The third thin film transistor (TR3) is connected to the reference line (R L), turned on or off by the Sensing Control Signal (SCS), and configured to sense a characteristic of the first thin film transistor (TR1) corresponding to the driving transistor in the sensing period.

The fourth thin film transistor (TR4) transmits the driving voltage (Vdd) to the first thin film transistor (TR1) or cuts off the driving voltage (Vdd) according to the emission control signal (EM). When the fourth thin film transistor (TR4) is turned on, current is supplied to the first thin film transistor (TR1), and thus light is emitted from the display unit 710.

The amount of current supplied to the organic light emitting diode (O L ED) corresponding to the display unit 710 through the first thin film transistor (TR1) is controlled according to the data voltage (Vdata), and thus the gray scale of light emitted from the display unit 710 can be controlled.

Referring to fig. 5, a Pixel Driving Circuit (PDC) is disposed on a substrate 110.

The substrate 110 may be formed of glass or plastic. The substrate 110 may be formed of plastic having flexibility, for example, Polyimide (PI).

The Pixel Driving Circuit (PDC) includes a first thin film transistor (TR1) and a second thin film transistor (TR 2).

The first thin film transistor (TR1) includes a first gate electrode (G1) on the substrate 110, a first active layer (a1) disposed to be spaced apart from the first gate electrode (G1) and to overlap at least a portion of the first gate electrode (G1), a first source electrode (S1) connected to the first active layer (a1), and a first drain electrode (D1) disposed to be spaced apart from the first source electrode (S1) and connected to the first active layer (a 1).

The second thin film transistor (TR2) includes a second active layer (a2) over the substrate 110 and a second gate electrode (G2) disposed to be spaced apart from the second active layer (a2) and to partially overlap at least a portion of the second active layer (a 2).

Referring to fig. 5, the first gate electrode (G1), the data line (D L), and the driving voltage line (P L) are disposed on the substrate 110.

The first gate electrode (G1), the data line (D L), and the driving voltage line (P L) may be formed of the same material and may be manufactured through the same process.

The first gate electrode (G1), the data line (D L), and the driving voltage line (P L) may include at least one of an aluminum-based metal (such as aluminum or an aluminum alloy), a silver-based metal (such as silver (Ag) or a silver alloy), a copper-based metal (such as copper (Cu) or a copper alloy), a molybdenum-based metal (such as molybdenum or a molybdenum alloy), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). the first gate electrode (G1), the data line (D L), and the driving voltage line (P L) may have a multi-layered structure including at least two layers having different physical properties.

A part of the first gate (G1) becomes a second capacitor electrode (CE 2).

The first gate insulating film 121 is disposed on the first gate (G1). The first gate insulating film 121 may include at least one of silicon oxide and silicon nitride, and may include metal oxide or metal nitride. The first gate insulating film 121 may have a single-layer structure or a multi-layer structure.

On the data line (D L) and the driving voltage line (P L), there is the same insulating film as the first gate insulating film 121 according to an aspect of the present disclosure, the insulating film disposed on the data line (D L) and the driving voltage line (P L) is also referred to as the first gate insulating film 121.

The first active layer (a1) is disposed on the first gate insulating film 121. The first active layer (a1) partially overlaps with some regions of the first gate electrode (G1).

The first active layer (a1) is formed of a first active material. The first active material may be an oxide semiconductor material. According to one aspect of the present disclosure, the first active layer (a1) is an oxide semiconductor layer.

For example, the first active layer (a1) may include at least one of izo (inzno) -based oxide semiconductor, igo (ingao) -based oxide semiconductor, ito (insno) -based oxide semiconductor, igzo (ingazno) -based oxide semiconductor, igzto (ingaznsno) -based oxide semiconductor, gzto (gaznsno) -based oxide semiconductor, gzo (gazno) -based oxide semiconductor, go (gao) -based oxide semiconductor, and itzo (insnzno) -based oxide semiconductor. However, one aspect of the present disclosure is not limited to the above. The first active layer (a1) may be formed of other oxide semiconductor materials known to those skilled in the art.

The first interlayer insulating layer 171 is disposed on the first active layer (a 1). The first interlayer insulating layer 171 may be formed of an organic insulating material or an inorganic insulating material. The first interlayer insulating layer 171 serves as an Etch Stopper (ES) of the first active layer (a1) of the first thin film transistor (TR 1). Accordingly, the first thin film transistor (TR1) may be referred to as a thin film transistor of a BCE structure having an Etch Stopper (ES).

Specifically, a first thin film transistor (TR1) according to one aspect of the present disclosure has an etch stopper layer (ES). The etch stopper layer (ES) is disposed in the same layer as the first interlayer insulating layer 171 on the first active layer (a1), and may be formed of the same material as that of the first interlayer insulating layer 171. The etch stopper layer (ES) protects the channel region of the first active layer (a 1).

The second active layer (a2) is disposed on the first interlayer insulating layer 171.

The second active layer (a2) is formed of a second active material. The second active material may be an oxide semiconductor material. According to one aspect of the present disclosure, the second active layer (a2) is an oxide semiconductor layer.

The second active layer (a2) may be formed of the same oxide semiconductor material as that of the first active layer (a1), or may be formed of an oxide semiconductor material different from that of the first active layer (a 1).

For example, the second active layer (a2) may include at least one of izo (inzno) -based oxide semiconductor, igo (ingao) -based oxide semiconductor, ito (insno) -based oxide semiconductor, igzo (ingazno) -based oxide semiconductor, igzto (ingaznsno) -based oxide semiconductor, gzto (gaznsno) -based oxide semiconductor, gzo (gazno) -based oxide semiconductor, go (gao) -based oxide semiconductor, and itzo (insnzno) -based oxide semiconductor. However, one aspect of the present disclosure is not limited to the above. The second active layer (a2) may be formed of other oxide semiconductor materials known to those skilled in the art.

According to an aspect of the present invention, the first source electrode (S1), the first drain electrode (D1), the second source electrode (S2), and the second drain electrode (D2) are disposed on the first interlayer insulating layer 171.

The first source (S1), the first drain (D1), the second source (S2), and the second drain (D2) may be formed of a second active material.

The second gate insulating film 122 is disposed on the second active layer (a2), and the second gate electrode (G2) is disposed on the second gate insulating film 122. As a result, the second thin film transistor (TR2) including the second gate electrode (G2), the second active layer (a2), the second source electrode (S2), and the second drain electrode (D2) is completed.

According to an aspect of the present disclosure, after a second active material layer of a second active material is formed on the first interlayer insulating layer 171, a portion of the second active material layer not overlapping the second gate (G2) is selectively electrically conductive, thereby forming a first source electrode (S1), a first drain electrode (D1), a second source electrode (S2), and a second drain electrode (D2). And, other regions of the second active material layer overlapping the second gate electrode (G2) become the second active layer (a2) without being electrically conducted. In the present disclosure, "conductive" means that a part of an active material is made a conductor.

The second active material for forming the second active layer (a2) is an oxide semiconductor material, and thus the second active material may be electrically conductive through plasma treatment or hydrogen treatment.

The electrically conductive portion of the second active material layer may be referred to as an electrically conductive portion. The plurality of conductive portions may be formed by making the second active material layer conductive.

Among the conductive portions, each portion connected to the first active layer (a1) becomes a first source electrode (S1) and a first drain electrode (D1). The first drain electrode (D1) is connected to the first active layer (a1) through a third contact hole (CH3) provided in the first interlayer insulating layer 171. The first source electrode (S1) is connected to the first active layer (a1) through a fourth contact hole (CH4) provided in the first interlayer insulating layer 171. Further, referring to fig. 5, an Etch Stopper (ES) is disposed between the third contact hole (CH3) and the fourth contact hole (CH 4). As a result, the first thin film transistor (TR1) including the first gate electrode (G1), the first active layer (a1), the first source electrode (S1), and the first drain electrode (D1) is completed.

According to an aspect of the present disclosure, the contact hole may not be completely filled with the second active material. For example, each of the first source electrode (S1) and the first drain electrode (D1) may have a recess in the contact holes (CH4, CH 3). Thereafter, the first source electrode (S1) and the first drain electrode (D1) are made conductive by plasma treatment or hydrogen treatment.

According to an aspect of the present disclosure, a portion of the first source electrode (S1) becomes the first capacitor electrode (CE 1). The first capacitor electrode (CE1) forms a first capacitor (C1) together with the second capacitor electrode (CE 2).

Further, among the plurality of conductive portions, the conductive portion connected to the second active layer (a2) becomes a second source electrode (S2) and a second drain electrode (D2). According to an aspect of the present disclosure, the second source electrode (S2) and the second drain electrode (D2) are formed integrally with the second active layer (a 2).

The second source electrode (S2) is connected to the data line (D L) through the first contact hole (CH1) provided in the first gate insulating film 121 and the first interlayer insulating layer 171. in addition, the second drain electrode (D2) is connected to the first gate electrode (G1) through the second contact hole (CH2) provided in the first gate insulating film 121 and the first interlayer insulating layer 171. as described above, a portion of the first gate electrode (G1) becomes the second capacitor electrode (CE 2.) therefore, depending on the second drain electrode (D2) being connected to the first gate electrode (G1), the second drain electrode (D2) is also connected to the second capacitor electrode (CE 2).

According to another aspect of the present disclosure, each of the conductive portions configured to be separated from each other and connected with the second active layer (a2) may be referred to as a source region and a drain region. However, the source region and the source are not distinguished from each other, and the source region may be referred to as a source. Also, the drain region and the drain are not distinguished from each other, and the drain region may be referred to as a drain.

The second interlayer insulating layer 172 is disposed on the first thin film transistor (TR1) and the second thin film transistor (TR 2). The second interlayer insulating layer 172 may be formed of an organic insulating material or an inorganic insulating material.

The gate line (G L), the light emission control line (E L), the driving voltage connection line (P L B), and the third capacitor electrode (CE3) are disposed on the second interlayer insulating layer 172.

Referring to fig. 3, one end of the driving voltage connection line (P L B) is connected to the driving voltage line (P L) through the contact holes (CH11, CH12), and the other end of the driving voltage connection line (P L B) is connected to the fourth thin film transistor (TR4) through the contact hole (CH13), thereby supplying the driving voltage to the fourth thin film transistor (TR4) corresponding to the light emission control transistor of each pixel (P).

The third capacitor electrode (CE3) is connected to the second drain electrode (D2) through a fifth contact hole (CH5) provided in the second interlayer insulating layer 172. Accordingly, the third capacitor electrode (CE3) may be connected to the second capacitor electrode (CE2) through the second drain electrode (D2). Therefore, the same voltage as that of the second capacitor electrode (CE2) is supplied to the third capacitor electrode (CE 3). The third capacitor electrode (CE3) overlaps the first capacitor electrode (CE1), thereby forming a second capacitor (C2). The first capacitor (C1) and the second capacitor (C2) constitute a storage capacitor (Cst).

The planarization layer 173 is disposed on the gate line (G L), the emission control line (E L), the driving voltage connection line (P L B), and the third capacitor electrode (CE3), the planarization layer 173 is configured to planarize an upper surface of the first thin film transistor (TR1) and an upper surface of the second thin film transistor (TR2), and also protect the first thin film transistor (TR1) and the second thin film transistor (TR 2).

The first electrode 711 of the display unit 710 is disposed on the planarization layer 173. The first electrode 711 of the display unit 710 may be connected to any one of the first source electrode (S1) and the first drain electrode (D1) included in the first thin film transistor (TR1) through a sixth contact hole (CH6) provided in the planarization layer 173 and the second interlayer insulating layer 172. In fig. 5, the first electrode 711 is connected to the first source (S1) of the first thin film transistor (TR 1). However, the first electrode 711 is not limited to this structure. The first electrode 711 may be connected to a first drain electrode (D1) of the first thin film transistor (TR 1).

The bank layer 750 is disposed in an edge of the first electrode 711. The bank layer 750 defines a light emitting area of the display unit 710.

The organic light emitting layer 712 is disposed on the first electrode 711, and the second electrode 713 is disposed on the organic light emitting layer 712, thus completing the display unit 710 shown in fig. 5 corresponds to an organic light emitting diode (O L ED).

According to one aspect of the present disclosure, the first thin film transistor (TR1) is a bottom gate type thin film transistor, wherein the first gate electrode (G1) is located under the first active layer (a 1). In addition, the second thin film transistor (TR2) is a top gate type thin film transistor in which the second gate electrode (G2) is positioned above the second active layer (a 2).

Referring to fig. 5, in the first thin film transistor (TR1), a first gate electrode (G1) is disposed between the substrate 110 and the first active layer (a 1). In the second thin film transistor (TR2), a second active layer (a2) is disposed between the substrate 110 and the second gate electrode (G2).

In addition, the first gate electrode (G1) and the second gate electrode (G2) are disposed on opposite layers to each other with respect to the second active layer (a 2).

Specifically, the first gate electrode (G1) is disposed at a position closer to the substrate 110 than the second active layer (a 2). Therefore, referring to the drawings, the first gate electrode (G1) is disposed at a lower layer than the second active layer (a 2).

In addition, the second gate electrode (G2) is disposed to be spaced farther from the substrate 110 than the second active layer (a 2). Therefore, referring to the drawings, the second gate electrode (G2) is disposed at an upper layer as compared to the second active layer (a 2).

In addition, the second active layer (a2) is disposed in the same layer as the first source electrode (S1) and the first drain electrode (D1). According to an aspect of the present disclosure, the second active layer (a2) is formed of an oxide semiconductor material, and the first source electrode (S1) and the first drain electrode (D1) may be formed of the same oxide semiconductor material as that of the second active layer (a 2). However, the second active layer (a2) is a non-conductive layer, and the first source electrode (S1) and the first drain electrode (D1) are conductive layers.

Further, the display device 100 according to an aspect of the present disclosure includes a storage capacitor (Cst) connected to the first thin film transistor (TR 1). The storage capacitor (Cst) includes a first capacitor (C1) and a second capacitor (C2).

Specifically, the storage capacitor (Cst) includes a first capacitor electrode (CE1) integrally formed with the first source electrode (S1) and a second capacitor electrode (CE2) integrally formed with the first gate electrode (G1). The first capacitor electrode (CE1) and the second capacitor electrode (CE2) constitute a first capacitor (C1).

The storage capacitor (Cst) further includes a third capacitor electrode (CE3), the third capacitor electrode (CE3) being disposed spaced apart from and over the first capacitor electrode (CE1) (CE 1). Here, the first capacitor electrode (CE1) is disposed between the second capacitor electrode (CE2) and the third capacitor electrode (CE 3). The first capacitor electrode (CE1) and the third capacitor electrode (CE3) constitute a second capacitor (C2).

According to an aspect of the present disclosure, the storage capacitor (Cst) includes a first capacitor (C1) and a second capacitor (C2) disposed in the same region. Accordingly, the capacitance of the storage capacitor (Cst) may be increased. Accordingly, in a high resolution display device having a high density of integrated thin film transistors, the capacitance of the storage capacitor (Cst) may be increased without increasing the area of the storage capacitor (Cst).

In general, in the case of a top gate type thin film transistor having an oxide semiconductor layer, a process of making the oxide semiconductor layer conductive is required, and a contact region of a source electrode and a drain electrode is also required, so the top gate type thin film transistor has a limitation on the size and thickness of a gate insulating film.

Further, with an aspect of the present disclosure, the first thin film transistor (TR1) for driving the display unit 710 is a bottom gate type. Further, the first active layer (a1) of the first thin film transistor (TR1) is formed of an oxide semiconductor, and a process of making the oxide semiconductor layer conductive is not required. Therefore, if necessary, the size and thickness of the first gate insulating film 121 included in the first thin film transistor (TR1) may be increased.

If the thickness of the first gate insulating film 121 is increased, the s-factor of the first thin film transistor (TR1) can be increased.

For the threshold voltage (Vth) portion of the thin film transistor, the s-factor (sub-threshold swing: s-factor) can be obtained by the inverse of the slope in the graph of gate voltage versus drain current. If the s factor becomes large, the rate of change of the gate voltage of the drain-source current (IDS) with respect to the threshold voltage (Vth) section becomes low, thus contributing to control of the level of the drain-source current (IDS) by the control gate voltage.

The pixel gray scale can be controlled by controlling the drain-source current (IDS). While helping to control the level of the drain-source current (IDS), helps to control the pixel grayscale.

According to an aspect of the present disclosure, it is facilitated to increase the thickness of the first gate insulating film 121 of the bottom gate type first thin film transistor (TR1), thereby facilitating to increase the s-factor of the first thin film transistor (TR 1). Therefore, if the first thin film transistor (TR1) according to an aspect of the present disclosure is used as a driving thin film transistor, it contributes to rendering a pixel gray scale.

According to an aspect of the present disclosure, the first gate electrode (G1), the first gate insulating film 121, and the first active layer (a1) may be formed together through the same etching process of the same manufacturing step, and thus the manufacturing process may be simplified and the manufacturing cost may be reduced.

Further, according to an aspect of the present disclosure, the first thin film transistor (TR1) of the bottom gate type is used together with the second thin film transistor (TR2) of the top gate type, so that the number of contact holes for electrical connection between the thin film transistor and the line can be reduced. If the number of the contact holes is reduced, the area occupied by the contact holes is reduced, so that the area of the storage capacitor (Cst) can be relatively increased. As a result, according to an aspect of the present disclosure, a capacitor region in the display device 100 may be sufficiently ensured.

Fig. 6A is a plan view showing any one pixel unit in a display device according to the related art. Fig. 6B is a sectional view illustrating a storage capacitor, a driving transistor, and a switching transistor included in a display device according to the related art. In fig. 6A, one pixel unit includes three pixels.

Referring to fig. 6A and 6B, both the switching thin film transistor and the driving thin film transistor are formed of a top gate type thin film transistor. As a result, referring to fig. 6A, it can be known that many contact holes are provided to electrically connect the thin film transistors with the wires.

Further, in the case of the display device 100 according to an aspect of the present disclosure, the number of contact holes provided in one pixel cell (PG) is relatively smaller than the number of contact holes provided in one pixel cell of the display device according to the related art. For example, the pixel cell of fig. 6A includes 39 contact holes. In addition, the pixel cell (PG) of the display device 100 according to an aspect of the present disclosure includes 26 contact holes. According to the present disclosure, the number of contact holes in the pixel driving circuit is reduced, and thus the area of the storage capacitor (Cst) is increased by reducing the number of contact holes.

Fig. 7 is a sectional view illustrating a pixel (P) of a display device 200 according to another aspect of the present disclosure. Hereinafter, a repetitive description of the same parts will be omitted to avoid unnecessary repetition.

According to another aspect of the present disclosure, at least one of the first active layer (a1) and the second active layer (a2) includes a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

Referring to fig. 7, the first active layer (A1) includes a first oxide semiconductor layer (A1a) and a second oxide semiconductor layer (A1b) on the first oxide semiconductor layer (A1 a). The first oxide semiconductor layer (A1a) serves as a support layer that supports the second oxide semiconductor layer (A1b), and the second oxide semiconductor layer (A1b) serves as a channel layer. The channel of the first active layer (A1) is generally formed in the second oxide semiconductor layer (A1 b).

The first oxide semiconductor layer (A1a) serving as a support layer has high film stability and good mechanical properties. In order to obtain high film stability, the first oxide semiconductor layer (A1a) may include gallium (Ga), wherein gallium (Ga) forms a stable bond with oxygen, and gallium oxide has good film stability.

For example, the first oxide semiconductor layer (A1a) may include at least one of an igzo (ingazno) -based oxide semiconductor material, an igo (ingao) -based oxide semiconductor material, an igto (ingasno) -based oxide semiconductor material, an igzto (ingaznsno) -based oxide semiconductor material, a gzto (gaznsno) -based oxide semiconductor material, a gzo (gazno) -based oxide semiconductor material, and a go (gao) -based oxide semiconductor material.

For example, the second oxide semiconductor layer (A1b) may include at least one of izo (inzno) -based oxide semiconductor material, igo (ingao) -based oxide semiconductor material, ito (insno) -based oxide semiconductor material, igzo (ingazno) -based oxide semiconductor material, igzto (ingaznsno) -based oxide semiconductor material, gzto (gaznsno) -based oxide semiconductor material, and itzo (insnzno) -based oxide semiconductor material. However, one aspect of the present disclosure is not limited to the above. The second oxide semiconductor layer (A1b) may be formed of other oxide semiconductor materials known to those skilled in the art.

In addition, the second active layer (A2) may include a first oxide semiconductor layer (A2a) and a second oxide semiconductor layer (A2b) on the first oxide semiconductor layer (A2 a). The first oxide semiconductor layer (A2a) serves as a support layer that supports the second oxide semiconductor layer (A2b), and the second oxide semiconductor layer (A2b) serves as a channel layer. The channel of the second active layer (A2) is generally formed in the second oxide semiconductor layer (A2 b).

The first oxide semiconductor layer (A2a) serving as a support layer has high film stability and good mechanical properties. For high film stability, the first oxide semiconductor layer (A2a) may include gallium (Ga), wherein gallium (Ga) forms a stable bond with oxygen, and gallium oxide has good film stability.

For example, the first oxide semiconductor layer (A2a) may include at least one of an igzo (ingazno) -based oxide semiconductor material, an igo (ingao) -based oxide semiconductor material, an igto (ingasno) -based oxide semiconductor material, an igzto (ingaznsno) -based oxide semiconductor material, a gzto (gaznsno) -based oxide semiconductor material, a gzo (gazno) -based oxide semiconductor material, and a go (gao) -based oxide semiconductor material.

For example, the second oxide semiconductor layer (A2b) may include at least one of izo (inzno) -based oxide semiconductor material, igo (ingao) -based oxide semiconductor material, ito (insno) -based oxide semiconductor material, igzo (ingazno) -based oxide semiconductor material, igzto (ingaznsno) -based oxide semiconductor material, gzto (gaznsno) -based oxide semiconductor material, and itzo (insnzno) -based oxide semiconductor material. However, one aspect of the present disclosure is not limited to the above. The second oxide semiconductor layer (A2b) may be formed of other oxide semiconductor materials known to those skilled in the art.

Fig. 8 is a circuit diagram illustrating a pixel of the display device 300 according to another aspect of the present disclosure. Fig. 8 is an equivalent circuit diagram of a pixel (P) of the organic light emitting display device.

The pixel (P) of the display apparatus 300 shown in fig. 8 includes an organic light emitting diode (O L ED) corresponding to the display unit 710 and a Pixel Driving Circuit (PDC) for driving the display unit 710 is connected with the Pixel Driving Circuit (PDC).

In the pixel (P), there are signal lines (D L, G L, P L, R L, SC L) for supplying signals to the Pixel Drive Circuit (PDC).

A data voltage (Vdata) is supplied to the data line (D L), a Scan Signal (SS) is supplied to the gate line (G L), a driving Voltage (VDD) for driving the pixel is supplied to the driving voltage line (P L), a reference voltage (Vref) is supplied to the reference line (R L), and a Sensing Control Signal (SCs) is supplied to the sensing control line (SC L).

Referring to fig. 8, when the gate line of the nth pixel (P) is referred to as "G L n", the gate line of the adjacent (n-1) th pixel (P) is "G L n-1", and the gate line of the (n-1) th pixel (P) serves as the sensing control line (SC L) of the nth pixel (P).

The Pixel Driving Circuit (PDC) includes a second thin film transistor (TR2, a switching transistor) connected to the gate line (G L) and the data line (D L), a first thin film transistor (TR1, a driving transistor) configured to control a level of a current supplied to the display unit 710 according to a data voltage (Vdata) transmitted through the second thin film transistor (TR2), and a third thin film transistor (TR3, a reference transistor) configured to sense a characteristic of the first thin film transistor (TR 1).

The storage capacitor (Cst) is positioned between the display unit 710 and the first gate electrode (G1) of the first thin film transistor (TR 1).

The second thin film transistor (TR2) is turned on by a Scan Signal (SS) supplied to the gate line (G L), and the second thin film transistor (TR2) transmits a data voltage (Vdata) supplied to the data line (D L) to the first gate electrode (G1) of the first thin film transistor (TR 1).

The third thin film transistor (TR3) is connected to the reference line (R L) and the first node (n1) between the display unit 710 and the first thin film transistor (TR1), the third thin film transistor (TR3) is turned on or off by the Sensing Control Signal (SCS), and the third thin film transistor (TR3) senses a characteristic of the first thin film transistor (TR1) corresponding to the driving transistor in the sensing period.

The second node (n2) connected to the first gate (G1) of the first thin film transistor (TR1) is connected to the second thin film transistor (TR 2). The storage capacitor (Cst) is formed between the second node (n2) and the first node (n 1).

When the second thin film transistor (TR2) is turned on, the data voltage (Vdata) supplied through the data line (D L) is supplied to the first gate electrode (G1) of the first thin film transistor (TR1) — the storage capacitor (Cst) formed between the first source electrode (S1) and the first gate electrode (G1) of the first thin film transistor (TR1) is charged with the data voltage (Vdata).

When the first thin film transistor (TR1) is turned on, light is emitted from the display unit 710 because a driving voltage (Vdd) for driving the pixel supplies a current to the display unit 710 through the first thin film transistor (TR 1).

In addition to the above-described structure, the Pixel Driving Circuit (PDC) according to another aspect of the present disclosure may be formed in various structures. For example, the Pixel Driving Circuit (PDC) may include five or more thin film transistors.

Hereinafter, a method of manufacturing the display device 100 according to an aspect of the present disclosure will be described with reference to fig. 9A to 9I and 10A to 10D.

Fig. 9A to 9I are sectional views illustrating a method of manufacturing the display device 100 according to an aspect of the present disclosure, and fig. 10A to 10D are plan views illustrating a method of manufacturing the display device 100 according to an aspect of the present disclosure.

Referring to fig. 9A, first, a first conductive material layer 115, a first insulating material layer 120, and a first active material layer 130 are sequentially deposited on a first substrate 110. Here, the first conductive material layer 115 is formed of a first conductive material, the first insulating material layer 120 is formed of a first insulating material, and the first active material layer 130 is formed of a first active material.

According to an aspect of the present disclosure, the first active material is an oxide semiconductor material, and the first active material layer 130 is an oxide semiconductor layer. The first active material layer 130 may include at least one of izo (inzno) -based oxide semiconductor material, igo (ingao) -based oxide semiconductor material, ito (insno) -based oxide semiconductor material, igzo (ingazno) -based oxide semiconductor material, igzto (ingaznsno) -based oxide semiconductor material, gzto (gaznsno) -based oxide semiconductor material, gzo (gazno) -based oxide semiconductor material, go (gao) -based oxide semiconductor material, and itzo (inszno) -based oxide semiconductor material.

In addition, referring to fig. 9A, a photoresist layer 310 is formed on the first active material layer 130. The photoresist layer 310 may be formed of a negative Photoresist (PR) material or a positive Photoresist (PR) material. According to an aspect of the present disclosure, the photoresist layer 310 may be formed of a positive Photoresist (PR) material.

A pattern mask 610 is disposed on the photoresist layer 310, and light (L) is irradiated through the pattern mask 610, thereby performing exposure of the photoresist layer 310.

A half-tone mask may be used for the pattern mask 610. Referring to fig. 9A, the pattern mask 610 is a half-tone mask including a transmission part 611, a half-transmission part 612, and a light-shielding part 613.

The photoresist layer 310 is selectively exposed by exposure using the pattern mask 610, the light shielding layer 613 of the pattern mask 610 corresponds to a region where the first active layer (a1) is to be disposed, the semi-transmission portion 612 of the pattern mask 610 corresponds to a region where the first gate electrode (G1), the data line (D L), and the driving voltage line (P L) are to be disposed, and the transmission portion 611 of the pattern mask 610 corresponds to a region where the first conductive material layer 115, the first insulating material layer 120, and the first active layer 130 are completely removed.

Referring to fig. 9B, the selectively exposed photoresist layer 310 is developed, thereby forming photoresist patterns 310a, 310B, and 310B.

Referring to fig. 9C, a first gate electrode (G1) of a first conductive material, a first gate insulating film 121 of a first insulating material, and a first active layer (a1) of a first active material are formed through a selective etching process.

Specifically, an etching process using the photoresist patterns 310a, 310b, and 310c as a mask is performed such that the first active layer (a1) is formed by patterning the first active material layer 130, the first gate insulating film 121 is formed by patterning the first insulating material layer 120, and the first gate electrode (G1) is formed by patterning the first conductive material layer 115, and in addition, the data line (D L) and the driving voltage line (P L) are formed by patterning the first conductive material layer 115.

Fig. 9C corresponds to fig. 10A in plan.

As described above, the first MASK process (MASK1) is performed to form the first gate electrode (G1) and the first active layer (a 1).

Referring to fig. 9D, a first interlayer insulating layer 171 is formed on the first active layer (a1), and a contact hole is formed in the first interlayer insulating layer 171 and the first gate insulating film 121, specifically, a first contact hole (CH1) is formed in the first interlayer insulating layer 171 and the first gate insulating film 121 such that a portion of the data line (D L) is exposed, a second contact hole (CH2) is formed in the first interlayer insulating layer 171 and the first gate insulating film 121 such that a portion of the first gate electrode (G1) is exposed, and a third contact hole (CH3) and a fourth contact hole (CH4) are formed in the first interlayer insulating layer 171 such that the first active layer (a1) is partially exposed.

In order to form a contact hole in the first interlayer insulating layer 171 and the first gate insulating film 121, a second MASK process (MASK2) is performed.

In addition, an Etch Stopper (ES) is formed on the first active layer (a1) for a process of forming contact holes (CH1, CH2, CH3, CH 4). An etch stopper layer (ES) is formed between the third contact hole (CH3) and the fourth contact hole (CH4), and is configured to protect a channel region of the first active layer (a 1).

Referring to fig. 9E, second active materials 151, 152, and 153 are formed on the first interlayer insulating layer 171. The second active material layers 151, 152, and 153 include a plurality of patterns.

A third MASK process (MASK3) is performed to form second active material layers 151, 152, and 153.

Fig. 9E corresponds to fig. 10B in plan.

An oxide semiconductor material may be used for the second active material. According to an aspect of the present disclosure, the second active material layers 151, 152, and 153 correspond to an oxide semiconductor layer.

The second active material layers 151, 152, and 153 may be formed of the same semiconductor material as that of the first active material layer 130, or may be formed of a semiconductor material different from that of the first active material layer 130.

For example, the second active material layers 151, 152, and 153 may include at least one of izo (inzno) -based oxide semiconductor material, igo (ingao) -based oxide semiconductor material, ito (insno) -based oxide semiconductor material, igzo (ingazno) -based oxide semiconductor material, igzto (ingaznsno) -based oxide semiconductor material, gzto (gaznsno) -based oxide semiconductor material, gzo (gazno) -based oxide semiconductor material, go (gao) -based oxide semiconductor material, and itzo (insnzno) -based oxide semiconductor material.

Referring to fig. 9F, a second gate insulating film 122 and a second gate electrode (G2) are formed on at least a portion of the second active material layers 151, 152, and 153.

Fig. 9F corresponds to fig. 10C in plan.

A fourth MASK process (MASK4) is performed to form the second gate insulating film 122 and the second gate electrode (G2).

After the second gate insulating film 122 and the second gate electrode (G2) are formed, portions of the second active material layers 151, 152, and 153 that do not overlap the second gate electrode (G2) become electrically conductive. As a result, the first source (S1), the first drain (D1), the second source (S2), and the second drain (D2) may be formed.

The plasma treatment or the hydrogen treatment may be performed for the conductive treatment.

The second active material for forming the second active layer (a2) is an oxide semiconductor material, and thus the second active material is electrically conductive through plasma treatment or hydrogen treatment.

The conductive portions of the second active material layers 151, 152, and 153 may be referred to as conductive portions. The plurality of conductive portions may be formed by a conductive process of the second active material layers 151, 152, and 153.

As a result, a second thin film transistor (TR2) including the second gate electrode (G2), the second active material layer (a2), a second source electrode (S2), and a second drain electrode (D2) may be formed, the second source electrode (S2) is connected to the data line (D L) through a first contact hole (CH1) provided in the first gate insulating film 121 and the first interlayer insulating layer 171, and the second drain electrode (D2) is connected to the first gate electrode (G1) through a second contact hole (CH2) provided in the first contact hole 121 and the first interlayer insulating layer 171.

The first source electrode (S1) and the first drain electrode (D1) are formed to be spaced apart from each other while being connected to the first active layer (a1) through a conductive step.

Referring to fig. 9F, regions of the conductive portions connected to the first active layer (a1) become a first source (S1) and a first drain (D1). For example, a region of the conductive portion connected to the first active layer (a1) becomes a first source electrode (S1), and a region spaced apart from the first source electrode (S1) while being connected to the first active layer (a1) becomes a first drain electrode (D1). Specifically, the first drain electrode (D1) is connected to the first active layer (a1) through a third contact hole (CH3) provided in the first interlayer insulating layer 171. The first source electrode (S1) is connected to the first active layer (a1) through a fourth contact hole (CH4) provided in the first interlayer insulating layer 171. Further, referring to fig. 5, an Etch Stopper (ES) is formed between the third contact hole (CH3) and the fourth contact hole (CH 4). As a result, a first thin film transistor (TR1) including the first gate electrode (G1), the first active layer (a1), the first source electrode (S1), and the first drain electrode (D1) is formed.

Further, referring to fig. 9F, some regions of the first source (S1) and some regions of the first gate (G1) overlapping each other form a first capacitor (C1). Specifically, the first capacitor (C1) is formed of a first capacitor electrode (CE1) integrally formed with the first source electrode (S1) and a second capacitor electrode (CE2) integrally formed with the first gate electrode (G1).

The storage capacitor (Cst) includes the first capacitor (C1).

Referring to fig. 9G, a second interlayer insulating layer 172 is formed on the first thin film transistor (TR1), the second thin film transistor (TR2), and the first capacitor (C1). The second interlayer insulating layer 172 may be formed of an organic or inorganic insulating material. A fifth contact hole (CH5) is formed in the second insulating layer 172, thus exposing a portion of the second drain electrode (D2).

In order to form the fifth contact hole (CH5) in the second interlayer insulating layer 172, a fifth MASK process (MASK5) is performed.

Referring to fig. 9H, a gate line (G L), a light emission control line (E L), a driving voltage connection line (P L B), and a third capacitor electrode (CE3) are formed on the second interlayer insulating layer 172 the gate line (G L), the light emission control line (E L), the driving voltage connection line (P L B), and the third capacitor electrode (CE3) are referred to as upper lines.

Fig. 9H corresponds to fig. 10D in plan.

A sixth MASK process (MASK6) is performed to form upper lines such as the gate line (G L), the light emission control line (E L), the driving voltage connection line (P L B), and the third capacitor electrode (CE 3).

According to one aspect of the present disclosure, a Pixel Driving Circuit (PDC) is formed by a six-mask process.

Referring to fig. 9H, a second interlayer insulating layer 172 is formed on the first source electrode (S1), and a third capacitor electrode (CE3) is partially overlapped with at least a portion of the first source electrode (S1) on the second interlayer insulating layer 172. The third capacitor electrode (CE3) is connected to the second drain electrode (D2) through a fifth contact hole (CH5) provided in the second interlayer insulating layer 172. Accordingly, the third capacitor electrode (CE3) may be connected to the second capacitor electrode (CE2) through the second drain electrode (D2).

The third capacitor electrode (CE3) forms a second capacitor (C2) together with the first capacitor electrode (CE 1). The first capacitor (C1) and the second capacitor (C2) constitute a storage capacitor (Cst).

Then, referring to fig. 9I, a planarization layer 173 is disposed on the gate line (G L), the emission control line (E L), the driving voltage connection line (P L B), and the third capacitor electrode (CE3), the first electrode 711 of the display unit 710 is disposed on the planarization layer 173, the organic light emitting layer 712 is disposed on the first electrode 711, and the second electrode 713 is disposed on the organic light emitting layer 712, thereby completing the display device 100 the first electrode 711 is connected to the source electrode (S1) of the first thin film transistor (TR1) through a sixth contact hole (CH6) disposed in the planarization layer 173 and the second interlayer insulating layer 172.

Fig. 11 is a diagram comparing a process of manufacturing a display device according to an aspect of the present disclosure with a process of manufacturing a display device according to the related art.

Specifically, fig. 11 compares the number of mask processes performed until a Pixel Driving Circuit (PDC) is completed in a display device according to an aspect of the present invention with the number of mask processes performed until the pixel driving circuit is completed in a display device according to the related art.

According to one aspect of the present disclosure, six mask processes are required to form a Pixel Driving Circuit (PDC).

Specifically, according to an aspect of the present disclosure, a first MASK process (MASK1) is performed to form a first gate electrode (G1) and a first active layer (a1), a second MASK process (MASK2) is performed to form a contact hole in the first interlayer insulating layer 171, a third MASK process (MASK3) is performed to form a second active material layer, and a fourth MASK process (MASK4) is performed to form a second gate electrode (G2), a conductive treatment for the second active material layer is performed during the fourth MASK process (MASK4), and a conductive treatment for the second active material layer may be performed by using the second gate electrode (G2) as a MASK.

In addition, seven mask processes are required to form a Pixel Driving Circuit (PDC) of the display device according to the related art shown in fig. 6A and 6B.

Specifically, according to the related art, a first MASK process (MASK1) is performed to form the lower metal pattern 116, a second MASK process (MASK2) is performed to form a contact hole in the buffer layer 125, a third MASK process (MASK3) is performed to form the active material layer (ACT1, ACT2), and a fourth MASK process (MASK4) is performed to form the gate electrode (TG1, TG 2.) a conductive process to the active material layer (ACT1, ACT2) is performed with respect to the fourth MASK process (MASK 4). furthermore, a fifth MASK process (MASK5) is performed to form the upper capacitor electrode (CE3), a sixth MASK process (MASK6) is performed to form a contact hole in the second interlayer insulating layer 172, and a seventh MASK process (MASK7) is performed to form an upper line such as the gate line (G L), the emission control line (E L), the driving voltage connection line (P L B), and the third capacitor electrode (CE 3).

The number of mask processes for forming a Pixel Driving Circuit (PDC) according to an aspect of the present disclosure is smaller than the number of mask processes for forming a pixel driver having a similar structure according to the related art. As a result, according to the present disclosure, the manufacturing process can be simplified, and the manufacturing cost and time can also be reduced.

It will be apparent to those skilled in the art that the present disclosure described above is not limited to the above-described aspects and drawings, and that various substitutions, modifications and changes may be made in the present disclosure without departing from the spirit or scope of the present disclosure. Accordingly, the scope of the present disclosure is defined by the appended claims, and all changes or modifications derived from the meaning, scope and equivalent concept of the claims are intended to fall within the scope of the present disclosure.

Cross Reference to Related Applications

This application claims priority from korean patent application No. 10-2018-.