阅读说明：本技术 一种静态随机存取存储器 (Static random access memory ) 是由 小嶋英充 于 2019-06-19 设计创作，主要内容包括：本发明的目的在于提供一种能够减少输入输出所需要的数据线的数量的静态随机存取存储器。静态随机存取存储器包括：单元阵列,其具有呈行列状配置的多个存储单元(MC)；以及输入输出电路(IO),其具有多个输入输出部(IOU)、外部输入端子和外部输出端子,该输入输出部(IOU)包括：输入部(I),其保持被输入的输入数据并将输入数据输出到存储单元(MC),由此向存储单元(MC)进行输入数据的写入；以及输出部(O),其保持从存储单元(MC)输出的输出数据并将输出数据输出,由此进行输出数据的读取,通过将各输入部(I)串联连接,输入数据被串联输入到各输入部(I),通过将各输出部(O)串联连接,各输出部(O)所保持的输出数据被串联输出。(The invention aims to provide a static random access memory capable of reducing the number of data lines required for input and output. The static random access memory includes: a cell array having a plurality of Memory Cells (MC) arranged in rows and columns; and an input/output circuit (IO) having a plurality of input/output units (IOU), an external input terminal, and an external output terminal, the IO circuit (IOU) including: an input unit (I) for holding input data to be input and outputting the input data to the Memory Cell (MC) to thereby write the input data to the Memory Cell (MC); and an output unit (O) that holds output data outputted from the Memory Cells (MC) and outputs the output data, thereby reading the output data, wherein the input data is inputted to the input units (I) in series by connecting the input units (I) in series, and the output data held by the output units (O) is outputted in series by connecting the output units (O) in series.)

1. A static random access memory, comprising:

a cell array having a plurality of memory cells arranged in rows and columns; and

an input-output circuit having a plurality of input-output sections, an external input terminal, and an external output terminal, the input-output section including: an input unit that holds input data to be input and outputs the input data to the storage unit, thereby writing the input data to the storage unit; and an output unit that holds output data output from the storage unit and outputs the output data, thereby reading the output data;

wherein the input data is serially input to the respective input portions by serially connecting the respective input portions;

by connecting the output sections in series, the output data held by the output sections are output in series.

2. The static random access memory of claim 1, wherein:

the input section includes an output-side selector that selects one of the memory cell and the other input sections connected in series as a connection target on an output side;

the output section includes an input side selector that selects one of the storage unit and the other output sections connected in series as a connection destination of the input side.

3. The static random access memory of claim 1, wherein:

the input/output circuit includes an input side division selector, one end of which is connected to the input section, and the other end of which is connected to the other input section or an external input terminal.

4. The static random access memory of claim 1, wherein:

the input/output circuit includes an output side division selector, one end of the output side division selector is connected to the output section, and the other end of the output side division selector is connected to the other output section or an external output terminal.

5. The static random access memory of claim 3, wherein: the input side division selector is connected in series between the preset input portions.

6. The SRAM of claim 4, wherein: the output side division selector is connected in series between the preset output parts.

7. The static random access memory of claim 1, wherein:

the serial input is based on a preset clock signal, so that input data in the input portions connected in series is shifted from one input portion to another input portion, thereby inputting the input data to each of the input portions connected in series.

8. The static random access memory of claim 1, wherein:

the serial output shifts the output data held by each of the output sections connected in series based on a preset clock signal, so that the output data in the output sections connected in series is shifted from one output section to another output section.

9. The static random access memory of claim 1, wherein:

the input section includes an input side selector that selects one of the other input sections and the external input terminal connected in series as a connection target of the input side,

the output unit includes an output-side selector that selects one of the other output units and the external output terminal connected in series as a connection destination on the output side.

10. A static random access memory, comprising:

a cell array having a plurality of memory cells arranged in rows and columns; and

an input-output circuit having a plurality of input-output sections, an external input terminal, and an external output terminal, the input-output section including: an input unit that holds input data to be input and outputs the input data to the storage unit; and an output unit that holds and outputs the output data output from the storage unit;

the input unit includes:

a first input-side selector that selects one of the other input units and the external input terminal connected in series as a connection destination of the input side; and

a first output-side selector that selects one of the memory cell and the other input units connected in series as a connection destination on an output side;

the output unit includes:

a second input-side selector that selects one of the storage unit and the other output units connected in series as a connection destination of the input side; and

a second output side selector that selects one of the other output units and the external output terminals connected in series as a connection destination on an output side;

in the input-output circuit,

an input-side division selector provided between the input portions connected in series and the preset input portions, one end of the input-side division selector being connected to the input portions, and the other end of the input-side division selector being connected to the other input portion or an external input terminal;

an output side division selector is provided between the preset output parts and among the output parts connected in series, one end of the output side division selector is connected to the output part, and the other end of the output side division selector is connected to the other output part or an external output terminal.

11. The sram of claim 10, wherein the input side division selector is connected in series between predetermined ones of the input sections.

12. The sram of claim 10, wherein the output side division selector is connected in series between the predetermined output portions.

Technical Field

The present invention relates to a static random access memory.

Background

A Static Random access memory (sram), which is one of volatile semiconductor memories, is used for devices requiring high speed and low power consumption because of its high-speed operation and low power consumption.

A Static Random Access Memory (SRAM) outputs data corresponding to the number of output bits in parallel from the viewpoint of high speed. For example, in a 32-bit SRAM, 32 bits are required for an input terminal and 32 bits are required for an output terminal, 64 external terminals of the SRAM are required to transfer 64 bits of data in total, and 64 data lines (wirings for connecting the SRAM and external elements) connected to the external terminals must be arranged in an integrated circuit. High-speed reading and writing can be performed by outputting each bit of data in parallel, but a large area is required for a data line in an integrated circuit including an SRAM.

In addition, in some cases, an instance (instance) of the SRAM is arranged to be horizontally long in accordance with the arrangement condition of the integrated circuit. In such a case, the lateral length may reach the order of millimeter, and when each bit of data is output in parallel, the occupied area of the data line further increases.

On the other hand, in a device having a low demand for high speed of the SRAM, the performance may be excessive due to the high speed of the parallel output, and even in such a case, the data line requires a large area due to the parallel output.

Disclosure of Invention

The present invention has been made in view of the above circumstances, and an object thereof is to provide an SRAM, a semiconductor integrated circuit, and an L CD driver capable of reducing the number of data lines required for input and output.

The present invention provides an SRAM, comprising: a cell array having a plurality of memory cells arranged in rows and columns; and an input/output circuit having a plurality of input/output sections, an external input terminal, and an external output terminal, the input/output section including: an input unit that holds input data to be input and outputs the input data to the storage unit, thereby writing the input data to the storage unit; and an output unit that holds output data output from the storage unit and outputs the output data, thereby reading the output data, wherein the input data is serially input to the input units by serially connecting the input units, and the output data held by the output units is serially output by serially connecting the output units.

According to the above configuration, the input/output unit for reading and writing data provided for a cell array having a plurality of memory cells arranged in rows and columns includes: an input unit that writes input data into the storage unit by holding the input data and outputting the input data to the storage unit; and an output unit that holds the output data output from the storage unit and outputs the output data, thereby reading the output data. Further, since the input units are connected in series, input data is input to the input units in series, and since the output units are connected in series, output data held by the output units is output in series. Therefore, when input data is input to the input portions of the input/output portions for writing data into the memory cells, the input data can be input in series to the input portions connected in series. Since data can be input to the respective input units connected in series, for example, from the input unit at one end of the series connection, the number of data lines required for input can be reduced as compared with a case where data is input in parallel to the input units of the respective input/output units.

In addition, when the output data is output from the output unit of each input/output unit in order to read the output data from the memory cell, the output data can be output in series from each output unit connected in series. Since data can be output from each output unit connected in series, for example, from the output unit at one end of the series connection, the number of data lines required for output can be reduced as compared with a case where data is output in parallel from the output units of the input/output units.

For example, when the input/output unit has 32 bits, 32 data lines are required for parallel output. However, when the input/output unit is divided into 4 parts (32 bits in units of 8 bits), serial output can be performed in units of 8 bits, and thus 4 data lines are required for data output. Therefore, the area required for the data line can be effectively reduced.

In the SRAM, the input unit may include an output-side selector that selects one of the memory cell and the other input units connected in series as a connection destination of an output side, and the output unit may include an input-side selector that selects one of the memory cell and the other output units connected in series as a connection destination of an input side.

According to the above configuration, since the input unit includes the output-side selector that selects one of the memory cell and the other input units connected in series as the connection destination on the output side, it is possible to write the input data into the memory cell by selecting the memory cell as the connection destination on the output side of the input unit, and it is possible to connect the input units in series by selecting the other input units connected in series as the connection destination on the output side of the input unit. Further, since the output unit includes the input-side selector that selects one of the storage unit and the other output units connected in series as the connection destination of the input side, the output data can be read from the storage unit by selecting the storage unit as the connection destination of the input side of the output unit, and the output units can be connected in series by selecting the other output units connected in series as the connection destination of the input side of the output unit.

In the SRAM, the input/output circuit may include input-side division selectors connected to the input units at one ends thereof and connected to the other input unit or an external input terminal at the other ends thereof, among the input units connected in series and between the preset input units.

According to the above configuration, since the input-side division selector having one end connected to the input portion and the other end connected to the other input portion or the external input terminal is provided among the input portions connected in series and between the preset input portions, the series connection state of the input portions can be changed. That is, by selecting the input units, the preset input units can be connected in series. Further, by selecting the external input terminal as a connection destination, the input units connected in series can be divided between the preset input units. Therefore, the series connection state of the input units connected in series can be divided.

In the SRAM, the input/output circuit may include an output side division selector having one end connected to the output unit and the other end connected to the other output unit or an external output terminal, the output unit being connected in series, and the output side division selector being provided between the preset output units.

According to the above configuration, since the output-side division selector that selects one of the output unit and the external output terminal as the connection destination of the output side is provided between the preset output units among the output units connected in series, the series connection state of the output units can be changed. That is, by selecting the output units as the connection targets, the preset output units can be connected in series. Further, by selecting the external output terminal as the connection target, the output units connected in series can be divided between the preset output units. Therefore, the series connection state of the output units connected in series can be divided.

In the SRAM, the serial input may shift input data in the input sections connected in series from one input section to another input section based on a preset clock signal, thereby inputting the input data to each of the input sections connected in series.

According to the above configuration, the input data can be stored in the serially connected input units by shifting the input data in the serially connected input units from one input unit to another input unit based on a preset clock signal and storing the input data in the serially connected input units. Therefore, the number of data lines can be reduced, and the area required for the data lines can be effectively reduced.

In the SRAM, the series output may shift the output data held by the output units connected in series based on a predetermined clock signal, so that the output data in the output units connected in series is shifted from one output unit to another output unit.

According to the configuration as described above, the output data in the output sections connected in series is shifted from one of the output sections to the other based on the preset clock signal, whereby the output data can be output from each of the output sections connected in series. Therefore, the number of data lines can be reduced, and the area required for the data lines can be effectively reduced.

In the SRAM, the input unit may include an input-side selector that selects one of the other input units and the external input terminals connected in series as a connection destination of the input side, and the output unit may include an output-side selector that selects one of the other output units and the external output terminals connected in series as a connection destination of the output side.

According to the above configuration, the input unit includes the input-side selector that selects one of the other input units and the external input terminal connected in series as the input-side connection destination. Therefore, if another input unit connected in series is selected as a connection destination on the input side, the input units can be connected in series, and if an external input terminal is selected as a connection destination, input data can be directly input to each input unit (parallel input). The output unit further includes an output-side selector that selects one of the other output units and the external output terminal connected in series as a connection destination on the output side. Therefore, if another output unit connected in series is selected as a connection destination on the output side, the output units can be connected in series, and if an external output terminal is selected as a connection destination, the output data can be directly output from each output unit (parallel output).

The present invention also provides an SRAM, comprising: a cell array having a plurality of memory cells arranged in rows and columns; and an input/output circuit having a plurality of input/output sections, an external input terminal, and an external output terminal, the input/output section including: an input unit that holds input data to be input and outputs the input data to the storage unit; and an output unit that holds and outputs the output data output from the storage unit, the input unit including: a first input-side selector that selects one of the other input units and the external input terminal connected in series as a connection destination of the input side; and a first output-side selector that selects one of the memory cell and the other input units connected in series as a connection destination on an output side, the output unit including: a second input-side selector that selects one of the storage unit and the other output units connected in series as a connection destination of the input side; and a second output-side selector that selects one of the other output sections and the external output terminals connected in series as a connection destination of the output side, wherein the input-output circuit includes, among the input sections connected in series and between the preset input sections, an input-side division selector having one end connected to the input section and the other end connected to the other input section or the external input terminal. And an output side division selector having one end connected to the output section and the other end connected to another output section or an external output terminal, among the output sections connected in series and between the preset output sections. .

According to the above configuration, when input data is input to the input unit, the external input terminal is selected by the first input-side selector, whereby parallel input can be performed. When input data is input to the input units, the input units can be connected in series and the input data can be input to the input units in series by selecting another input unit connected in series in the first input-side selector and selecting another input unit connected in series in the first output-side selector. Further, by selecting the storage cell in the first output side selector, the input data can be output to the storage cell and written.

Further, by selecting the storage unit in the second input-side selector, the output data can be output from the storage unit to the output section. Further, by selecting another output unit connected in series in the second input-side selector and selecting another output unit connected in series in the second output-side selector, it is possible to connect the output units in series and output the output data from the output units in series. In addition, by selecting the external output terminal in the second output side selector, parallel output can be performed.

Further, the input section is connected to one end of an input-side division selector having one end connected to the input section and the other end connected to another input section or an external input terminal, among the input sections connected in series and between the preset input sections, so that the series connection state of the input sections can be changed. That is, by selecting the input units, the preset input units can be connected in series. Further, by selecting the external input terminal as a connection destination, the input units connected in series can be divided between the preset input units. Further, since the output section is connected to one end of the output-side division selector and the other end of the output-side division selector is connected to another output section or an external output terminal, the series connection state of the output sections can be changed. That is, by selecting the output units as the connection targets, the preset output units can be connected in series. Further, by selecting the external output terminal as the connection target, the output units connected in series can be divided between the preset output units.

The invention also provides a semiconductor integrated circuit comprising the SRAM.

The invention also provides an L CD driver including the semiconductor integrated circuit.

Effects of the invention

According to the present invention, the number of data lines required for input/output can be reduced.

Drawings

Fig. 1 is a diagram showing a schematic configuration of an SRAM according to an embodiment of the present invention.

Fig. 2 is a diagram showing an example of the structure of an SRAM according to an embodiment of the present invention.

Fig. 3 is a diagram showing a configuration example of an input/output circuit according to an embodiment of the present invention.

Fig. 4 is a diagram showing a configuration example of an input unit according to an embodiment of the present invention.

Fig. 5 is a diagram showing a configuration example of an output unit according to an embodiment of the present invention.

Fig. 6 is a diagram showing a parallel input/output pattern of the input/output circuit according to the embodiment of the present invention.

Fig. 7 is a diagram showing a serial input/output pattern (with division) of the input/output circuit according to the embodiment of the present invention.

Fig. 8 is a diagram showing a serial input/output pattern (no division) of the input/output circuit according to the embodiment of the present invention.

Fig. 9 is a diagram showing a comparison of occupied areas of data lines required for respective operation modes of the input-output circuit according to the embodiment of the present invention.

Fig. 10 is a diagram for explaining an operation of a series output of the input/output circuit according to the embodiment of the present invention.

Fig. 11 is a diagram for explaining an operation of a serial input of the input/output circuit according to the embodiment of the present invention.

Description of the reference numerals

A: first input terminal

B: second input terminal

C: first output terminal

CA: cell array

CB: control block

C L control part

D: second output terminal

E: first input terminal

F: second input terminal

G: first output terminal

H: second output terminal

I: input unit

IDS: input side division selector

IN 1-IN 10: inverter with a capacitor having a capacitor element

IO: input/output circuit

IOCK: clock signal

IOS: selector device

IOU: input/output unit

IS1, IS 2: input side selector

MC: memory cell

O: output unit

OS1, OS 2: output side selector

ODS: output side division selector

P L1, P L2 latches

S L1, S L2 latch

And (3) SI: SRAM example

TG 1-TG 4: transmission gate

TG 6-TG 9: transmission gate

WD: word line driver

Detailed Description

Hereinafter, an embodiment of a Static Random Access Memory (SRAM), a semiconductor integrated circuit, and an L CD drive according to the present invention will be described with reference to the drawings.

The SRAM in the present embodiment is provided in a semiconductor integrated circuit, and is provided in a device such as an L CD drive, and the device having the SRAM mounted thereon is not limited to the L CD drive as long as it is a device having a low high-speed performance required for the SRAM.

Fig. 1 is a diagram showing a structure of an SRAM according to an embodiment of the present invention, a plurality of SRAM instances SI are provided in the SRAM, the SRAM instances SI being unit elements constituting the SRAM, and the SRAM having a capacity necessary for a system (semiconductor integrated circuit) is configured by providing the plurality of SRAM instances SI, the SRAM instances SI can take various shapes as shown in fig. 2, the SRAM instances SI are L type, 2MAT type, 4MAT type, and the like, as shown in fig. 2, and fig. 1 illustrates a case where the SRAM instances SI is 2MAT type.

As shown in fig. 1, the SRAM example SI includes a cell array CA, a word line driver WD, and an input/output circuit IO., and the other type of SRAM example SI also includes a cell array CA, a word line driver WD, and an input/output circuit IO., and each SRAM example SI is provided with a control unit C L that controls the SRAM example SI, and various processes described later with a control block CB. that controls the whole SRAM are controlled by the control unit C L or the control block CB, or signals can be directly input from the outside to each terminal to control the SRAM example SI.

The memory cell array CA includes a plurality of memory cells MC. arranged in rows and columns, each memory cell MC being a flip-flop and capable of holding data, and the memory cell MC may be, for example, a CMOS type, a high resistance load type, a TFT load type, or the like, when the memory cells MC are arranged in rows 0 to m and columns 0 to n in the column direction, (m +1) × (n +1) memory cells MC. are arranged in the cell array CA, word lines are provided in the cell array CA in correspondence with the rows, bit lines are provided in correspondence with the columns, the word lines are connected to the memory cells MC provided in the corresponding rows, the bit lines are connected to the memory cells MC provided in the corresponding columns, the word lines are connected to word line drivers, the bit lines are connected to input/output circuits IO, the word lines are provided with (m +1) in correspondence with the rows of the memory cells MC, the bit lines are bit line pairs (BT) and/bit line (BB), the bit lines are provided in correspondence with the Bar bit lines, and the memory cells MC can read and write data to the memory cell array MC, and the bit line pair (BB) can be provided as long as the structure is not limited to the memory cell array MC.

By setting the word line to High (High level), reading and writing can be performed with respect to the memory cell MC in the corresponding row. When the word line is High, the memory cell MC in the corresponding row is activated, the stored data is output (read) on the bit line, and the data is output (written) on the bit line by the input/output circuit IO.

For example, in the case of data of High (1), the bit line is High, the/bit line is L ow, in the case of data of L ow (0), the bit line is L ow, and the/bit line is High, and in the case of data reading, the bit line and/or bit line is input to a differential sense amplifier, which of the bit line and/or bit line is High is determined, and High or L ow. is output to the input/output circuit IO.

In the case of data writing, data output from the input/output circuit IO is input to the write amplifier, and the write amplifier outputs data to the bit line and/or the bit line based on the input data (High or L ow).

In this way, the memory cells MC in the predetermined row corresponding to the word line are activated, and data is read from and written to the corresponding column by the bit line, so that data can be read from and written to the predetermined memory cells MC arranged in rows and columns. For example, when each memory cell MC in the first row is activated by the word line in the first row and data is read from the bit line in the 10 th column, data is read from the memory cell MC arranged in the 10 th column in the first row.

The word line driver WD activates the word lines of the corresponding row in accordance with the supplied address signal. For example, word line driver WD activates a word line by bringing the word line in the corresponding row into a High state. As a result, each memory cell MC in the corresponding row is activated, and data can be read from and written to each activated memory cell MC.

The input/output circuit IO reads and writes data from and into each memory cell MC of the cell array CA. The input/output circuits IO are connected to the respective bit lines. As shown in fig. 3, the input/output circuit IO has a plurality of input/output units IOU. In the input/output circuit IO shown in fig. 3, for example, a configuration including 8 input/output units IOU (8 bits) is adopted. In FIG. 3, the parallel input terminals inputted from the input/output units IOU are shown as DI [0] to DI [7], the parallel output terminals outputted from the input/output units IOU are shown as Q [0] to Q [7], the series input terminals inputted to the input units I connected in series are shown as SI [0] and SI [1], and the series output terminals outputted from the output units O connected in series are shown as SO [0] and SO [1 ]. Note that the method of assigning the bit number to the SRAM1 may be set not only in the above-described manner. For example, in the circuit shown in FIG. 3, even bits (e.g., DI [0], DI [2], DI [4 ]. cndot.) and odd bits (e.g., DI [1], DI [3], DI [5 ]. cndot.) may be divided and arranged. Thus, in fig. 3, the input unit I and the output unit O can hold and input/output 8-bit information. The configuration of the input/output circuit IO (the number of input/output units IOU provided, etc.) is not limited to the configuration of fig. 3. In the input/output circuit IO shown in fig. 3, the input/output unit IOU is divided into 4 blocks, for example, and the serial connection state can be changed by selectors (IDS, ODS), and the positions and the number of blocks are not limited to the configuration shown in fig. 3.

The input/output unit IOU is provided with 1 for a plurality of bit lines, for example. For example, 1 input/output unit IOU is provided every 4 bit lines (every 4 columns). The input/output unit IOU can be connected to a plurality of bit lines via a bit line selector, for example, and can select one of the plurality of bit lines to be connected to 1 input/output unit IOU. That is, each bit line is connected to a bit line selector via a sense amplifier/write amplifier, and a bit line (column) selected by the bit line selector is connected to the input/output unit IOU.

As shown in fig. 3, the input/output unit IOU includes an input unit I for writing data into the memory cell MC, an output unit O for reading data from the memory cell MC, and a selector IOS. The input/output units IOU have the same configuration, and are configured by arranging the input/output units IOU and appropriately connecting terminals (terminals relating to input and output of the input/output units IOU, for example, terminals a to f).

The input unit I holds input data to be input and outputs the input data to the memory cell MC, thereby writing the input data to the memory cell MC. Since the input units I are connected in series, input data is input to the input units I in series. The input unit I has a flip-flop (FF) configuration and has a 2-input-2-output configuration. That IS, the input unit I includes an input side selector (first input side selector) IS1 for selecting an input side connection destination and an output side selector (first output side selector) OS1 for selecting an output side connection destination, and IS configured to have a 2-input-2-output.

Specifically, the input section I IS the configuration shown IN fig. 4, the configuration of fig. 4 IS only an example, and IS not limited to this configuration, as shown IN fig. 4, IN the input section I, an input side selector IS1 that selects one of a first input terminal a and a second input terminal B IS connected to a latch P L, and a latch P L IS connected to an output side selector OS1, further, the output side selector OS1 IS connected to a first output terminal C via an inverter (inverter) IN5, and IS connected to a second output terminal D via a latch S L, the first input terminal a IS connected to a parallel input terminal, the second input terminal B IS connected to the other input section I connected IN series, the first output terminal C IS connected to a memory cell MC (write amplifier), the second output terminal D IS connected to the other input section I connected IN series, as described later, the input side selector IS1 selects the other input section I connected to the parallel input terminal (external input terminal) as an input side, the input side selector IS connected to the latch IN via an inverter P8672, and the input side selector IS connected to an inverter 2, and the feedback gate TG 72, the input side selector IS connected to an inverter 2, and the input side selector IN2, and the feedback gate TG 72 connected to the latch P8672, and the input side selector IS connected to the latch P8672, and the input side selector IN2, and the feedback gate 2 connected to the latch P2, wherein the input side selector IS connected to the same as an inverter 2, and the input side selector IS connected to the input side selector IN 2.

When the clock signal IOCK IS High (when the latch P L takes IN data and the latch S L11 holds data), the transfer gate TG L and the transfer gate TG L are IN a conductive state, and the transfer gate TG L are IN a non-conductive state), when the clock signal IOCK IS L2 ow (when the latch P L holds data and the latch S L takes IN data), the transfer gate TG L and the transfer gate TG L are IN a non-conductive state, the output of the latch P L IS IN a conductive state, that IS, when the clock signal IOCK IS High, the output of the latch P L IS output from the input side of the input side selector IS L (i.e., when the latch P L holds data and the latch S L takes IN data), the transfer gate TG L and the transfer gate TG L are output state, that IS output from the latch P L to the output side of the latch S L, when the clock signal IOCK IS input to the input terminal of the latch S L, the output terminal of the latch P L, the latch P L IS output terminal of the latch S L, when the output of the latch P L IS output terminal C, the latch P L IS output of the output terminal C, when the latch S72 IS output of the latch S72C, the output terminal C, the output of the latch S72C, and the output terminal C, when the output of the latch S72C, the output terminal C, when the output of the latch S72 IS selected by the latch S72C, the first output terminal C, the latch S72C, the output terminal C, and the second output terminal C, the output terminal C, and the output terminal of the second output terminal C, the output terminal C, and the output terminal of the output.

In the configuration of the input unit I shown in fig. 4, the case where the input signal is output without being inverted is exemplified, but the inverted output may be performed by another configuration connected to the input unit I.

The first input terminal a of the input unit I is connected to the terminal c of the input/output unit IOU, the second input terminal B is connected to the terminal a of the input/output unit IOU, and the second output terminal D is connected to the terminal f of the input/output unit IOU. In addition, the first output terminal C is connected to the selector IOS.

The output unit O holds the output data output from the memory cell MC, and reads the output data by outputting the output data. Since the output units O are connected in series, the output data held by the output units O are output in series. The output unit O has a flip-flop (FF) structure and has a 2-input-2-output structure. That IS, the input unit I includes an input side selector (second input side selector) IS2 for selecting an input side connection destination and an output side selector (second output side selector) OS2 for selecting an output side connection destination, and IS configured to have a 2-input-2-output.

Specifically, the output section O IS the configuration shown IN fig. 5, the configuration of fig. 5 IS only an example, and the configuration IS not limited to this configuration, as shown IN fig. 5, IN the input section O, the input side selector IS2 that selects one of the first input terminal E and the second input terminal F IS connected to the latch P L2, and the latch P L IS connected to the output side selector OS2, further, the output side selector OS2 IS connected to the first output terminal G via the inverter IN10, and IS connected to the second output terminal H via the latch S L, the first input terminal E IS connected to the memory cell MC (sense amplifier), the second input terminal F IS connected to the other output section O connected IN series, the first output terminal G IS connected to the parallel output terminal, the second output terminal H IS connected to the other output section O connected IN series, as described later, as described, the input side selector IS2 selects one of the memory cell MC and the other output section O connected IN series as the input side as the connection destination of the input side, as the inverter IN, as described later, the output side selector IS connected to the inverter IN via the inverter IN7, and the feedback gate TG7, the feedback gate 7 IS connected to the latch P8672, the inverter IN7, the input side selector IN7, and the feedback gate 7 connected to the inverter IN7, the inverter 8472, and the feedback gate 7 connected to the inverter IN7, and the feedback gate 7, and the inverter IN7 connected to the same gate TG7, and the feedback gate 7 connected to the latch P7.

When the clock signal IOCK IS High (when the latch P L takes IN data and the latch S L12 holds data), the transfer gate TG L and the transfer gate TG L are IN a conductive state, and the transfer gate TG L are IN a non-conductive state), when the clock signal IOCK IS L2 ow (when the latch P L holds data and the latch S L takes IN data), the transfer gate TG L and the transfer gate TG L are IN a non-conductive state, the output of the latch P L IS IN a conductive state, that IS, when the clock signal IOCK IS High, the output of the latch P L IS output from the input side of the input side selector IS L (i.e., when the latch P L holds data and the latch S L takes IN data), the transfer gate TG L and the transfer gate TG L are output from the output side of the latch P L to the output side of the latch S L, when the clock signal IOCK IS input to the input side selector IS output from the input terminal of the input side selector IS a first input terminal of the input/output terminal of the latch S L, when the latch P L IS output terminal H, the output terminal of the latch P L, the latch P L IS output terminal H, when the output terminal H, the output terminal H IS output of the latch P L, when the latch P L IS output terminal H, when the output terminal H, the latch S L IS output terminal H, the output terminal H, when the output terminal H IS output terminal H, when the output terminal H IS selected by the output terminal H, when the output terminal H IS selected by.

In the configuration of the output unit O shown in fig. 5, the case where the input signal is output without being inverted is exemplified, but the inverted output may be performed by another configuration to which the output unit O is connected.

The second input terminal F of the output unit O is connected to the terminal b of the input/output unit IOU, the first output terminal G is connected to the terminal d of the input/output unit IOU, and the second output terminal H is connected to the terminal e of the input/output unit IOU. In addition, the first input terminal E is connected to the selector IOS.

The selector IOS selects one of the input unit I and the output unit O as a connection destination on the memory cell MC side. That is, the selector IOS selectively connects the first output terminal C of the input section I and the first input terminal E of the output section O. The selected terminal is connected to the memory cell MC side, that is, to a bit line (column) selected by the bit line selector. Specifically, when the first output terminal C of the input unit I is selected by the selector IOS, the bit line selected by the bit line selector is connected to the corresponding write amplifier. When the first input terminal E of the output unit O is selected by the selector IOS, the bit line selected by the bit line selector is connected to the corresponding sense amplifier.

In this way, the input/output circuit IO is provided with a plurality of input/output units IOU. The input/output units IOU are connected to each other. Specifically, the input units I of the preset input/output units IOU are connected in series (cascade connection), and the output units O of the preset input/output units IOU are connected in series (cascade connection). That is, at least two or more input/output units IOU among the input/output units IOU included in the input/output circuit IO are connected in series (cascade connection). The larger the number of input/output units IOU connected in series, the more the number of external terminals (the number of data lines connected to the external terminals) can be suppressed by the series input and the series output. In the present embodiment, as shown in fig. 3, 8 input/output units IOU included in the input/output circuit IO are connected in series. That is, the input units I of the input/output units IOU are connected in series, and the output units O of the input/output units IOU are connected in series.

The input units I are connected in series by connecting the output (second output terminal D) of the input unit I to the input (second input terminal B) of another input unit I (terminal f to terminal a). Specifically, the output (second output terminal D) of the input unit I of the input/output unit IOU connected in series is connected to the input (second input terminal B) of the input unit I of another input/output unit IOU so as to be connected in series. The input (second input terminal B) of the input unit I of the input/output unit IOU is connected to a series input terminal as an external input terminal. The output (second output terminal D) of the output unit O of the other input/output unit IOU is, for example, off (open). In this way, since the input units I are connected in series and the D flip-flops can be connected in series (cascade connection), the input data in the series form input from the series input terminal of the input unit I can be shifted (shift) to another input unit I (flip-flop) based on the preset clock signal IOCK, and thus the data can be input to each input unit I.

In the example of fig. 3, the first input terminal a (terminal c) of each input unit I is connected to a parallel input terminal as an external input terminal, and as described later, one of the series input and the parallel input can be selected by the OPT terminal, but the parallel input terminal may not be provided when the parallel input is not necessary, or a data line for connection to the outside may not be connected even when the parallel input terminal is provided.

The output units O are connected in series by connecting the output (second output terminal H) of the output unit O and the input (second input terminal F) of another output unit O (terminal e and terminal b). Specifically, the output (second output terminal H) of the output unit O of the input/output unit IOU connected in series is connected to the input (second input terminal F) of the output unit O of another input/output unit IOU, and the next stage and thereafter are connected in series in the same manner. The input (second input terminal F) of the output unit O of the input/output unit IOU is, for example, off (open). The output (second output terminal H) of the output unit O of the other input/output unit IOU is connected to a series output terminal as an external output terminal. Since the output units O are connected in series in this way, the D flip-flops can be connected in series (cascade connection), and therefore, the output data held by each of the output units O connected in series can be shifted based on the predetermined clock signal IOCK, and the output data in the series form can be output from the output units O connected in series, whereby data can be input to each of the output units O.

In the example of fig. 3, the first input terminal E (terminal d) of each output unit O is connected to a parallel output terminal as an external input terminal. As will be described later, one of the series output and the parallel output can be selected by the OPT terminal, but when the parallel output is not necessary, the parallel output terminal may not be provided, or even if the parallel output terminal is provided, the data line for external connection may not be connected.

Further, as shown in fig. 3, the series connection state can be divided by using division selectors (an input side division selector IDS and an output side division selector ODS). Specifically, in the input-output circuit IO, an input-side division selector IDS is provided in input sections I connected in series and between preset input sections I, one end of the input-side division selector IDS is connected to an input section I, and the other end of the input-side division selector IDS is connected to another input section I or an external input terminal, and further, in the input-output circuit IO, an output-side division selector ODS is provided in output sections O connected in series and between preset output sections O, one end of the output-side division selector ODS is connected to an output section O, and the other end of the output-side division selector ODS is connected to another output section O or an external output terminal. Although fig. 3 shows an example of a configuration using a division selector, a configuration not using a division selector may be employed. Further, the position where the division selector is provided is not limited to the position of fig. 3.

The input-side division selector IDS is used to change a connection state between two input units I set in advance in the input units I connected in series, and divides the series connection state of the input units I connected in series between the two input units I. That is, the input-side division selector IDS is provided between the output of the input section I (second output terminal D) and the input of another input section I (second input terminal B) (terminal f and terminal a). Specifically, the input-side division selector IDS is connected to the output (second output terminal D) of the input section I and the external input terminal (series input terminal) in a selectable manner, and connects a selected one of them to the input (second input terminal B) of the other input section I. The selection state of the input side division selector IDS is controlled by an OPT terminal described later.

In the example of fig. 3, in the input-side division selector IDS, by connecting the output (second output terminal D) of an input section I to the input (second input terminal B) of another input section I, all 8 input sections I are connected in series, and data can be input from the series input terminal (SI [0] of fig. 3) to each of the 8 input sections I. In the input-side division selector IDS, an external input terminal (serial input terminal) is connected to an input (second input terminal B) of another input unit I, and data can be input from the serial input terminal (SI [0] or SI [1] in fig. 3) to each of the 4 input units I by connecting the serial input terminals to the inputs (second input terminals B) of the other input units I in series for every 4 input units I. That is, in the example of fig. 3, by controlling the selection state of the input side division selector IDS, it is possible to change between a state in which 8 input sections I are connected in series and a state in which 4 input sections I are connected in series.

The output-side division selector ODS is provided for changing a connection state between two output units O set in advance among the output units O connected in series, and divides the series connection state of the output units O connected in series between the two output units O. That is, the output side division selector ODS is provided between the output of the output section O (second output terminal H) and the input of another output section O (second input terminal F) (terminals e and b). Specifically, the output side division selector ODS connects the input (second input terminal F) of the output section O and the external output terminal (series output terminal) in a selectable manner, and connects the selected one of them to the output (second output terminal H) of the other output section O. The selected state of the output side segment selector ODS is controlled by an OPT terminal described later.

In the example of fig. 3, the output-side division selector ODS connects the output (second output terminal H) of the output unit O and the input (second input terminal F) of another output unit O, and connects all 8 output units O in series, SO that data can be output from the series input terminal (SO [1] of fig. 3) and from each output unit O provided with 8 output units. In addition, the output side division selector ODS is capable of outputting data from the serial output terminal (SO 0 or SO 1 in FIG. 3) and each of the 4 output units O by connecting the external output terminal (serial output terminal) to the input (second input terminal F) of the other output unit O and connecting the serial output terminals in series for each of the 4 output units O. That is, in the example of fig. 3, by controlling the selected state of the output side division selector ODS, it is possible to change between a state in which 8 output sections O are connected in series and a state in which every 4 output sections O are connected in series.

The input/output circuit IO is provided with a selection terminal (hereinafter referred to as "OPT terminal"). The OPT terminal sets the selection states of the selectors (IS1, OS1, IS2, OS2) and the segment selectors (IDS, ODS) of the input unit I and the output unit O. In the example of fig. 3, the input side selector IS1 and the output side selector OS1 of the input section I, the input side selector IS2 and the output side selector OS2 of the output section O, the input side division selector IDS, and the output side division selector ODS are controlled by the OPT terminal. The number of bits of the OPT terminal is set according to the number of operation modes of the input/output circuit IO. In the present embodiment, 2-bit data (00, 01, 11) can be set to the OPT terminal. The input/output circuit IO is in a parallel input/output mode (described later) when 00 is input from the OPT terminal, in a series input/output mode (described later) when 01 is input from the OPT terminal, and in a series input/output mode (described later) when 11 is input from the OPT terminal. In addition, in the present embodiment, as shown in fig. 3, since 1 input-side division selector IDS and 1 output-side division selector ODS are provided each, the serially connected state can be divided into two parts with the division selectors (IDS, ODS) as boundaries. Therefore, the operation mode is 3 modes of a parallel input/output mode, a series input/output mode (with division), and a series input/output mode (without division). However, in the case where the input-side division selector IDS and the output-side division selector ODS are provided two or more each, the series connection state can be divided into two parts or 4 parts, for example. Therefore, the operation mode changes depending on the number of sets of the division selectors (IDS, ODS) (for example, a parallel input/output mode, a serial input/output mode (divided into two parts), a serial input/output mode (divided into 4 parts), a serial input/output mode (non-divided), and the like), and the number of bits of the OPT terminal is set so that each operation mode can be switched.

Next, a connection state of the input/output circuit IO in each operation mode will be described. The operation state refers to a parallel input/output mode, a series input/output mode (with division), and a series input/output mode (without division).

Fig. 6 is a diagram showing a connection state of the input/output circuit IO in the parallel input/output mode. The connection state in fig. 6 corresponds to the case where the OPT terminal indicates 00. In fig. 6, lines selected by the selectors (IS1, OS1, IS2, OS2, IDS, ODS) of the input unit I and the output unit O are indicated by solid lines, and unselected lines are indicated by broken lines. Which of the input and output is to be performed is set by the selector IOS. In the case of parallel input, data is directly input to each input unit I using the parallel input terminal. As shown in fig. 6, in input section I, parallel input terminals (DI [0] -DI [7]) are selected in input side selector IS1, and memory cell MC IS selected in output side selector OS 1. Therefore, data can be directly input to the input unit I from each parallel input terminal.

Thus, in the case of parallel input, the number of input sections I provided, i.e., 8 parallel input terminals (DI [0] -DI [7]) in FIG. 6, is used.

When parallel output is performed, data is directly output from each output unit O using the parallel output terminal. In fig. 6, lines selected by the selectors (IS1, OS1, IS2, OS2, IDS, ODS) of the input unit I and the output unit O are indicated by solid lines, and unselected lines are indicated by broken lines. As shown in fig. 6, in the output unit O, the memory cell MC IS selected in the input side selector IS2, and the parallel output terminals (Q0 to Q7) are selected in the output side selector OS 2. Therefore, data can be directly output from the parallel output terminals.

Thus, when parallel output is performed, the number of output units O provided, that is, 8 parallel output terminals (Q0-Q7) in FIG. 6 are used.

Fig. 7 is a diagram showing a connection state of the input/output circuit IO in the series input/output mode (with division). Fig. 7 shows connection states in a case where data is input to the input unit I and in a case where data is output from the output unit O. The connection state of fig. 7 corresponds to the case where the OPT terminal indicates 01. In fig. 7, lines selected by the selectors (IS1, OS1, IS2, OS2, IDS, ODS) of the input unit I and the output unit O are indicated by solid lines, and unselected lines are indicated by broken lines. In addition, the following is shown in the example of fig. 7: a serial input terminal (SI 1) is connected to another input unit (I) in an input-side division selector IDS, and an output unit (O) is connected to a serial output terminal (SO 0) in an output-side division selector ODS. Which of the input and output is to be performed is set by the selector IOS. When the serial input is performed, the input units I are connected in series, and data is input by the serial input method. As shown in fig. 7, among the input sections I, the other input sections I connected in series in the input side selector IS1 are selected, and the other input sections I connected in series in the output side selector OS1 are selected. Then, the input-side division selector IDS and the output-side division selector ODS divide the 8 input/output units IOU into two parts (4 input/output units IOU). Therefore, the input data can be input to the serial input terminals (SI 0-SI 1) by connecting the input sections I in series after division and inputting the input data to the other input section I by shifting the input data to the other input section I based on a predetermined clock signal IOCK for each divided unit.

Thus, when the serial input is performed (there is division), the number of divisions, that is, two serial input terminals (SI 0 to SI 1) in FIG. 7 are used.

When the serial output is performed, the output units O are connected in series, and data is output by the serial output method. As shown in fig. 7, among the output sections O, the other output sections O connected in series in the input side selector IS2 are selected, and the other output sections O connected in series in the output side selector OS2 are selected. Then, the input-side division selector IDS and the output-side division selector ODS divide the 8 input/output units IOU into two parts (4 input/output units IOU). Therefore, the output units O can be connected in series after division, and the output data held by the output units O connected in series can be shifted for each divided unit based on a predetermined clock signal IOCK, whereby the output data can be outputted from the series output terminals (SO 0-SO 1) of the output units O connected in series.

Thus, when the serial output is performed (there is division), the number of divisions, that is, two serial output terminals (SO 0-SO 1) in FIG. 7 are used.

Fig. 8 is a diagram showing a connection state of the input/output circuit IO in the series input/output mode (no division). Fig. 8 shows connection states in a case where data is input to the input unit I and in a case where data is output from the output unit O. The connection state of fig. 8 corresponds to the case of the OPT terminal representation 11. In fig. 8, lines selected by the selectors (IS1, OS1, IS2, OS2, IDS, ODS) of the input unit I and the output unit O are indicated by solid lines, and unselected lines are indicated by broken lines. In addition, the following is shown in the example of fig. 8: the input side division selector IDS has an input section I connected to another input section I, and the output side division selector ODS has an output section O connected to another output section O. Which of the input and output is to be performed is set by the selector IOS. When the serial input is performed, the input units I are connected in series, and data is input by the serial input method. As shown in fig. 8, among the input sections I, the other input sections I connected in series in the input side selector IS1 are selected, and the other input sections I connected in series in the output side selector OS1 are selected. Therefore, the input data can be input to the series input terminal (SI [0]) by connecting the input sections I in series, and the input data can be input to the input sections I connected in series by shifting the input data to another input section I based on the preset clock signal IOCK.

Thus, when a serial input (no division) is performed, 1 serial input terminal (SI [0]) is used.

When the serial output is performed, the output units O are connected in series, and data is output by the serial output method. As shown in fig. 8, among the output sections O, the other output sections O connected in series in the input side selector IS2 are selected, and the other output sections O connected in series in the output side selector OS2 are selected. Therefore, the output units O can be connected in series, and the output data held by the output units O connected in series can be shifted based on the preset clock signal IOCK, whereby the output data can be outputted from the series output terminal (SO 1) of the output units O connected in series.

Thus, when a series output (no division) is performed, 1 series output terminal (SO 1) is used.

In this way, the number of external terminals used differs depending on the operation mode. The external terminal is connected to a data line for data transmission to the outside. In a semiconductor integrated circuit including an SRAM, the data lines are arranged in a space other than the space occupied by the SRAM, and the larger the number of data lines, the larger the wiring area required. Therefore, the number of necessary external terminals can be suppressed in the series input/output mode (with division) or the series input/output mode (without division) as compared with the parallel input/output mode, and therefore the number of data lines can be suppressed. For example, fig. 9 is a diagram showing an area required for wiring. In fig. 9, the area occupied by the data lines necessary in the parallel input/output mode is compared with the area occupied by the data lines necessary in the series input/output mode (without division). In the parallel input-output mode, in the example of fig. 6, 8 parallel input terminals are required and 8 parallel output terminals are required, so 16 data lines in total are required. On the other hand, in the serial input-output mode (without division), in the example of fig. 8, 1 serial input terminal is required and 1 serial output terminal is required, so two data lines are required in total. That is, the occupied area of the data line in the series input/output mode (no division) can be 1/8 of the occupied area of the data line in the parallel input/output mode. In the present embodiment, the case where the number of input/output units IOU is 8 is described as an example, and the effect of reducing the area becomes remarkable with respect to the increase in the number of bits.

Next, an operation of the input/output circuit IO in the series input/output mode (no division) will be described. Fig. 10 is a diagram showing a serial output (Read), and fig. 11 is a diagram showing a serial input (Write). Fig. 10 and 11 correspond to the case where the input/output unit shown in fig. 3 and the like is set to 8 bits.

First, with reference to fig. 10, a description will be given of a case where a serial output (Read) IS performed, that IS, output data stored in each output section O IS output from a serial output terminal (SO [1 ]). when an OPT terminal IS input to 11 and output in series IS performed, first, output data output from a memory cell MC IS stored in each output section O in latches P L and S L, a first input terminal E IS selected in an input side selector IS2 of the output section O, output data output from a memory cell MC IS input to the first input terminal E of the output section O (selector IOS selects output section O side), when output in series IS performed, an operation for storing the output data output from the memory cell MC into each output section O IS performed (selector IOS selects output section O side) when output in series IS performed, an operation for storing the output data output from the memory cell MC into each output section O IS performed when the output data IS input to a first input side selector IS input to a second input side selector IS input from a memory cell MC, and the output section oc IS output from the first input to a second input terminal, and the second input to the output section O6326, when output data IS output from the first input to the second selector IS input side selector IS input to the output, the output section MC, the output section oc IS input to the output section oc, and the output section oc 2, the output section oc IS set when the output state, the first input to the second selector IS input to the output gate, the output gate IS input to the output gate, the output gate IS input gate, the output gate IS set when the output gate IS set, the output gate IS set when the output gate, the output gate IS set, the output gate IS set, the output gate IS set, the output gate IS set when the output gate, the output gate IS set, the output gate, the output state, the output gate IS set, the output gate, the.

When output data IS set to each output section O, a total of 8 output sections O are connected in series as shown in fig. 8 ("operation switching") when connected in series, the output of the output section O IS output from the series output terminal (SO 1) (data output of eighth bit) when connected in series, further, since the output of the output section O IS output from the series output terminal (SO 1), the operation for connecting in series the output sections O (operation of selecting the second input terminal F in the input side selector IS2 and selecting the second output terminal H in the output side selector OS2) IS set to each output section O according to the setting of the bit number, and IS controlled in the control block C L or CB when output data IS set to each output section O, then, in the state where the output sections O are connected in series, when #0 of the IOCK rises, the value of P2 of the output section O IS set by the latch C6754 or the control block CB, and when output data IS output from the output section O #0, the output data held by the latch P54 IS output data held by the series output section O2, the output data held by the output terminal O # 2 when output data IS output from the output terminal O2, the output data held by the series output section O2, the output data holding latch 82, the output data output section O2, the output data held by the output terminal O2, the output data output terminal P2, the output data held by the output section O laid down (output).

In this way, when the series output IS performed, first, the first input terminal E IS selected in the input side selector IS2 of the output unit O, the output unit O side IS selected in the selector IOS, the operation for storing the output data output from the memory cell MC in each output unit O IS performed, and then the operation IS switched to the operation for connecting the output units O in series (the operation for selecting the second input terminal F in the input side selector IS2 and the second output terminal H in the output side selector OS2) to output the output data in series.

The case of serial input (Write) will be described with reference to fig. 11, that IS, input data input from the serial input terminal IS input from the serial input terminal (SI [0]) to each input unit I connected in series, IOCK in fig. 11 IS input as a clock signal to each transfer gate TG 1-tg4 in the latches P L, S L of each input unit I, and when input to the OPT terminal 11 IS input in series, input data in the serial form IS input to the serial input terminal (SI [0]), input data in the serial form refers to data in which input data to be held to each input unit I are arranged in series, that IS, input data of the eighth bit to be written IS arranged in series to input data of the first bit, input from the serial input terminal (SI [0]) IS input, the OPT terminal IS set 11, 8 input units I are connected in series as shown in fig. 8, that, input units I are connected in series, that when input to the serial input, the operation for each input unit I IS connected in series (input side selector IS 25, output terminal IS selected by the OS, and the second input/output terminal IS/output selector C/output unit pc 3864 IS connected to the serial input/output stage, and the control unit cs IS selected by the second input/output terminal nos. 12, and the serial input/output unit cs, and the input/output unit cs 93C, and the input/output unit IS selected by the input/output unit cs 73, and the input/output unit cs, or OS, respectively connected to the input/output unit C/output unit 3, respectively, and the output unit 3, when.

When #0 of the IOCK rises in a state where input data of the eighth bit is input from the serial input terminal, the transmission gates TG1, TG4 of the input section I become a conductive state (the transmission gates TG2, TG3 are in a non-conductive state), and data of the eighth bit is output to the latch P L of the input section I, then, when #0 of the IOCK falls, the transmission gates TG1, TG4 become a non-conductive state, and the transmission gates TG2, TG3 become a conductive state, and thus input data of the eighth bit is output from the latch S L1 of the input section I, then, when #1 of the IOCK rises in a state where input data of the seventh bit is input from the serial input terminal (SI [0]), input data of the eighth bit is output to the latch P L1 of another input section I (shift), and input data of the seventh bit is output to the latch P L of the input section I, then, when input data of the IOCK #1 falls, input data of the eighth bit is output to the latch P L of another input section I (shift), and then, input data of the input section I is stored in the input section I631, and is shifted to the input section I632.

Specifically, when input data is input in series, the operation for outputting the input data stored in each input unit I to the memory cell MC (the operation for selecting the input unit I side in the output side selector OS1 of the input unit I (the operation for selecting the input unit I side in the selector IOS)) is set as input data to each input unit I, and then the control unit C L or the control block CB performs control.

In this way, when the serial input IS performed, first, the second input terminal B IS selected by the input-side selector IS1, the second output terminal D IS selected by the output-side selector OS1, the operation for connecting the input units I in series IS performed, and then the operation IS switched to the operation for outputting the input data stored in the input units I to the memory cell MC (the operation for selecting the first output terminal C by the output-side selector OS1 of the input unit I and the input unit I side by the selector IOS), and the serial input IS performed.

In this way, the writing of input data to the memory cell MC and the writing of output data held by the memory cell MC are performed by the serial input/output.

The SRAM in this embodiment is included in a semiconductor integrated circuit together with other circuits and mounted in a device, since high-speed performance is generally required of the SRAM, each data is output in parallel from an input-output circuit IO, however, in a device having a low requirement of high-speed performance, there is a case where it is not necessary to output each data in parallel from the SRAM, a device having a low requirement of high-speed performance is, for example, a L CD driver, when parallel output is performed, there is a case where the number of data lines for connection to the SRAM is increased and a large area is required for laying of the data lines, therefore, in a device having a low requirement of high-speed performance such as a L CD driver, by inputting and outputting data in series as described above, the number of data lines for connection to the SRAM can be suppressed, and therefore, the occupied area of the data lines can be suppressed, this point is that the total distance of the data lines is longer the more effectively the more the input-output bits is, in a L CD driver, in the case where RGB requires n bytes, it is necessary to input and output data lines of 3 × n bits, therefore, if parallel connection is performed in a parallel connection, the number of data lines is increased, the input-line length is effectively reduced, and thus, the data lines are connected in a non-parallel connection scheme, and thus, the input-output is possible to be performed by a non-input-output method, and thus, which is effectively suppressing the number of data lines is effectively suppressing the data lines in a configuration of the parallel connection of the data lines, and a configuration of the data lines is.

In the present embodiment, parallel connection and series connection can be selected by the OPT terminal. Therefore, the parallel connection and the series connection can be selected according to the specification of the mounted equipment. That is, the SRAM of the present embodiment has high versatility, and can be mounted by selecting an appropriate operation mode in accordance with a speed requirement, a wiring area requirement, and the like.

As described above, according to the SRAM, the semiconductor integrated circuit, and the L CD driver according to the present embodiment, in the input/output unit IOU for reading and writing data provided for the cell array CA having a plurality of memory cells MC arranged in rows and columns, the input unit I that holds input data to be input and outputs the input data to the memory cells MC to write the input data to the memory cells MC, and the output unit O that holds output data to be output from the memory cells MC to output the output data to read the output data are provided.

When the output data is output from the output units O of the input/output units IOU in order to read the output data from the memory cells MC, the output data can be output in series from the output units O connected in series. The output of data from the output units O connected in series can be performed from the output unit O at one end of the series connection, for example, and therefore, the number of data lines required for output can be reduced as compared with a case where data is output in parallel from the output units O of the input/output units.

For example, when the input/output unit IOU has 32 bits, 32 data lines are required for parallel output. However, when the input/output unit IOU is divided into 4 parts (32 bits in units of 8 bits), the serial output can be performed in units of 8 bits, and thus 4 data lines necessary for data output are provided. Therefore, the area required for the data line can be effectively reduced.

Further, since the input unit I includes the output-side selector OS1, and the output-side selector OS1 selects one of the memory cell MC and the other input units I connected in series as the connection destination on the output side, it is possible to write input data into the memory cell MC by selecting the memory cell MC as the connection destination on the output side of the input unit I, and it is possible to connect the input units I in series by selecting the other input units I connected in series as the connection destination on the output side of the input unit I. Further, since the output section O includes the input side selector IS2, and the input side selector IS2 selects one of the memory cell MC and the other output section O connected in series as the connection destination of the input side, it IS possible to read the output data from the memory cell MC by selecting the memory cell MC as the connection destination of the input side of the output section O, and it IS possible to connect the output sections O in series by selecting the other output section O connected in series as the connection destination of the input side of the output section O.

Further, among the input sections I connected in series and between the preset input sections I, there is an input side division selector IDS having one end connected to the input section I and the other end connected to another of the input section I or an external input terminal. Therefore, the serial connection state of the input unit I can be changed. That is, the preset input units I can be connected in series by selecting the input units I. Further, by selecting the series input terminal as a connection destination, the input units I connected in series can be divided between the preset input units I. Therefore, the series connection state of the input units I connected in series can be divided.

Further, among the output sections O connected in series and between the preset output sections O, there is an output-side division selector ODS having one end connected to the output section O and the other end connected to another of the output sections O or an external output terminal. Therefore, the series connection state of the output units O can be changed. That is, by selecting the output units O as the connection destination on the output side, the preset output units O can be connected in series. Further, by selecting the series output terminal as a connection destination, the output units O connected in series can be divided between the preset output units O. Therefore, the series connection state of the output units O connected in series can be divided.

Further, input data in the input sections I connected in series is shifted from one input section I to another based on a preset clock signal IOCK, whereby the input data can be stored in each input section I connected in series. Therefore, the number of data lines can be reduced, and the area required for the data lines can be effectively reduced.

Further, the output data in the output sections O connected in series is shifted from one output section O to another output section O based on the preset clock signal IOCK, whereby the output data can be output from each output section O connected in series. Therefore, the number of data lines can be reduced, and the area required for the data lines can be effectively reduced.

The input section I has an input side selector IS1, and the input side selector IS1 selects one of the other input section I and the parallel input terminal connected in series as a connection destination of the input side. Therefore, if another input unit I connected in series is selected as a connection destination on the input side, the input units I can be connected in series, and if a parallel input terminal is selected as a connection destination, input data can be directly input to each input unit I (parallel input). The output section O has an output-side selector OS2, and the output-side selector OS2 selects one of the other output section O and the parallel output terminal connected in series as a connection destination on the output side. Therefore, if another output unit O connected in series is selected as a connection destination on the output side, the output units O can be connected in series, and if a parallel output terminal is selected as a connection destination, the output data can be directly output from each output unit O (parallel output).

When input data IS input to the input unit I, the parallel input terminal IS1 IS selected as an input side selector (first input side selector), whereby parallel input IS possible. When input data IS input to the input unit I, the input unit I can be connected in series by selecting another input unit I connected in series in the input side selector (first input side selector) IS1 and selecting another input unit I connected in series in the output side selector (first output side selector) OS1, and the input data can be input to each input unit I in series. Further, the output-side selector (first output-side selector) OS1 selects the memory cell MC, and thereby input data can be output to the memory cell MC and written.

Further, by selecting the memory cell MC in the input side selector (second input side selector) IS2, the output data can be output from the memory cell MC to the output unit O. Further, by selecting another output section O connected in series in the input side selector (second input side selector) IS2 and selecting another output section O connected in series in the output side selector (second output side selector) OS2, the output sections O can be connected in series, and output data can be output from the output sections O in series. In addition, parallel output can be performed by selecting a parallel output terminal in the output side selector (second output side selector) OS 2.

Further, in the input sections I connected in series and between the preset input sections I, there is an input side division selector IDS having one end connected to the input section I and the other end connected to another input section I or an external input terminal, so the series connection state of the input sections I can be changed. That is, by selecting the input portions I, the preset input portions I can be connected in series. Further, by selecting the series input terminal as a connection destination, the input units I connected in series can be divided between the preset input units I. Further, among the output sections O connected in series and between the preset output sections O, there is an output side division selector ODS, one end of which is connected to the output section O and the other end of which is connected to another output section O or an external output terminal, so that the series connection state of the output sections O can be changed. That is, by selecting the output units O as the connection destination on the output side, the preset output units O can be connected in series. Further, by selecting the series output terminal as a connection destination, the output units O connected in series can be divided between the preset output units O.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.