阅读说明：本技术 储存单元 (Storage unit ) 是由 孙文堂 徐清祥 于 2020-01-08 设计创作，主要内容包括：本发明公开了一种储存单元包括选择电路、第一储存晶体管及第二储存晶体管。选择电路耦接于源极线及共同节点,选择电路可被导通以建立源极线及共同节点之间的电性连接,及被截止以阻断电性连接。第一储存晶体管的第一端耦接于共同节点,第一储存晶体管的第二端耦接于第一位线,而第一储存晶体管的控制端耦接于控制线。第二储存晶体管的第一端耦接于共同节点,第二储存晶体管的第二端耦接于第二位线,而第二储存晶体管的控制端耦接于控制线。第一储存晶体管及第二储存晶体管是二维的电荷捕捉装置或三维的电荷捕捉装置。(The invention discloses a storage unit which comprises a selection circuit, a first storage transistor and a second storage transistor. The selection circuit is coupled to the source line and the common node, and the selection circuit can be turned on to establish electrical connection between the source line and the common node and turned off to block the electrical connection. The first end of the first storage transistor is coupled to the common node, the second end of the first storage transistor is coupled to the first bit line, and the control end of the first storage transistor is coupled to the control line. The first end of the second storage transistor is coupled to the common node, the second end of the second storage transistor is coupled to the second bit line, and the control end of the second storage transistor is coupled to the control line. The first storage transistor and the second storage transistor are two-dimensional charge trapping devices or three-dimensional charge trapping devices.)

1. A storage unit, comprising:

a selection circuit coupled to a source line and a common node, and configured to be turned on to establish an electrical connection between the source line and the common node, and turned off to block the electrical connection;

a first storage transistor having a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a control terminal coupled to a control line; and

a second storage transistor having a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a control terminal coupled to the control line;

wherein the first storage transistor and the second storage transistor are two-dimensional charge trapping devices or three-dimensional charge trapping devices.

2. The storage unit of claim 1, wherein in a first write procedure of the registration operation:

the source line is at a source voltage;

the selection circuit is turned on;

the first bit line and the second bit line are at a reference voltage;

the control line is at a control voltage; and

the control voltage is greater than or equal to the source voltage, and the source voltage is greater than the reference voltage.

3. The storage unit of claim 2, wherein after the first write procedure of the registration operation, in a first read procedure of the registration operation:

the first bit line and the second bit line are at a first read voltage;

the source line is at a second read voltage greater than the first read voltage;

the selection circuit is turned on; and

the control line is at a third read voltage greater than the second read voltage.

4. A storage unit according to claim 3, wherein:

and when the read current of the first bitline or the read current of the second bitline reaches a default value in the first read program, raising the control voltage, and lowering or keeping the source voltage unchanged to execute a second write program of the registration operation.

5. A storage unit according to claim 3, wherein:

and when the read current of the first bit line or the read current of the second bit line does not reach a default value in the first read program, reducing the control voltage to execute a second write program of the registration operation.

6. A storage unit according to claim 3, wherein:

and when the reading current of the first bit line or the reading current of the second bit line does not reach a default value in the first reading program and a writing program of a preset number of times is executed, the source voltage and the control voltage are boosted to execute a second writing program of the registration operation.

7. The storage cell of claim 1, wherein in a read operation:

the first bit line and the second bit line are at a first read voltage;

the source line is at a second read voltage greater than the first read voltage;

the selection circuit is turned on; and

the control line is at a third read voltage greater than the second read voltage.

8. A storage unit according to claim 1, wherein in a purge operation:

the source line, the first bit line, and the second bit line are at a first clear voltage;

the selection circuit is turned on; and

the control line is at a second clear voltage that is less than the first clear voltage.

9. The memory cell of claim 1, wherein the selection circuit comprises:

a first select transistor having a first terminal coupled to the common node, a second terminal coupled to the source line, and a control terminal for receiving a select signal.

10. The memory cell of claim 9 wherein said first terminal of said first select transistor, said first terminal of said first storage transistor, and said first terminal of said second storage transistor are coupled to said common node through an oxide diffusion layer.

11. The memory cell of claim 10 wherein the channel width of said first select transistor is less than the sum of the channel width of said first storage transistor and the channel width of said second storage transistor.

12. The memory cell of claim 1, wherein the selection circuit comprises:

a first select transistor having a first terminal coupled to the common node and the first terminal of the first storage transistor body, a second terminal coupled to the source line, and a control terminal for receiving a select signal; and

a second select transistor having a first terminal coupled to the common node and the first terminal of the second storage transistor body, a second terminal coupled to the source line, and a control terminal for receiving the select signal.

13. The memory cell of claim 12, wherein the first terminal of the first select transistor, the first terminal of the second select transistor, the first terminal of the first storage transistor, and the first terminal of the second storage transistor are coupled to the common node through an oxide diffusion layer.

14. The memory cell of claim 12, wherein the first terminal of the first select transistor, the first terminal of the second select transistor, the first terminal of the first storage transistor, and the first terminal of the second storage transistor are coupled to the common node through a metal layer.

15. A method of operating a storage cell, the storage cell comprising a selection circuit, a first storage transistor, and a second storage transistor, the selection circuit coupled to a source line and a common node, the first storage transistor having a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a control terminal coupled to a control line, the second storage transistor having a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a control terminal coupled to the control line, the method comprising:

in the registration operation:

executing a first write program;

executing a first reading program to judge whether the reading current of the first bit line or the reading current of the second bit line reaches a default value after the first writing program; and

executing a second writing program according to the result of the first reading program;

wherein the first storage transistor and the second storage transistor are two-dimensional charge trapping devices or three-dimensional charge trapping devices.

16. The method of claim 15, wherein executing the first writer comprises:

applying a source voltage to the source line;

turning on the selection circuit; and

applying a control voltage to the control line;

applying a reference voltage to the first bit line and the second bit line;

wherein the first control voltage is greater than or substantially equal to the first source voltage, and the source voltage is greater than the reference voltage.

17. The method of claim 16, wherein performing the first read procedure to determine whether the read current of the first bitline or the read current of the second bitline reaches the default value after the first write procedure comprises:

applying a first read voltage to the first bit line and the second bit line;

applying a second read voltage greater than the first read voltage to the source line;

turning on the selection circuit; and

applying a third read voltage greater than the second read voltage to the control line.

18. The method of claim 16, wherein performing the second write procedure according to the result of the first read procedure comprises raising the control voltage and lowering or holding the source voltage constant to perform the second write procedure when the read current of the first bitline or the read current of the second bitline has reached the default value in the first read procedure.

19. The method of claim 16, wherein performing the second write process according to the result of the first read process comprises decreasing the control voltage to perform the second write process when the read current of the first bitline and the read current of the second bitline do not reach the default value in the first read process.

20. The method of claim 16, wherein performing the second write process according to the result of the first read process comprises boosting the source voltage and the control voltage to perform the second write process when the read current of the first bitline or the read current of the second bitline reaches the default value in the first read process and a predetermined number of write processes have been performed.

Technical Field

The present invention relates to a memory cell, and more particularly, to a memory cell including a two-dimensional charge trapping device or a three-dimensional charge trapping device.

Background

With the wider application field of electronic devices, the security of data communication between the inside of the electronic device and the electronic device is also receiving more and more attention. As reverse engineering of chips and electronic devices becomes automated, and the ability to attack by-pass channels becomes stronger and more affordable, it becomes increasingly difficult to protect electronic devices from unauthorized access.

In the prior art, a Physical Unclonable Function (PUF) circuit can generate random numbers as keys using its native properties to protect the system from physical attacks. For example, a latch in a Static Random Access Memory (SRAM) enters a specific steady state according to its initial electrical distribution in the absence of an input signal, and can be implemented as a physically unclonable function circuit to generate random numbers because the initial electrical distribution is unpredictable and uncontrollable. However, since the random number stored in the latch of the sram is volatile, the random number stored therein is erased and must be regenerated whenever the power is reset.

Disclosure of Invention

An embodiment of the invention provides a storage unit, which includes a selection circuit, a first storage transistor and a second storage transistor.

The selection circuit is coupled to the source line and the common node, and when the selection circuit is turned on, the selection circuit establishes an electrical connection between the source line and the common node, and when the selection circuit is turned off, the selection circuit blocks the electrical connection. The first storage transistor has a first terminal, a second terminal and a control terminal, the first terminal of the first storage transistor is coupled to the common node, the second terminal of the first storage transistor is coupled to the first bit line, and the control terminal of the first storage transistor is coupled to the control line. The second storage transistor has a first terminal, a second terminal and a control terminal, the first terminal of the second storage transistor is coupled to the common node, the second terminal of the second storage transistor is coupled to the second bit line, and the control terminal of the second storage transistor is coupled to the control line.

The first storage transistor and the second storage transistor are two-dimensional charge trapping devices or three-dimensional charge trapping devices.

Another embodiment of the present invention provides a method of operating a storage unit. The storage unit comprises a selection circuit, a first storage transistor and a second storage transistor, wherein the selection circuit is coupled to a source line and a common node. The first storage transistor has a first terminal, a second terminal and a control terminal, the first terminal of the first storage transistor is coupled to the common node, the second terminal of the first storage transistor is coupled to the first bit line, and the control terminal of the first storage transistor is coupled to the control line. The second storage transistor has a first terminal, a second terminal and a control terminal, the first terminal of the second storage transistor is coupled to the common node, the second terminal of the second storage transistor is coupled to the second bit line, and the control terminal of the second storage transistor is coupled to the control line.

The method for operating the storage unit includes executing a first write program in a registration operation, executing a first read program to determine whether a read current of the first bitline or a read current of the second bitline reaches a default value after the first write program, and executing a second write program according to a result of the first read program.

The first storage transistor and the second storage transistor are two-dimensional charge trapping devices or three-dimensional charge trapping devices.

Drawings

Fig. 1 is a schematic diagram of a storage unit according to an embodiment of the invention.

FIG. 2 is a flowchart illustrating a method for operating the storage unit of FIG. 1 to perform a registration operation according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of voltages received by the storage unit when the method of FIG. 2 is applied.

FIG. 4 is a layout diagram of the memory cell of FIG. 1 according to an embodiment of the present invention.

FIG. 5 is a layout diagram of the memory cell of FIG. 1 according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of a storage unit according to another embodiment of the invention.

FIG. 7 is a layout diagram of the memory cell of FIG. 6 according to an embodiment of the present invention.

Wherein the reference numerals are as follows:

100. 300 storage unit

110. 310 selection circuit

112. 312, 314 select transistors

120A, 120B storage transistor

B L1, B L2 bit line

NC1 common node

S L1 Source line

C L1 control line

SIG_SELSelection signal

200 method

Method of S210 to S270

VR1 first read Voltage

VR2 second read voltage

VR3 third read Voltage

VC1 control Voltage

VS1 source voltage

Programs written in PP1, PP2, PP3, PP4 and PP5

RD1, RD2, RD3 and RD4 reading programs

DNW N type deep well region

OD1 diffusion layer

P L1 and P L2 polysilicon layers

MT1 metal layer

Detailed Description

Fig. 1 is a schematic diagram of a storage unit 100 according to an embodiment of the invention. The memory cell 100 includes a selection circuit 110 and storage transistors 120A and 120B. In some embodiments, the storage transistors 120A and 120B may be two-dimensional charge trapping devices or three-dimensional charge trapping devices. For example, the storage transistors 120A and 120B may be silicon-oxide-nitride-oxide-silicon (SONOS) transistors.

The selection circuit 110 may be coupled to the source line S L1 and the common node NC 1. when the selection circuit 110 is turned on, the selection circuit 110 may establish an electrical connection between the source line S L1 and the common node NC1, and when the selection circuit 110 is turned off, the selection circuit 110 may block an electrical connection between the source line S L1 and the common node NC 1.

In FIG. 1, the selection circuit 110 may include a selection transistor 112, the selection transistor 112 has a first terminal, a second terminal, and a control terminal, the first terminal of the selection transistor 112 is coupled to the common node NC1, the second terminal of the selection transistor 112 is coupled to the source line S L1, and the control terminal of the selection transistor 112 may receive a selection signal SIG_SEL。

In addition, the storage transistor 120A has a first terminal, a second terminal, and a control terminal, the first terminal of the storage transistor 120A is coupled to the common node NC1, the second terminal of the storage transistor 120A is coupled to the bit line B L1, and the control terminal of the storage transistor 120A is coupled to the control line C L1. the storage transistor 120B has a first terminal, a second terminal, and a control terminal, the first terminal of the storage transistor 120B is coupled to the common node NC1, the second terminal of the storage transistor 120B is coupled to the bit line B L2, and the control terminal of the storage transistor 120B is coupled to the control line C L1.

In some embodiments, to register the memory cell 100, i.e., generate and store random bits as a physical unclonable function, the storage transistors 120A and 120B undergo multiple write operations. In this case, one of the storage transistors 120A and 120B may be written first, while the other one remains unwritten, according to unpredictable physical structural differences in the storage transistors 120A and 120B. Thus, the different write states of the storage transistors 120A and 120B can be recorded as random numbers.

FIG. 2 is a flowchart of a method 200 for operating the storage unit 100 to perform a registration operation according to an embodiment of the invention. FIG. 3 is a schematic diagram of voltages received by the memory cell 100 when the method 200 is applied. The method 200 may include steps S210 to S270.

S210: executing the writing program;

s220: executing a reading program;

s230, if the read current on the bit line B L1 or the read current on the bit line B L2 reaches a default value, the step S240 is entered, otherwise, the step S250 is entered;

s240: raising the control voltage VC1 and lowering or keeping the source voltage VS1 to execute the writing procedure again;

s250: if the write-in program has been executed for more than a predetermined number of times, go to step S260, otherwise go to step S270;

s260: raising the control voltage VC1 and the source voltage VS1 to perform the writing process again, and returning to step S220; and

s270: the control voltage VC1 is lowered to perform the writing process again, and the process returns to step S220.

In step S210, the program PP1 of the register operation applies a source voltage VS1 to the source line S L1, a reference voltage VR1 to the bit lines B L1 and B L2, a control voltage VC1 to the control line C L1, and a select signal SIG_SELA voltage less than the source voltage VS1 is set to turn the selection circuit 110 on. In addition, the control voltage V1 may be greater than or substantially equal to the source voltage VS1, and the source voltage VS1 may be greater than the reference voltage VR 1. For example, but not limited to, in the program PP1, the control voltage VC1 may be 7.4V, the source voltage VS1 may be 5.2V, and the reference voltage VR1 may be 0V.

In some embodiments, if the storage transistors 120A and 120B are not written to, the storage transistors 120A and 120B will still have a larger resistance, and thus the voltage of the common node NC1 is close to the source voltage VS1, so that an electric field is generated between the first terminal and the second terminal of the storage transistor 120A, and an electric field is also generated between the first terminal and the second terminal of the storage transistor 120B. In this case, the electric field across storage transistors 120A and 120B may cause hot electron injection due to control voltage VC 1.

However, since the storage transistors 120A and 120B have the native characteristic difference, hot electron injection occurs in one of the storage transistors 120A and 120B first. In addition, once one of the storage transistors 120A or 120B causes hot electron injection, the resistance of the storage transistor that captures electrons first drops, so that the voltage of the common node NC1 is pulled down, making it difficult for the other storage transistor to cause hot electron injection and therefore unable to capture electrons.

In some embodiments, hot electron injection is most easily induced when the voltage difference between the control voltage VC1 and the source voltage VS1 is close to the threshold voltage of the storage transistor. Therefore, in order to avoid the difference between the two transistors that is difficult to distinguish due to the electron capture caused by the hot electron injection caused by the too fast speed of the storage transistors 120A and 120B, the control voltage VC1 can be set to be greater than or equal to the source voltage VS1 in the write process PP 1. In this way, the storage transistors 120A and 120B are less likely to be written after a single write process and generate a read current exceeding a default value, and the difference between the threshold voltage of the storage transistor 120A and the threshold voltage of the storage transistor 120B can be gradually increased in subsequent write processes.

After the program PP1, step S220 executes a read process RD1 to determine whether the read current on bit lines B L1 or B L2 reaches a predetermined value, in FIG. 3, the read process RD1 applies a first read voltage VRD1 to bit lines B L1 and B L2, a second read voltage VRD2 greater than the first read voltage VRD1 to source line S L1, and a third read voltage VRD3 greater than the second read voltage VRD2 to control line C L1. for example, but not limited to, the first read voltage VRD1 may be 1V, the second read voltage VRD2 may be 2.2V, and the third read voltage VRD3 may be 2.4V. in the read process RD1, the selection circuit 110 is also turned on.

In this case, if the storage transistor 120A causes hot electron injection in the write process PP1 and captures enough electrons, then the storage transistor 120A will generate a significant read current on the bit line B L1 during the read process RD 1. however, if the storage transistor 120A does not capture enough electrons, then there will not be a significant read current on the bit line B L1. therefore, by detecting the read currents on the bit lines B L1 and B L2, the write state of the storage transistors 120A and 120B can be determined during the read process RD 1. in some embodiments, the default value of the read current for determining the write state can be set according to the system requirements, such as but not limited to 1 μ A or 5 μ A in some embodiments.

In FIG. 3, since the read currents on the bit lines B L1 and B L2 do not reach the default value, step S250 is performed after step S230. in step S250, since only one write process is currently performed, i.e., the write process has not been performed more than a predetermined number of times (e.g., but not limited to 10 times), step S270 is performed after step S250. in step S270, the control voltage VC1 is lowered to perform the write process PP2 of the register operation, as shown in the flowchart of FIG. 2.

In this case, the control voltage VC1 is lowered, so the voltage difference between the control voltage VC1 and the source voltage VS1 is closer to the threshold voltage of the storage transistors 120A and 120B. Thus, hot electron injection is more easily induced in the program PP 2.

After the program PP2, step S220 is performed again to determine the writing status of the storage transistors 120A and 120B. in the read program RD2 of FIG. 3, since the read currents on the bit lines B L1 and B L2 have not yet reached the predetermined value, the control voltage VC1 is again lowered to perform the program PP 3.

However, if the write process is performed more than a predetermined number of times, such as but not limited to more than 10 times, the control voltage VC1 may be lowered to be no longer suitable for inducing hot electron injection during the repeated execution of step S270. therefore, as described in steps S250 and S260, the control voltage VC1 and the source voltage VS1 are raised to perform the subsequent write process, thereby maintaining a proper hot electron injection inducing environment during the write process.

For example, in the read process RD3 of FIG. 3, if the read currents on the bit lines B L1 and B L2 have not reached the predetermined value, step S250 is executed after steps S220 and S230, and it is further determined whether the write process has been performed a predetermined number of times, since the read currents on the bit lines B L1 and B L2 have not reached the predetermined value after the write process has been performed the predetermined number of times, the source voltage VS1 and the control voltage VC1 are raised to perform the write process PP4 in step S260. in some embodiments, the control voltage VC1 is raised to be higher than the control voltage VC1 used in the write process PP 1.

In some embodiments, the predetermined number of times of performing the write process is determined according to the magnitude of the control voltage VC1, since the magnitude of the control voltage VC1 decreases in the two write processes before and after the control voltage VC1 determines the decreasing speed of the control voltage VC 1.

In addition, if the read current on the bit lines B L and B L does not reach the default value after the program PP4 is written, the control voltage VC1 is still lowered to perform the next program, as shown in FIG. 3, thereby increasing the probability of hot electron injection.

In the read process RD4 of fig. 3, the read current of one of the bit lines B L1 and B L2 is determined to reach the default value in step S230, so the control voltage VC1 is raised in step S240, and the source voltage VS1 is lowered or kept unchanged to execute the write process PP 5.

In this case, increasing the control voltage VC1 can help the storage transistor that has captured electrons during hot electron injection to further increase its threshold voltage, and can also prevent another storage transistor that has not captured electrons from being written. Thus, after the registration operation is completed, one of the storage transistors 120A and 120B is written, while the other one remains unwritten. The written state of the storage transistors 120A and 120B can be used as a random bit generated by the memory cell 100. For example, if storage transistor 120A is written and storage transistor 120B is not written, then the random bit is a "1"; conversely, if storage transistor 120B is written to, but storage transistor 120A is not written to, then the random bit is a "0".

For example, in a read operation, the bit lines B L1 and B L2 may be at the first read voltage VRD1, the source line S L1 may be at the second read voltage VRD2, and the control line C L1 may be at the third read voltage VRD 3. in this case, the random bit stored in the memory cell 100 may be read by detecting the read current on the bit lines B L1 and B L2 during the read operation.

In some embodiments, the random bit stored in the memory cell 100 may be cleared by performing a clear operation, for example, the source line S L1 and bit lines B L1 and B L2 may be at a first clear voltage and the control line C L1 may be at a second clear voltage that is less than the first clear voltage, for example, in a clear operation, the select circuit 110 may be turned on, in some embodiments, the first clear voltage may be 6.4V and the second clear voltage may be-6V, such that a large voltage difference applied across the storage transistors 120A and 120B may cause Fowler-Nordheim tunneling (Fowler-Nordheim tunneling), thereby clearing the random bit stored in the memory cell 100.

In some embodiments, the storage unit 100 may be registered again after the purge operation. However, since the erase operation may change a part of the characteristics of the storage transistors 120A and 120B, the result of performing the registration operation after the erase operation may be different from the result of the registration operation before the erase operation.

FIG. 4 is a layout diagram of a memory cell 100 according to an embodiment of the invention, in FIG. 4, the select transistor 112 and the storage transistors 120A and 120B may be disposed in a deep N-well DNW, the storage transistors 120A and 120B may be formed by a diffusion layer OD1 and a polysilicon layer P L1, and the select transistor 112 may be formed by a diffusion layer OD1 and a polysilicon layer P L2. that is, the first terminal of the select transistor 112, the first terminal of the storage transistor 120A, and the first terminal of the storage transistor 120B may be coupled to a common node NC1 through an oxide diffusion layer OD 1.

In addition, in fig. 4, the channel width of the selection transistor 112 may be smaller than the sum of the channel width of the storage transistor 120A and the channel width of the storage transistor 120B. In this case, once one of the storage transistors 120A and 120B causes hot electron injection during the write process of the register operation, the voltage of the common node NC1 drops rapidly, thereby ensuring that the other storage transistor remains in an unwritten state.

However, in some other embodiments, the channel width of the selection transistor 112 may be larger than the sum of the channel width of the storage transistor 120A and the channel width of the storage transistor 120B to ensure that the layout of the circuit structure remains symmetrical. FIG. 5 is a layout diagram of a memory cell 100 according to another embodiment of the present invention. In fig. 5, the oxide diffusion layer OD1 may extend directly from the storage transistors 120A and 120B to maintain a relatively simple profile, thereby maintaining a relatively symmetrical structure during the manufacturing process and ensuring randomness of the registration operation results.

In addition, since the symmetrical structure of the storage unit 100 helps to maintain the randomness of the result of the registration operation, the storage unit may also include two selection circuits to make the circuit structure more symmetrical. Fig. 6 is a schematic diagram of a storage unit 300 according to another embodiment of the invention.

The storage unit 300 and the storage unit 100 have similar structures and may operate according to similar principles. However, the selection circuit 310 of the storage cell 300 may include two selection transistors 312 and 314.

The select transistor 312 has a first terminal, a second terminal and a control terminal, the first terminal of the select transistor 312 is coupled to the common node NC1 and the first terminal of the storage transistor 120A, the second terminal of the select transistor 312 is coupled to the source line S L1, and the control terminal of the select transistor 312 receives a select signal SIG_SELThe select transistor 314 has a first terminal, a second terminal, and a control terminal, the first terminal of the select transistor 314 is coupled to the common node NC1 and the first terminal of the storage transistor 120B, the second terminal of the select transistor 314 is coupled to the source line S L1, and the control terminal of the select transistor 314 receives a select signal SIG_SEL。

In fig. 6, since the storage transistors 120A and 120B can be coupled to the selection transistors 312 and 314, respectively, the layout symmetry of the memory cell 300 can be maintained during the manufacturing process. FIG. 7 is a layout diagram of a memory cell 300 according to an embodiment of the invention. In FIG. 7, the first terminal of the select transistor 312, the first terminal of the select transistor 314, the first terminal of the storage transistor 120A, and the first terminal of the storage transistor 120B may be coupled to a common node NC1 through a metal layer MT 1.

Although metal layer MT1 is used to connect the select transistors 312 and 314 and the storage transistors 120A and 120B to the common node NC1 in FIG. 7, in some other embodiments, the first terminal of the select transistor 312, the first terminal of the select transistor 314, the first terminal of the storage transistor 120A, and the first terminal of the storage transistor 120B may be coupled to the common node NC1 through diffusion layers.

In summary, embodiments of the present invention provide a memory cell that can generate and store random bits using two-dimensional charge trapping devices or three-dimensional charge trapping devices. In addition, the random bits stored in the storage unit can be cleared by the clearing operation, thereby improving the flexibility and safety of the storage unit in use.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.