阅读说明：本技术 半导体器件及其形成方法 (Semiconductor device and method of forming the same ) 是由 林孟汉 吴伟成 于 2019-08-27 设计创作，主要内容包括：提供一种用于制造集成半导体器件的方法,该集成半导体器件包括形成在半导体衬底的凹进区域中的嵌入式闪存阵列,该方法包括：在形成存储器阵列的浮置和控制栅极堆叠件之前,在栅极材料层上方沉积保护层,并且在保护层上方沉积自流平牺牲层,以产生基本平坦的上表面。然后将牺牲层蚀刻到去除牺牲层并在保护层上留下基本平坦的面的深度。然后在保护层上沉积光掩模,并且从栅极材料层蚀刻栅极堆叠件。本发明的实施例还涉及半导体器件及其形成方法。(There is provided a method for manufacturing an integrated semiconductor device including an embedded flash memory array formed in a recessed region of a semiconductor substrate, the method comprising: prior to forming the floating and control gate stacks of the memory array, a protective layer is deposited over the gate material layer, and a self-leveling sacrificial layer is deposited over the protective layer to create a substantially planar upper surface. The sacrificial layer is then etched to a depth that removes the sacrificial layer and leaves a substantially planar face on the protective layer. A photomask is then deposited on the protective layer and the gate stack is etched from the gate material layer. Embodiments of the invention also relate to semiconductor devices and methods of forming the same.)

1. A method of forming a semiconductor device, comprising:

forming a protective layer over a non-planar surface of a semiconductor substrate (102);

forming a sacrificial layer over the protective layer;

forming a surface on the sacrificial layer; and

planarizing the surface of the sacrificial layer to a depth sufficient to remove the sacrificial layer and remove portions of the protective layer.

2. The method of claim 1, wherein planarizing the surface of the sacrificial layer to a depth sufficient to remove the sacrificial layer and remove portions of the protective layer comprises: etching the surface of the sacrificial layer to completely remove the sacrificial layer and partially remove the protective layer.

3. The method of claim 1, wherein the sacrificial layer comprises a photoresist material, and wherein forming the sacrificial layer over the protective layer and forming the surface on the sacrificial layer together comprise: spin coating a self-leveling material on the semiconductor substrate.

4. The method of claim 1, wherein forming the protective layer over the non-planar surface of the semiconductor substrate comprises: the protective layer is formed over a recessed region of the semiconductor substrate.

5. The method of claim 4, comprising:

forming a material for a plurality of floating gates and control gates of a memory array in a layer above the recessed region prior to forming the protective layer; and

forming a material for the plurality of floating gates in a layer above the recessed region.

6. The method of claim 5, wherein forming material for the plurality of floating gates in a layer above the recessed region comprises:

forming a first dielectric layer over the semiconductor substrate;

forming a first polysilicon layer over the first dielectric layer;

forming a second dielectric layer over the first polysilicon layer; and

a second polysilicon layer is formed over the second dielectric layer.

7. A method of forming a semiconductor device, comprising:

forming a recess region in a semiconductor substrate;

forming gate material for a plurality of floating gates and control gates of a memory array in a layer above the recessed region;

forming a protective layer over the gate material in the recessed region;

planarizing the protective layer;

forming an etching mask layer over the planarized protection layer; and

forming a plurality of gate stacks in the recessed regions by etching the gate material.

8. The method of claim 7, wherein planarizing the protective layer comprises:

forming a sacrificial layer over the protective layer;

planarizing the sacrificial layer; and

after planarizing the sacrificial layer, a planarized surface of the sacrificial layer is etched at a uniform rate across the recessed region to a depth sufficient to leave a planarized surface on the protective layer.

9. A method of forming a semiconductor device, comprising:

forming a protective layer over the stack of gate material layers in the recessed region of the semiconductor substrate;

depositing a sacrificial layer over the protective layer, the sacrificial layer having a depth sufficient to create a planarized surface on the semiconductor substrate; and

the sacrificial layer is removed to a depth sufficient to create a planar surface on the protective layer.

10. A semiconductor device, comprising:

a semiconductor substrate including a recessed region having a central portion and an outer peripheral portion; and

a flash memory array in the recessed region, the flash memory array including a plurality of gate stacks, and each of the gate stacks having a width, the width of the gate stacks being uniform for the gate stacks in the central portion of the recessed region and the gate stacks in the peripheral portion of the recessed region.

Technical Field

Embodiments of the invention relate to semiconductor devices and methods of forming the same.

Background

Flash memory has certain advantages and benefits over other types of solid state non-volatile memory structures. Many of these advantages and benefits are associated with, for example, improved read, write and/or erase speeds, power consumption, compactness, cost, and the like. Flash memory is commonly used in high density data storage devices configured for use with cameras, cell phones, voice recorders, portable USB data storage devices (commonly referred to as thumb drives or flash drives, etc.). Typically, in such applications, the flash memory is fabricated on a dedicated microchip and then coupled in a single package with another chip or chips containing appropriate processor circuitry, or in separate packages configured to be electrically coupled.

Processors with embedded flash memory are a recent development. In such devices, the flash array is fabricated on a single chip along with logic and control circuitry. Such arrangements are typically used in microcontroller units (MCUs) (i.e., small computer devices integrated on a single chip), which are typically designed to repeatedly perform a limited number of specific tasks. MCUs are often used in smart cards, wireless communication devices, automotive control units, etc. Integration of memory with associated processing circuitry may increase processing speed while reducing package size, power consumption, and cost.

Disclosure of Invention

An embodiment of the present invention provides a method of forming a semiconductor device, including: forming a protective layer over a non-planar surface of a semiconductor substrate (102); forming a sacrificial layer over the protective layer; forming a surface on the sacrificial layer; and planarizing the surface of the sacrificial layer to a depth sufficient to remove the sacrificial layer and remove portions of the protective layer.

Another embodiment of the present invention provides a method of forming a semiconductor device, including: forming a recess region in a semiconductor substrate; forming gate material for a plurality of floating gates and control gates of a memory array in a layer above the recessed region; forming a protective layer over the gate material in the recessed region; planarizing the protective layer; forming an etching mask layer over the planarized protection layer; and forming a plurality of gate stacks in the recessed regions by etching the gate material.

Yet another embodiment of the present invention provides a method of forming a semiconductor device, including: forming a protective layer over the stack of gate material layers in the recessed region of the semiconductor substrate; depositing a sacrificial layer over the protective layer, the sacrificial layer having a depth sufficient to create a planarized surface on the semiconductor substrate; and removing the sacrificial layer to a depth sufficient to create a planar surface on the protective layer.

Still another embodiment of the present invention provides a semiconductor device including: a semiconductor substrate including a recessed region having a central portion and an outer peripheral portion; and a flash memory array in the recessed region, the flash memory array including a plurality of gate stacks, and each of the gate stacks having a width, the width of the gate stacks being uniform for the gate stacks in the central portion of the recessed region and the gate stacks in the peripheral portion of the recessed region.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 is a schematic side cross-sectional view of a portion of a semiconductor device having an embedded flash memory (e.g., a microcontroller unit) during fabrication according to an embodiment.

Fig. 2A-2D are schematic side cross-sectional views of the semiconductor device of fig. 1 at respective stages of the fabrication process, particularly illustrating recessed regions during control of the embedded memory array and formation of the floating gates, and illustrating the source of problems addressed by the various disclosed embodiments.

Fig. 3A-3F are schematic side cross-sectional views of the semiconductor device of fig. 1 at various stages of the fabrication process and illustrate the control and floating gate formation of the device 100 of fig. 1, according to an embodiment. In particular, the process of fig. 3A-3F continues from the stage described above with reference to fig. 2B and replaces portions of the process described with reference to fig. 2C-2D.

Fig. 4 and 5 are flow charts summarizing methods of manufacturing according to respective embodiments, consistent with the process described with reference to fig. 2A-2B and 3A-3F.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, forming a first feature over a second feature refers to forming the first feature in direct contact with the second feature. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatial relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures for ease of description. Spatial relationship terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.

In the drawings, some elements are indicated by reference numerals followed by letters, such as "704 a, 704 b". In this case, letter designations are used in the respective description to refer to or distinguish particular elements or differences between particular elements among a number of other similar or identical elements. If the specification omits letters from the reference and refers to these elements only by number, it is to be understood that a general reference to any or all of the elements identified by the reference number, unless other distinguishing language is used.

Unless the context clearly further limits the scope, reference to a semiconductor substrate may include within its scope any element formed or deposited on the substrate. For example, reference to planarizing a surface of a semiconductor substrate may refer to planarizing one or more layers of material deposited or otherwise formed over the actual base material of the substrate, including, for example, polysilicon layers, metal layers, dielectric layers, or combinations of materials, layers, and/or elements.

A microcontroller unit (MCU) typically includes a number of discrete devices such as a Central Processing Unit (CPU) core, a Static Random Access Memory (SRAM) array (or module), a flash memory module, a system integration module, a timer, an analog-to-digital converter (ADC), a communication and networking module, a power management module, and the like. Each of these devices, in turn, includes a number of passive and active electronic components, such as resistors, capacitors, transistors, and diodes. A large number of these components, in particular active components, are based on various types of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or variants thereof. In a MOSFET, the conductivity in the channel region extending between the source and drain terminals is controlled by the electric field in the channel region, which is generated by the voltage difference between the control gate and the body of the device.

Fig. 1 is a schematic side cross-sectional view of a portion of a device 100 (e.g., MCU) during fabrication on a semiconductor material substrate 102, according to an embodiment. The device 100 includes a processor having an embedded flash memory array 104 and other processor circuitry 106 formed on a semiconductor substrate 102. Other processor circuits 106 include a plurality of transistors 108 configured for various different functions, but for this purpose will be referred to as logic transistors, each including a control gate 110 isolated from a channel region 112 by a gate dielectric 114. Source and drain regions 116 are formed at opposite ends of the channel region 112. Isolation regions 115 electrically isolate various components of device 100 to prevent interference between different elements during operation.

The flash array 104 is located within the recessed region 140 and is isolated by Shallow Trench Isolation (STI) regions 115 a. Memory array 104 includes a plurality of flash memory cells 118, flash memory cells 118 being similar in many respects to logic transistors 108, each flash memory cell 118 having a control gate 120, a channel region 122, and a gate dielectric 124. However, each flash memory cell 118 also includes a floating gate 126 located between the control gate 120 and the gate dielectric 124. In the illustrated embodiment, an erase gate dielectric 128 is located between each floating gate 126 and a corresponding erase gate 130. The alternating source and drain regions 132, 134 are interleaved between the memory cells 118 such that each memory cell shares the source 132 with an adjacent memory cell on one side and the drain 134 with an adjacent memory cell on the opposite side. Select gate 136 is located between drain 134 and the control and floating gates 120, 126 of each memory cell 118. The various material layers 138 are shown in general outline, not configured to function as conductors or semiconductors in the device 100. These layers may include dielectrics, resist capping layers, passivation layers, etch stop layers, spacers, etc., and include a dielectric layer 138a between each floating gate 126 and the corresponding control gate 120 of the memory cell 118.

Due to the similarity in structure of the logic transistor 108 and the flash memory cell 118, they will have similar heights, except for the additional height of the floating gate 126 and the corresponding dielectric layer 138 of the memory cell. This can be a problem because at several points during the manufacturing process, a chemical/mechanical polishing (CMP) procedure is performed to produce a substantially planar surface for subsequent process steps. The CMP process to reduce the control gate 110 of the logic transistor 108 to an appropriate height may damage the higher control gate 120 of the memory cell 118.

One solution is to form the memory array 102 in a recessed region 140, wherein the height of the surface 142 of the semiconductor substrate 102 within the recessed region is reduced relative to the height of the surface 144 of the substrate outside the recessed region by a distance approximately equal to the total thickness of the floating gate 126 and dielectric 138 a. Such a difference in height between surfaces 142 and 144 may be referred to as a step height or difference in step height between surface 142 of recessed region 140 (where memory cells of memory array 102 are formed) and surface 144 of the periphery around the recessed region (where other components are formed). According to an embodiment, recessed regions 140 are formed by an etching process in which the surface of semiconductor substrate 102 is uniformly etched to a desired depth over the intended recessed regions, thereby creating a substantially planar surface 142 on which memory cells 118 are subsequently formed.

According to an alternative embodiment, a layer of semiconductor material is deposited or grown on the surface of substrate 102 outside of intended recessed region 140, raising surface 144 to a desired height above recessed surface 142. For the purposes of the present invention, reference to the formation of a recessed region includes any process that results in a defined region having a depth relative to the surrounding substrate that is approximately equal to the difference in height between a floating gate transistor and a MOSFET transistor that does not employ a floating gate.

As described above, the logic transistors 108 operate by applying an electric field over the respective channel regions 112, thereby changing the conductivity of the channel regions. The electric field is generated by applying a voltage potential between the control gate 110 and the semiconductor body 102. When an electric field of a selected polarity is present, the MOSFET can be configured to increase or decrease conductivity. In general, transistors in logic circuits are designed to function as switches, turn on or off in response to an electric field of a selected strength, and control current flow in a channel region.

In memory cell 118, during a write operation, electrons may be forced to tunnel through gate dielectric 124 to floating gate 126, where they may remain trapped indefinitely by applying a write voltage to control gate 120 while a voltage potential is applied to the channel region. If a sufficient number of electrons are trapped on the floating gate 126, the electrons may block the electric field generated by the control gate 120, thereby preventing the control gate from acting to alter the conductivity in the channel. Thus, the presence of electrons can be detected by applying voltage potentials on the drain and source regions 132, 134 while applying a read voltage to the control gate 120 to generate an electric field, and testing the flow of current in the channel region 122. Typically, a binary value of 1 is the default setting of the flash cell at the time of manufacture and prior to programming, and indicates a binary value of zero if the channel current is not affected by the read voltage at control gate 120. A binary zero value on the flash cell can be erased-i.e., returned to 1-by applying a sufficiently strong erase voltage to erase gate 130. This causes electrons trapped on the floating gates 126 of the memory cells 118 adjacent to the activated erase gate 130 to tunnel through the erase gate dielectric 128 to the erase gate 130. In practice, there are more memory cells 118 adjacent to erase gate 130, extending along a row perpendicular to the view of fig. 1. During an erase operation, each memory cell is erased, hence the term flash memory.

As technology advances, components are smaller and more compact, reducing power consumption and voltage requirements while increasing memory density and speed. However, a problem that arises with decreasing size is that very small changes in gate size can have a progressively increasing effect on performance, since such changes represent larger changes relative to a proportionally smaller nominal gate size. This becomes a greater problem as technology nodes fall below 65nm, 40nm and 28 nm.

Fig. 2A-2D are schematic side cross-sectional views of the substrate 102 at various stages of the fabrication process, particularly illustrating the recessed region 140 during formation of the control and floating gates 120, 126 of the memory array 108 of the device 100 of fig. 1. The diagrams and corresponding descriptions shown in fig. 2A-2D are merely isolated steps in a manufacturing process and are not intended to provide general information about the manufacturing process.

Initially, as shown in fig. 2A, a protective layer 150 is formed on the surface 144 of the semiconductor material substrate 102 and may comprise a plurality of layers, e.g., silicon oxide, silicon nitride, etc. Isolation regions 115 are formed in substrate 102 and a hard mask layer 152 is deposited. Then, the recess region 140 is formed in an anisotropic etching process. An oxide layer 154 is formed on the substrate surface 142 within the recessed region 140 and a polysilicon layer 156 is grown on the oxide layer. The oxide layer 154 and the polysilicon layer 156 comprise the materials that will ultimately form the gate dielectric 124 and the floating gate 126 of the memory array 104.

Entering the stage shown in fig. 2B, a dielectric layer 158 is deposited over the substrate 102, followed by a polysilicon layer 160 and a protective layer 162. The dielectric layer 158 and the polysilicon layer 160 comprise the materials that will ultimately form the dielectric layer 138a and the control gate 120 of the memory array 104, while the protective layer 162 is patterned in the presence of the dielectric layer and the polysilicon layer to form a protective cap over the gate stack to protect the control gate and the floating gate during subsequent process steps. According to an embodiment, the protective layer 162 is a hard mask material-typically an oxide, nitride, amorphous carbon, combinations of these materials, or the like. The term hard mask material refers to a layer (or layers) of material that is substantially resistant to the selected process to be employed after the mask is formed. The resistance to the selected process to be employed after mask formation may be a result of a composition of the hard mask material or a combination of a composition of the hard mask material and a thickness of the hard mask material. The thickness of the hard mask material may vary, and embodiments of the invention are not limited to the particular thicknesses described below. In various embodiments, the hard mask material comprises 400 to 500 angstroms

Silicon nitride (SiN) layer of (a), 1000 to 1200 angstroms of silicon dioxide (SiO)₂) A layer and a 700 to 900 angstrom SiN layer. In some embodiments, the hard mask material comprises a 440 angstroms layer of SiN, 1100 angstroms of SiO₂A layer and an 800 angstrom SiN layer. In these embodiments, the total thickness of the hard mask material formed by these layers is 2340 angstroms greater than the depth of the recessed regions 140, where the depth of the recessed regions is greater than 300 angstroms. The thicknesses of these layers are based on the etch selectivity of the subsequent etch process described below with reference to fig. 2D. In various embodiments, the total thickness of the hardmask material formed from these layers is in the range of 2100 angstroms to 2600 angstroms and is selected to be greater than that of the recessed region 140A depth, wherein the recessed region has a depth greater than 300 angstroms.

In fig. 2C, a bottom antireflective coating (BARC)164 is applied over the protective layer 162, followed by a patterning film layer 166. The patterned film layer 166 will be patterned to create an etch mask with the BARC 164 located between the substrate and the patterned film layer for preventing damage to the film layer caused by reflections off the surface of the substrate 102 during patterning of the film. The BARC is typically applied by a spin-on process, while the patterned film 166 may be applied by any of several processes, depending on the type of patterned film, including, for example, a deposition process such as thermal deposition or Chemical Vapor Deposition (CVD). As shown in fig. 2C, the BARC 164 tends to deposit thicker around the edge (164b) than in the center (164a) of the recessed region 140. If the patterned film is applied by spin coating, the patterned film may also be thicker at the edges (166b) than in the middle of the recessed region (166 a).

Turning finally to fig. 2D, after the patterning of the patterned film layer 166, an etching process is performed, resulting in a plurality of gate stacks 168, each gate stack 168 having a protective cap 170, a control gate 120, and a dielectric layer 138 a. The remnants of oxide layer 158, polysilicon layer 160, and protective layer 162 remain around the periphery of recessed region 140. After performing further process steps, including the deposition of further dielectric layers, the gate dielectric 124 and the floating gate 126 will be etched from their mother layers 154, 156 during subsequent steps.

As shown in fig. 2D, gate stack 168a near the center of recessed region 140 is narrower than gate stack 168b closer to the edge of the region. This is caused by the thicker BARC and patterned film layer portion 164b near the edge of the recessed region 140, as described above with reference to fig. 2C. In general, BARC materials are considered conformal and the effects of small variations in thickness caused by surface features of the substrate are negligible. As the scale continues to decrease, the effects of small variations in thickness caused by surface features of the substrate can become a significant problem, particularly at technology nodes below the scale of, for example, 65nm, 40nm, and 28 nm. This is because the dimensions of the control gate 120 and floating gate 126 have a direct impact on the critical operating characteristics of the device, such as read and write speed, program and erase state voltages and currents, and power consumption.

To utilize memory cells 118 near the edges of recessed region 140, the operating parameters of the entire memory array 108 may be modified to ensure that data is not lost or corrupted because memory cells near the edges of the recessed region are not properly written to or erased. Modifying the operating parameters of the entire memory cell in this manner may result in less than optimal performance of the entire array. One option is to deactivate the cells closest to the edge of the recessed area 140-or leave the edge area empty-but this will result in a capacity loss. The reduced total capacity may be minimal if all memory cells of the device are in a single array, but many MCU devices are designed to place smaller memory arrays adjacent to the circuits that will use them to improve throughput speed. In such devices, smaller memory arrays are located at multiple locations on the device. Thus, the total area of the edge regions is much larger than in a single array, and therefore the lost capacity is much larger.

The inventors have also recognized that this problem can be eliminated if the BARC is deposited on a substantially planar surface. However, planarizing the surface at the stage of the process shown in fig. 2B is problematic. The CMP process will have a tendency to recess over the recessed regions 140 and other planarization processes are not suitable or will require many additional process steps.

The embodiments described below with reference to FIGS. 3A-3F reduce or eliminate the BARC layer thickness variation and associated gate uniformity variation described above. Fig. 3A-3F are schematic side cross-sectional views of the substrate 106 at various stages of the fabrication process, illustrating the formation of the control gate 120 and floating gate 126 of the memory array 108 of the device 100 of fig. 1, according to an embodiment. In particular, the process of fig. 3A-3F continues from the stage described above with reference to fig. 2B and replaces portions of the process described with reference to fig. 2C-2D. Thus, starting at the stage of fig. 2B, fig. 3A shows the deposition of a sacrificial layer 180 over the protective layer 162. According to an embodiment of the present invention, sacrificial layer 180 is a photoresist layer applied in a spin-on process, the thickness of the photoresist layer being sufficient to completely fill the recess in protective layer 162 over recessed region 140. The sacrificial layer 180 is self-leveling, meaning that its upper surface 182 is substantially flat when applied without further treatment. In one embodiment of the invention, the sacrificial layer 180 for each spin-on process is approximately 1000 angstroms thick. The thickness of the sacrificial layer 180 is not limited to about 1000 angstroms per spin-on process, and each spin-on process may be greater or less than 1000 angstroms. Sacrificial layer 180 is not limited to being a photoresist layer and may be other flowable materials in other embodiments of the invention. In addition, the flowable material of the sacrificial layer 180 is not limited to being applied by a spin-on process, and other suitable processes are utilized to apply the flowable material in other embodiments.

As shown in fig. 3B, a non-selective etching process is performed to etch back the surface of the substrate into the protection layer 162 while completely removing the sacrificial layer 180. The chemistry of the etching process is selected such that the etch rates of the sacrificial layer 180 and the protective layer 162 are substantially equal. Thus, the etching process proceeds uniformly over the surface of the substrate, leaving a planarized face 184 on the surface of the protective layer 162. A patterned film layer 186 and a BARC layer 188 are then deposited with uniform thickness over the planarized surface 184 of the protective layer 162. The BARC layer 188 is typically a suitable flowable material and is formed by a spin-on process, while the patterned film layer 186 is formed by a suitable process, such as a Chemical Vapor Deposition (CVD) process, as discussed above with respect to the corresponding layers associated with fig. 2A-2D. In embodiments of the present invention, the upper surface 182 is said to be substantially planar, where the term "substantially" means that the upper surface is sufficiently planar to enable subsequent formation of the patterned film layer 186 and the BARC layer 188 with reduced thickness variation, thereby enabling formation of a control gate having a uniform thickness as described above.

Other processes may be utilized to remove sacrificial layer 180 and partially remove protective layer 162. The portion of the protective layer 162 that remains after etching the surface of the substrate to remove the sacrificial layer 180 and partially remove the protective layer 162 depends on the particular etching process used. In one embodiment, the etch process partially removes the protective layer 162 such that the remaining portion of the protective layer has a depth of 1500-2000 angstroms. The described embodiments of the invention improve the uniformity of the BARC layer 188 deposited across the central and peripheral portions of flash memory array 104 (FIG. 1) by spin coating applying sacrificial layer 180 and removing the sacrificial layer, and partially removing the protective layer. This uniformity of the BARC layer 188 enables the formation of a gate stack 168C (fig. 3C) having a uniform thickness for the gate stack in the central and peripheral portions of the flash memory array 104.

According to an embodiment, the etching of the sacrificial layer 180 is performed directly after deposition-and if necessary-planarizing the sacrificial layer without any intermediate process steps. According to another embodiment, one or more process steps are performed between the deposition of the sacrificial layer 180 and its subsequent removal in an etching process. These intermediate process steps may include processes unrelated to the formation of the memory array 104.

Proceeding to fig. 3C, the patterned film layer 188 is patterned to form an etch mask, and the protective layer 162, the polysilicon layer 160, and the dielectric layer 158 are etched to form the gate stack 168C. In contrast to gate stacks 168a and 168b of fig. 2D, gate stack 168C of fig. 3C has substantially the same width due to the uniform thickness of BARC layer 188 and patterned film layer 186, which in turn is caused by planarized surface 184 of protective layer 162.

Fig. 3D-3E are schematic side cross-sectional views of substrate 106 showing a small portion of recessed region 140 and illustrating the fabrication process at a stage substantially completed by gate stack 168 of the memory array. In fig. 3D, one or more dielectric layers 190 are deposited over the gate stack 168. In fig. 3E, the floating gate 126 and gate dielectric 124 are formed in an etching process, wherein the gate stack 168 serves as a self-aligned mask. Finally, in fig. 3F, an oxide is formed over the gate stack 168 and etched to leave a protective dielectric layer 192 on the sides of the gate stack.

Fig. 4 and 5 are flow diagrams summarizing methods of manufacture according to various embodiments, consistent with the processes described above with reference to fig. 2A-2B and 3A-3F.

Fig. 4 outlines a method 200 according to an embodiment, wherein in step 202 a recessed region 140 is formed in the semiconductor substrate 102. In step 204, a first dielectric layer 154 is formed over the substrate 102 within the recessed region 140, and in step 206, a first polysilicon layer 156 is formed over the first dielectric layer 154. In step 208, a second dielectric layer 158 is formed, and then a second polysilicon layer 160 is formed in step 210. In step 212, a protective layer 162 is formed over the second polysilicon layer 160. In step 214, a sacrificial layer 180 is formed over the protective layer 162, self-leveling to form a planar upper surface 182. In step 216, portions of the sacrificial layer 180 and the protective layer 162 are removed together in a non-selective etching process to planarize the exposed surface 184 of the protective layer. In respective steps 218 and 220, a patterned film 186 is deposited on the surface 184 of the protective layer 162 and an antireflective coating 188 is deposited on the substrate, and the patterned film 186 is patterned in step 222. Finally, in step 224, a plurality of control gates 120 are defined in an etch process conditioned by the patterned film layer.

Fig. 5 is a flow chart summarizing a method 240 for providing a planarized surface in a manufacturing process, according to another embodiment. In step 242, a protective layer 162 is deposited on the non-planar surface on the semiconductor substrate 102. In step 244, a self-leveling sacrificial layer 180 is formed over the protective layer 162, forming a planar upper surface 182. In step 246, a non-selective etch process is performed in which the entire sacrificial layer 180 and a portion of the protective layer 162 are removed to leave a planarized surface 184 for the remaining portion of the protective layer 162.

The embodiments shown and described herein provide improvements in processes for fabricating microelectronic devices that include embedded flash memory arrays. According to various embodiments, prior to defining the control and floating gate stacks of the memory array in recessed regions on a semiconductor substrate, a planar surface is provided on the substrate over the material layers that will form the gate stacks for depositing an antireflective coating and patterning film of uniform thickness. This is beneficial because the anti-reflective coating has a tendency to vary in thickness, particularly when it is deposited on non-planar surfaces, which in turn can lead to non-uniformity in the dimensions of the control gate and the floating gate. The dimensions of the control gate and floating gate directly affect key operating characteristics of the memory device, such as read, write and erase speeds, program and erase state voltage and current levels, power consumption, and the like. If the gate dimensions vary within the memory array, it is typical to operate the entire array based on the operating characteristics of the weakest cell. Thus, significant variations in size are a problem because even if a small fraction of the cells in the array require higher voltages and/or longer read and write times, the entire array operates at the same level, resulting in a loss of efficiency and speed for the entire array. By providing a planar surface, non-uniformity in the gate dimensions of the memory array is reduced or eliminated. This in turn results in an array with higher overall speed and efficiency.

According to an embodiment, the improvement comprises forming a protective layer over a non-planar surface of a semiconductor substrate, particularly, for example, over a recessed region of the semiconductor substrate in which an embedded memory array is to be formed. A sacrificial layer is then deposited over the protective layer, the sacrificial layer having a depth sufficient to allow a substantially planar surface to be formed on the sacrificial layer. The sacrificial layer is then etched to a depth that removes the sacrificial layer and leaves a planar surface formed in the protective layer.

According to another embodiment, the method includes forming a recessed region in a semiconductor substrate, and forming a gate material for a plurality of floating gates and control gates of a memory array in a layer above the recessed region. A protective layer is then formed over the gate material in the recessed region and planarized to improve gate dimension uniformity. An etch mask is formed over the planarized protective layer and a gate stack of the memory array is formed in the recessed region by etching the gate material. According to an embodiment, planarizing the protective layer includes depositing a self-leveling sacrificial layer over the protective layer to create a substantially planar surface, then etching the surface at a uniform rate and to a depth sufficient to remove the sacrificial layer, which creates a planar surface on the protective layer.

According to another embodiment, the method includes forming a protective layer over the stack of gate material layers in the recessed region of the semiconductor substrate. A self-leveling sacrificial layer is then deposited over the protective layer, the self-leveling sacrificial layer having a depth sufficient to produce a planarized surface of the semiconductor substrate, and the sacrificial layer is etched back at a uniform rate to a depth sufficient to produce a substantially planar surface on the protective layer.

An embodiment of the present invention provides a method of forming a semiconductor device, including: forming a protective layer over a non-planar surface of a semiconductor substrate (102); forming a sacrificial layer over the protective layer; forming a surface on the sacrificial layer; and planarizing the surface of the sacrificial layer to a depth sufficient to remove the sacrificial layer and remove portions of the protective layer.

In the above method, wherein planarizing the surface of the sacrificial layer to a depth sufficient to remove the sacrificial layer and remove portions of the protective layer comprises: etching the surface of the sacrificial layer to completely remove the sacrificial layer and partially remove the protective layer.

In the above method, wherein the sacrificial layer comprises a photoresist material, and wherein forming the sacrificial layer over the protective layer and forming the surface on the sacrificial layer together comprise: spin coating a self-leveling material on the semiconductor substrate.

In the above method, wherein forming the protective layer over the non-planar surface of the semiconductor substrate comprises: the protective layer is formed over a recessed region of the semiconductor substrate.

In the above method, wherein forming the protective layer over the non-planar surface of the semiconductor substrate comprises: forming the protective layer over the recessed region of the semiconductor substrate, comprising: forming a material for a plurality of floating gates and control gates of a memory array in a layer above the recessed region prior to forming the protective layer; and forming a material for the plurality of floating gates in a layer above the recessed region.

In the above method, wherein forming the protective layer over the non-planar surface of the semiconductor substrate comprises: forming the protective layer over the recessed region of the semiconductor substrate, comprising: forming a material for a plurality of floating gates and control gates of a memory array in a layer above the recessed region prior to forming the protective layer; and forming a material for the plurality of floating gates in the layer above the recessed region, wherein forming the material for the plurality of floating gates in the layer above the recessed region comprises: forming a first dielectric layer over the semiconductor substrate; forming a first polysilicon layer over the first dielectric layer; forming a second dielectric layer over the first polysilicon layer; and forming a second polysilicon layer over the second dielectric layer.

Yet another embodiment of the present invention provides a method of forming a semiconductor device, including: forming a recess region in a semiconductor substrate; forming gate material for a plurality of floating gates and control gates of a memory array in a layer above the recessed region; forming a protective layer over the gate material in the recessed region; planarizing the protective layer; forming an etching mask layer over the planarized protection layer; and forming a plurality of gate stacks in the recessed regions by etching the gate material.

In the above method, wherein planarizing the protective layer comprises: forming a sacrificial layer over the protective layer; planarizing the sacrificial layer; and after planarizing the sacrificial layer, etching the planarized surface of the sacrificial layer at a uniform rate across the recessed region to a depth sufficient to leave a planarized surface on the protective layer.

In the above method, wherein planarizing the protective layer comprises: forming a sacrificial layer over the protective layer; planarizing the sacrificial layer; and after planarizing the sacrificial layer, etching the planarized surface of the sacrificial layer at a uniform rate across the recessed region to a depth sufficient to leave a planarized surface on the protective layer, wherein etching the planarized surface of the sacrificial layer to a depth sufficient to leave a planarized surface on the protective layer comprises: the planarized surface of the sacrificial layer is etched to a depth sufficient to completely remove the sacrificial layer.

In the above method, wherein planarizing the protective layer comprises: forming a sacrificial layer over the protective layer; planarizing the sacrificial layer; and after planarizing the sacrificial layer, etching a planarized surface of the sacrificial layer at a uniform rate across the recessed region to a depth sufficient to leave a planarized surface on the protective layer, wherein forming the sacrificial layer over the protective layer and planarizing the sacrificial layer together comprise: depositing a self-leveling sacrificial layer over the protective layer.

In the above method, wherein planarizing the protective layer comprises: forming a sacrificial layer over the protective layer; planarizing the sacrificial layer; and after planarizing the sacrificial layer, etching a planarized surface of the sacrificial layer at a uniform rate across the recessed region to a depth sufficient to leave a planarized surface on the protective layer, wherein forming the sacrificial layer over the protective layer and planarizing the sacrificial layer together comprise: depositing a self-leveling sacrificial layer over the protective layer, wherein depositing the self-leveling sacrificial layer over the protective layer comprises: the self-leveling sacrificial layer is deposited using a spin-on process.

In the above method, wherein planarizing the protective layer comprises: forming a sacrificial layer over the protective layer; planarizing the sacrificial layer; and after planarizing the sacrificial layer, etching the planarized surface of the sacrificial layer at a uniform rate across the recessed region to a depth sufficient to leave a planarized surface on the protective layer, wherein etching the planarized surface of the sacrificial layer comprises: the planarized surface of the sacrificial layer is etched directly after deposition and planarization of the sacrificial layer without intermediate process steps.

In the above method, wherein forming the etch mask layer over the planarized protection layer comprises: forming an anti-reflective coating over the planarized protective layer; and forming the etch mask layer over the antireflective coating.

In the above method, wherein forming the gate material for the plurality of floating gates and control gates comprises: forming a gate dielectric layer over the recessed region; forming a first polysilicon layer over the gate dielectric layer; forming an inter-gate dielectric layer over the first polysilicon layer; and depositing a second polysilicon layer on the inter-gate dielectric layer.

In the above method, wherein forming the gate material for the plurality of floating gates and control gates comprises: forming a gate dielectric layer over the recessed region; forming a first polysilicon layer over the gate dielectric layer; forming an inter-gate dielectric layer over the first polysilicon layer; and depositing a second polysilicon layer on the inter-gate dielectric layer, wherein forming the plurality of gate stacks in the recessed region comprises: providing the etching mask layer having a pattern corresponding to a gate pattern; and etching the inter-gate dielectric layer and the second polysilicon layer using the patterned etch mask layer.

Yet another embodiment of the present invention provides a method of forming a semiconductor device, including: forming a protective layer over the stack of gate material layers in the recessed region of the semiconductor substrate; depositing a sacrificial layer over the protective layer, the sacrificial layer having a depth sufficient to create a planarized surface on the semiconductor substrate; and removing the sacrificial layer to a depth sufficient to create a planar surface on the protective layer.

In the above method, wherein forming the protective layer comprises: forming the protective layer comprising one or more of amorphous silicon, oxide, and nitride.

In the above method, wherein depositing the sacrificial layer comprises: and spin-coating a photoresist material layer on the semiconductor substrate.

In the above method, wherein forming the protective layer over the stack of gate material layers in the recessed region of the semiconductor substrate comprises: forming the protective layer comprising a first dielectric layer, a first polysilicon layer, a second dielectric layer, and a second polysilicon layer over the stack of gate material layers.

In the above method, further comprising: after removing the sacrificial layer, a plurality of gate stacks are formed from the stack of gate material layers and the protective layer.

An embodiment of the present invention provides a semiconductor device including: a semiconductor substrate including a recessed region having a central portion and an outer peripheral portion; and a flash memory array in the recessed region, the flash memory array including a plurality of gate stacks, and each of the gate stacks having a width, the width of the gate stacks being uniform for the gate stacks in the central portion of the recessed region and the gate stacks in the peripheral portion of the recessed region.

In the above semiconductor device, wherein each of the gate stacks includes: a floating gate on the recessed region of the semiconductor substrate; the control grid is positioned on the floating grid; and the protective cap layer is positioned on the floating gate.

In the above semiconductor device, wherein each of the gate stacks includes: a floating gate on the recessed region of the semiconductor substrate; the control grid is positioned on the floating grid; and the protective cap layer is positioned on the floating gate, wherein the protective cap layer has the depth of 1500-2000 angstroms.

In accordance with conventional claim practice, ordinal numbers are used in the claims, e.g., first, second, third, etc., i.e., to clearly distinguish between claimed elements or features thereof. Ordinal numbers may be arbitrarily assigned or simply assigned in the order in which the elements are introduced. The use of such numbers does not indicate any other relationship, such as order of operation, relative position of the elements, etc. Furthermore, ordinal numbers used to refer to elements in the claims should not be assumed to be associated with numerals used in the specification to refer to elements of the disclosed embodiments that are read by the claims, nor are numerals used to refer to similar elements or features in unrelated claims.

Although the method and process steps recited in the claims may be presented in an order corresponding to the steps disclosed and described in the specification, unless explicitly stated otherwise, the order in which the steps are presented in the specification or claims is not limited to the order in which the steps may be performed.

The abstract of the invention is provided as a brief summary of some principles of the invention according to embodiments, and is not intended as a complete or definitive description of any embodiment thereof, nor should it be relied upon to define terms used in the specification or claims. The abstract does not limit the scope of the claims.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.