阅读说明：本技术 储存装置及其nand快闪记忆体控制器 (Storage device and NAND flash memory controller thereof ) 是由 黄识夫 林书民 吴若华 陈政宇 于 2018-09-07 设计创作，主要内容包括：本发明公开了储存装置及其NAND快闪记忆体控制器。一种快闪记忆体控制器适于一NAND快闪记忆体及一电压供应电路,该电压供应电路供应一电流给该快闪记忆体。快闪记忆体控制器包括快闪控制电路、电流感测电路、及处理器。快闪控制电路用以控制该快闪记忆体之操作,电流感测电路用以量测该快闪记忆体于该操作时的该电流,并输出一电流值,处理器用以依据该电流值输出一控制信号。因此,快闪记忆体控制器可即时获得快闪记忆体运作时消耗的电流值,并据以判断快闪记忆体运作是否正常。具有该快闪记忆体控制器的储存装置可即时判断快闪记忆体运作是否正常。(The invention discloses a storage device and a NAND flash memory controller thereof. A flash memory controller is suitable for a NAND flash memory and a voltage supply circuit which supplies a current to the flash memory. The flash memory controller includes a flash control circuit, a current sensing circuit, and a processor. The flash control circuit is used for controlling the operation of the flash memory, the current sensing circuit is used for measuring the current of the flash memory during the operation and outputting a current value, and the processor is used for outputting a control signal according to the current value. Therefore, the flash memory controller can obtain the current value consumed by the flash memory during operation in real time, and determine whether the flash memory is operating normally. The storage device with the flash memory controller can immediately determine whether the flash memory is operating normally.)

1. A flash memory controller, suitable for a NAND flash memory and a voltage supply circuit supplying a current to the NAND flash memory, the flash memory controller comprising:

a flash control circuit for controlling the operation of the NAND flash memory;

a current sensing circuit for measuring the current of the NAND flash memory during the operation and outputting a current value; and

a processor for outputting a control signal according to the current value.

2. The flash memory controller of claim 1, wherein the current sensing circuit comprises:

a current-to-voltage circuit connected between the voltage supply circuit and the NAND flash memory for converting the current to a differential voltage;

a sensing control circuit for generating a level signal;

a level generating circuit for generating a plurality of levels according to the level signal; and

a flash analog-to-digital conversion circuit for outputting a digital signal according to the differential voltage and the levels, and the sensing control circuit outputs the current value according to the level signal and the digital signal.

3. The flash memory controller of claim 2, wherein the level generating circuit comprises:

an adjustable current source for generating a reference current according to the level signal; and

a plurality of resistors connected in series in sequence, the resistors receiving the reference current to generate the levels.

4. The flash memory controller of claim 3, wherein the sense control circuit receives a plurality of the digital signals in a time sequence and adjusts the level signal according to the digital signals.

5. A storage device, comprising:

a NAND flash memory;

a voltage supply circuit for supplying a current to the NAND flash memory; and a flash memory controller, comprising:

a flash control circuit for controlling the operation of the NAND flash memory;

a current sensing circuit for measuring the current of the NAND flash memory during the operation and outputting a current value; and

a processor for outputting a control signal according to the current value.

6. The storage device of claim 5, wherein the current sensing circuit comprises:

a current-to-voltage circuit connected between the voltage supply circuit and the NAND flash memory for converting the current to a differential voltage;

a sensing control circuit for generating a level signal;

a level generating circuit for generating a plurality of levels according to the level signal; and

a flash analog-to-digital conversion circuit for outputting a digital signal according to the differential voltage and the levels, and the sensing control circuit outputs the current value according to the level signal and the digital signal.

7. The storage device of claim 6, wherein the level generating circuit comprises:

an adjustable current source for generating a reference current according to the level signal; and

a plurality of resistors connected in series in sequence, the resistors receiving the reference current to generate the levels.

8. The storage device of claim 7, wherein the sensing control circuit receives a plurality of the digital signals in a time sequence and adjusts the level signal according to the digital signals.

9. The storage device according to any one of claims 5 to 8, wherein the processor determines whether the plurality of current values are normal when receiving the plurality of current values, and outputs the control signal as a normal signal when the plurality of current values are normal, and outputs the control signal as an abnormal signal when the plurality of current values are abnormal.

10. The storage device according to any one of claims 5 to 8, wherein the processor compares the currents with a predetermined current sample to determine whether the current values are normal when receiving a plurality of the current values, the processor outputs the control signal as a normal signal when the current values are normal, and outputs the control signal as an abnormal signal when the current values are abnormal.

Technical Field

The present invention relates to a flash memory controller, and more particularly to a NAND flash memory controller.

Background

NAND Flash memories (NAND Flash memories) are mostly applied to Solid State Drives (SSDs), portable disks and memory cards, depending on their memory characteristics.

Each Cell (Cell) of a NAND flash memory represents its stored information by its voltage level. Taking a Triple-Level Cell (TLC) as an example, each Triple-Level Cell can store 8 different contents, including: 111,011,001,101,100,000,010,110, the 8 contents each correspond to one of 1 erase level (erasetate) and 7 program levels (ProgramStates). Specifically, when the recording voltage of a third-order cell falls to a certain level, it indicates that the content stored in the third-order cell is the content corresponding to the level.

In order to ensure the correctness of the written data in the NAND flash memory, after a storage unit is written in, a controller in the flash memory reads the voltage of the storage unit and determines whether the voltage reaches a predetermined voltage range (higher than the lower limit of the corresponding level), and if the voltage does not reach the predetermined voltage range, the voltage is written again until the voltage of the storage unit reaches the predetermined voltage range, which is generally called Verification (Verification). Therefore, for the storage unit with better characteristics or the storage unit with the early life, the operating voltage is lower or the number of times of being written is still less; for the storage units with poor characteristics or worn-out, the storage units, memory pages and memory blocks in the NAND flash memory can be written repeatedly, the number of times of writing in each storage unit, memory page and memory block is different, and the number of times of programming and erasing of the NAND flash memory directly influences the service life of the NAND flash memory.

One way is to determine the possible lifetime of the NAND flash memory by monitoring whether the Error Corrected Code (ECC) tends to increase. However, since the above-mentioned verification mechanism is applied to the flash memory, the ECC will not change significantly under normal operation conditions, and therefore, if the ECC is monitored, it is often the imminent end of life of a certain block of the flash memory when the instantaneous surge of ECC is found. Therefore, the method of monitoring ECC cannot effectively know the current life status of the flash memory.

One way is to use a Cell Voltage Distribution diagram (ISPP, integrated step programming pulse) to determine, where the threshold Voltage Distribution diagram refers to a graph plotting the recording Voltage of each storage unit in the whole Page (Page) or Block (Block), and the horizontal axis of the graph is Voltage and the vertical axis is the number of storage units. When the flash memory state is normal, the voltage of each storage unit in the voltage distribution chart will fall at the corresponding level. When the flash memory is abnormal, the number of the storage units falling at the corresponding level is greatly reduced. As mentioned above, since the flash memory has the above-mentioned verification mechanism, when the threshold voltage distribution diagram shows an abnormal condition, the lifetime of the flash memory is approaching, so the method can not effectively know the current lifetime status of the flash memory.

Disclosure of Invention

In addition to the foregoing methods having the ability to only identify the imminent end of life of the flash memory, known methods need to be operable off-line (removing the NAND flash memory from the storage device or system).

In view of the above, the present disclosure provides a flash memory controller, which is suitable for a NAND flash memory and a voltage supply circuit, which supplies a current to the flash memory. The flash memory controller includes a flash control circuit, a current sensing circuit, and a processor. The flash control circuit is used for controlling the writing, reading and erasing of the flash memory, the current sensing circuit is used for measuring the current of the flash memory during the operation and outputting a current value, and the processor is used for outputting a control signal according to the current value.

According to some embodiments, the current sensing circuit includes a current-to-voltage circuit, a sensing control circuit, a level generation circuit, and a flash ADC circuit. The current-to-voltage circuit is connected between the voltage supply circuit and the flash memory and is used for converting the current into a differential voltage. The sensing control circuit is used for generating a level signal, the level generating circuit is used for generating a plurality of levels according to the level signal, the flash analog-to-digital conversion circuit is used for outputting a digital signal according to the differential voltage and the levels, and the sensing control circuit outputs the current value according to the level signal and the digital signal.

According to some embodiments, the level generating circuit includes an adjustable current source and a plurality of resistors. The adjustable current source is used for generating a reference current according to the level signal; the resistors are connected in series in sequence, and the resistors receive the reference current to generate the levels.

According to some embodiments, the sensing control circuit receives a plurality of the digital signals in a time sequence and adjusts the level signal according to the digital signals.

According to some embodiments, the storage device includes the aforementioned flash memory controller, a voltage supply circuit, and a NAND flash memory. The voltage supply circuit is used to provide a current to the flash memory. The flash memory controller includes a flash control circuit, a current sensing circuit, and a processor. The flash control circuit is used for controlling the writing of the flash memory, the current sensing circuit is used for measuring the current of the flash memory during the operation and outputting a current value, and the processor is used for outputting a control signal according to the current value.

In summary, according to some embodiments, the flash memory controller can obtain the current value consumed by the flash memory during operation in real time, and accordingly determine whether the flash memory is operating normally. According to some embodiments, the storage device with the flash memory controller can determine whether the flash memory is operating normally in real time.

Drawings

FIG. 1 is a schematic block diagram of an embodiment of the storage device.

FIG. 2 is a block diagram of an embodiment of the current sensing circuit.

FIG. 3 is a block diagram of an embodiment of a flash ADC circuit.

FIG. 4 is a schematic diagram illustrating the current sensing result of an embodiment of the current sensing circuit.

Fig. 5 is a partially enlarged view of the position marked 5 to 5 in fig. 4.

Description of the symbols

10 storage device 20 NAND flash memory

30 voltage supply circuit 200 block

40 flash memory controller 42 flash control circuit

44 current sensing circuit 46 processor

440 current-to-voltage circuit 441 resistor

442 sensing control circuit 444 level generating circuit

445a Adjustable Current Source 445b resistor

446 flash analog-to-digital converter 448M-to-N coding circuit

447a,447b,447c,447d differential comparator

DI input DO output pin

PRG programming interval Vip, Vin differential voltage

Vrm, Vrm-1 …, Vr1, Vr0 levels

Detailed Description

Referring to fig. 1, fig. 1 is a schematic circuit block diagram of an embodiment of the storage device. The storage device 10 includes a NAND flash memory 20, a voltage supply circuit 30, and a flash memory controller 40.

The storage device 10 may be any storage device having the NAND flash memory 20, and in some embodiments, the storage device 10 is a Solid State Drive (SSD), a flash Drive, or a memory card.

The voltage supply circuit 30 is used to provide a current to the flash memory 20. Flash memory controller 40 is adapted for NAND flash memory 20 and voltage supply circuit 30. flash memory controller 40 controls the operation of flash memory 20, including programming (Program), erasing (Erase) and reading, where programming and erasing may be collectively referred to as writing. The flash memory 20 includes a plurality of blocks (blocks) 200, each Block 200 includes a plurality of pages (not shown), and Block Erase (Block Erase) is used when the flash memory 20 is erased; when programming the flash memory 20, a page program (PageProgram) is used. The amount of current required by the flash memory 20 during programming, erasing and reading is different, and the current is supplied by the voltage supply circuit 30.

The flash memory controller 40 includes a flash control circuit 42, a current sense circuit 44, and a processor 46. The flash control circuit 42 is used to control the writing of the flash memory 20, specifically, the flash control circuit 42 controls the programming and erasing of the flash memory 20. In addition, the flash control circuit 42 also controls the operations of reading the flash memory 20. Flash control circuit 42 controls flash control circuit 42 to control flash memory 20 to write or read according to the control of processor 46.

The current sensing circuit 44 is used to measure the current of the flash memory 20, for example, the current sensing circuit 44 is used to measure the current of the flash memory 20 during the write operation and output a current value. Specifically, the current-to-voltage circuit 440 of the current sensing circuit 44 is connected between the voltage supply circuit 30 and the flash memory 20 (between the power lines), the current-to-voltage circuit 440 has a current sensor, such as but not limited to a resistor 441, when the voltage supply circuit 30 supplies current to the flash memory 20 through the current-to-voltage circuit 440, a differential voltage (Vip, Vin, Vip being P-potential and Vin being N-potential) is generated across the current-to-voltage circuit 440, and the current sensing circuit 44 divides the differential voltage (Vip, Vin) by the impedance of the current sensor (such as but not limited to the impedance of the resistor 441) to obtain the current value consumed by the flash memory 20 during the writing. Similarly, the current sensing circuit 44 can also be used to measure the current consumed by the flash memory 20 during the erasing or reading process and output a current value.

The processor 46 is used for outputting a control signal according to the current value. Specifically, the processor 46 receives the current value outputted from the current sensing circuit 44 and outputs a control signal according to the current value. In some embodiments, when the current value exceeds the predetermined upper limit of the one-time programming current, the control signal output by the processor 46 is an abnormal signal, and the error location of the flash memory can be recorded. The upper limit of the one-time programming current may be a value of abnormal current that is determined whether the flash memory 20 consumes during one-time programming.

Other embodiments of the processor 46 outputting the control signal according to the current value will be described in detail later.

Therefore, as can be seen from the above description, the flash memory controller 40 can measure the current consumed by the flash memory 20 during the programming, erasing, reading, etc. operations in real time by the current sensing circuit 44. The processor 46 determines whether the operating state of the flash memory 20 is maintained in a normal state according to the current value. In addition to the real-time measurement, the processor 46 can know whether a page or a block is damaged or not in real time while the flash memory 20 is operating, the processor 46 can use a statistical method to predict the possible damage time of the flash memory 20 by collecting a sufficient amount of current (in terms of time), or the number of write, erase, or read operations that can be used continuously.

Next, the current converting circuit 440 of the current sensing circuit 44 of fig. 1 is located outside the flash memory controller 40, but in some embodiments, the current converting circuit 440 is built in the flash memory controller 40, and the current outputted by the voltage supply circuit 30 is still transmitted to the flash memory 20 through the current converting circuit 440.

Referring to fig. 2, fig. 2 is a schematic circuit block diagram of an embodiment of the current sensing circuit. In some embodiments, the current sensing circuit 44 includes a current converting circuit 440, a sensing control circuit 442, a level generating circuit 444, and a flash analog to digital converting circuit 446.

The current-to-voltage circuit 440 is connected between the voltage supply circuit 30 and the flash memory 20 and is used to convert the current into a differential input, node A of the current-to-voltage circuit 440 of FIG. 2 is connected to the voltage supply circuit 30, and node B is connected to the flash memory 20. When the flash control circuit 42 controls the flash memory 20 to perform writing (programming or erasing) or reading, the current provided by the voltage supply circuit 30 passes through the resistor 441, the two ends (nodes A, B) of the resistor 441 respectively have a P potential Vip and an N potential Vin, i.e. the two ends of the resistor 441 have a differential voltage (Vip, Vin), and the current sensing circuit 44 divides the difference value (Vip-Vin) of the differential voltage by the resistance of the resistor 441 to obtain the current value.

The sensing control circuit 442 is used for generating a level signal. The level signal is related to the current value. The range of the measurable current value is larger as the level signal is higher, and smaller as the level signal is lower, as will be described in detail later.

The level generating circuit 444 generates a plurality of levels Vrm, Vrm-1Vr0 according to the level signal. The number of levels of the level generation circuit 444 is the resolution of the current sensing circuit 44. For example, if the level generation circuit 444 can generate 2 to 3 levels, the flash analog to digital conversion circuit 446 is configured to express the output as two bits (2bits), i.e., DO [1:0 ]. If the level generation circuit 444 is capable of generating 4 to 7 levels, the flash analog to digital conversion circuit 446 is configured to output three bits (3bits), i.e., DO [2:0 ].

In some embodiments, the level generating circuit 444 includes an adjustable current source 445a and a plurality of resistors 445 b. The adjustable current source 445a is used for correspondingly generating a reference current according to the level signal. The resistors 445b are serially connected in sequence, and the resistors 445b receive the reference current to generate the levels Vrm, Vrm-1 …, Vr1, Vr 0.

The sensing control circuit 442 controls the magnitude of the reference current generated by the adjustable current source 445a by using the level signal, wherein the reference current is larger when the level signal is higher, and the reference current is smaller when the level signal is lower. When the reference current is larger, the voltage difference between the two ends of the resistor 445b after being connected in series is larger, so that the voltage difference (Vrm-Vr0) of the maximum level generated by the level generating circuit 444 is larger under the same resolution, and the difference (corresponding current value) of the differential voltage measured by the sensing control circuit 442 is larger. On the contrary, when the reference current is smaller, the voltage difference between the two ends of the resistor 445b after being connected in series is smaller, so that the voltage difference (Vrm-Vr0) of the maximum level generated by the level generating circuit 444 is smaller under the same resolution, and the difference of the differential voltage measured by the sensing control circuit 442 is smaller.

The flash ADC 446 outputs a digital signal according to the differential voltage (Vip-Vin) and the levels Vrm, Vrm-1Vr 0. In some embodiments, the flash adc 446 compares the difference between the differential voltages (Vip, Vin) with the differences between the levels Vrm, Vrm-1 …, Vr0 (Vrm-Vr0, Vrm-1-Vr 0, etc.) to obtain the level difference corresponding to the difference between the differential voltages (Vip-Vin), and the flash adc 446 converts the corresponding level difference into a binary value and outputs the binary value as the digital signal. The digital signal corresponds to the level difference.

The sensing control circuit 442 outputs the current value according to the level signal and the digital signal, which will be described in detail later.

Referring to fig. 3, fig. 3 is a schematic circuit block diagram of an embodiment of the flash adc according to the present invention. The flash adc 446 includes a plurality of differential comparators (comp)447a,447b,447c,447d and an M-to-N encoder circuit 448 (M-to-N encoder logic), each of the differential comparators 447a,447b,447c,447d receiving and comparing the difference value of the differential voltage (Vip-Vin) with the corresponding level difference value Vrm, Vrm-1 …, Vr2, Vr1, Vr0, when the difference value of the differential voltage (Vip-Vin) is greater than the corresponding level difference value Vrm, Vrm-1 …, Vr2, Vr1, Vr0, the differential comparator 447a,447b,447c,447d outputs 1 (high level), otherwise outputs 0 (low level). Thus, when the difference in differential voltages (Vip-Vin) falls between levels Vrm and Vrm-1, the first differential comparator 447a outputs a 0 and the remaining differential comparators 447b,447c,447d output 1.

The M-to-N encoding circuit 448 encodes an input signal, converts the encoded input signal into a binary value, and outputs the binary value as the digital signal. Continuing with the above example, if the flash adc circuit includes 4 differential comparators 447a,447b,447c,447d, the first differential comparator 447a outputs 0, and the remaining differential comparators 447b,447c,447d output 1, at this time, the M-to-N coding circuit 448 receives a value of 0,1,1,1 from top to bottom, i.e., the M-to-N coding circuit 448 codes the value into DO [2:0] ═ 011 (binary). The M-to-N encoding circuit 448 may be implemented by a logic circuit.

Referring to fig. 2 again, continuing with the above example of the flash analog to digital circuit 446, if the number of the resistors 445b is 4 and the resistance of each resistor 445b is equal to 1k ohm, the level signal output by the sensing control circuit 442 makes the reference current output by the adjustable current source 445 be 10uA, the level generated by the level generating circuit 444 is 0mV,10mV,20mV,30mV and 40mV, the voltage difference of the levels includes 10mV,20mV,30mV and 40mV, that is, the voltage difference received by the differential comparators 447a,447b,447c and 447d is 40mV,30mV,20mV and 10mV, respectively. When the digital signal output value is DO [2:0] ═ 011 (binary), that is, the differential voltage output by the current-to-voltage circuit 440 is between 30-40mV corresponding to DO [2:0] = 011. If the resistance of the resistor 441 is 0.5 ohm, the current of the flash memory during the write is 60-80 mA.

Further to the above example of the flash adc 446, if the number of the resistors 445b is 4 and the resistance of each resistor 445b is equal to 1k ohm, the level signal output by the sensing control circuit 442 makes the reference current output by the adjustable current source 445 be 20uA, the level generated by the level generating circuit 444 is 0mV,20mV,40mV,60mV and 80mV, and the voltage differences of the levels include 20mV,40mV,60mV and 80mV, i.e. the differential comparators 447a,447b,447c and 447d respectively receive level voltage differences of 80mV,60mV,40mV and 20 mV. When the digital signal output value is DO [2:0] ═ 011 (binary), that is, the differential voltage output by the current-to-voltage circuit 440 is between 60-80mV corresponding to DO [2:0] = 011. If the resistance of the resistor 441 is 0.5 ohm, the current of the flash memory during the write operation is between 120 mA and 160 mA.

As can be seen from the above two examples, the flash ADC circuit 446 outputs the same digital signal, the voltage value represented by the same digital signal is related to the level, and the higher the level (level voltage difference), the larger the voltage value represented by the same digital signal; when the level (voltage difference) is lower, the voltage value represented by the same digital signal is smaller. As described above, the levels are determined by the level signal from the sensing control circuit 442. Therefore, the sensing control circuit 442 can obtain the corresponding voltage value and current value according to the level signal and the digital signal.

Secondly, during operation, the sensing control circuit 442 continuously obtains a plurality of current values, when the digital signal continuously received by the sensing control circuit 442 is the upper limit of the output of the flash adc 446 (for example, the upper limit is DO [2:0] ═ 100), which means that the continuously received differential voltage is higher than the maximum level voltage difference (Vrm-Vr0) generated by the level generating circuit 444, therefore, the sensing control circuit 442 increases the level signal, so that the current sensing circuit 44 can further measure the actual differential voltage value of the differential voltage; conversely, when the digital signal continuously received by the sensing control circuit 442 is the lower limit of the output of the flash adc 446 (for example, the lower limit of the output is DO [2:0] ═ 000), which means that the differential voltage continuously received is lower than the lowest level voltage difference (Vr1-Vr0) generated by the level generating circuit 444, the sensing control circuit 442 lowers the level signal, so that the current sensing circuit 44 can further measure the actual differential voltage value of the differential voltage.

As can be seen from the above description, the sensing control circuit 442 receives a plurality of the digital signals in a time sequence, and adjusts the level signal according to the digital signals. Specifically, the sensing control circuit 442 determines the magnitude of the output level signal according to the continuously obtained current value, so as to more accurately measure the current value consumed by the flash memory 20. When the majority of the digital signals continuously received by the sensing control circuit 442 (for example, but not limited to, 90% of the digital signals continuously received) are between the upper limit and the lower limit of the output of the flash analog-to-digital converter 446, that means the current level signal is appropriate, the sensing control circuit 442 maintains the level signal. Secondly, when the flash memory controller 40 starts to operate, the sensing control circuit 442 can use a preset value as the level signal, and after a period of adjustment of the level signal, an appropriate level signal can be obtained. The default value can be obtained experimentally by designing or testing values in the flash memory controller 40.

The sampling frequency of the flash ADC circuit 446 is related to the time of one-time programming, erasing and reading of the flash memory 20, and is illustrated by the time-current diagram of the flash memory 20 in FIG. 5 (described in detail later), which shows that the time of one-time programming is about 5 microseconds (us), and if 5 sampling points (5 digital signals) are to be obtained in the time of one-time programming, the sampling frequency of the flash ADC circuit 446 can be 1 MHz.

To assist in understanding some embodiments in which processor 46 outputs control signals based on the current values consumed by flash memory 20, a time-current plot of a plurality of current values received by processor 46 is described. Referring to fig. 4 and 5, fig. 4 is a schematic diagram illustrating a current sensing result of an embodiment of the current sensing circuit. Fig. 5 is a partially enlarged view of the position marked 5 to 5 in fig. 4.

FIG. 4 is a graph of time-current with time on the horizontal axis (from 730 milliseconds us to 9.73 microseconds ms) and current on the vertical axis of the graph, which is continuously received by the processor 46 during data programming of the flash memory 20 by the processor 40 via the flash control circuit 42, and is plotted by the processor 46. The upper curve in the time-current diagram is the current value during programming, and the lower curve represents the ongoing process of the flash memory 20. For example, the PRG time interval is shown as the time interval during which flash memory 20 is being programmed, and the time interval between two adjacent PRG program intervals is used for flash control circuit 42 to transfer data to flash memory 20. Similarly, when the processor 46 performs a data erase operation on the flash memory 20 through the flash control circuit 42, an erase time-current diagram can also be obtained; when the processor 46 performs a data read operation on the flash memory 20 through the flash control circuit 42, a read time-current diagram can also be obtained.

As can be seen in FIG. 5, the noise level current value is about 44.8 mA. In the 3.92ms to 4.42ms interval, the maximum current during programming is about 40mA (i.e., 84.8-44.8 mA), while the lower current during the programming time interval is about 5.2mA (i.e., 50-44.8 mA). As can be seen from the plurality of current values in the PRG interval of fig. 5, most of the measured current values (called as the programmed current values, described in detail later) are between 5.2mA and 40mA, and there is no excessive current value at the lower limit or the upper limit, which means that the level signal outputted by the sensing control circuit 442 is appropriate and there is no need to increase or decrease the level signal.

The single program interval (PRG) in fig. 4 corresponds to the programming of a specific page (referred to as page programming), and the time interval of 3.92-4.42 ms in fig. 5 corresponds to the "page programming" of a specific page, each "page programming" includes a plurality of "programming operations", i.e., each peak of the current in fig. 5 corresponds to one programming operation of the flash memory 20 for the page, and the current measured in a single programming operation is referred to as the programming current. The programming operation refers to that after the flash memory 20 receives data to be written (including programming and erasing) from the flash control circuit 42 (the written data correspond to 111,011,001,010,100,000,101,110, and are divided into eight groups), a programming operation is performed on each storage Cell (Cell) in the page (first time), in some embodiments, the programming Pulse voltage (ProgramPulse) used in the first programming operation corresponds to the lowest voltage level of the 1 Erase level (Erase State) and the 7 programming levels (Program States), after the first programming operation is completed, it is determined whether the storage Cell to be written with the lowest voltage level (referred to as verify) already exists, if the lowest voltage level is reached, the flash memory 20 does not apply the programming Pulse voltage (Program Pulse) to the storage Cell at the next (second) programming operation, that is, the flash memory 20 only performs the programming operation corresponding to the next lower voltage level for the remaining storage units; upon completion of the second programming operation, the flash memory 20 also performs Verification (Verification), and so on, until the programming operation corresponding to the highest voltage level is completed. That is, each memory cell is applied with a Program Pulse voltage (Program Pulse) 1 to N times (N is a positive integer greater than 1) according to the data content to be stored.

As mentioned above, in the normal situation of the flash memory 20, the programming pulse voltage is applied 1 to N times to program each Cell (Cell), i.e. the programming operation is performed N times to the Cell, so that the recording voltage stored in the Cell falls within the corresponding programming level interval. The high current values in fig. 4 and 5 correspond to programming of the memory cells with a higher number of programming operations (which store higher programming levels of data), while the lower current values correspond to programming of the memory cells with a lower number of programming operations (which store lower programming levels of data). For example, the programming level of data 011 is lower than the programming level of data 110 in the third level of memory cells, so that the required current for programming 011 in a certain memory cell of flash memory 20 is lower than the current for programming 110.

On the contrary, when a certain memory cell is worn out excessively or is nearing the end of its life, the number of programming operations of the flash memory 20 to the memory cell is higher than the normal number, so that the recording voltage stored in the memory cell can be matched with the corresponding programming level, and therefore, the overall current consumption for programming the memory cell is larger than that of the normal memory cell. If the entire page or block includes more storage units that are over worn or are imminent to the end of life, the total current consumption corresponding to the page or block will increase, and thus, the processor 46 can determine whether the page or block is abnormal or is about to be abnormal by setting the sum, block and threshold of the total current value of the page.

Some embodiments of the processor 46 outputting the control signal according to the current value consumed by the flash memory 20 are described below.

In some embodiments, the processor 46 determines whether a page or a sector in the flash memory 20 is in a normal state according to the current value, and outputs a corresponding control signal. Specifically, the processor 46 determines whether the current values are normal when receiving a plurality of current values corresponding to a certain page, the control signal output by the processor 46 is a normal signal when the current values are normal, and the control signal output by the processor 46 is an abnormal signal when the current values are abnormal. The current value may be a current value in a page writing operation, a current value in a page programming operation, a current value in a page erasing operation, or a current value in a page reading operation.

In some embodiments, the determining according to the plurality of current values is as follows: when the sum of the total current values corresponding to a certain page is greater than a page and a threshold, the page is abnormal; otherwise, the page is normal. The page and threshold refer to the total amount of current consumed in the flash memory 20 when a page is written (including programming and erasing). In some embodiments, a page is abnormal when the sum of the total programming current values corresponding to the page is greater than a page programming sum threshold; otherwise, the page is normal. The total current of the page may also be a total current of page erase, and the page and the threshold correspond to the page erase and the threshold.

In some embodiments, the determining according to the plurality of current values is as follows: when the proportion of the quantity of the programming current value in a certain page which is larger than the upper limit of the programming current to the whole quantity is larger than twenty percent, the page belongs to an abnormity; otherwise, the page is normal. The programming current value is a current value measured in each programming operation of the flash memory 20 during page programming (Program), for example, each peak value in fig. 5; the upper programming current limit indicates that most of the memory cells of the page are likely to be near defective if the current of the flash memory 20 is greater than the upper programming current limit during a single programming operation. Therefore, if the ratio of the total number of times that the programming current value is greater than the upper limit of the programming current to the total number of programming operations (i.e., the number of times of programming operations in page programming) is greater than twenty percent during page programming, it is determined that the page is abnormal.

In some embodiments, when the sum of the total current values corresponding to a block is greater than a block sum threshold, the block is abnormal; otherwise, the block is normal. The total block current value and the block and threshold may be changed to the total block current value and the block and threshold for programming and erasing. In some embodiments, the determining method according to the plurality of current values is: when the proportion of the quantity of each programming current value in a certain block which is larger than the upper limit of the programming current to the whole quantity is larger than twenty percent, the block belongs to an abnormity; otherwise, the block is normal.

In some embodiments, when the processor 46 receives a plurality of current values, the processor 46 compares the current values with a predetermined current sample to determine whether the current values are normal. When the current values are normal, the processor 46 outputs the control signal as a normal signal; when the current values are abnormal, the output control signal is an abnormal signal. The predetermined current sample is an upper limit of a slope between pages, the processor 46 determines a plurality of current values of a plurality of pages received continuously, for example, an average value of 10% of the highest current values in each page is obtained, an approximation line operation is performed on the average values of the successive pages to obtain a slope of the approximation line, when the slope of the approximation line is greater than the upper limit of the slope of the successive pages, the processor 46 determines that the pages are abnormal or that blocks to which the pages belong are abnormal, and the output control signal is an abnormal signal.

The processor 46 determines that a page or a block is abnormal based on the current value is not that the page or the block is damaged but is likely to be damaged, and thus the abnormality may be that damage is imminent. The processor 46 determines whether a page or a block is normal according to the current value, which means that the page or the block is not abnormal according to the determination method, but does not mean that the page or the block is not determined to be abnormal (may be damaged) by other determination methods. When the processor 46 determines that a page or a block is normal according to a certain determination method, the control signal may not be output.

When the control signal output by the processor 46 is abnormal, the processor 46 may further indicate that the page or block corresponding to the abnormality is damaged, so as to avoid generating errors in the information written into the page or block. The processor 46 may be configured with a Bad Block Management (BBM) mechanism to manage the Bad blocks.

The page and threshold, page program and threshold, page erase and threshold, upper programming current limit, sum of total page current values, block and threshold, and upper inter-page slope limit described in some of the above embodiments can be obtained experimentally. For example, burn-in tests can be performed on a plurality of flash memories 20, and the consumption current values thereof can be continuously measured, and the thresholds, the sums, and the upper limits can be obtained by counting and considering the safety factors; alternatively, the thresholds, sums and upper limits may be obtained by performing burn-in tests on different pages and blocks within the same flash memory 20, or by any statistical prediction method.

In summary, according to some embodiments, the flash memory controller can obtain the current value consumed by the flash memory during operation in real time, and accordingly determine whether the flash memory is operating normally. According to some embodiments, a storage device having the flash memory controller can determine whether the flash memory is operating normally in real time.