Three-dimensional memory device programming with reduced disturb
阅读说明:本技术 具有减小的干扰的三维存储器件编程 (Three-dimensional memory device programming with reduced disturb ) 是由 王明 刘红涛 宋雅丽 于 2019-05-29 设计创作,主要内容包括:公开了3D存储器件和用于操作所述3D存储器件的方法的实施例。在示例中,公开了一种用于操作3D存储器件的方法。所述3D存储器件包括存储堆栈,每个存储堆栈在竖直方向上包括多个存储层。第一存储堆栈中的每个存储层被第一编程。第一编程包括将编程电压施加至所述存储层,并且将小于所述编程电压的第一沟道通过电压施加至其余存储层中的每者。处于所述第一存储堆栈上方的第二存储堆栈中的每个存储层被第二编程,所述第二编程包括:将所述编程电压施加至所述存储层,并且将所述第一沟道通过电压施加至其余存储层中的每者。所述第二编程还包括:将小于所述第一沟道通过电压的第二沟道通过电压施加至所述第一存储堆栈中的每个存储层。(Embodiments of a 3D memory device and a method for operating the 3D memory device are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes memory stacks each including a plurality of memory layers in a vertical direction. Each storage layer in the first storage stack is first programmed. The first programming includes applying a program voltage to the memory layer, and applying a first channel pass voltage, which is less than the program voltage, to each of the remaining memory layers. Each storage layer in a second storage stack above the first storage stack is second programmed, the second programming comprising: the program voltage is applied to the memory layer, and the first channel pass voltage is applied to each of the remaining memory layers. The second programming further comprises: applying a second channel pass voltage that is less than the first channel pass voltage to each storage layer in the first storage stack.)
1. A method for operating a three-dimensional (3D) memory device, wherein the 3D memory device includes a plurality of memory stacks, each memory stack including a plurality of memory layers in a vertical direction, the method comprising:
performing a first programming on each storage layer in a first storage stack of the plurality of storage stacks, the first programming including applying a programming voltage to the storage layer and applying a first channel pass voltage less than the programming voltage to each of the remaining storage layers in the first storage stack; and
performing second programming on each storage layer in a second storage stack of the plurality of storage stacks that is above the first storage stack, the second programming comprising (i) applying the programming voltage to the storage layer and applying the first channel pass voltage to each of the remaining storage layers in the second storage stack; and (ii) applying a second channel pass voltage, less than the first channel pass voltage, to each storage layer in the first storage stack.
2. The method of claim 1, wherein the 3D memory device includes a third memory stack between the first and second memory stacks in a vertical direction and a plurality of dummy memory layers between the first and third memory stacks, the second programming further comprising applying the second channel pass voltage to each of the memory layers in the third memory stack and the dummy memory layers.
3. The method of claim 1 or 2, wherein the second channel pass voltage is about 0V.
4. The method of any of claims 1-3, wherein the 3D memory device comprises a plurality of NAND memory strings, each NAND memory string extending vertically through the plurality of storage stacks and each NAND memory string comprising a drain select transistor, the method further comprising:
applying a select voltage to a drain select transistor of a first one of the NAND memory strings to select the first NAND memory string; and
applying a deselect voltage to a drain select transistor of a second one of the NAND memory strings to deselect the second NAND memory string.
5. The method of claim 4, wherein the second programming further comprises applying the first channel pass voltage to each of the remaining storage layers in the second storage stack and applying the second channel pass voltage to each storage layer in the first storage stack such that a portion of the coupling potential in the deselected second NAND string does not extend to the first storage stack.
6. The method of claim 1, wherein the 3D memory device further comprises a plurality of dummy memory layers between the first and second memory stacks in the vertical direction, the second programming further comprising applying a cutoff voltage less than a threshold voltage of a control gate to the control gate of at least one of the dummy memory layers to turn off the control gate.
7. The method of claim 6, wherein the second programming further comprises applying a set of voltages to a set of the dummy storage layers above the at least one dummy storage layer.
8. The method of claim 7, wherein the set of voltages gradually decreases from the first channel pass voltage to the cutoff voltage.
9. The method of any of claims 6-8, wherein the cutoff voltage is about 0V.
10. The method of any of claims 6-9, wherein the at least one dummy storage layer comprises a lowest of the dummy storage layers.
11. A method for operating a three-dimensional (3D) memory device, wherein the 3D memory device comprises: a plurality of storage stacks, each storage stack including a plurality of storage layers in a vertical direction; and a plurality of first dummy storage layers between the first storage stack and the second storage stack in the vertical direction, the method comprising:
performing a first programming on each storage layer in a first storage stack of the plurality of storage stacks, the first programming including applying a programming voltage to the storage layer and applying a channel pass voltage less than the programming voltage to each of the remaining storage layers in the first storage stack; and
second programming each storage layer in a second storage stack of the plurality of storage stacks above the first storage stack, the second programming comprising:
applying the programming voltage to the storage layer and the channel pass voltage to each of the remaining storage layers in the second storage stack;
applying a voltage of 0V to at least one of the first dummy storage layers; and
applying the 0V voltage to each storage layer in the first storage stack.
12. The method of claim 11, wherein the second programming further comprises applying a set of voltages to a set of the first dummy storage layers above the at least one first dummy storage layer.
13. The method of claim 12, wherein the set of voltages is gradually decreased from the channel-passing voltage to about 0V.
14. The method of any of claims 11-13, wherein the at least one first dummy storage layer comprises a lowest first dummy storage layer of the first dummy storage layers.
15. The method of any of claims 11-14, wherein the 3D memory device includes a third memory stack between the first and second memory stacks in the vertical direction and a plurality of second dummy memory layers between the first and third memory stacks, the second programming further comprising applying the 0V voltage to each of the memory layers in the third memory stack and the second dummy memory layers.
16. A three-dimensional (3D) memory device, comprising:
a plurality of storage stacks, each storage stack including a plurality of storage layers in a vertical direction; and
peripheral circuitry configured to program each storage layer in a first storage stack of the plurality of storage stacks and then each storage layer in a second storage stack of the plurality of storage stacks that is above the first storage stack,
wherein to program each storage layer in the first storage stack, the peripheral circuitry is further configured to apply a programming voltage to the storage layer and a first channel pass voltage less than the programming voltage to each of the remaining storage layers in the first storage stack; and is
To program each storage layer in the second storage stack, the peripheral circuitry is further configured to:
applying the programming voltage to the storage layer and the first channel pass voltage to each of the remaining storage layers in the second storage stack; and is
Applying a second channel pass voltage that is less than the first channel pass voltage to each storage layer in the first storage stack.
17. The 3D memory device of claim 16,
the 3D memory device includes a third memory stack between the first memory stack and the second memory stack in a vertical direction and a plurality of dummy memory layers between the first memory stack and the third memory stack; and is
To program each storage layer in the second storage stack, the peripheral circuitry is further configured to apply the second channel pass voltage to each of the storage layers in the third storage stack and the dummy storage layer.
18. The 3D memory device of claim 16 or 17, wherein the second channel pass voltage is about 0V.
19. The 3D memory device of any one of claims 16-18,
the 3D memory device includes a plurality of NAND memory strings, each NAND memory string extending vertically through the plurality of memory stacks and including a drain select transistor; and is
The peripheral circuitry is further configured to:
applying a select voltage to a drain select transistor of a first one of the NAND memory strings to select the first NAND memory string; and
applying a deselect voltage to a drain select transistor of a second one of the NAND memory strings to deselect the second NAND memory string.
20. The 3D memory device of claim 19, wherein to program each memory layer in the second memory stack, the peripheral circuitry is further configured to apply the first channel pass voltage to each of the remaining memory layers in the second memory stack and to apply the second channel pass voltage to each memory layer in the first memory stack such that a portion of the coupling potential in the deselected second NAND memory string does not extend to the first memory stack.
21. The 3D memory device of claim 16,
the 3D memory device further includes a plurality of dummy memory layers between the first memory stack and the second memory stack in the vertical direction; and is
The peripheral circuit is further configured to apply an off-voltage less than a threshold voltage of a control gate to the control gate of at least one of the dummy storage layers to turn off the control gate.
22. The 3D memory device of claim 21, wherein to program each memory layer in the second memory stack, the peripheral circuitry is further configured to apply a set of voltages to a set of the dummy memory layers above the at least one dummy memory layer.
23. The 3D memory device of claim 22, wherein the set of voltages gradually drops from the first channel pass voltage to the cutoff voltage.
24. The 3D memory device of any one of claims 21-23, wherein the cutoff voltage is about 0V.
25. The 3D memory device of any one of claims 21-24, wherein the at least one dummy memory layer comprises a lowest of the dummy memory layers.
26. A three-dimensional (3D) memory device, comprising:
a plurality of storage stacks and a plurality of first dummy storage layers between a first storage stack and a second storage stack in a vertical direction, wherein each storage stack includes a plurality of storage layers in the vertical direction; and
peripheral circuitry configured to program each storage layer in a first storage stack of the plurality of storage stacks and then each storage layer in a second storage stack of the plurality of storage stacks that is above the first storage stack,
wherein to program each storage layer in the first storage stack, the peripheral circuitry is further configured to apply a programming voltage to the storage layer and to apply a channel pass voltage less than the programming voltage to each of the remaining storage layers in the first storage stack; and is
To program each storage layer in the second storage stack, the peripheral circuitry is further configured to:
applying the programming voltage to the storage layer and the channel pass voltage to each of the remaining storage layers in the second storage stack;
applying a voltage of 0V to at least one of the first dummy storage layers; and
applying the 0V voltage to each storage layer in the first storage stack.
27. The 3D memory device of claim 26, wherein to program each memory layer in the second memory stack, the peripheral circuitry is further configured to apply a set of voltages to a set of the first dummy memory layers above the at least one first dummy memory layer.
28. The 3D memory device of claim 27, wherein the set of voltages is gradually decreased from the channel-passing voltage to about 0V.
29. The 3D memory device of any one of claims 26-28, wherein the at least one first dummy memory layer comprises a lowest first dummy memory layer of the first dummy memory layers.
30. The 3D memory device of any one of claims 26-29, wherein,
the 3D memory device includes a third memory stack between the first memory stack and the second memory stack in the vertical direction and a plurality of second dummy memory layers between the first memory stack and the third memory stack; and is
To program each storage layer in the second storage stack, the peripheral circuitry is further configured to apply the 0V voltage to each of the storage layers in the third storage stack and the second dummy storage layer.
Background
Embodiments of the present disclosure relate to a three-dimensional (3D) memory device and a method of operating the same.
Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the feature size of the memory cell approaches the lower limit, the planar processes and fabrication techniques become more difficult and more costly. As a result, the storage density of the planar memory cell approaches the upper limit.
The 3D memory architecture can address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.
Disclosure of Invention
Embodiments of a 3D memory device and a method for operating a 3D memory device are disclosed herein.
In one example, a method for operating a 3D memory device is disclosed. The 3D memory device includes a plurality of memory stacks, each including a plurality of memory layers in a vertical direction. Each storage layer in a first storage stack of the plurality of storage stacks is first programmed. The first programming includes applying a program voltage to the storage layer and applying a first channel pass voltage, which is less than the program voltage, to each of the remaining storage layers in the first storage stack. Each storage layer in a second storage stack of the plurality of storage stacks above the first storage stack is second programmed. The second programming includes applying a programming voltage to the storage layer and applying a first channel pass voltage to each of the remaining storage layers in the second storage stack. The second programming further includes applying a second channel pass voltage, which is less than the first channel pass voltage, to each of the memory layers in the first memory stack.
In another example, a method for operating a 3D memory device is disclosed. The 3D memory device includes: a plurality of storage stacks, each storage stack including a plurality of storage layers in a vertical direction; and a plurality of first dummy storage layers between the first storage stack and the second storage stack in a vertical direction. Each storage layer in a first storage stack of the plurality of storage stacks is first programmed. The first programming includes applying a program voltage to the storage layer and applying a channel pass voltage less than the program voltage to each of the remaining storage layers in the first storage stack. Each storage layer in a second storage stack of the plurality of storage stacks above the first storage stack is second programmed. The second programming includes applying a programming voltage to a storage layer and applying the channel pass voltage to each of the remaining storage layers in the second storage stack. The second programming further includes applying a voltage of 0V to at least one of the first dummy storage layers. The second programming further includes applying a voltage of 0V to each memory layer in the first memory stack.
In yet another example, a 3D memory device includes a peripheral circuit and a plurality of memory stacks, each including a plurality of memory layers in a vertical direction. The peripheral circuitry is configured to program each storage layer in a first storage stack of the plurality of storage stacks and then program each storage layer in a second storage stack of the plurality of storage stacks that is above the first storage stack. To program each storage layer in the first storage stack, the peripheral circuitry is further configured to apply a programming voltage to the storage layer and a first channel pass voltage less than the programming voltage to each of the remaining storage layers in the first storage stack. To program each storage layer in the second storage stack, the peripheral circuitry is further configured to apply a programming voltage to the storage layer and a first channel pass voltage to each of the remaining storage layers in the second storage stack and a second channel pass voltage less than the first channel pass voltage to each storage layer in the first storage stack.
In yet another example, a 3D memory device includes: a peripheral circuit; a plurality of storage stacks, each storage stack including a plurality of storage layers in a vertical direction; and a plurality of first dummy storage layers between the first storage stack and the second storage stack in a vertical direction. The peripheral circuitry is configured to program each storage layer in a first storage stack of the plurality of storage stacks and then program each storage layer in a second storage stack of the plurality of storage stacks that is above the first storage stack. To program each storage layer in the first storage stack, the peripheral circuitry is further configured to apply a programming voltage to the storage layer and to apply a channel pass voltage, less than the programming voltage, to each of the remaining storage layers in the first storage stack. To program each storage layer in the second storage stack, the peripheral circuitry is further configured to apply a programming voltage to the storage layer and to apply the channel pass voltage to each of the remaining storage layers in the second storage stack. To program each storage layer in the second storage stack, the peripheral circuitry is further configured to apply a 0V voltage to at least one of the first dummy storage layers and to apply a 0V voltage to each storage layer in the first storage stack.
Drawings
The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.
FIG. 1 shows a diagram of an exemplary 3D memory device, according to some embodiments of the present disclosure.
Fig. 2 illustrates a cross-sectional view of an exemplary memory array device, in accordance with some embodiments of the present disclosure.
FIG. 3A illustrates a programming scheme for a single stack 3D NAND memory device.
FIG. 3B shows a programming scheme for a multi-stack 3D NAND memory device.
FIG. 4 illustrates an exemplary programming scheme for a multi-stack 3D NAND memory device, according to some embodiments of the present disclosure.
Fig. 5A and 5B illustrate another example programming scheme for a multi-stack 3D NAND memory device, according to some embodiments of the present disclosure.
FIG. 6 illustrates yet another example programming scheme for a multi-stack 3D NAND memory device, according to some embodiments of the present disclosure.
FIG. 7 is a flow diagram of an exemplary method for operating a 3D memory device according to some embodiments of the present disclosure.
Embodiments of the present disclosure will be described with reference to the accompanying drawings.
Detailed Description
While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. One skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.
It is noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
In general, terms may be understood at least in part from the context in which they are used. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending at least in part on the context. Similarly, terms such as "a" or "the" may likewise be understood to convey a singular use or to convey a plural use, depending at least in part on the context. Moreover, the term "based on" may be understood as a set of factors that are not necessarily intended to convey exclusivity, and may instead allow for the presence of additional factors that are not necessarily expressly described, again depending at least in part on the context.
It should be readily understood that the meaning of "on …," "over …," and "over …" in this disclosure should be read in the broadest manner such that "on …" means not only "directly on" but also including the meaning of "on" something with intervening features or layers therebetween, and "over …" or "over …" means not only "over" or "on" something, but may also include the meaning of "over" or "on" something with no intervening features or layers therebetween (i.e., directly on something).
Furthermore, spatially relative terms such as "under …," "under …," "lower," "over …," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations in use or operation of the device in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, the term "substrate" refers to a material to which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafers.
As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any horizontal pair of surfaces at the top and bottom surfaces or between the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.
As used herein, the term "nominal" refers to a desired or targeted value of a characteristic or parameter for a component or process operation, as well as a range of values above and/or below the desired value, set during a design phase of a product or process. The range of values may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given amount that may vary based on the particular technology node associated with the subject semiconductor device. The term "about" may indicate a given amount of a value that varies, for example, within 10% -30% of the value (e.g., ± 10%, ± 20% or ± 30% of the value), based on the particular technology node.
As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," e.g., NAND memory strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to a lateral surface of a substrate.
Various embodiments according to the present disclosure provide a novel programming scheme for 3D memory devices, particularly for multi-stack 3D NAND memory devices, with reduced disturb. For a selected 3D NAND memory string, the programming scheme disclosed herein can reduce channel pass voltage induced disturbance to the programmed storage layer (also known as "channel pass voltage disturbance"). For deselected 3D memory strings, the programming scheme disclosed herein can also reduce the disturbance caused by the programming voltage to the memory layer being programmed (also known as "program voltage disturbance"). During a programming operation of any upper storage stack, a reduced channel pass voltage (e.g., 0V) may be applied to each storage layer or dummy storage layer that is below the upper storage stack to reduce channel pass voltage disturb and avoid channel coupling effects in lower regions of deselected NAND memory strings. In some embodiments, at least one of the dummy storage layers between the lower and upper storage stacks is turned off by applying a voltage of 0V to its control gate, thereby preventing leakage current between the upper and lower storage stacks. In some embodiments, a set of voltages that are ramped down is applied to the dummy storage layer between the upper and lower storage stacks to form a voltage gradient from the channel pass voltage to 0V, which can avoid channel hot electron injection (CHE) effects in deselected NAND memory strings.
Fig. 1 shows a diagram of an exemplary
In some embodiments, each memory cell 106 is a Single Level Cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first range of voltages, and a second memory state "1" may correspond to a second range of voltages. In some embodiments, each memory cell 106 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four memory states. For example, MLCs are capable of storing two bits per cell, three bits per cell (also known as tertiary cells (TLC)), or four bits per cell (also known as quaternary cells (QLC)). Each MLC can be programmed to exhibit a range of possible nominal memory cells. In one example, if each MLC stores two bits of data, the MLC may be programmed from the erased state to assume one of three possible programmed levels by writing one of three possible nominal storage values to the cell. The fourth nominal storage value may be used for the erased state.
As shown in FIG. 1, each
The memory cells 106 of adjacent
Fig. 2 illustrates a cross-sectional view of an exemplary
As shown in fig. 2, a 3D
The
As shown in fig. 2, a 3D
In some embodiments, the 3D
In some embodiments, the 3D
In fig. 2, a 3D
Referring back to FIG. 1, the
In some embodiments,
FIG. 3A illustrates a programming scheme for a single stack 3D
During a programming operation of the 3D
During a program operation of the 3D
During a programming operation of the 3D
As the number of stacked memory layers in 3D NAND memory devices continues to increase, channel pass voltage disturb becomes more significant because the duration of applying a channel pass voltage to a programmed memory layer also increases. At the same time, program voltage disturb also becomes more pronounced as the channel depth (in the vertical direction) increases, thereby reducing the coupling potential. For example, FIG. 3B illustrates a programming scheme for a multi-stack 3D
The storage layer in the
As detailed below in connection with fig. 4-7, the present disclosure provides a novel programming scheme with reduced disturbs (e.g., program voltage disturbs and channel pass voltage disturbs) for 3D memory devices, particularly for 3D NAND memory devices having multiple memory stacks. FIG. 4 illustrates an exemplary programming scheme for a multi-stack 3D
As shown in FIG. 4, the 3D
As shown in fig. 4, the 3D
During a program operation of the 3D
During a program operation of the 3D
On the other hand, when the channel pass voltage is reduced below the threshold voltage of the control gate of the memory cell (e.g., 0V), a portion of the
In some embodiments, to reduce leakage current between the lower and upper storage stacks 410, 412 when programming the
According to some embodiments, a set of voltages is applied to a set of intermediate dummy storage layers 414 above at least one dummy storage layer (e.g., the lowest intermediate dummy storage layer 426). To avoid CHE effects in the deselected
The programming scheme described above in connection with the 3D
During a program operation of the 3D
According to some embodiments, to program the
In some embodiments, to reduce leakage current between the lower and intermediate storage stacks 502, 504 when programming the
Similarly, during a program operation of the 3D
In some embodiments, to reduce leakage current between the
The programming scheme described above in connection with the 3D NAND memory devices having two or three memory stacks in fig. 4, 5A and 5B can be extended to any 3D NAND memory device having n memory stacks, where n is a positive integer greater than 1. For example, fig. 6 illustrates yet another exemplary programming scheme for a multi-stack 3D
Assuming that the programming order of the n memory stacks is bottom-up, each memory layer in MD 1 (the lowest memory stack) is first sequentially programmed in the programming order during the program operation of the 3D
In some embodiments, to reduce the time between MD i and MD i-1 when programming MD i0V voltage is applied to the control gate of at least one of the DM i (e.g., the lowest DM i 606) to turn off the control gate. To avoid CHE effects in the deselected
FIG. 7 is a flow diagram of an
Referring to FIG. 7, a
The
The
According to one aspect of the present disclosure, a method for operating a 3D memory device is disclosed. The 3D memory device includes a plurality of memory stacks, each including a plurality of memory layers in a vertical direction. Each storage layer in a first storage stack of the plurality of storage stacks is first programmed. The first programming includes applying a program voltage to the storage layer and applying a first channel pass voltage, which is less than the program voltage, to each of the remaining storage layers in the first storage stack. Each storage layer in a second storage stack of the plurality of storage stacks above the first storage stack is second programmed. The second programming includes applying a programming voltage to the storage layer and applying a first channel pass voltage to each of the remaining storage layers in the second storage stack. The second programming further includes applying a second channel pass voltage, which is less than the first channel pass voltage, to each of the memory layers in the first memory stack.
In some embodiments, the 3D memory device includes a third memory stack between the first memory stack and the second memory stack and a plurality of dummy memory layers between the first memory stack and the third memory stack in a vertical direction. According to some embodiments, the second programming further comprises applying a second channel pass voltage to each of the storage layers in a third storage stack and the dummy storage layer.
In some embodiments, the second channel pass voltage is about 0V.
In some embodiments, the 3D memory device includes a plurality of NAND memory strings, each of which vertically extends through the plurality of memory stacks and each includes a drain select transistor. A select voltage may be applied to a drain select transistor of a first one of the NAND memory strings to select the first NAND memory string. A deselect voltage may be applied to a drain select transistor of a second one of the NAND memory strings to deselect the second NAND memory string. In some embodiments, a first channel pass voltage is applied to each of the remaining storage layers in the second storage stack and a second channel pass voltage is applied to each storage layer in the first storage stack such that a portion of the coupling potential in the deselected second NAND memory string does not extend to the first storage stack.
In some embodiments, the 3D memory device further includes a plurality of dummy memory layers between the first memory stack and the second memory stack in a vertical direction. An off-voltage smaller than a threshold voltage of the control gate may be applied to the control gate of at least one of the dummy storage layers to turn off the control gate. A set of voltages may be applied to a set of dummy storage layers above the at least one dummy storage layer. In some embodiments, the set of voltages gradually decreases from the first channel pass voltage to the cutoff voltage. In some embodiments, the cutoff voltage is about 0V. According to some embodiments, the at least one dummy storage layer comprises a lowest dummy storage layer of the dummy storage layers.
According to another aspect of the present disclosure, a method for operating a 3D memory device is disclosed. The 3D memory device includes: a plurality of storage stacks, each storage stack including a plurality of storage layers in a vertical direction; and a plurality of first dummy storage layers between the first storage stack and the second storage stack in a vertical direction. Each storage layer in a first storage stack of the plurality of storage stacks is first programmed. The first programming includes applying a program voltage to the storage layer and applying a channel pass voltage less than the program voltage to each of the remaining storage layers in the first storage stack. Each storage layer in a second storage stack of the plurality of storage stacks above the first storage stack is second programmed. The second programming includes applying a programming voltage to a storage layer and applying the channel pass voltage to each of the remaining storage layers in the second storage stack. The second programming further includes applying a voltage of 0V to at least one of the first dummy storage layers. The second programming further includes applying a 0V voltage to each storage layer in the first storage stack.
In some embodiments, a set of voltages is applied to a set of first dummy storage layers above the at least one first dummy storage layer. The set of voltages may gradually decrease from the channel pass voltage to about 0V.
In some embodiments, the at least one first dummy storage layer includes a lowest first dummy storage layer of the first dummy storage layers.
In some embodiments, the 3D memory device includes a third memory stack between the first memory stack and the second memory stack and a plurality of second dummy memory layers between the first memory stack and the third memory stack in a vertical direction. A voltage of 0V may be applied to each of the storage layers in the third storage stack and the second dummy storage layer.
According to still another aspect of the present disclosure, a 3D memory device includes a peripheral circuit and a plurality of memory stacks, each including a plurality of memory layers in a vertical direction. The peripheral circuitry is configured to program each storage layer in a first storage stack of the plurality of storage stacks and then program each storage layer in a second storage stack of the plurality of storage stacks that is above the first storage stack. To program each storage layer in the first storage stack, the peripheral circuitry is further configured to apply a programming voltage to the storage layer and a first channel pass voltage less than the programming voltage to each of the remaining storage layers in the first storage stack. To program each storage layer in the second storage stack, the peripheral circuitry is further configured to apply a programming voltage to the storage layer and a first channel pass voltage to each of the remaining storage layers in the second storage stack and a second channel pass voltage less than the first channel pass voltage to each storage layer in the first storage stack.
In some embodiments, the 3D memory device includes a third memory stack between the first memory stack and the second memory stack and a plurality of dummy memory layers between the first memory stack and the third memory stack in a vertical direction. To program each storage layer in the second storage stack, the peripheral circuitry may be further configured to apply a second channel pass voltage to each of the storage layers in the third storage stack and the dummy storage layer. In some embodiments, the second channel pass voltage is about 0V.
In some embodiments, the 3D memory device includes a plurality of NAND memory strings, each NAND memory string extending vertically through the plurality of memory stacks and including a drain select transistor. The peripheral circuit may be further configured to apply a selection voltage to a drain select transistor of a first one of the NAND memory strings to select the first NAND memory string, and to apply a deselect voltage to a drain select transistor of a second one of the NAND memory strings to deselect the second NAND memory string.
In some embodiments, to program each storage layer in the second storage stack, the peripheral circuit is further configured to apply a first channel pass voltage to each of the remaining storage layers in the second storage stack and a second channel pass voltage to each storage layer in the first storage stack such that a portion of the coupling potential in the deselected second NAND memory string does not extend to the first storage stack.
In some embodiments, the 3D memory device further includes a plurality of dummy memory layers between the first memory stack and the second memory stack in a vertical direction. The peripheral circuit is further configured to apply an off-voltage smaller than a threshold voltage of the control gate to the control gate of at least one of the dummy storage layers to turn off the control gate. In some embodiments, to program each storage layer in the second storage stack, the peripheral circuitry is further configured to apply a set of voltages to a set of dummy storage layers above the at least one dummy storage layer. The set of voltages gradually decreases from the first channel pass voltage to the cutoff voltage. According to some embodiments, the cut-off voltage is about 0V. In some embodiments, the at least one dummy storage layer includes a lowest dummy storage layer of the dummy storage layers.
According to still another aspect of the present disclosure, a 3D memory device includes: a peripheral circuit; a plurality of storage stacks, each storage stack including a plurality of storage layers in a vertical direction; and a plurality of first dummy storage layers between the first storage stack and the second storage stack in a vertical direction. The peripheral circuitry is configured to program each storage layer in a first storage stack of the plurality of storage stacks and then program each storage layer in a second storage stack of the plurality of storage stacks that is above the first storage stack. To program each storage layer in the first storage stack, the peripheral circuitry is further configured to apply a programming voltage to the storage layer and to apply a channel pass voltage, less than the programming voltage, to each of the remaining storage layers in the first storage stack. To program each storage layer in the second storage stack, the peripheral circuitry is further configured to apply a programming voltage to the storage layer and to apply the channel pass voltage to each of the remaining storage layers in the second storage stack. To program each storage layer in the second storage stack, the peripheral circuitry is further configured to apply a 0V voltage to at least one of the first dummy storage layers and to apply a 0V voltage to each storage layer in the first storage stack.
In some embodiments, to program each storage layer in the second storage stack, the peripheral circuitry is further configured to apply a set of voltages to a set of first dummy storage layers above the at least one first dummy storage layer. In some embodiments, the set of voltages may gradually decrease from the channel pass voltage to about 0V.
In some embodiments, the at least one first dummy storage layer includes a lowest first dummy storage layer of the first dummy storage layers.
In some embodiments, the 3D memory device includes a third memory stack between the first memory stack and the second memory stack in a vertical direction and a plurality of second dummy memory layers between the first memory stack and the third memory stack. To program each storage layer in the second storage stack, the peripheral circuitry may be further configured to apply a 0V voltage to each of the storage layers in the third storage stack and the second dummy storage layer.
The foregoing description of the specific embodiments will so fully reveal the general nature of the disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments without undue experimentation and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. Boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.