阅读说明：本技术 闪存的数据写入方法与其控制装置 (Data writing method of flash memory and control device thereof ) 是由 杨宗杰 于 2015-03-31 设计创作，主要内容包括：本发明公开了一种闪存的数据写入方法与其控制装置，所述闪存包括有多个多层单元，其中每一个多层单元可用来储存多个位，所述方法包括有：分别对所述多个多层单元中的每一个多层单元储存一第一位；判断所述每一个多层单元是否都分别储存了所述第一位；以及当所述每一个多层单元都分别储存了所述第一位时，分别对所述每一个多层单元储存一第二位。本发明可大幅减少所述闪存内满载数据被抹去的次数，并增加所述闪存内未满载数据被抹去的次数，以提高所述闪存的写入速度和使用寿命。(The invention discloses a data writing method of flash memory and a control device thereof, wherein the flash memory comprises a plurality of multi-layer units, each multi-layer unit can be used for storing a plurality of bits, and the method comprises the following steps: storing a first bit for each of the plurality of multi-level cells, respectively; judging whether each multi-layer unit stores the first bit or not; and storing a second bit for each of the multi-level cells when the first bit is stored for each of the multi-level cells. The invention can greatly reduce the times of erasing the full-load data in the flash memory and increase the times of erasing the non-full-load data in the flash memory so as to improve the writing speed and the service life of the flash memory.)

1. A method for writing data into a flash memory, the flash memory comprising a plurality of multi-level cells, wherein each multi-level cell is configured to store a plurality of bits, the method comprising:

storing a set of data on an nth bit of each of the plurality of MLCs on average, wherein n is a positive integer greater than 0;

judging whether the nth bit of each multi-layer unit stores data respectively; and

when the nth bit of each multi-layer unit stores the first bit respectively, storing the (n + 1) th bit of each multi-layer unit respectively;

wherein storing the set of data in the nth bit of each MLC on average comprises, for each MLC:

determining a data polarity of data to be written to the nth bit of the multi-layered cell to determine whether an amount of injected charge is to the multi-layered cell; wherein if the data polarity is a first polarity, a first amount of charge is not injected into a floating gate of the multi-layered cell; and injecting the first amount of charge into the floating gate of the multi-layered cell if the data polarity is a second polarity, the second polarity being different from the first polarity.

2. The method of claim 1, wherein for each of the multilevel cells, the nth bit is a most significant bit stored by the multilevel cell and the n +1 th bit is a least significant bit stored by the multilevel cell.

3. The method of claim 1, wherein for each of the multilevel cells, the nth bit is a least significant bit stored by the multilevel cell and the n +1 th bit is a most significant bit stored by the multilevel cell.

4. The method of claim 1, wherein: also includes:

judging whether each multi-layer unit stores the (n + 1) th bit respectively; and

when the (n + 1) th bit is stored in each multi-level cell, a data one is stored in the (n + 2) th bit of each multi-level cell.

5. The method of claim 4, wherein for each of the multilevel cells, the nth bit is a most significant bit stored by the multilevel cell, the n +1 th bit is a second significant bit stored by the multilevel cell, and the n +2 th bit is a least significant bit stored by the multilevel cell.

6. The method of claim 4, wherein for each of the multilevel cells, the nth bit is a least significant bit stored by the multilevel cell, the n +1 th bit is a second significant bit stored by the multilevel cell, and the n +2 th bit is a most significant bit stored by the multilevel cell.

7. The method of claim 1, wherein the first polarity is bit 1 and the second polarity is bit 0; or the first polarity is bit 0 and the second polarity is bit 1.

8. The method of claim 1, wherein the step of storing the (n + 1) th bit for each of the multilevel cells comprises:

for each of the multi-layer units:

determining the data polarity of the (n + 1) th bit to be written to the multi-level cell;

not injecting a second amount of charge into the floating gate of the multi-layered cell if the data polarity of the nth bit of the multi-layered cell is the first polarity and if the data polarity of the n +1 th bit of the multi-layered cell is the first polarity;

injecting the second amount of charge into the floating gate of the multi-layered cell if the data polarity of the nth bit of the multi-layered cell is the first polarity and if the data polarity of the n +1 th bit of the multi-layered cell is the second polarity;

not injecting a third amount of charge into the floating gate of the multi-layered cell if the data polarity of the nth bit of the multi-layered cell is the second polarity and if the data polarity of the n +1 th bit of the multi-layered cell is the first polarity;

injecting the third amount of charge into the floating gate of the multi-layered cell if the data polarity of the nth bit of the multi-layered cell is the second polarity and if the data polarity of the n +1 th bit of the multi-layered cell is the second polarity.

9. The method of claim 8, wherein the second amount of charge is different from the third amount of charge.

10. The method of claim 4, wherein the step of storing the (n + 2) th bit for each of the multilevel cells comprises:

for each of the multi-layer units:

determining the data polarity of the n +2 th bit to be written to the multi-level cell;

if the data polarity of the nth bit of the multi-level cell is the first polarity, if the data polarity of the n +1 th bit of the multi-level cell is the first polarity, and

if the data polarity of the n +2 th bit of the multi-level cell is the first polarity,

injecting no fourth charge amount into the floating gate of the multi-layered cell;

if the data polarity of the nth bit of the multi-level cell is the first polarity, if the data polarity of the n +1 th bit of the multi-level cell is the first polarity, and

if the data polarity of the n +2 th bit of the multi-level cell is the second polarity,

injecting the fourth amount of charge into the floating gate of the multi-layered cell;

if the data polarity of the nth bit of the multi-level cell is the first polarity, if the data polarity of the n +1 th bit of the multi-level cell is the second polarity, and

if the data polarity of the n +2 th bit of the multi-level cell is the first polarity,

injecting no fifth charge amount into the floating gate of the multi-layered cell;

if the data polarity of the nth bit of the multi-level cell is the first polarity, if the data polarity of the n +1 th bit of the multi-level cell is the second polarity, and

if the data polarity of the n +2 th bit of the multi-level cell is the second polarity,

injecting the fifth amount of charge into the floating gate of the multi-layered cell;

if the data polarity of the nth bit of the multi-level cell is the second polarity, if the data polarity of the n +1 th bit of the multi-level cell is the first polarity, and

if the data polarity of the n +2 th bit of the multi-level cell is the first polarity,

injecting no sixth charge amount into the floating gate of the multi-layered cell;

if the data polarity of the nth bit of the multi-level cell is the second polarity, if the data polarity of the n +1 th bit of the multi-level cell is the first polarity, and

if the data polarity of the n +2 th bit of the multi-level cell is the second polarity,

injecting the sixth amount of charge into the floating gate of the multi-layered cell;

if the data polarity of the nth bit of the multi-level cell is the second polarity, if the data polarity of the n +1 th bit of the multi-level cell is the second polarity, and

if the data polarity of the n +2 th bit of the multi-level cell is the first polarity,

injecting no seventh amount of charge into the floating gate of the multi-layered cell;

if the data polarity of the nth bit of the multi-level cell is the second polarity, if the data polarity of the n +1 th bit of the multi-level cell is the second polarity, and

if the data polarity of the n +2 th bit of the multi-level cell is the second polarity,

the seventh amount of charge is injected into the floating gate of the multi-layered cell.

11. The method of claim 10, wherein the fourth, fifth, sixth, and seventh amounts of charge are different amounts of charge from one another.

12. A control device for writing data to a flash memory, the flash memory including a plurality of multi-level cells, each multi-level cell operable to store a plurality of bits, the control device comprising:

a write circuit for storing a set of data on average in an nth bit of each of the plurality of MLCs, wherein n is a positive integer greater than 0; (ii) a And

a judging circuit for judging whether the nth bit of each of the plurality of layers of cells is stored; wherein if the nth bit of each of the multi-level cells stores the first bit, the (n + 1) th bit of each of the multi-level cells is stored;

wherein the write circuit includes:

a judging unit for judging the data polarity of the data to be written into the nth bit of the multi-layer unit to determine whether the injection charge quantity to the multi-layer unit is available; and a write unit, wherein if the data polarity is a first polarity, the write unit does not inject a first charge amount to a floating gate of the multi-layered cell; and if the data polarity is a second polarity, the writing unit injects the first charge amount to the floating gate of the multi-layered unit, and the second polarity is different from the first polarity.

13. The control apparatus of claim 12 wherein, for each of said multilevel cells, said nth bit is a most significant bit stored by said multilevel cell and said n +1 th bit is a least significant bit stored by said multilevel cell.

14. The control apparatus of claim 12 wherein, for each of said multilevel cells, said nth bit is a least significant bit stored by said multilevel cell and said n +1 th bit is a most significant bit stored by said multilevel cell.

15. The control apparatus as claimed in claim 12, wherein the determining circuit is further configured to determine whether each of the multi-level cells stores the (n + 1) th bit, and the writing circuit stores an (n + 2) th bit for each of the multi-level cells when the determining circuit determines that each of the multi-level cells stores the (n + 1) th bit.

16. The control device as claimed in claim 15, wherein for each of said multilevel cells, said nth bit is a most significant bit stored by said multilevel cell, said n +1 th bit is a second significant bit stored by said multilevel cell, and said n +2 th bit is a least significant bit stored by said multilevel cell.

17. The control apparatus of claim 15, wherein for each of the multi-level cells, the nth bit is a least significant bit stored by the multi-level cell, the n +1 th bit is a second significant bit stored by the multi-level cell, and the n +2 th bit is a most significant bit stored by the multi-level cell.

18. The control apparatus of claim 12, wherein the first polarity is bit 1 and the second polarity is bit 0; or the first polarity is bit 0 and the second polarity is bit 1.

19. The control apparatus as claimed in claim 12, wherein said judging unit is further operable to judge the polarity of said data to be written into said n +1 th bit of said multi-level cell; if the data polarity of the nth bit of the multi-layered cell is the first polarity and if the data polarity of the n +1 th bit of the multi-layered cell is the first polarity, the write unit does not inject a second amount of charge into the floating gate of the multi-layered cell; the write unit injects the second amount of charge into the floating gate of the multi-layered cell if the data polarity of the nth bit of the multi-layered cell is the first polarity and if the data polarity of the n +1 th bit of the multi-layered cell is the second polarity; if the data polarity of the nth bit of the multi-layered cell is the second polarity and if the data polarity of the n +1 th bit of the multi-layered cell is the first polarity, the write unit does not inject a third amount of charge into the floating gate of the multi-layered cell; the write unit injects the third amount of charge into the floating gate of the multi-layered cell if the data polarity of the nth bit of the multi-layered cell is the second polarity and if the data polarity of the n +1 th bit of the multi-layered cell is the second polarity.

20. The control apparatus of claim 19, wherein the second amount of charge is different from the third amount of charge.

21. The control apparatus as claimed in claim 15, wherein said judging unit is further operable to judge the polarity of said data to be written into said n +2 th bit of said multi-level cell; if the data polarity of the nth bit of the multi-layered cell is the first polarity, if the data polarity of the n +1 th bit of the multi-layered cell is the first polarity, and if the data polarity of the n +2 th bit of the multi-layered cell is the first polarity, the write unit does not inject a fourth amount of charge into the floating gate of the multi-layered cell; the write unit injects the fourth amount of charge into the floating gate of the multi-layered cell if the data polarity of the nth bit of the multi-layered cell is the first polarity, if the data polarity of the n +1 th bit of the multi-layered cell is the first polarity, and if the data polarity of the n +2 th bit of the multi-layered cell is the second polarity; the write unit does not inject a fifth amount of charge into the floating gate of the multi-layered cell if the data polarity of the nth bit of the multi-layered cell is the first polarity, if the data polarity of the n +1 th bit of the multi-layered cell is the second polarity, and if the data polarity of the n +2 th bit of the multi-layered cell is the first polarity; the write unit injects the fifth amount of charge into the floating gate of the multi-layered cell if the data polarity of the nth bit of the multi-layered cell is the first polarity, if the data polarity of the n +1 th bit of the multi-layered cell is the second polarity, and if the data polarity of the n +2 th bit of the multi-layered cell is the second polarity; if the data polarity of the nth bit of the multi-layered cell is the second polarity, if the data polarity of the n +1 th bit of the multi-layered cell is the first polarity, and if the data polarity of the n +2 th bit of the multi-layered cell is the first polarity, the write unit does not inject a sixth charge amount to the floating gate of the multi-layered cell; the write unit injects the sixth amount of charge into the floating gate of the multi-layered cell if the data polarity of the nth bit of the multi-layered cell is the second polarity, if the data polarity of the n +1 th bit of the multi-layered cell is the first polarity, and if the data polarity of the n +2 th bit of the multi-layered cell is the second polarity; if the data polarity of the nth bit of the multi-layered cell is the second polarity, if the data polarity of the n +1 th bit of the multi-layered cell is the second polarity, and if the data polarity of the n +2 th bit of the multi-layered cell is the first polarity, the write unit does not inject a seventh amount of charge into the floating gate of the multi-layered cell; the write unit injects the seventh amount of charge into the floating gate of the multi-layered cell if the data polarity of the nth bit of the multi-layered cell is the second polarity, if the data polarity of the n +1 th bit of the multi-layered cell is the second polarity, and if the data polarity of the n +2 th bit of the multi-layered cell is the second polarity.

22. The control apparatus of claim 21, wherein the fourth, fifth, sixth, and seventh charge amounts are different charges from each other.

Technical Field

The present invention relates to a method for writing data into a flash memory and a control device thereof, and more particularly, to a method for improving the lifespan and operating speed of a flash memory and a control device thereof.

Background

Generally, when a flash memory control circuit writes a data into a memory cell of a flash memory, the flash memory control circuit erases the data previously stored in the memory cell before writing the data into the memory cell. However, this slows down the data writing speed of the flash memory because the flash memory control circuit must take time to erase the data previously stored in the memory cells. Furthermore, in general, the lifetime of a flash memory is limited by the number of writes and erases to the flash memory. If the number of times of writing and erasing of the flash memory is higher, the service life of the flash memory is shorter. In summary, the shorter the number of writes and erases of the flash memory, the longer the lifetime of the flash memory. Therefore, how to simultaneously increase the data writing speed and the service life of the flash memory has become an urgent problem to be solved in the field.

Disclosure of Invention

Therefore, the method and the control device disclosed by the invention mainly improve the service life and the operation speed of the flash memory.

According to a first embodiment of the present invention, a method for writing data into a flash memory is disclosed, wherein the flash memory comprises a plurality of multi-level cells, each of which is configured to store a plurality of bits, the method comprising: storing a set of data on an nth bit of each of the plurality of MLCs on average, wherein n is a positive integer greater than 0; judging whether the nth bit of each multi-layer unit stores data respectively; and storing the (n + 1) th bit of each multi-layer unit when the nth bit of each multi-layer unit stores the first bit respectively; wherein storing the set of data in the nth bit of each MLC on average comprises, for each MLC: determining a data polarity of data to be written to the nth bit of the multi-layered cell to determine whether an amount of injected charge is to the multi-layered cell; wherein if the data polarity is a first polarity, a first amount of charge is not injected into a floating gate of the multi-layered cell; and injecting the first amount of charge into the floating gate of the multi-layered cell if the data polarity is a second polarity, the second polarity being different from the first polarity.

According to a second embodiment of the present invention, a control device for writing data into a flash memory is disclosed, wherein the flash memory comprises a plurality of multi-level cells, each of which is configured to store a plurality of bits. The control device comprises a write circuit and a judgment circuit, wherein the write circuit is used for respectively storing a group of data in an nth bit of each multi-layer unit in the multi-layer units on average, and n is a positive integer greater than 0; and the judging circuit is used for judging whether the nth bit of each multi-layer unit is stored respectively; wherein if the nth bit of each of the multi-level cells stores the first bit, the (n + 1) th bit of each of the multi-level cells is stored. Wherein, the write circuit includes: a judging unit for judging the data polarity of the data to be written into the nth bit of the multi-layer unit to determine whether the injection charge quantity to the multi-layer unit is available; and a write unit, wherein if the data polarity is a first polarity, the write unit does not inject a first charge amount to a floating gate of the multi-layered cell; and if the data polarity is a second polarity, the writing unit injects the first charge amount to the floating gate of the multi-layered unit, and the second polarity is different from the first polarity.

According to the above embodiment, the present invention can greatly reduce the number of times of erasing the full-loaded data in the flash memory, and increase the number of times of erasing the non-full-loaded data in the flash memory, so as to improve the writing speed and the service life of the flash memory.

Drawings

Fig. 1 is a schematic diagram of a control device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a multi-level cell according to an embodiment of the present invention.

FIG. 3 is a flowchart of an embodiment of a method for writing data to a flash memory.

FIG. 4 is a schematic diagram of an embodiment of the charge distribution after 8192 multi-level cells in a flash memory are all written with one bit of data.

FIG. 5 is a schematic diagram of an embodiment of the charge distribution after 8192 multi-level cells in a flash memory are written with two bits of data.

FIG. 6 is a schematic diagram of an embodiment of the charge distribution after three bits of data are written to 8192 multi-level cells in a flash memory according to the present invention.

FIG. 7 is a schematic diagram of an embodiment of the criteria for writing three bits of data to each MLC in a flash memory according to the present invention.

Wherein the reference numerals are as follows:

100 control device

102 flash memory

104 write circuit

106 judging circuit

108 setting circuit

110 reading circuit

102_1-102_ n flash paging

200 multi-layer cell

202 control gate

204 floating gate

206 oxide layer

208 source region

210 drain region

212P type substrate

300 method

302 to 324 steps

Curves 402-404, 502-508, 602-616

Detailed Description

Certain terms are used throughout the description and following claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This specification and the claims that follow do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" is used herein to encompass any direct and indirect electrical connection, such that if a first device is coupled to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Please refer to fig. 1. Fig. 1 is a schematic diagram of a control device 100 according to an embodiment of the present invention. The control device 100 is a flash control circuit, and thus fig. 1 further illustrates a flash memory 102. The flash memory 102 includes a plurality of multi-level cells (mlcs), each of which is used for storing a plurality of bits of data. For example, the flash memory 102 may be a flash Block (Block) or a flash Page (Page). In the present embodiment, the flash memory 102 shown in fig. 1 is a flash block, and the flash block includes a plurality of flash pages 102_1-102_ n, wherein the plurality of flash pages 102_1-102_ n are respectively controlled by a plurality of Word lines (Word lines) WL _1-WL _ n. Further, each of the flash pages 102_1-102_ n has multiple MLCs. For example, the gates (gates) of the multi-level cells T1_1-T1_ m in the first page 102_1 are coupled to the first word line WL _1, and the gates of the multi-level cells T2_1-T2_ m in the second page 102_2 are coupled to the second word line WL _ 2. In addition, the drains (Drain) of the multi-level cells Tn _1-Tn _ m in the nth flash page 102_ n are output from the Bit line (Bit line) of the flash memory 102 of this embodiment, and the sources (Source) of the multi-level cells T1_1-T1_ m in the 1 st flash page 102_1 are coupled to a specific voltage, such as a ground voltage. Please note that the flash memory 102 shown in this embodiment is a simplified flash memory block, and in an embodiment, the flash memory 102 may further include other control circuits for selectively controlling the output of each bit line and for selectively controlling the grounding of each source. Since the circuit is not the focus of the present invention, it is not described herein.

In addition, each of the multi-layer cells can be regarded as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), as shown in fig. 2. FIG. 2 is a schematic diagram of a multi-level cell 200 according to an embodiment of the present invention. The multi-layer cell 200 includes a control gate 202 and a floating gate 204, wherein the control gate 202 and the floating gate 204 are separated by an oxide layer 206. For convenience, the multi-layer cell 200 of the present embodiment is implemented as an N-type mosfet, such that a source region 208 and a drain region 210 of the mosfet are both N-type regions, and a P-type substrate 212 is disposed between the source region 208 and the drain region 210.

In addition, in order to more clearly describe the spirit of the present invention, the multi-level cell described in the present embodiment is a Triple Level Cell (TLC) as an example. However, the present invention is not limited thereto, and any Multi-level flash memory cell (MLC) is within the scope of the present invention.

According to the embodiment of the present invention, the control device 100 includes a write circuit 104, a determination circuit 106, a setting circuit 108, and a read circuit 110. The write circuit 104 is used to store a first bit for each of the multi-level cells (i.e., T1_1-T1_ m, …, Tn _1-Tn _ m) in the flash memory 102. The determining circuit 106 is used for determining whether each of the plurality of levels stores the first bit. If the determining circuit 106 determines that each of the plurality of layers stores the first bit, the writing circuit 104 stores a second bit for each of the plurality of layers. Then, the determining circuit 106 determines again whether each of the plurality of levels stores the second bit. If the determining circuit 106 determines that each of the plurality of layers stores the second bit, the writing circuit 104 stores a third bit for each of the plurality of layers. The setting circuit 108 is used for setting at least one threshold voltage. The reading circuit 110 is used for reading the bit data stored in the multi-level cells in the flash memory 102 according to the at least one threshold voltage.

Further, the operation of the control device 100 can be simplified to the steps shown in fig. 3. FIG. 3 is a flow chart illustrating an embodiment of a method 300 for writing data to the flash memory 102 according to the present invention. The order of steps in the flowchart shown in fig. 3 need not be necessarily performed, and the steps shown in fig. 3 need not be performed continuously, that is, other steps may be inserted, if substantially the same result is achieved. In addition, the following description of the features of the present embodiment assumes that the multiple levels of cells in the flash memory 102 do not initially store any data bits. Therefore, the method 300 of the present embodiment includes:

step 302: starting a data write operation of the flash memory 102;

step 304: storing the first bit separately for each of the plurality of multi-level cells;

step 306: judging whether each multi-layer unit stores the first bit respectively, if so, jumping to a step 308, and if not, jumping to a step 304;

step 308: judging whether data are written into the flash memory 102, if so, jumping to the step 310, otherwise, jumping to the step 324;

step 310: storing the second bit separately for each of the plurality of multi-level cells;

step 312: judging whether each multi-layer unit stores the second bit respectively, if so, jumping to step 314, and if not, jumping to step 310;

step 314: judging whether data are written into the flash memory 102, if so, jumping to step 316, otherwise, jumping to step 324;

step 316: storing the third bit separately for each of the plurality of multi-level cells;

step 318: judging whether each multi-layer unit stores the third bit respectively, if so, jumping to step 320, and if not, jumping to step 316;

step 320: judging whether data are written into the flash memory 102, if so, jumping to step 322, otherwise, jumping to step 324;

step 322: writing data to another flash memory or erasing (erase) charge within the plurality of multi-level cells of flash memory 102 to continue writing data to flash memory 102;

step 324: the data write operation of the flash memory 102 is ended.

First, the floating gates of the plurality of multi-level cells of flash memory 102 do not have charge before flash memory 102 has been written with data bits. Then, when data is to be written into the flash memory 102, the write circuit 104 starts to store a first bit for each of the multi-level cells (step 304). For example, if there are 8192 cells in the flash memory 102, the write circuit 104 sequentially writes one bit of data to each cell in step 304 until the data is written or one bit of data is stored in each cell. Further, for each multi-layer cell, the determining circuit 106 determines a data polarity of the first bit to be written into the multi-layer cell, and if the data polarity is a first polarity, the writing circuit 104 does not inject a first charge amount into the floating gate of the multi-layer cell. In summary, if the data polarity is a second polarity, the write circuit 104 injects the first charge amount into the floating gate of the multi-layered cell. Please note that in the present embodiment, the first polarity is bit 1, and the second polarity is bit 0, but the invention is not limited thereto. In other words, it is within the scope of the present invention that the first polarity is bit 0 and the second polarity is bit 1.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating the charge distribution after 8192 multi-level cells in the flash memory 102 are all written with one bit of data according to an embodiment of the present invention, wherein a curve 402 represents that a total of 4096 multi-level cells store data of bit 1, and a curve 404 represents that a total of 4096 multi-level cells store data of bit 0. Please note that the charge distribution shown in FIG. 4 is only an embodiment of the present invention, and the present invention is not limited thereto. In other words, in other embodiments of the present invention, the number of multi-level cells used to store bit 1 is not necessarily equal to the number of multi-level cells used to store bit 0.

In addition, in this embodiment, since the write circuit 104 does not inject the first charge amount into the floating gate of the multi-layered cell when the data polarity is bit 1, the charge stored in the floating gate of the multi-layered cell written to bit 1 is less than the charge stored in the floating gate of the multi-layered cell written to bit 0. Thus, the voltage corresponding to bit 1 in FIG. 4 is lower than the voltage corresponding to bit 0. Therefore, when the reading circuit 110 is to read data stored in a multi-level cell in the flash memory 102, the word line of the multi-level cell is coupled to a threshold voltage Vth1, wherein the threshold voltage Vth1 is generated by the setting circuit 108. Further, when the threshold voltage Vth1 is coupled to the gates of the multi-layer cells, if the multi-layer cells output a current signal corresponding to the word line, the data stored in the multi-layer cells is bit 1. In summary, when the threshold voltage Vth1 is coupled to the gate of the multi-layer cell, if the multi-layer cell does not output a current signal to the corresponding word line, the data stored in the multi-layer cell is bit 0.

On the other hand, in step 306, if the determining circuit 106 determines that there is a multi-level cell in the flash memory 102 that has not been written with one bit of data, the writing circuit 104 will continue to write one bit of data into the multi-level cell until the data is written or one bit of data is stored in each multi-level cell. If the determining circuit 106 determines that one bit of data is written into each multi-level cell in the flash memory 102, the data still remains to be written into the flash memory 102 (step 308), and the writing circuit 104 stores the second bit into each multi-level cell in the multi-level cells in sequence until the data is written or two bits of data are stored in each multi-level cell (step 310).

In step 308, if the determining circuit 106 determines that no data is to be written into the flash memory 102, the control device 100 ends the data writing operation of the flash memory 102 (step 324).

In step 310, the write circuit 104 continues to write a second bit to the multi-level cells already storing one bit of data until the data is written or each multi-level cell stores two bits of data. Further, for each multi-layer cell, the determining circuit 106 determines the data polarity of the first bit originally stored in the multi-layer cell and the data polarity of the second bit to be written next, and if the data polarity of the first bit of the multi-layer cell is bit 1 and the data polarity of the second bit is also bit 1, the writing circuit 104 does not inject a second charge amount to the floating gate of the multi-layer cell. If the data polarity of the first bit of the multi-layered cell is bit 1 and the data polarity of the second bit is bit 0, then write circuit 104 injects the second amount of charge into the floating gate of the multi-layered cell. If the data polarity of the first bit of the multi-layered cell is bit 0 and the data polarity of the second bit is bit 1, the write circuit 104 does not inject a third amount of charge into the floating gate of the multi-layered cell. If the data polarity of the first bit of the multi-layered cell is bit 0 and the data polarity of the second bit is also bit 0, then write circuit 104 injects the third amount of charge into the floating gate of the multi-layered cell, where the second amount of charge is different from the third amount of charge. In the present embodiment, the second charge amount is larger than the third charge amount, as shown in fig. 5.

Fig. 5 is a schematic diagram illustrating the charge distribution after 8192 multi-level cells in the flash memory 102 are written with two bits of data according to an embodiment of the present invention, wherein a curve 502 represents that a total of 2048 multi-level cells store data of bit 11, a curve 504 represents that a total of 2048 multi-level cells store data of bit 01, a curve 506 represents that a total of 2048 multi-level cells store data of bit 00, and a curve 508 represents that a total of 2048 multi-level cells store data of bit 10. Please note that the charge distribution shown in FIG. 5 is only an embodiment of the present invention, and the present invention is not limited thereto. In other words, in other embodiments of the present invention, the numbers of the multi-level cells for storing the bits 11, 01, 00, and 10 are not necessarily equal, and the numbers may be arbitrarily distributed. Therefore, as can be seen from the above-mentioned writing operation, for a multi-layer cell, the first bit written for the first time can be regarded as the Most Significant Bit (MSB) of the data stored in the multi-layer cell, and the second bit written for the second time can be regarded as the Least Significant Bit (LSB) of the data stored in the multi-layer cell.

Furthermore, as can be seen from the above data writing operation, when the data polarity of the first bit of the multi-layered cell is bit 1 and the data polarity of the second bit is also bit 1, the write circuit 104 does not inject any charge amount into the floating gate of the multi-layered cell; when the data polarity of the first bit of the multi-layered cell is bit 1 and the data polarity of the second bit is bit 0, the write circuit 104 only injects the second amount of charge into the floating gate of the multi-layered cell; when the data polarity of the first bit of the multi-layered cell is bit 0 and the data polarity of the second bit is bit 1, the write circuit 104 only injects the first amount of charge into the floating gate of the multi-layered cell; and when the data polarity of the first bit of the multi-layered cell is bit 0 and the data polarity of the second bit is also bit 0, the write circuit 104 injects the first amount of charge and the third amount of charge into the floating gate of the multi-layered cell. Accordingly, the charges stored in the floating gates of the multi-layered cells written with data as bits 11, 01, 00, and 10 are sequentially increased, as shown in fig. 5. In this way, when the reading circuit 110 is to read data stored in a multi-layer cell in the flash memory 102, two bits of data stored in the multi-layer cell can be distinguished by sequentially coupling the word lines of the multi-layer cell to three different threshold voltages (i.e., the threshold voltages Vth1, Vth2, and Vth3), wherein the threshold voltages Vth1, Vth2, and Vth3 are generated by the setting circuit 108. Please note that the present invention does not limit the method for the reading circuit 110 to read the two bits of data stored in the multi-level cells of the flash memory 102. Since a person skilled in the art can easily read the data of two bits stored in a multi-level cell according to the threshold voltages Vth1, Vth2, and Vth3, detailed operations of the reading circuit 110 are not described herein.

In step 312, if the determining circuit 106 determines that two bits of data are not written into the multi-layer cells in the flash memory 102, the writing circuit 104 will continue to write the second bit of data into the multi-layer cells until the data is written or each multi-layer cell stores two bits of data. If the determining circuit 106 determines that two bits of data are written into each multi-level cell in the flash memory 102 and data still remain to be written into the flash memory 102 (step 314), the writing circuit 104 stores the third bit into each multi-level cell in the multi-level cells in sequence until the data is written or three bits of data are stored in each multi-level cell (step 316).

In step 314, if the determining circuit 106 determines that no data is to be written into the flash memory 102, the control device 100 ends the data writing operation of the flash memory 102 (step 324).

In step 316, the write circuit 104 continues to write a third bit to the multi-level cells already storing two bits of data until the data is written or each multi-level cell stores three bits of data. Further, for each multi-layer cell, the determining circuit 106 determines the data polarity of the first bit and the second bit originally stored in the multi-layer cell and the data polarity of the third bit to be written in the multi-layer cell, and if the data polarity of the first bit and the second bit of the multi-layer cell is bit 11 and the data polarity of the third bit is also bit 1, the writing circuit 104 does not inject a fourth charge amount to the floating gate of the multi-layer cell. If the data polarity of the first bit, the second bit, and the third bit of the multi-layered cell is bit 11 and bit 0, the write circuit 104 injects the fourth charge into the floating gate of the multi-layered cell. If the data polarity of the first bit, the second bit, and the third bit of the multi-layered cell is bit 01 and bit 1, the write circuit 104 does not inject a fifth charge into the floating gate of the multi-layered cell. If the data polarity of the first bit, the second bit, and the third bit of the multi-layered cell is bit 01 and bit 0, the write circuit 104 injects the fifth charge into the floating gate of the multi-layered cell. If the data polarity of the first bit, the second bit, and the third bit of the multi-layered cell is bit 00 and bit 1, the write circuit 104 does not inject a sixth charge into the floating gate of the multi-layered cell. If the data polarity of the first bit, the second bit, and the third bit of the multi-layered cell is bit 00 and bit 0, the write circuit 104 injects the sixth charge into the floating gate of the multi-layered cell. If the data polarity of the first bit, the second bit, and the third bit of the multi-layered cell is bit 10 and bit 1, the write circuit 104 does not inject a seventh charge into the floating gate of the multi-layered cell. If the data polarity of the first bit, the data polarity of the second bit is bit 10, and the data polarity of the third bit is bit 0, the write circuit 104 injects the seventh charge amount into the floating gate of the multi-layered cell, wherein the fourth charge amount, the fifth charge amount, the sixth charge amount, and the seventh charge amount are different from each other. In the present embodiment, the fourth charge amount, the fifth charge amount, the sixth charge amount, and the seventh charge amount are gradually increased, as shown in fig. 6.

Fig. 6 is a schematic diagram illustrating the charge distribution after 8192 cells in the flash memory 102 are written with three bits of data according to an embodiment of the present invention, in which a curve 602 represents that a total of 1024 cells store data as bit 111, a curve 604 represents that a total of 1024 cells store data as bit 011, a curve 606 represents that a total of 1024 cells store data as bit 001, a curve 608 represents that a total of 1024 cells store data as bit 101, a curve 610 represents that a total of 1024 cells store data as bit 100, a curve 612 represents that a total of 1024 cells store data as bit 000, a curve 614 represents that a total of 1024 cells store data as bit 010, and a curve 616 represents that a total of 1024 cells store data as bit 110. Please note that the charge distribution shown in FIG. 6 is only an embodiment of the present invention, and the present invention is not limited thereto. In other words, in other embodiments of the present invention, the numbers of the multi-layer cells for storing the bits 111, 011, 001, 101, 100, 000, 010, and 110 are not necessarily equal, and the numbers may be arbitrarily allocated. Therefore, as can be seen from the above-mentioned writing operation, for a multi-layer cell, the first bit written for the first time can be regarded as the Most Significant Bit (MSB) of the data stored in the multi-layer cell, the second bit written for the second time can be regarded as the second MSB of the data stored in the multi-layer cell, and the third bit written for the third time can be regarded as the Least Significant Bit (LSB) of the data stored in the multi-layer cell.

Furthermore, as can be seen from the above data writing operation, when the data polarity of the first bit and the data polarity of the second bit of the multi-layered cell are bit 11 and the data polarity of the third bit is bit 1, the write circuit 104 does not inject any charge amount into the floating gate of the multi-layered cell; when the data polarity of the first bit, the second bit, and the third bit of the multi-layered cell is bit 11 and bit 0, the write circuit 104 only injects the fourth charge into the floating gate of the multi-layered cell; when the data polarity of the first bit, the second bit, and the third bit of the multi-layered cell is bit 01 and bit 1, the write circuit 104 only injects the first charge amount into the floating gate of the multi-layered cell; when the data polarity of the first bit, the data polarity of the second bit is bit 01, and the data polarity of the third bit is bit 0, the write circuit 104 injects the first charge amount and the sixth charge amount into the floating gate of the multi-layered cell; when the data polarity of the first, second bits of the multi-layered cell is bit 00 and the data polarity of the third bit is bit 1, the write circuit 104 only injects the first and third charge amounts into the floating gate of the multi-layered cell; when the data polarity of the first, second bits of the multi-layered cell is bit 00 and the data polarity of the third bit is bit 0, the write circuit 104 only injects the first, third and seventh charge amounts into the floating gate of the multi-layered cell; when the data polarity of the first bit, the second bit, and the third bit of the multi-layered cell is bit 10 and bit 1, the write circuit 104 only injects the second charge amount into the floating gate of the multi-layered cell; when the data polarity of the first bit, the second bit, and the third bit of the multi-layered cell is bit 10 and bit 0, the write circuit 104 only injects the second charge amount and the fifth charge amount into the floating gate of the multi-layered cell. Accordingly, the charges stored in the floating gates of the multi-layered cells written with data of bits 111, 011, 001, 101, 100, 000, 010, and 110 are sequentially increased, as shown in fig. 6. In this way, when the reading circuit 110 is to read data stored in a multi-layer cell in the flash memory 102, three bits of data stored in the multi-layer cell can be distinguished by sequentially coupling the word lines of the multi-layer cell to six different threshold voltages (i.e., threshold voltages Vth1, Vth2, Vth3, Vth4, Vth5, and Vth6), where the threshold voltages Vth1, Vth2, Vth3, Vth4, Vth5, and Vth6 are generated by the setting circuit 108. Please note that the present invention does not limit the method for reading the three bits of data stored in the multi-level cells of the flash memory 102 by the reading circuit 110. Since a person skilled in the art can easily read the data of three bits stored in a multi-layer cell according to the threshold voltages Vth1, Vth2, Vth3, Vth4, Vth5 and Vth6, detailed operations of the reading circuit 110 are not described herein.

In step 318, if the determining circuit 106 determines that three bits of data are not written into the multi-layer cell in the flash memory 102, the writing circuit 104 will continue to write the third bit of data into the multi-layer cell until the data is written or each multi-layer cell stores three bits of data. If the determining circuit 106 determines that three bits of data are written into each multi-layer cell in the flash memory 102, and data still remain to be written into the flash memory 102 (step 320), the writing circuit 104 writes data into another flash memory or erases (erase) charges in the multi-layer cells of the flash memory 102 to continue writing data into the flash memory 102, and repeats the above steps 302 and 322.

In step 320, if the determining circuit 106 determines that no data is to be written into the flash memory 102, the control device 100 ends the data writing operation of the flash memory 102 (step 324).

It can be seen from the above-described steps of method 300 that when write circuit 104 is to write bit 1 into a multi-layer cell, write circuit 104 does not inject charge into the floating gate of the multi-layer cell, and when write circuit 104 is to write bit 0 into the multi-layer cell, write circuit 104 injects charge into the floating gate of the multi-layer cell, as shown in FIG. 7. FIG. 7 is a schematic diagram illustrating an embodiment of criteria for writing three bits of data to each MLC in the flash memory 102 according to the invention. Therefore, when the multi-layer cell is written for the first time, if the bit of the data is 1, no charge is injected, and if the bit of the data is 0, the first charge amount is injected. When writing the multi-layer unit for the second time, if the bit of the data is 11 or 01, no charge is injected; injecting the second amount of charge if the bit of the data is 10; if the bit of data is 00, the third amount of charge is injected. When writing the multi-layer unit for the third time, if the bit of the data is 111, 101, 011 or 001, no charge is injected; injecting the fourth amount of charge if the bit of data is 110; injecting the fifth amount of charge if the bit of data is 100; injecting the sixth amount of charge if the bit of data is 010; if the bit of data is 000, the seventh amount of charge is injected.

It should be noted that although the above embodiments are exemplified by three-level flash memory cells capable of storing three bits, it should be understood by those skilled in the art that the data writing method of the present invention is also applicable to any multi-level flash memory cells after reading the operation characteristics of the embodiments, and thus the present invention also falls within the scope of the present invention.

According to the method 300 of the present invention, the control device 100 can have at least two different data writing operations. First, if a large amount of data is to be written into the flash memory 102, the control device 100 will write the second bit of data into each multi-level cell of the flash memory 102 after the multi-level cell is filled with one bit of data, and will write the third bit of data into each multi-level cell of the flash memory 102 after the multi-level cell is filled with two bits of data. When each multi-level cell in the flash memory 102 is full of three bits of data, the control device 100 will continue to store data in another flash memory. Second, if only a small amount of data is to be written into the flash memory 102 each time, for example, the small amount of data is to be written into only one or two bits of each multi-level cell in the flash memory 102, the control device 100 can erase the flash memory 102 before each new amount of data is to be written into the flash memory 102, so as to erase the data previously written into one or two bits of the multi-level cell. Then, the control device 100 writes new data to the flash memory 102.

It can be known from the two different data writing operations that the control device 100 performs the erasing operation on the flash memory 102 after at least three bits of data are written in each multi-level cell in the flash memory 102 in the first data writing operation. Therefore, the first data writing operation can greatly reduce the erasing times of three bits of data (i.e. full data), thereby improving the writing speed and the service life of the flash memory 102. The second data writing operation is an operation in which the control device 100 erases the flash memory 102 after data is written into one or two bits of each multi-level cell in the flash memory 102. Although the second data writing operation has a relatively large number of data erasing operations, the control device 100 only erases one or two bits of data (i.e., data that is not full) in the flash memory 102, but not three bits of data. Therefore, the second data writing operation can also improve the lifespan of the flash memory 102.

In summary, the control method of the flash memory control circuit disclosed in the present invention writes data into the lower bits of each multi-level cell in a flash memory, and writes data into the upper bits of each multi-level cell after the lower bits are all written with data. Therefore, the invention can greatly reduce the times of erasing the full-load data in the flash memory and increase the times of erasing the non-full-load data in the flash memory so as to improve the writing speed and the service life of the flash memory.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.