阅读说明：本技术 存储装置及该存储装置的操作方法 (Storage device and operation method thereof ) 是由 许民虎 金东眩 金承日 郑然镐 于 2019-04-29 设计创作，主要内容包括：本发明提供一种可靠性提高的存储器装置,该存储器装置包括：存储器单元阵列,包括存储器单元；编程操作控制器,对存储器单元执行编程操作以使存储器单元具有第一至第n状态之中的任意一个状态；电压发生器,在编程操作中生成分别对应于第一至第n状态的操作电压；验证操作控制器,验证是否已经完成对选择的存储器单元执行以使选择的存储器单元具有第k状态的编程操作,并且对选择的存储器单元之中、具有比对应于第k状态的阈值电压大的阈值电压的过度编程的存储器单元的数量进行计数；以及过度编程管理器,根据过度编程的存储器单元的数量,增加对应于第k+1至第n状态的操作电压,以使对应于第k+1至第n状态的操作电压大于默认值。(The present invention provides a memory device with improved reliability, comprising: a memory cell array including memory cells; a program operation controller performing a program operation on the memory cell to make the memory cell have any one of first to nth states; a voltage generator generating operation voltages respectively corresponding to first to nth states in a program operation; a verification operation controller verifying whether a program operation performed on the selected memory cells to have the selected memory cells have a k-th state has been completed and counting the number of over-programmed memory cells having a threshold voltage greater than a threshold voltage corresponding to the k-th state among the selected memory cells; and an over program manager increasing the operating voltages corresponding to the (k + 1) th to nth states according to the number of over programmed memory cells such that the operating voltages corresponding to the (k + 1) th to nth states are greater than a default value.)

1. A memory device, comprising:

a memory cell array including memory cells;

a program operation controller performing a program operation on the memory cell to have the memory cell have any one of first to nth states distinguished according to a threshold voltage, where n is a natural number greater than 1;

a voltage generator generating operation voltages respectively corresponding to the first to nth states in the program operation;

a verification operation controller verifying whether the program operation performed on a selected memory cell to have the selected memory cell have a k-th state, where k is a natural number less than n, has been completed, and counting the number of over-programmed memory cells having a threshold voltage greater than a threshold voltage corresponding to the k-th state among the selected memory cells; and

and the over programming manager increases the operating voltages respectively corresponding to the (k + 1) th to the (n) th states according to the number of the over programmed memory cells, so that the operating voltages respectively corresponding to the (k + 1) th to the (n) th states are larger than respective corresponding default values.

2. The memory device of claim 1, wherein the over programming manager comprises an offset voltage table storing an offset value representing a width by which the operating voltage is shifted from a default value according to a number of the over programmed memory cells.

3. The memory device of claim 2, wherein the over programming manager comprises an over programming processor that generates over programming status information that indicates whether a number of the over programmed memory cells exceeds a reference number.

4. The memory device according to claim 3, wherein when the number of over-programmed memory cells exceeds the reference number, the over-programmed processor generates offset voltage information representing information on offset values of operating voltages respectively corresponding to the k +1 th to n-th states based on the offset voltmeter.

5. The memory device of claim 4, further comprising a status register storing the over program status information and the offset voltage information.

6. The memory device of claim 5, wherein the status register stores status information about the memory device,

wherein the state information includes ready information indicating that an operation capable of receiving a new command and being performed in response to a previously received command has been completed, the over program state information, the offset voltage information, and failure information indicating that an operation corresponding to the previously received command has failed.

7. The memory device according to claim 4, wherein the over-programmed processor controls magnitudes of operating voltages respectively corresponding to the k +1 th to n-th states based on the offset voltage information.

8. The memory device of claim 1, wherein the operating voltage comprises at least one voltage among a verify voltage, a program voltage, and a pass voltage.

9. A memory device, comprising:

a memory device increasing voltages used in a program operation and a verify operation for memory cells in k +1 th to nth states, where n is a natural number greater than 1 and k is a natural number less than n, according to the number of over-programmed memory cells having a threshold voltage greater than a threshold voltage corresponding to the k-th state among selected memory cells programmed to the k-th state; and

a memory controller to treat a memory block including the selected memory cell as a bad block when the number of over-programmed memory cells exceeds a reference number.

10. The storage device of claim 9, wherein the memory controller comprises a bad block manager that reads data of a memory block including the selected memory cell and programs the read data in another memory block.

11. The storage device of claim 10, wherein the bad block manager reads data of a memory block including the selected memory cell by adjusting a default read voltage value according to the number of over programmed memory cells.

12. The storage device according to claim 10, wherein the bad block manager includes a bad block table that stores information on a bad memory block among a plurality of memory blocks included in the memory device,

wherein the bad block manager adds information on a memory block including the selected memory cell to the bad block table or updates information on a memory block including the selected memory cell when the number of over-programmed memory cells exceeds the reference number.

13. A method for operating a memory device, the memory device comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, the method comprising:

performing a program operation on a selected memory cell to have a kth state among first to nth states, where n is a natural number greater than 1 and k is a natural number less than n;

generating operation voltages respectively corresponding to the first to nth states in the program operation;

performing a verify operation on the selected memory cell;

counting a number of over programmed memory cells having a threshold voltage greater than a threshold voltage corresponding to the k-th state when the verify operation passes; and

and increasing the operating voltages respectively corresponding to the (k + 1) th to nth states among the operating voltages according to the number of the over-programmed memory cells, so that the operating voltages respectively corresponding to the (k + 1) th to nth states among the operating voltages are greater than respective default values.

14. The method of claim 13, wherein increasing the operating voltage comprises: generating over-programmed state information indicating whether the number of over-programmed memory cells exceeds a reference number.

15. The method of claim 14, wherein increasing the operating voltage comprises: generating offset voltage information based on the number of over-programmed memory cells when the number of over-programmed memory cells exceeds the reference number, the offset voltage information representing information on offset values of operating voltages respectively corresponding to the (k + 1) -th states, the offset values of the operating voltages respectively corresponding to the (k + 1) -th states representing widths of the operating voltages respectively corresponding to the (k + 1) -th states shifted from respective default values.

16. The method according to claim 15, wherein when increasing the operating voltage, operating voltages respectively corresponding to the (k + 1) th to n-th states are adjusted based on the offset voltage information.

17. The method of claim 15, wherein the offset value increases as the number of over programmed memory cells increases.

18. The method of claim 15, further comprising storing the over program state information and the offset voltage information in a status register.

19. The method of claim 18, further comprising providing information stored in the status register to a memory controller.

20. The method of claim 13, wherein the operating voltage comprises at least one voltage among a verify voltage, a program voltage, and a pass voltage.

Technical Field

The present disclosure relates generally to an electronic device, and more particularly, to a memory device and an operating method of the memory device.

Background

The storage device stores data under the control of a host device such as a computer or smart phone. The memory device may include a memory device for storing data and a memory controller for controlling the memory device. The memory device may be a volatile memory device or a non-volatile memory device.

In a volatile memory device, stored data is retained only when power is supplied; when the power supply is interrupted, the stored data is lost. The volatile memory device may be any one of a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), and the like.

In the nonvolatile memory device, stored data is retained even when power supply is interrupted. The non-volatile memory device may be any of read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable ROM (EEROM), flash memory, and the like.

Disclosure of Invention

Drawings

Various embodiments will now be described more fully with reference to the accompanying drawings; however, the elements and features may be configured or arranged differently than disclosed herein. Accordingly, the present invention is not limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

In the drawings, the size may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout. Moreover, references throughout this specification to "an embodiment," "another embodiment," etc., do not necessarily refer to only one embodiment, and different references to any such phrase do not necessarily refer to the same embodiment.

Fig. 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

Fig. 2 is a diagram illustrating a structure of a memory device according to an embodiment of the present disclosure.

Fig. 3 is a diagram illustrating a memory cell array according to an embodiment of the present disclosure.

Fig. 4 is a diagram illustrating a memory cell array according to an embodiment of the present disclosure.

Fig. 5 is a circuit diagram illustrating any one of memory blocks according to an embodiment of the present disclosure.

Fig. 6 is a circuit diagram illustrating any one of memory blocks according to an embodiment of the present disclosure.

Fig. 7 is a diagram illustrating threshold voltage distributions of memory cells formed by a program operation.

Fig. 8 is a diagram illustrating a program operation of a memory device.

Fig. 9 is a diagram illustrating threshold voltage distributions of a normal program state.

Fig. 10 is a diagram illustrating a method for determining whether an over program operation has been performed and controlling an operation voltage corresponding to a program state.

Fig. 11 is a diagram illustrating an operation of an over program manager of a memory device according to an embodiment of the present disclosure.

Fig. 12 is a diagram illustrating an offset voltmeter according to an embodiment of the present disclosure.

Fig. 13 is a diagram illustrating a status register according to an embodiment of the present disclosure.

Fig. 14 is a diagram illustrating a method for acquiring over programming determination information according to an embodiment of the present disclosure.

Fig. 15 is a diagram illustrating an operation of a bad block manager of a memory controller according to an embodiment of the present disclosure.

Fig. 16 is a flowchart illustrating an operation of a memory device according to an embodiment of the present disclosure.

Fig. 17 is a flow chart illustrating operation of a memory controller according to an embodiment of the present disclosure.

Fig. 18 is a flowchart illustrating an operation of a memory device according to an embodiment of the present disclosure.

Fig. 19 is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

Fig. 20 is a block diagram illustrating a memory card system to which a storage device is applied according to an embodiment of the present disclosure.

Fig. 21 is a block diagram illustrating a Solid State Drive (SSD) to which a storage device is applied according to an embodiment of the present disclosure.

Fig. 22 is a block diagram illustrating a user system applying a storage device according to an embodiment of the present disclosure.

Embodiments provide a memory device having improved reliability and an operating method of the memory device.

According to an aspect of the present disclosure, there is provided a memory device including: a memory cell array including memory cells; a program operation controller configured to perform a program operation on the memory cell to make the memory cell have any one state among first to nth states distinguished according to a threshold voltage, wherein n is a natural number greater than 1; a voltage generator configured to generate operation voltages respectively corresponding to first to nth states in a program operation; a verifying operation controller configured to verify whether a programming operation performed on the selected memory cells to have the selected memory cells have a k-th state, where k is a natural number less than n, has been completed, and to count the number of over-programmed memory cells having a threshold voltage greater than a threshold voltage corresponding to the k-th state among the selected memory cells; and an over-program manager configured to increase the operating voltages respectively corresponding to the (k + 1) th to nth states according to the number of over-programmed memory cells so that the operating voltages respectively corresponding to the (k + 1) th to nth states are greater than respective corresponding default values.

According to another aspect of the present disclosure, there is provided a storage apparatus including: a memory device configured to increase voltages used in a program operation and a verify operation on memory cells in k +1 th to nth states, where n is a natural number greater than 1 and k is a natural number less than n, according to the number of over-programmed memory cells having a threshold voltage greater than a threshold voltage corresponding to the k-th state among selected memory cells programmed to the k-th state; and a memory controller configured to treat a memory block including the selected memory cell as a bad block when the number of over-programmed memory cells exceeds a reference number.

According to yet another aspect of the present disclosure, there is provided a method for operating a memory device including a plurality of memory blocks, each memory block including a plurality of memory cells, the method including: performing a program operation on the selected memory cell to have a kth state among first to nth states, where n is a natural number greater than 1 and k is a natural number less than n; generating operation voltages respectively corresponding to first to n-th states in a program operation; performing a verify operation on the selected memory cell; counting the number of over programmed memory cells having a threshold voltage greater than a threshold voltage corresponding to a k-th state when the verify operation passes; and increasing the operation voltages respectively corresponding to the (k + 1) th to nth states among the operation voltages according to the number of the over-programmed memory cells, so that the operation voltages respectively corresponding to the (k + 1) th to nth states among the operation voltages are greater than respective default values.

According to still another aspect of the present disclosure, there is provided a storage apparatus including: a memory device including a plurality of memory cells, a voltage generator adapted to generate operating voltages respectively corresponding to program states, and control logic; and a memory controller, wherein the control logic is configured to: controlling a program operation on a selected memory cell among the plurality of memory cells to have a selected state among the program states; detecting over programmed memory cells among the selected memory cells through a program verify operation; controlling a voltage generator to generate an increased operating voltage for at least one other state among the programmed states based on the detected number of over-programmed memory cells, a threshold voltage corresponding to the at least one other state being greater than a threshold voltage corresponding to the selected state; and providing over-programming determination information regarding the over-programmed memory cells to a memory controller, wherein the memory controller is configured to receive the over-programming determination information and treat a memory block including at least some of the over-programmed memory cells as a bad block based on the over-programming determination information.