阅读说明：本技术 一种分栅快闪存储器的版图、掩膜版及版图制作方法 (Layout and mask of split-gate flash memory and layout manufacturing method ) 是由 陈宏� 于 2019-10-25 设计创作，主要内容包括：本发明提供一种分栅快闪存储器的版图、掩膜版及版图制作方法，所述分栅快闪存储器的版图包括一浮栅版图层，所述浮栅版图层的浮栅图形区四周形成有冗余图形区，采用该版图制得掩膜版，从而形成分栅快闪存储器时，形成的分栅快闪存储器的浮栅结构的四围还围绕着没有功能的冗余结构，该冗余结构在后续对存储器的源线进行研磨时，起到负载作用，可在一定程度上保护浮栅结构的边缘不会被过度研磨，从而可以避免字线高度过低。即，本发明提供的分栅快闪存储器的版图、掩膜版及版图制作方法解决了分栅快闪存储器编程串扰失效的问题。(The invention provides a layout of a split-gate flash memory, a mask and a layout manufacturing method, wherein the layout of the split-gate flash memory comprises a floating gate layout layer, a redundant graphic area is formed around the floating gate graphic area of the floating gate layout layer, the mask is manufactured by adopting the layout, so that when the split-gate flash memory is formed, the periphery of a floating gate structure of the formed split-gate flash memory also surrounds a redundant structure without functions, and the redundant structure plays a role in loading when a source line of the memory is ground subsequently, can protect the edge of the floating gate structure from being excessively ground to a certain extent, and can avoid the situation that the height of a word line is too low. Namely, the layout, the mask and the layout manufacturing method of the split-gate flash memory provided by the invention solve the problem of programming crosstalk failure of the split-gate flash memory.)

1. The layout of the split-gate flash memory is characterized in that the layout of the split-gate flash memory comprises a floating gate layout layer, the floating gate layout layer comprises a floating gate graphic region and a redundant graphic region, and the redundant graphic region surrounds the floating gate graphic region and keeps a set distance with the floating gate graphic region.

2. The layout of the split-gate flash memory according to claim 1, wherein the set distance is in a range of 1.5 μm to 2.5 μm.

3. The layout of the split-gate flash memory according to claim 1, wherein the redundant pattern area comprises at least one redundant pattern, and the redundant pattern is in a rectangular frame shape.

4. The layout of the split-gate flash memory according to claim 3, wherein when the number of the redundant patterns is greater than or equal to 2, all the redundant patterns are concentrically distributed.

5. The layout of the split-gate flash memory according to claim 1, wherein the layout of the split-gate flash memory further comprises a word line layout layer, and the word line layout layer is located above the floating gate layout layer.

6. A mask of a split-gate flash memory, which is manufactured by using the layout of the split-gate flash memory according to any one of claims 1 to 5.

7. A manufacturing method of a split-gate flash memory layout is characterized by comprising the following steps:

acquiring an original layout, wherein the original layout comprises a floating gate layout layer, and the floating gate layout layer comprises a floating gate graphic area;

and forming a redundant pattern area, wherein the redundant pattern area is arranged around the floating gate pattern area and keeps a set distance with the floating gate pattern area.

8. The method for manufacturing the split-gate flash memory layout according to claim 7, wherein the set distance is in a range of 1.5 μm to 2.5 μm.

9. The method for manufacturing a split-gate flash memory layout according to claim 7, wherein the redundant pattern region comprises at least one redundant pattern, and the redundant pattern is in a rectangular frame shape.

10. The method for manufacturing a split-gate flash memory layout according to claim 9, wherein when the number of the redundant patterns is greater than or equal to 2, all the redundant patterns are concentrically distributed.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a layout of a split-gate flash memory, a mask and a layout manufacturing method.

Background

In general, flash memories (flash memories) include two basic structures: gate stack (stackgate) and split gate (split gate) type structures. Referring to fig. 1, a conventional memory cell structure of a split-gate flash memory includes: a semiconductor substrate 10, a drain region (i.e., a bit line, BL)111, a source region 112, a source line polysilicon layer (i.e., a source line, SL)12, a floating gate Oxide layer 13, a floating gate polysilicon layer (FG) 14, a first sidewall (FGspacer1, FGSP1)151, a second sidewall 152(FG spacer2, FGSP1), a Tunnel Oxide layer 16(Tunnel Oxide), a word line polysilicon layer (i.e., a word line d line, WL)17, and a word line sidewall 18 (WLSP). When the split-gate flash memory cell is programmed, a word line is used as a Control Gate (CG), a high voltage is applied to the source line polysilicon layer 12, a voltage capable of opening a channel is applied to the word line polysilicon layer 17, and a constant current is injected through the drain region 111, and the source line polysilicon layer 12 is at a high potential, under the action of the high potential, on one hand, hot electrons are generated in the channel, on the other hand, the high potential is coupled to the floating gate polysilicon layer 14, the floating gate polysilicon layer 14 generates a coupling voltage, and under the action of the coupling voltage, electrons are injected from the floating gate polysilicon layer 14 to the floating gate polysilicon layer 14 near the source region, thereby realizing programming.

Due to the special structure of the split-gate flash memory, the problem of programming crosstalk failure (PTC) is easily caused, the PTC is often found at the edge of the wafer, and the failure bit is located at the edge of the flash memory array. This failure is often due to the word line height being too low, resulting in subsequent ion implantation through the word line into the channel, causing punch-through failure of the word line transistor.

Disclosure of Invention

The invention aims to provide a layout and a mask of a split-gate flash memory and a layout manufacturing method, so as to solve the problem of programming crosstalk failure of the split-gate flash memory.

In order to solve the technical problem, the invention provides a layout of a split-gate flash memory, wherein the layout of the split-gate flash memory comprises a floating gate layout layer, the floating gate layout layer comprises a floating gate pattern area and a redundant pattern area, and the redundant pattern area is arranged around the floating gate pattern area and keeps a set distance with the floating gate pattern area.

Optionally, in the layout of the split-gate flash memory, the range of the set distance is 1.5 μm to 2.5 μm.

Optionally, the layout of the split-gate flash memory is that the redundant graph area includes at least one redundant graph, and the redundant graph is in a rectangular frame shape.

Optionally, in the layout of the split-gate flash memory, when the number of the redundant graphs is greater than or equal to 2, all the redundant graphs are concentrically distributed.

Optionally, the layout of the split-gate flash memory further includes a word line layout layer, and the word line layout layer is located above the floating gate layout layer.

The invention also provides a mask of the split-gate flash memory, which is made by utilizing the layout of the split-gate flash memory.

The invention also provides a manufacturing method of the split-gate flash memory layout, which comprises the following steps:

acquiring an original layout, wherein the original layout comprises a floating gate layout layer, and the floating gate layout layer comprises a floating gate graphic area;

and forming a redundant pattern area, wherein the redundant pattern area is arranged around the floating gate pattern area and keeps a set distance with the floating gate pattern area.

Optionally, in the method for manufacturing the split-gate flash memory layout, the set distance ranges from 1.5 μm to 2.5 μm.

Optionally, in the method for manufacturing the split-gate flash memory layout, the redundant pattern area includes at least one redundant pattern, and the redundant pattern is in a rectangular frame shape.

Optionally, in the manufacturing method of the split-gate flash memory layout, when the number of the redundant patterns is greater than or equal to 2, all the redundant patterns are concentrically distributed.

In the layout, the mask and the layout manufacturing method of the split-gate flash memory provided by the invention, the layout of the split-gate flash memory comprises a floating gate layout layer, a redundant graphic area is formed around the floating gate graphic area of the floating gate layout layer, and the mask is manufactured by adopting the layout, so that when the split-gate flash memory is formed, the periphery of the floating gate structure of the formed split-gate flash memory also surrounds a redundant structure without functions, and the redundant structure can protect the edge of the floating gate structure from being excessively ground to a certain extent when a source line of the memory is ground subsequently, so that the phenomenon that the height of a word line is too low can be avoided. Namely, the layout, the mask and the layout manufacturing method of the split-gate flash memory provided by the invention solve the problem of programming crosstalk failure of the split-gate flash memory.

Drawings

FIG. 1 is a schematic diagram of a conventional split-gate flash memory cell structure;

fig. 2 is a layout of an exemplary split-gate flash memory according to the present embodiment;

fig. 3 is a layout of another exemplary split-gate flash memory provided in this embodiment;

fig. 4 is a flowchart illustrating a method for manufacturing a split-gate flash memory layout according to this embodiment;

wherein the reference numerals are as follows:

10-a semiconductor substrate; 111-drain region; 112-source region; a 12-source line polysilicon layer; 13-floating gate oxide layer; 14-floating gate polysilicon layer; 151-first side wall; 151-second side wall; 16-tunneling oxide layer; 17-word line polysilicon layer; 18-word line sidewalls.

20-floating gate layout layer; 21-floating gate pattern region; 22-redundant pattern area; 201-floating gate pattern; 202-redundant graphics; 30-wordline layout layer.

Detailed Description

The layout, the mask and the layout manufacturing method of the split-gate flash memory according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures shown in the drawings are often part of actual structures. In particular, the drawings may show different emphasis on the side points and may sometimes be in different proportions.

The conventional method for forming a split-gate flash memory generally includes the following steps: (1) providing a semiconductor substrate, and forming a floating gate structure and a word line structure on the semiconductor substrate; (2) forming a source line polycrystalline silicon layer in the groove between the adjacent floating gate structures and the epitaxial part of the groove; (3) and grinding the source line polysilicon layer. The floating gate structure and the word line structure may be formed by any relevant process known to those skilled in the art, and are not described herein again.

When the source line polysilicon layer is ground, the edge of the floating gate structure is easily over ground due to a load effect, and further, the word line height is too low, which causes a problem of programming crosstalk failure.

In view of this, referring to fig. 2, the present embodiment provides a layout of a split-gate flash memory, where the layout of the split-gate flash memory includes a floating gate layout layer 20, the floating gate layout layer 20 includes a floating gate pattern region 21 and a redundant pattern region 22, and the redundant pattern region 22 is disposed around the floating gate pattern region 21 and keeps a set distance from the floating gate pattern region 21.

On the basis, the embodiment also provides a mask of the split-gate flash memory, and the mask is made by adopting the layout of the split-gate flash memory provided by the embodiment.

The layout of the split-gate flash memory is adopted to manufacture the mask, so that when the split-gate flash memory is formed, the periphery of the floating gate structure of the formed split-gate flash memory is surrounded by a redundant structure without function, and the redundant structure can protect the edge of the floating gate structure from being excessively ground to a certain extent when a source line of the memory is ground subsequently, so that the phenomenon that the height of a word line is too low can be avoided, and the programming crosstalk failure of the split-gate flash memory can be improved. Particularly, since the redundant structure is formed to surround the periphery of the floating gate structure, the improvement effect is particularly remarkable in the case of facing the load effect, compared with the case where the redundant structure is formed only on both sides of the floating gate structure.

Preferably, the set distance D is in the range of 1.5 μm to 2.5. mu.m, and may be, for example, 1.5. mu.m, 2 μm, 2.5. mu.m, or the like. When the distance in this range is adopted, the improvement effect is the best.

The mask of the split-gate flash memory provided in this embodiment is further described below.

In fig. 2, the floating gate pattern area 21 is shown as an exemplary floating gate pattern 201, but the floating gate pattern 201 may be changed according to the process requirements, for example, the floating gate pattern 201 of the floating gate pattern area 21 may be as shown in fig. 3. The specific shape of the floating gate pattern 201 is not particularly required in this embodiment, but those skilled in the art will understand that, in general, the floating gate pattern 201 is substantially in the shape of a stripe, and a plurality of floating gate patterns 201 are sequentially arranged in parallel.

On this basis, in this embodiment, the redundant pattern region 22 is configured to include at least one redundant pattern 202, the redundant pattern 202 is in a rectangular frame shape, and the specific length and width of the redundant pattern 202 are matched with those of the floating gate pattern region 21.

Generally, in consideration of the difficulty of the actual process operation, referring to fig. 2, the number of the redundant patterns 202 in this embodiment may be 1, and when the number of the redundant patterns 202 is 1, a better improvement effect may be achieved. However, if the process conditions allow, the number of the redundant patterns 202 may be set to be greater than or equal to 2 (not shown), and when the number of the redundant patterns 202 is greater than or equal to 2, all the redundant patterns 202 are concentrically distributed.

The layout of the split-gate flash memory provided in this embodiment may further include other layers, such as a word line layout layer 30 and a source line layout layer. Fig. 2 and 3 only illustrate the wordline layout layer 30, and the wordline layout layer 30 is located above the floating gate layout layer 20.

Based on the same idea, please refer to fig. 4, this embodiment further provides a method for manufacturing a split gate flash memory layout, which includes the following steps:

s11, acquiring an original layout, wherein the original layout comprises a floating gate layout layer 20, and the floating gate layout layer 20 comprises a floating gate graphic area 21;

s12, forming a redundant pattern region 22, wherein the redundant pattern region 22 is disposed around the floating gate pattern region 21 and keeps a set distance from the floating gate pattern region 21.

The manufacturing method of the split-gate flash memory layout provided in this embodiment is further described below.

Firstly, step S11 is executed to obtain an original layout, referring to fig. 3, where the original layout includes a floating gate layout layer 20, and may further include a word line layout layer 30, a source line layout layer, and the like, and only the word line layout layer 30 is illustrated in fig. 3, and the word line layout layer 30 is located above the floating gate layout layer 20. The floating gate layout layer 20 includes a plurality of floating gate patterns 201, and all the floating gate patterns 201 are sequentially arranged in parallel. Likewise, the specific shape of the floating gate pattern 201 is not particularly required here.

Next, step S12 is executed to form a redundant pattern region 22, where the redundant pattern region 22 is disposed around the floating gate pattern region 21 and keeps a set distance from the floating gate pattern region 21, and the set distance is preferably in a range from 1.5 μm to 2.5 μm, and may be, for example, 1.5 μm, 2 μm, 2.5 μm, and the like. When the distance in this range is adopted, the improvement effect is the best.

Similarly, the number of the redundant patterns 202 may be 1, and when the number of the redundant patterns 202 is 1, a better improvement effect may be achieved. However, if the process conditions allow, the number of the redundant patterns 202 may also be set to be greater than or equal to 2, and when the number of the redundant patterns 202 is greater than or equal to 2, all the redundant patterns 202 are concentrically distributed.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.