阅读说明：本技术 显示面板及改善显示面板的显示质量的方法 (Display panel and method for improving display quality of display panel ) 是由 刘轩辰 詹建廷 张崇霖 于 2018-08-14 设计创作，主要内容包括：本发明公开一种显示面板，包括基板、第一子像素、第二子像素、第一栅极驱动单元及第二栅极驱动单元。基板表面包括显示区与周边区，显示区包括第一区域和第二区域，第一区域具有第一扫描线，第二区域具有第二扫描线。第一子像素设置在第一区域内，部分第一子像素电连接第一扫描线。第二子像素设置在第二区域内，部分第二子像素电连接第二扫描线。第一栅极驱动单元具有第一驱动晶体管，第一栅极驱动单元电连接第一扫描线。第二栅极驱动单元具有第二驱动晶体管，第二栅极驱动单元电连接第二扫描线。第一栅极驱动单元驱动的第一子像素的数量小于由第二栅极驱动单元驱动的第二子像素的数量，且第一驱动晶体管的通道宽度小于第二驱动晶体管的通道宽度。(The invention discloses a display panel, which comprises a substrate, a first sub-pixel, a second sub-pixel, a first grid driving unit and a second grid driving unit. The substrate surface comprises a display area and a peripheral area, the display area comprises a first area and a second area, the first area is provided with a first scanning line, and the second area is provided with a second scanning line. The first sub-pixels are arranged in the first area, and part of the first sub-pixels are electrically connected with the first scanning lines. The second sub-pixels are arranged in the second area, and part of the second sub-pixels are electrically connected with the second scanning lines. The first grid driving unit is provided with a first driving transistor and is electrically connected with the first scanning line. The second grid driving unit is provided with a second driving transistor and is electrically connected with the second scanning line. The number of the first sub-pixels driven by the first gate driving unit is smaller than the number of the second sub-pixels driven by the second gate driving unit, and the channel width of the first driving transistor is smaller than the channel width of the second driving transistor.)

1. A display panel, comprising:

the display device comprises a substrate, a first light source and a second light source, wherein the substrate is provided with a surface, the surface comprises a display area and a peripheral area arranged on at least one side of the display area, the display area comprises a first area and a second area, the first area is provided with a first scanning line, and the second area is provided with a second scanning line;

a plurality of first sub-pixels disposed in the first region, wherein at least a portion of the first sub-pixels are electrically connected to the first scan lines;

a plurality of second sub-pixels disposed in the second region, wherein at least a portion of the second sub-pixels are electrically connected to the second scan lines;

the first gate driving unit is arranged in the peripheral area and provided with a first driving transistor, and the first gate driving unit is electrically connected with the first scanning line and drives the first sub-pixel electrically connected with the first scanning line through the first scanning line; and

the second grid driving unit is arranged in the peripheral area and provided with a second driving transistor, and the second grid driving unit is electrically connected with the second scanning line and drives the second sub-pixel electrically connected with the second scanning line through the second scanning line;

wherein the number of the first sub-pixels driven by the first gate driving unit is smaller than the number of the second sub-pixels driven by the second gate driving unit, and the channel width of the first driving transistor is smaller than the channel width of the second driving transistor.

2. The display panel according to claim 1, wherein gates of the first driving transistor and the second driving transistor are formed of a first conductive layer, sources and drains of the first driving transistor and the second driving transistor are formed of a second conductive layer, the first conductive layer is provided between the second conductive layer and the substrate, and areas of the source and drain of the first driving transistor are smaller than areas of the source and drain of the second driving transistor.

3. The display panel according to claim 2, wherein the first gate driving unit includes at least one opening disposed at one side of the first driving transistor in a first direction, the opening is formed in the first conductive layer, the first scan line and the second scan line extend in a second direction, and the first direction is not parallel to the second direction.

4. The display panel according to claim 3, further comprising a sealant disposed in the peripheral region, wherein the sealant at least partially covers the first gate driving unit and the second gate driving unit, and the sealant and the opening of the first gate driving unit at least partially overlap.

5. The display panel according to claim 2, wherein a width of a part of the first conductive layer forming the gate electrode of the first driving transistor in the first direction is smaller than a width of a part of the first conductive layer forming the gate electrode of the second driving transistor in the first direction.

6. The display panel of claim 1, wherein the first gate driving unit includes a first signal output waveform, the second gate driving unit includes a second signal output waveform, and a difference between a slope of a falling portion of the first signal output waveform and a slope of a falling portion of the second signal output waveform is less than or equal to 2%.

7. The display panel of claim 1, wherein the first gate driving unit includes a first signal output waveform, the second gate driving unit includes a second signal output waveform, and a difference between a falling time of the first signal output waveform and a falling time of the second signal output waveform is less than or equal to 2%.

8. A method of improving display quality of a display panel, comprising:

providing a layout design of a display panel, comprising:

the display device comprises a substrate, a first light source and a second light source, wherein the substrate is provided with a surface, the surface comprises a display area and a peripheral area arranged on at least one side of the display area, the display area comprises a first area and a second area, the first area is provided with a first scanning line, and the second area is provided with a second scanning line;

a plurality of first sub-pixels disposed in the first region, wherein at least a portion of the first sub-pixels are electrically connected to the first scan lines;

a plurality of second sub-pixels disposed in the second region, wherein at least a portion of the second sub-pixels are electrically connected to the second scan lines;

the first gate driving unit is arranged in the peripheral area and provided with a first driving transistor, and the first gate driving unit is electrically connected with the first scanning line and drives the first sub-pixel electrically connected with the first scanning line through the first scanning line; and

a second gate driving unit disposed in the peripheral region, the second gate driving unit having a second driving transistor, the second gate driving unit being electrically connected to the second scan line and driving the second sub-pixels electrically connected thereto through the second scan line, wherein the number of the first sub-pixels driven by the first gate driving unit is smaller than the number of the second sub-pixels driven by the second gate driving unit;

estimating the resistance-capacitance load of the first scanning line and the second scanning line;

performing a first driving unit adjustment step to adjust a channel width of the first driving transistor according to a resistance-capacitance load estimation result of the first scanning line and the second scanning line;

simulating the first gate driving unit and the second gate driving unit to obtain a plurality of signal output waveforms of the first gate driving unit and the second gate driving unit; and

and performing a second driving unit adjusting step, and adjusting the channel width of the first driving transistor according to the signal output waveforms of the first gate driving unit and the second gate driving unit.

9. The method of improving the display quality of a display panel according to claim 8, wherein the second driving unit adjusting step includes adjusting a channel width of the first driving transistor in the first gate driving unit according to a slope difference between a plurality of falling portions of the signal output waveform.

10. The method according to claim 9, wherein after the adjusting step of the second driving unit, a difference between a slope of a falling portion of a first signal output waveform of the first gate driving unit and a slope of a falling portion of a second signal output waveform of the second gate driving unit is less than or equal to 2%.

Technical Field

The present invention relates to a display panel and a method for improving display quality of the display panel, and more particularly, to a display panel capable of improving poor gray scales between regions of different shapes in a display region and a method for improving display quality of the display panel.

Background

The display panel is composed of two substrates, a plurality of film layers arranged between the two substrates and various electronic components, so as to achieve the function of displaying pictures. Because the display panel has the characteristics of being light and thin, low in power consumption, and free from radiation pollution, the display panel has been widely applied to various portable or wearable electronic products, such as a notebook computer (notebook), a smart phone (smart phone), a watch, a car display, and the like, to provide more convenient information transmission and display.

Display areas in display panels of today can have different shapes, so that scanning signals can face different resistive-capacitive loads when transmitted in different shaped areas. Under the condition, when the same scanning signal is input to the pixels in different areas, the phenomenon that the gray scales cannot be consistent occurs, and the problem of uneven brightness of different areas of the display panel is caused.

Disclosure of Invention

The invention aims to solve the technical problem that gray scales of areas with different shapes in a display area can not be consistent or the brightness is not uniform.

In order to solve the above technical problems, the present invention provides a display panel, which includes a substrate, a plurality of first sub-pixels, a plurality of second sub-pixels, a first gate driving unit, and a second gate driving unit. The substrate has a surface, the surface includes a display area and a peripheral area disposed on at least one side of the display area, the display area includes a first area and a second area, the first area has a first scan line, and the second area has a second scan line. The first sub-pixel is arranged in the first area, wherein at least part of the first sub-pixel is electrically connected with the first scanning line. The second sub-pixel is arranged in the second area, wherein at least part of the second sub-pixel is electrically connected with the second scanning line. The first gate driving unit is arranged in the peripheral area and provided with a first driving transistor, and the first gate driving unit is electrically connected with the first scanning line and drives the first sub-pixel electrically connected with the first scanning line through the first scanning line. The second gate driving unit is arranged in the peripheral area and provided with a second driving transistor, and the second gate driving unit is electrically connected with the second scanning line and drives the second sub-pixel electrically connected with the second scanning line through the second scanning line. The number of the first sub-pixels driven by the first gate driving unit is smaller than the number of the second sub-pixels driven by the second gate driving unit, and the channel width of the first driving transistor is smaller than that of the second driving transistor.

In order to solve the above technical problem, the present invention provides a method for improving the display quality of a display panel, which includes the following steps. First, a layout design of a display panel is provided, which includes a substrate, a plurality of first sub-pixels, a plurality of second sub-pixels, a first gate driving unit and a second gate driving unit. The substrate has a surface, the surface includes a display area and a peripheral area disposed on at least one side of the display area, the display area includes a first area and a second area, the first area has a first scan line, and the second area has a second scan line. The first sub-pixel is arranged in the first area, wherein at least part of the first sub-pixel is electrically connected with the first scanning line. The second sub-pixel is arranged in the second area, wherein at least part of the second sub-pixel is electrically connected with the second scanning line. The first gate driving unit is arranged in the peripheral area and provided with a first driving transistor, and the first gate driving unit is electrically connected with the first scanning line and drives the first sub-pixel electrically connected with the first scanning line through the first scanning line. The second gate driving unit is arranged in the peripheral area and provided with a second driving transistor, the second gate driving unit is electrically connected with the second scanning line and drives second sub-pixels electrically connected with the second scanning line through the second scanning line, and the number of the first sub-pixels driven by the first gate driving unit is smaller than that of the second sub-pixels driven by the second gate driving unit. Then, the resistance-capacitance load of the first scanning line and the second scanning line is estimated. Then, a first driving unit adjusting step is carried out, and the channel width of the first driving transistor is adjusted according to a resistance-capacitance load estimation result of the first scanning line and the second scanning line. And then, simulating the first gate driving unit and the second gate driving unit to obtain a plurality of signal output waveforms of the first gate driving unit and the second gate driving unit. And then, a second driving unit adjusting step is carried out, and the channel width of the first driving transistor is adjusted according to the signal output waveforms of the first grid driving unit and the second grid driving unit.

In the display panel and the method for improving the display quality of the display panel, the channel width of the first driving transistor is reduced according to the resistance-capacitance load of the first scanning line to reduce the thrust of the first gate driving unit, and the thrust of each first gate driving unit can be matched with the resistance-capacitance load of the corresponding first scanning line, so that the transmission quality of scanning signals in the first area and the second area is consistent, the problem of uneven brightness of different areas in the display panel is solved, and the display quality is improved.

Drawings

Fig. 1 is a schematic top view of a display panel according to a first embodiment of the invention.

Fig. 2 is a schematic diagram of a gate driving circuit according to a first embodiment of the invention.

Fig. 3 is an equivalent circuit diagram of a portion of an nth-stage gate driving unit in the gate driving circuit of fig. 2.

Fig. 4 is an equivalent circuit diagram of another portion of the nth stage gate driving unit in the gate driving circuit of fig. 2.

Fig. 5A is a circuit layout diagram of a first gate driving unit according to a first embodiment of the invention.

Fig. 5B is a schematic view of a channel width of a thin film transistor of the first gate driving unit according to the first embodiment of the invention.

Fig. 6A is a circuit layout diagram of a second gate driving unit according to the first embodiment of the invention.

Fig. 6B is a schematic view of a channel width of a thin film transistor of a second gate driving unit according to the first embodiment of the invention.

Fig. 7 is a schematic diagram of a thin film transistor in the first gate driving unit of fig. 5A.

Fig. 8 is a schematic diagram of a thin film transistor in the second gate driving unit of fig. 6A.

Fig. 9 is a waveform diagram of signal output of the gate driving unit according to the first embodiment of the present invention.

FIG. 10 is a flowchart illustrating steps of improving display quality of a display panel according to the present invention.

Fig. 11 is a circuit layout diagram of a first gate driving unit according to a second embodiment of the invention.

Wherein the reference numerals are as follows:

10 display panel

100 substrate

102. 1021, 1022 gate drive circuit

104 precharge unit

106 pull-up unit

108 first pull-down unit

110 second pull-down unit

112 first conductive layer

114 second conductive layer

116 semiconductor layer

118 frame glue

Area of A1a-A13a, A1b-A13b

BW reverse input signal

BWL inverted input signal line

C1a-C13a, C1b-C13b patterned semiconductor layer

CL1-CL4 clock signal line

CS1-CS4, CSN clock signals

Cx capacitance

Cwa, Cwb channel width

D1 first direction

D2 second direction

D1a-D13a and D1b-D13b drain

DR display area

DTa first drive transistor

DTb second drive transistor

EL termination signal line

ES end signal

FT fall time

FW forward input signal

FWL forward input signal line

G1a-G13a, G1b-G13b grid

IL initial signal line

IN1, IN2 input signals

IS Start signal

MP convex part

M1-M13, M1a-M13a, M1b-M13b thin film transistors

NT notch

O1 and O2 openings

OUT (1) -OUT (N), OUT (n) scanning signal

P, Q, X node

PC (n) precharge signal

PR peripheral zone

S1a-S13a, S1b-S13b Source

SL scanning line

SL1 first scanning line

SL2 second scanning line

SP sub-pixel

SP1 first sub-pixel

SP2 second sub-pixel

SR, SR (n) grid driving unit

SRa first gate driving unit

SRb second gate driving unit

time t

V, V1, V2 Voltage

Maximum voltage of V3

High potential of VGH gate

VGL Gate Low potential

VPWL1, VPWL2 pull-down control signals

Wa, Wb, W1a-W13a, W1b-W13b width

Detailed Description

In order to make the present invention more comprehensible to those skilled in the art, preferred embodiments of the present invention are specifically described below, and the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the drawings are simplified schematic diagrams, and therefore, only the components and combinations related to the present invention are shown to provide a clearer description of the basic architecture or implementation method of the present invention, and the actual components and layout may be more complicated. In addition, for convenience of description, the components shown in the drawings are not necessarily drawn to scale, and the actual implementation numbers, shapes and sizes may be adjusted according to design requirements.

Referring to fig. 1 to 9, fig. 1 is a schematic top view of a display panel according to a first embodiment of the present invention, fig. 2 is a schematic diagram of a gate driving circuit according to the first embodiment of the present invention, fig. 3 is an equivalent circuit diagram of a portion of an nth stage gate driving unit in the gate driving circuit of fig. 2, fig. 4 is an equivalent circuit diagram of another portion of an nth stage gate driving unit in the gate driving circuit of fig. 2, fig. 5A is a circuit layout diagram of a first gate driving unit according to the first embodiment of the present invention, fig. 5B is a schematic diagram of a channel width of a thin film transistor of the first gate driving unit according to the first embodiment of the present invention, fig. 6A is a circuit layout diagram of a second gate driving unit according to the first embodiment of the present invention, fig. 6B is a schematic diagram of a channel width of a thin film transistor of the second gate driving unit according to the first embodiment of the present invention, fig. 7 is a schematic diagram of a thin film transistor in the first gate driving unit of fig. 5A, fig. 8 is a schematic diagram of a thin film transistor in the second gate driving unit of fig. 6A, and fig. 9 is a waveform diagram of a signal output from the gate driving unit according to the first embodiment of the present invention. The display panel of the present invention can be various types of flat display panels, such as a liquid crystal display panel, an electrophoretic display panel, an organic light emitting display panel, or a micro light emitting diode display panel, but not limited thereto. The display area of the display panel of the present invention can have different shapes, for example, but not limited to, a wearable display. As shown in fig. 1, the substrate 100 of the display panel 10 has a surface including a display region DR and a peripheral region PR disposed at least one side outside the display region DR. In the present embodiment, the peripheral region PR surrounds the display region DR, but is not limited thereto. The substrate 100 may be a hard substrate such as a glass substrate, a plastic substrate, a quartz substrate, or a sapphire substrate, or may be a flexible substrate including a Polyimide (PI) material or a polyethylene terephthalate (PET) material, but is not limited thereto. The display panel 10 includes a plurality of sub-pixels SP, a plurality of scan lines SL and a plurality of data lines disposed in the display region DR, and in order to simplify the drawing and simplify the drawing, only a portion of the sub-pixels SP and a portion of the scan lines SL are shown in the display region DR and the data lines are omitted in fig. 1. The data lines may extend substantially along a first direction D1, the scan lines SL may extend substantially along a second direction D2, and the first direction D1 and the second direction D2 are not parallel. The first direction D1 and the second direction D2 of the present embodiment are perpendicular, but not limited thereto. The sub-pixels SP may be arranged in an array, and each sub-pixel SP is electrically connected to one scan line SL and one data line. For example, three sub-pixels SP adjacent to each other in the second direction D2 may form a pixel, and the sub-pixels SP may be electrically connected to the same scan line SL and may be respectively configured to display different colors, such as red, blue, and green, but not limited thereto. In the present embodiment, the display region DR is substantially rectangular (but not limited thereto), and has two sides substantially parallel to the first direction D1 and two sides substantially parallel to the second direction D2, and the display region DR has a notch (notch) NT, wherein the notch NT is disposed on one side of the display region DR parallel to the second direction D2, and the display region DR has two protrusions MP disposed on two sides of the notch NT in the second direction D2, but the shape of the display region is not limited thereto. As shown in fig. 1, the display region DR includes a first region R1 and a second region R2, wherein the first region R1 includes the notch NT and the protruding portion MP, and the second region R2 is a portion of the display region DR without the notch NT. Further, the sub-pixel SP includes a plurality of first sub-pixels SP1 and a plurality of second sub-pixels SP2, the first sub-pixel SP1 is disposed in the first region R1, and the second sub-pixel SP2 is disposed in the second region R2, wherein the first sub-pixel SP1 is disposed in the convex portion MP. The first region R1 has a plurality of first scan lines SL1, each of the first scan lines SL1 is electrically connected to a part of the first sub-pixels SP1, and for example, each of the first scan lines SL1 is electrically connected to the first sub-pixels SP1 in a corresponding one of the sub-pixel rows. The second region R2 has a plurality of second scan lines SL2, each of the second scan lines SL2 is electrically connected to a portion of the second sub-pixels SP2, and for example, each of the second scan lines SL2 is electrically connected to the second sub-pixels SP2 in a corresponding one of the sub-pixel rows. In the first region R1, since the first subpixels SP1 are disposed in the convex portion MP and not in the notch NT, the number of the first subpixels SP1 in the first region R1 is smaller than the number of the second subpixels SP2 in the second region R2, and the number of the first subpixels SP1 to which the respective first scan lines SL1 are electrically connected is smaller than the number of the second subpixels SP2 to which the respective second scan lines SL2 are electrically connected. In other words, the number of first sub-pixels SP1 driven by the respective first scan lines SL1 is smaller than the number of second sub-pixels SP2 driven by the respective second scan lines SL 2.

The display panel 10 may include at least one gate driver circuit (gate driver circuit)102 disposed in the peripheral region PR and disposed at one side of the display region DR in the second direction D2. The gate driving circuit 102 may be electrically connected to the scan lines SL, and may transmit scan signals to the scan lines SL to drive the sub-pixels SP in the display region DR. In addition, the gate driving circuit 102 may be electrically connected to at least one control Integrated Circuit (IC), and the control IC may transmit control signals (e.g., clock signals, start signals, and end signals) to the gate driving circuit 102. The control integrated circuit may also be disposed in the peripheral region PR, but not limited thereto. In the present embodiment, the display panel 10 includes two gate driving circuits 1021, 1022 respectively disposed on two sides of the display region DR in the second direction D2, but not limited thereto. As shown in fig. 1, one of the two adjacent first scan lines SL1 may be electrically connected to the gate driving circuit 1021, and the other may be electrically connected to the gate driving circuit 1022. Similarly, in two adjacent second scan lines SL2, one may be electrically connected to the gate driving circuit 1021, and the other may be electrically connected to the gate driving circuit 1022. The resolution of the display panel 10 of the present embodiment is, for example, 720 × 1512, and the display panel 10 includes 1512 scan lines SL, wherein the scan lines SL include 72 first scan lines SL1 and 1440 second scan lines SL 2. For example, the gate driving circuit 1021 may be electrically connected with 36 first scan lines SL1 and 720 second scan lines SL2, and the gate driving circuit 1022 may be electrically connected with another 36 first scan lines SL1 and 720 second scan lines SL2, but not limited thereto. The Gate driving circuits 1021, 1022 in this embodiment are in a Gate driver on array (GOA) circuit structure, but not limited thereto. The components and their structure in the gate driving circuit 102 will be described in detail below.

As shown in fig. 2, the gate driving circuit 102 of the present embodiment includes clock signal lines CL1-CL4, a start signal line IL, an end signal line EL, a forward input signal line FWL, a reverse input signal line BWL, and 1 st to nth gate driving units SR (1) -SR (N), where N is a positive integer greater than or equal to 5, but not limited thereto. The gate driving unit SR of the present embodiment can be, for example, a shift register, but is not limited thereto. The clock signal lines CL1-CL4 provide the clock signals CS1-CS4 to the corresponding gate driving units SR (1) -SR (N). The 1 st to nth Gate driving units SR (1) -SR (N) may be Gate driver on Array (GOA) circuit structures. In addition, N may be a multiple of 4, and the clock signal line CL1 provides the clock signal CS1 to the 1 st, 5 th, …, and (N-3) th stage gate driving units SR (1), SR (5), and SR (3), the clock signal line CL2 provides the clock signal CS2 to the 2 nd, 6 th, …, and (N-2) th stage gate driving units SR (N-2), the clock signal line CL3 provides the clock signal CS3 to the 3 rd, 7 th, …, and (N-1) th stage gate driving units SR (N-1), and the clock signal line CL4 provides the clock signal CS4 to the 4 th, 8 th, SR (8), and SR (4), … and an Nth stage gate driving unit SR (N). In addition, the forward input signal line FWL respectively provides the forward input signal FW with respective reverse input signals BW to the 1 st-N gate driving units SR (1) -SR (N), the start signal line IL provides the start signal IS to the 1 st-2 nd gate driving units SR (1), SR (2), and the end signal line EL provides the end signal ES to the (N-1) th-N gate driving units SR (N-1), SR (N). The clock signal lines CL1-CL4, the start signal line IL, the end signal line EL, the forward input signal line FWL, and the backward input signal line BWL may be coupled to one or more chips, i.e., the clock signals CS1-CS4, the start signal IS, the end signal ES, the forward input signal line FWL, and the backward input signal line BWL may be provided by one or more chips, such as a driving chip and/or a timing control chip, but not limited thereto.

In addition, the 1 st to nth gate driving units SR (1) -SR (N) respectively generate the 1 st to nth scan signals OUT (1) -OUT (N), and the scan signals OUT (1) -OUT (N) can be respectively output to the corresponding scan lines SL in fig. 1, and the sub-pixels SP electrically connected thereto are driven by the scan lines SL. Wherein, the 1 st and 2 nd scan signals OUT (1), OUT (2) are respectively input to the 3 rd and 4 th gate driving units SR (3), SR (4), the (N-1) th and N-th scan signals OUT (N-1), OUT (N) are respectively input to the (N-3) th and (N-2) th gate driving units SR (N-3), SR (N-2), and each of the 3 rd to (N-2) th scan signals OUT (3) -OUT (N-2) is input to the gate driving unit of the upper and lower stages thereof. For example, the 3 rd stage scan signal OUT (3) is input to the 1 st and 5 th stage gate driving units SR (1), SR (5).

As shown in fig. 3, the nth stage (where N is a positive integer from 1 to N) gate driving unit sr (N) includes a pre-charge unit 104 and a pull-up unit 106, wherein one end of the pre-charge unit 104 and one end of the pull-up unit 106 are coupled to a node X (which corresponds to the pre-charge signal pc (N)), and the other end of the pull-up unit 106 can output the nth stage scan signal out (N) to a corresponding scan line SL. The precharge unit 104 receives the input signals IN1, IN2, and outputs a precharge signal pc (n) to the node X according to the input signals IN1, IN 2. The precharge unit 104 includes thin film transistors M2, M3. IN the present embodiment, the gate driving circuit 102 is a bidirectional scanning driving circuit, and IN the gate driving units SR (1) -SR (n), the control terminal of the thin film transistor M2 receives the input signal IN1, the first terminal of the thin film transistor M2 receives the forward input signal FW, and the second terminal of the thin film transistor M2 is coupled to the node X. The control terminal of the tft M3 receives the input signal IN2, the first terminal of the tft M3 receives the inverted input signal BW, and the second terminal of the tft M3 is coupled to the second terminal of the tft M2, wherein the forward input signal FW and the inverted input signal BW are opposite IN phase during the display period of the display panel, i.e. when one of the forward input signal FW and the inverted input signal BW is at a high potential (electric potential), the other one is at a low potential. In addition, in the embodiment of the driving circuit in which the gate driving circuit 102 is a unidirectional scan, the first terminal of the thin film transistor M2 receives a high potential and the first terminal of the thin film transistor M3 receives a low potential, and in the schematic diagram of the gate driving circuit of fig. 2, the forward input signal line FWL and the backward input signal line BWL can be replaced with a high potential line and a low potential line, respectively. The remainder is similar to the description above. For example, the High potential may be a Gate High Voltage (VGH) and the low potential may be a Gate low Voltage (VGL). Herein, the "control terminal", "first terminal", and "second terminal" of the thin film transistor refer to a gate electrode, a source electrode, and a drain electrode of the thin film transistor, respectively, or refer to a gate electrode, a drain electrode, and a source electrode of the thin film transistor, respectively.

If the gate driving unit SR (n) IS the 1 st or 2 nd stage gate driving unit (i.e., n IS 1 or 2), the input signal IN1 IS the start signal IS, and the input signal IN2 IS the scan signal OUT (n +2) outputted by the (n +2) th stage gate driving unit SR (n +2) (i.e., the 3 rd stage scan signal OUT (3) or the 4 th stage scan signal OUT (4)). If the gate driving unit SR (N) is any one of the 3 rd to (N-2) th gate driving units (i.e., N is any positive integer from 3 to (N-2)), the input signals IN1 and IN2 are the (N-2) th scanning signal OUT (N-2) output by the (N-2) th gate driving unit SR (N-2) and the (N +2) th scanning signal OUT (N +2) output by the (N +2) th gate driving unit SR (N +2), respectively. If the gate driving unit SR (N) is the (N-1) th stage or the nth stage (i.e., N is (N-1) or N), the input signal IN1 is the scan signal OUT (N-2) outputted by the (N-2) th stage gate driving unit SR (N-2) (i.e., the (N-3) th stage scan signal OUT (N-3) or the (N-2) th stage scan signal OUT (N-2)), and the input signal IN2 is the end signal ES. It should be noted that when the gate driving circuit 102 IS in forward scanning, that IS, the forward input signal FW IS at a high potential and the backward input signal BW IS at a low potential, IS a start signal and ES IS an end signal; when the gate driving circuit 102 IS in the reverse scan mode, i.e. the forward input signal FW IS at a low potential and the reverse input signal BW IS at a high potential, ES IS the start signal and IS the end signal.

The pull-up unit 106 is coupled to the precharge unit 104, receives the precharge signal pc (n) and the clock signal CSN, and outputs the scan signal out (n) according to the precharge signal pc (n) and the clock signal CSN, wherein the clock signal CSN is any one of the clock signals CS1-CS 4. In the embodiment where N is a multiple of 4, if N is 1, 5, …, (N-3), the clock signal CSN is the clock signal CS 1; if N is 2, 6, … or (N-2), the clock signal CSN is the clock signal CS 2; if N is 3, 7, …, or (N-1), the clock signal CSN is the clock signal CS 3; if N is 4, 8, …, N, the clock signal CSN is the clock signal CS 4. The pull-up unit 106 includes a thin film transistor M1 and a capacitance Cx. The control terminal of the thin film transistor M1 receives the precharge signal pc (n), the first terminal of the thin film transistor M1 receives the clock signal CSN, and the second terminal of the thin film transistor M1 outputs the scan signal out (n). The first terminal of the capacitor Cx is coupled to the control terminal of the TFT M1, and the second terminal of the capacitor Cx is coupled to the second terminal of the TFT M1.

As shown in fig. 4, the nth shift register stage sr (n) of the present embodiment further includes a first pull-down unit 108 and a second pull-down unit 110, wherein one end of the precharge unit 104, the pull-up unit 106, the first pull-down unit 108 and the second pull-down unit 110 is coupled to the node X (which corresponds to the precharge signal pc (n)), and the other end of the pull-up unit 106, the first pull-down unit 108 and the second pull-down unit 110 outputs the nth scan signal out (n) to the corresponding scan line SL. The first pull-down unit 108 is coupled to the precharge unit 104 and the pull-up unit 106, receives the precharge signal pc (n) and the pull-down control signals VPWL1, VPWL2, and controls whether to pull down and maintain the scan signal out (n) to the reference potential according to the precharge signal pc (n) and the pull-down control signals VPWL1, VPWL 2. As shown in fig. 4, the reference potential in the present embodiment is a gate low Voltage (VGL), but not limited thereto. In the frame time, the pull-down control signals VPWL1, VPWL2 are inverted, i.e., one of the pull-down control signals VPWL1, VPWL2 is at a high potential and the other is at a low potential. The first pull-down unit 108 includes thin film transistors M4, M6, M8, M10, and M12. A control terminal and a first terminal of the thin film transistor M10 input the pull-down control signal VPWL 1. The control terminal of the thin film transistor M12 inputs the pull-down control signal VPWL2, the first terminal of the thin film transistor M12 is coupled to the reference potential VGL, the second terminal of the thin film transistor M12 is coupled to the second terminal of the thin film transistor M10, and the second terminals of the thin film transistor M12 and the thin film transistor M10 are coupled to the node P. The control terminal of the TFT M8 is coupled to the node X, the first terminal of the TFT M8 is coupled to the reference potential VGL, and the second terminal of the TFT M8 is coupled to the second terminal of the TFT M10. The control terminal of the thin film transistor M8 is coupled to the second terminal of the thin film transistor M8, the first terminal of the thin film transistor M8 is coupled to the reference potential VGL, and the second terminal of the thin film transistor M8 is coupled to the node X. The control terminal of the thin film transistor M4 is coupled to the second terminal of the thin film transistor M8, the first terminal of the thin film transistor M4 is coupled to the reference potential VGL, and the second terminal of the thin film transistor M4 is coupled to the scan signal out (n).

When the shift register sr (n) outputs the scan signal out (n) to activate the corresponding pixel column, that is, the scan signal out (n) rises to the high potential and maintains the high potential for a period of time and then falls to the low potential, the node X falls from the high potential to the low potential, and the first pull-down unit 108 starts to operate. When the pull-down control signal VPWL1 is at a low potential and the pull-down control signal VPWL2 is at a high potential, the node P is at a low potential state, so that the thin film transistors M4 and M8 are turned off; while the pull-down control signal VPWL1 is at a high potential and the pull-down control signal VPWL2 is at a low potential, the node P is at a high potential state, so that the thin film transistors M4 and M8 are turned on to set the potential of the node X to the reference potential VGL. In a frame time, when the shift register sr (n) outputs the scan signal out (n) to activate the corresponding pixel row, that is, the scan signal out (n) rises to the high potential and maintains the high potential for a period of time and then falls to the low potential, if the noise signal is coupled to the node X to cause ripple (ripple) of the potential of the node X, the turned-on thin film transistors M4 and M8 pull the node X down to the low potential (e.g., the reference potential VGL) or pull the scan signal out (n) down to and maintain the low potential without the scan signal out (n) being interfered by the noise.

The second pull-down unit 110 is coupled to the precharge unit 104 and the pull-up unit 106, receives the precharge signal pc (n) and the pull-down control signals VPWL1, VPWL2, and controls whether to pull down and maintain the scan signal out (n) at the reference potential VGL according to the precharge signal pc (n) and the pull-down control signals VPWL1, VPWL 2. The second pull-down unit 110 includes thin film transistors M5, M7, M9, M11, and M13. A control terminal and a first terminal of the thin film transistor M11 input the pull-down control signal VPWL 2. The control terminal of the thin film transistor M13 inputs the pull-down control signal VPWL1, the first terminal of the thin film transistor M13 is coupled to the reference potential VGL, the second terminal of the thin film transistor M13 is coupled to the second terminal of the thin film transistor M11, and the second terminals of the thin film transistor M11 and the thin film transistor M13 are coupled to the node Q. The control terminal of the TFT M7 is coupled to the node X, the first terminal of the TFT M7 is coupled to the reference potential VGL, and the second terminal of the TFT M7 is coupled to the second terminal of the TFT M11. The control terminal of the thin film transistor M9 is coupled to the second terminal of the thin film transistor M7, the first terminal of the thin film transistor M9 is coupled to the reference potential VGL, and the second terminal of the thin film transistor M9 is coupled to the node X. The control terminal of the thin film transistor M5 is coupled to the second terminal of the thin film transistor M7, the first terminal of the thin film transistor M5 is coupled to the reference potential VGL, and the second terminal of the thin film transistor M5 is coupled to the scan signal out (n).

When the shift register sr (n) outputs the scan signal out (n) to activate the corresponding pixel row, that is, the scan signal out (n) rises to the high potential and maintains the high potential for a period of time and then falls to the low potential, the node X falls from the high potential to the low potential, and the second pull-down unit 110 starts to operate. When the pull-down control signal VPWL1 is at a low potential and the pull-down control signal VPWL2 is at a high potential, the node Q is in a high potential state, so that the thin film transistors M9 and M5 are turned on to set the potential of the node X to the reference potential VGL; when the pull-down control signal VPWL1 is at a high potential and the pull-down control signal VPWL2 is at a low potential, the node Q is at a low potential, such that the tfts M9 and M5 are turned off. In a frame time, after the shift register sr (n) outputs the scan signal out (n) to activate the corresponding pixel row, i.e., the scan signal out (n) rises to the high potential and stays at the low potential for a period of time, if the noise signal is coupled to the node X, the turned-on tfts T7 and T8 pull the node X down to the low potential, or pull the scan signal out (n) down to and stays at the low potential, so that the scan signal out (n) is not interfered by the noise.

The circuit layout diagrams of the gate driving unit shown in fig. 5A and fig. 6A can both correspond to the equivalent circuit diagrams of fig. 3 and fig. 4 and the above description. To simplify the drawings, fig. 5A and 6A only show the first conductive layer 112, the second conductive layer 114, the semiconductor layer 116 and the sealant 118. In fig. 5A and 6A, the range of the sealant 118 in the local region is shown by a thick solid line, but the range of the sealant 118 in the peripheral region PR is not limited thereto, and may extend along the edge of the display panel 10. In the embodiment, the first conductive layer 112 is disposed between the second conductive layer 114 and the substrate 100, the semiconductor layer 116 is disposed between the first conductive layer 112 and the second conductive layer 114, and the sealant 118 is disposed on the second conductive layer 114, but not limited thereto. The gate driving unit SR includes a plurality of first gate driving units SRa (shown in fig. 5A) and a plurality of second gate driving units SRb (shown in fig. 6), wherein each of the first gate driving units SRa is electrically connected to one of the first scan lines SL1 in the first region R1, and each of the second gate driving units SRb is electrically connected to one of the second scan lines SL2 in the second region R2. In other words, each of the first gate driving units SRa may drive the first sub-pixel SP1 electrically connected to the first scan line SL1 through the corresponding first scan line SL1, and each of the second gate driving units SRb may drive the second sub-pixel SP2 electrically connected to the second scan line SL2 through the corresponding second scan line SL 2. Each gate driving unit SR includes 13 thin film transistors, but the number of the thin film transistors is not limited thereto. For example, each of the first gate driving units SRa includes tfts M1a-M13a, and each of the second gate driving units SRb includes tfts M1b-M13 b. As shown in fig. 5A and 6A, the arrangement of the tfts M1a-M13a in each first gate driving unit SRa may be the same as the arrangement of the tfts M1b-M13b in each second gate driving unit SRb, but not limited thereto. Each thin film transistor comprises a grid electrode, a source electrode, a drain electrode and a patterned semiconductor layer. As shown in fig. 5A, in the thin film transistors M1a-M13a, the gates G1a-G13a are formed of the first conductive layer 112, the sources S1a-S13a and the drains D1a-D13a are formed of the second conductive layer 114, and the patterned semiconductor layers C1a-C13a are formed of the semiconductor layer 116. Similarly, in the thin film transistors M1b-M13b of fig. 6, the gate electrodes G1b-G13b are formed of the first conductive layer 112, the source electrodes S1b-S13b and the drain electrodes D1b-D13b are formed of the second conductive layer 114, and the patterned semiconductor layers C1b-C13b are formed of the semiconductor layer 116. The first conductive layer 112 and the second conductive layer 114 may be a metal material, but not limited thereto. The semiconductor layer 116 may be amorphous silicon, but is not limited thereto.

Fig. 7 illustrates areas A1a-a13a of the tfts M1a-M13a in the first gate driving unit SRa of fig. 5A, and fig. 8 illustrates areas A1b-a13b of the tfts M1b-M13b in the second gate driving unit SRb of fig. 6A. Fig. 5B and 6B illustrate the channel widths CWa, CWb of the tfts M1a, M1B in fig. 5A and 6A, which can be the length of the serpentine path between the sources S1a, S1B and the drains D1a, D1B. It should be noted that the area of each tft may also be used to indicate the channel width (channel width) of each tft, and the larger the area of each tft is, the longer the channel width of each tft is. As shown in fig. 5A, 6A, 7 and 8, in this embodiment, the area of each thin film transistor in the first gate driving unit SRa is smaller than the area of each corresponding thin film transistor in the second gate driving unit SRb. In other words, the channel width of each thin film transistor in the first gate driving unit SRa is smaller than the channel width of each thin film transistor corresponding thereto in the second gate driving unit SRb. For example, the channel width CWa of the tft M1a is smaller than the channel width CWb of the tft M1B (as shown in fig. 5B and 6B), and the channel widths of the other tfts M2a-M13a are also smaller than the channel widths of the corresponding tfts M2B-M13B. In addition, the area A1a of the tft M1a is smaller than the area A1b of the tft M1b, and the areas A2a-a13a of the remaining tfts M2a-M13a may also be smaller than or equal to the areas A2b-a13b of the corresponding tfts M2b-M13 b. As shown in fig. 5 and fig. 7, taking the thin film transistor M1a of the present embodiment as an example, the area A1a can be defined as the area of the gate electrode G1a or the area of the patterned semiconductor layer C1a, but not limited thereto. The source S1a and the drain D1a of the present embodiment have a grid structure, wherein the grid structure has a main electrode and a plurality of branch electrodes connected to the main electrode, the branch electrodes of the two grid structures are alternately arranged, so that the source S1a and the drain D1a form an integrated structure, and the area A1a of the thin film transistor M1a can also be defined as the area of the integrated structure of the source S1a and the drain D1 a. The reduction in the area of the source S1a and the drain D1a can be regarded as the reduction in the channel width CWa of the thin film transistor M1 a. According to the present invention, regardless of which of the above-mentioned manners is used to define the area or channel width of the thin film transistor, the same definition shall be used to represent the area or channel width of the thin film transistor in the first gate driving unit SRa and the second gate driving unit SRb, that is, when comparing the area or channel width of the thin film transistor in the first gate driving unit SRa and the second gate driving unit SRb, the same definition shall be used for both. The area A1a or the channel width CWa of the thin film transistor M1a being smaller than the area A1b or the channel width CWb of the thin film transistor M1b can make the operation current of the thin film transistor M1a smaller than the operation current of the thin film transistor M1b, but is not limited thereto. In addition, in the present embodiment, a width W1a of the tft M1a in the first direction D1 is smaller than a width W1b of the tft M1b in the first direction D1, so that the area A1a is smaller than the area A1b, and the channel width CWa of the tft M1a is smaller than the channel width CWb of the tft M1 b. In other embodiments, the width of the thin film transistor M1a in the second direction D2 may be smaller than the width of the thin film transistor M1b in the second direction D2. Taking the thin film transistor M1a of the present embodiment as an example, the width W1a may be, for example, the width of the gate G1a in the first direction D1 or the width of the patterned semiconductor layer C1a in the first direction D1, but not limited thereto. The width W1a may also be the distance from the main electrode of the source S1a to the main electrode of the drain D1a in the first direction D1. In addition, the above descriptions for the tfts M1a and M1b can also be applied to the remaining tfts M2a-M13a in the first gate driving unit SRa and the remaining tfts M2b-M13b in the second gate driving unit SRb.

The magnitude of the pushing force (pushing power) of the gate driving unit SR is mainly influenced by the channel width or area of the thin film transistor M1, wherein the pushing force may indicate the strength of the output signal of the gate driving unit SR, such as the magnitude of the signal current, the magnitude of the signal voltage, and the like. Therefore, in the present embodiment, the tft M1a in each first gate driving unit SRa is defined as a first driving transistor DTa, and the tft M1b in each second gate driving unit SRb is defined as a second driving transistor DTb, wherein the area A1a or the channel width CWa of the first driving transistor DTa is smaller than the area A1b or the channel width CWb of the second driving transistor DTb. Since the shape of the first region R1 in the display region DR of the present embodiment includes a notch NT, the number of the first sub-pixels SP1 electrically connected to each of the first scan lines SL1 is smaller than the number of the second sub-pixels SP2 electrically connected to each of the second scan lines SL2, so that the resistance capacitance loading (RC loading) of the signal transmitted in the first scan line SL1 is different from the RC loading of the signal transmitted in the second scan line SL 2. For example, the RC load of the first scan line SL1 is smaller than that of the second scan line SL 2. Therefore, when the first gate driving unit SRa and the second gate driving unit SRb have the same driving force (for example, the first driving transistor DTa and the second driving transistor DTb have the same area or channel width), the gray scales of the sub-pixels SP in the first region R1 and the second region R2 are not consistent, and the luminance of the display panel 10 is not uniform in the first region R1 and the second region R2. However, in the embodiment, the area A1a or the channel width CWa of the first driving transistor DTa is reduced according to the lower RC load of the first scan line SL1, so that the pushing force of the first gate driving units SRa can be reduced, and the pushing force of each first gate driving unit SRa can be matched with the RC load of the corresponding first scan line SL1, so that the transmission quality of the scan signal in the first region R1 and the second region R2 can be consistent, thereby improving the above problem.

In addition, the signal output waveforms corresponding to the gate driving units SR can be obtained through simulation or measurement, and the signal output waveforms can be as shown in fig. 9. FIG. 9 is a waveform of voltage V versus time t, where voltage V1 has a value of 20% of the maximum voltage V3 of the signal, time t1 is the time the signal has voltage V1, voltage V2 has a value of 80% of the maximum voltage V3 of the signal, and time t2 is the time the signal has voltage V2. A section where the waveform falls from the voltage V2 to the voltage V1 is defined as a falling section, a time taken for the waveform to fall from the voltage V2 to the voltage V1 is defined as a falling time FT, and the falling time FT is equivalent to a difference between the time t1 and the time t 2. The fall time FT may also be used to represent the slope of the falling portion of the waveform. Furthermore, the first gate driving unit SRa has a corresponding first signal output waveform, and the second gate driving unit SRb has a corresponding second signal output waveform. For example, in the present embodiment, the channel width CWa of the first driving transistor DTa of one of the first gate driving units SRa is 1350 micrometers (um), and the channel width CWb of the second driving transistor DTb of one of the second gate driving units SRb is 2436 micrometers. In the first signal output waveform of the first gate driving unit SRa and the second signal output waveform of the second gate driving unit SRb, the falling time of the first signal output waveform is 0.955 microseconds (mistecond) and the falling time of the second signal output waveform is 0.956 microseconds, the difference ((0.956-0.955)/0.956) of the two is about 0.1%. Since the falling time FT can also be used to represent the slope of the falling portion of the waveform, the difference between the slope of the falling portion of the first signal output waveform and the slope of the falling portion of the second signal output waveform is also about 0.1%. Therefore, in the present embodiment, the difference between the falling time of the first signal output waveform and the falling time of the second signal output waveform may be less than or equal to 2%, and the difference between the slope of the falling portion of the first signal output waveform and the slope of the falling portion of the second signal output waveform may also be less than or equal to 2%. Therefore, the problem of inconsistent gray levels of the sub-pixels SP in the first region R1 and the second region R2 of the display panel 10 can be solved, and the problem of uneven brightness of the first region R1 and the second region R2 can be solved. In addition, in the present embodiment, each of the first gate driving units SRa may adjust the area A1a or the channel width CWa of the first driving transistor DTa according to the corresponding RC load, so that the first gate driving units SRa have different areas A1a or channel widths CWa. For example, the channel width CWa of the first driving transistor DTa may decrease from 2260 micrometers to 1350 micrometers in a direction from the boundary of the first region R1 and the second region R2 to the notch NT, and the falling time (or the slope of the falling portion) of the first signal output waveform of each first gate driving unit SRa may be maintained at 0.954 microseconds to 0.956 microseconds, but not limited thereto.

As shown in fig. 5 and 6, the display panel 10 further includes a sealant 118 disposed in the peripheral region PR, wherein the sealant 118 at least partially covers the first gate driving unit SRa and the second gate driving unit SRb. Since the sealant 118 of the present embodiment can be, for example, a photo-curing adhesive, a plurality of light-transmissive openings (for example, the opening O1) can be formed in the first gate driving unit SRa and the second gate driving unit SRb, and the openings can overlap with the sealant 118 to help the photo-curing adhesive to be cured. Since the notch NT of the present embodiment is disposed in the first region R1, the shape of the first region R1 has more corners, so that the photo-curable adhesive near the first region R1 is relatively difficult to cure compared with the photo-curable adhesive at other portions of the peripheral region PR. In order to improve the above problem, in the present embodiment, by reducing the width of the source S1a and the drain D1a (the second conductive layer 114) in the first direction D1 and the width of the patterned semiconductor layer C1a (the semiconductor layer 116) in each of the at least one first gate driving unit SRa, a portion of the first conductive layer 112 above and below the first driving transistor DTa in the first direction D1 can be exposed. Furthermore, the first gate driving unit SRa of the embodiment further includes two openings O2 formed on the exposed portion of the first conductive layer 112, the opening O2 may overlap with the sealant 118, wherein one opening O2 is disposed on one side of the first driving transistor DTa in the first direction D1, and the other opening O2 is disposed on the other side of the first driving transistor DTa in the first direction D1, so that the first driving transistor DTa is disposed between the two openings O2. The opening O2 may be rectangular and have a long side parallel to the second direction D2, but is not limited thereto. The number of the openings O2 is not limited to the present embodiment. Therefore, the light-transmitting area in the first gate driving unit SRa can be increased by providing the opening O2, so as to improve the problem of poor curing of the photo-curable adhesive at the corner position.

The method of the present embodiment for improving the display quality of the display panel will be described in detail below. Referring to fig. 10, fig. 10 is a flowchart illustrating a process for improving the display quality of the display panel according to the present invention. First, step S10 is performed to provide a layout design of the display panel 10, which includes the substrate 100, the plurality of first sub-pixels SP1, the plurality of second sub-pixels SP2, the plurality of first gate driving units SRa and the plurality of second gate driving units SRb. The substrate 100 has a surface including a display region DR and a peripheral region PR disposed at least one side of the display region DR. The display region DR includes a first region R1 and a second region R2, the first region R1 has one or more first scan lines SL1, and the second region R2 has one or more second scan lines SL 2. In addition, the shape of the first region R1 includes a notch NT. The first sub-pixels SP1 are disposed in the first region R1, wherein each of the first scan lines SL1 electrically connects at least a part of the first sub-pixels SP 1. The second sub-pixels SP2 are disposed in the second region R2, wherein each of the second scan lines SL2 electrically connects at least a portion of the second sub-pixels SP 2. The first gate driving units SRa are disposed in the peripheral region PR, each of the first gate driving units SRa has a first driving transistor DTa, and each of the first gate driving units SRa is electrically connected to one of the first scan lines SL1 and drives the first subpixel SP1 electrically connected thereto through the first scan line SL 1. The second gate driving units SRb are disposed in the peripheral region PR, each of the second gate driving units SRb has a second driving transistor DTb, and each of the second gate driving units SRb is electrically connected to one of the second scan lines SL2 and drives the second subpixel SP2 electrically connected thereto through the second scan line SL 2. In addition, since the shape of the first region R1 includes the notch NT, the number of the first sub-pixels SP1 driven by each of the first gate driving units SRa is smaller than the number of the second sub-pixels SP2 driven by each of the second gate driving units SRb.

Next, in step S12, RC loads of the first scan line SL1 and the second scan line SL2 are estimated. Since the number of the first sub-pixels SP1 electrically connected to the first scan line SL1 is different from the number of the second sub-pixels SP2 electrically connected to the second scan line SL2, the RC load of the signal transmitted at the first scan line SL1 is different from the RC load of the signal transmitted at the second scan line SL 2. For example, since the number of the first sub-pixels SP1 electrically connected to the first scan line SL1 is smaller than the number of the second sub-pixels SP2 electrically connected to the second scan line SL2, the RC load of the first scan line SL1 is smaller than that of the second scan line SL2 in the present embodiment.

Then, step S14 is performed to perform a first driving unit adjusting step. In this step, the channel width of the first driving transistor DTa in the first gate driving unit SRa is adjusted based on the channel width of the second driving transistor DTb in the second gate driving unit SRb (as shown in fig. 6) and according to the rc load estimation results of the first scan line SL1 and the second scan line SL 2.

Next, in step S16, the first gate driving unit SRa and the second gate driving unit SRb are simulated to obtain a plurality of signal output waveforms of the first gate driving unit SRa and the second gate driving unit SRb, wherein the signal output waveforms can refer to fig. 9 and the related description above. At this time, the signal output waveforms of the first and second gate driving units SRa and SRb may be compared to know a difference in a falling time or a difference in a slope of a falling portion between the signal output waveforms.

Then, step S18 is performed to perform a second driving unit adjusting step. In this step, the channel width (or area) of the first driving transistor DTa is adjusted according to the signal output waveforms of the first gate driving unit SRa and the second gate driving unit SRb. For example, in the second driving unit adjusting step, the channel width (or area) of the first driving transistor DTa in the first gate driving unit SRa may be adjusted according to a slope difference between falling portions of the signal output waveforms, or the channel width (or area) of the first driving transistor DTa in the first gate driving unit SRa may be adjusted according to a falling time difference between the signal output waveforms. In the present embodiment, since the RC load of the first scan line SL1 is smaller than that of the second scan line SL2, the adjustment of the channel width (or area) of the first driving transistor DTa in the first driving unit adjustment step (S14) or the second driving unit adjustment step (S18) may be performed by, for example, reducing the areas of the source S1a and the drain D1a of the first driving transistor DTa (thin film transistor M1a) to be smaller than the areas of the source S1b and the drain D1b of the second driving transistor DTb (thin film transistor M1b) (as shown in fig. 5 and 6). Furthermore, adjusting the channel width (or area) of the first driving transistor DTa can also reduce the area of the patterned semiconductor layer C1a of the first driving transistor DTa to be smaller than the area of the patterned semiconductor layer C1b of the second driving transistor DTb.

After the second driving unit adjusting step, a first signal output waveform corresponding to the first gate driving unit SRa and a second signal output waveform corresponding to the second gate driving unit SRb may be obtained through simulation or measurement, wherein a difference between a falling time of the first signal output waveform and a falling time of the second signal output waveform is less than or equal to 2%, and a difference between a slope of a falling portion of the first signal output waveform and a slope of a falling portion of the second signal output waveform is less than or equal to 2%. For example, after the first driving unit adjusting step and the second driving unit adjusting step, the channel width CWa of the first driving transistor DTa of one of the first gate driving units SRa in the embodiment is 1350 micrometers, and the channel width CWb of the second driving transistor DTb of one of the second gate driving units SRb is 2436 micrometers. In the first signal output waveform of the first gate driving unit SRa and the second signal output waveform of the second gate driving unit SRb, the falling time of the first signal output waveform is 0.955 microseconds, and the falling time of the second signal output waveform is 0.956 microseconds, which are different by about 0.1%. In other words, the difference between the slope of the falling portion of the first signal output waveform and the slope of the falling portion of the second signal output waveform is also about 0.1%. As can be seen from the above, in the present embodiment, the area or the channel width of the first driving transistor DTa is adjusted by the first driving unit adjusting step and the second driving unit adjusting step, so as to effectively reduce the difference between the corresponding first signal output waveform and the corresponding second signal output waveform. Therefore, by using the method for improving the display quality of the display panel of the present embodiment, the thrust of each first gate driving unit SRa can be matched with the RC load of the corresponding first scan line SL1, so that the transmission quality of the scan signals in the first region R1 and the second region R2 can be consistent, and the problem of uneven brightness in different regions of the display panel 10 can be improved, thereby improving the display quality.

The display panel and the method for improving the display quality of the display panel of the invention are not limited to the above embodiments. While other embodiments and variations of the present invention will be described below, the same components will be denoted by the same reference numerals and the repeated description thereof will not be repeated in order to simplify the description and to highlight the differences between the embodiments and variations.

Referring to fig. 11, fig. 11 is a circuit layout diagram of a first gate driving unit according to a second embodiment of the invention. As shown in fig. 11, one difference between the present embodiment and the first embodiment is that the width Wa in the first direction D1 of a portion of the first conductive layer 112 forming the gate electrode G1a of the first driving transistor DTa (thin film transistor M1a) is also reduced with the width of the thin film transistor M1 a. Accordingly, a width Wa of a portion of the first conductive layer 112 forming the gate electrode G1a of the first driving transistor DTa is smaller than a width Wb of a portion of the first conductive layer 112 forming the gate electrode G1b of the second driving transistor DTb. Therefore, two openings O2 are formed in the portion of the first conductive layer 112 located at the upper and lower sides of the first driving transistor DTa in the first direction D1, and the opening O2 can overlap the sealant 118 and can increase the light-transmitting area in the first gate driving unit SRa, so as to improve the problem of poor curing of the light-curing adhesive located at the corner position. Another difference between the present embodiment and the first embodiment is that the area or channel width of the thin film transistors M2a-M13a in each first gate driving unit SRa is not reduced, but only the area or channel width of the first driving transistor DTa is reduced. For example, the area or channel width of the tfts M2a-M13a may be equal to that of the tfts M2b-M13b in each second gate driving unit SRb, but not limited thereto.

Furthermore, features of the various embodiments may be interchanged with one another. For example, in an embodiment, the width of a portion of the first conductive layer 112 in the first direction D1, which forms the gate electrode G1a of the first driving transistor DTa (the thin film transistor M1a), is not reduced with the width of the thin film transistor M1a, as in the first embodiment; however, the area or channel width of the tfts M2a-M13a in each of the first gate driving units SRa is not reduced, but only the area or channel width of the first driving transistor DTa is reduced, as in the second embodiment. In another embodiment, the width of a portion of the first conductive layer 112 in the first direction D1, which forms the gate electrode G1a of the first driving transistor DTa (thin film transistor M1a), is reduced with the width of the thin film transistor M1a, as in the second embodiment; however, the area or channel width of the tfts M2a-M13a in each of the first gate driving units SRa is reduced together with the area or channel width of the first driving transistor DTa, as in the first embodiment.

In summary, in the display panel and the method for improving the display quality of the display panel of the invention, the area or the channel width of the first driving transistor is reduced according to the RC load of the first scan line to reduce the thrust of the first gate driving unit, and the thrust of each first gate driving unit can be matched with the RC load of the corresponding first scan line, so that the transmission quality of the scan signal in the first region and the second region is consistent. The difference between the falling time of the first signal output waveform of each first gate driving unit and the falling time of the second signal output waveform of each second gate driving unit is less than or equal to 2%, and the difference between the slope of the falling part of the first signal output waveform and the slope of the falling part of the second signal output waveform is less than or equal to 2%, so that the problem of uneven brightness of different areas in the display panel is solved, and the display quality is improved. In addition, two openings are formed in the partial first conductive layer which is positioned above and below the first driving transistor in the first direction, so that the light-transmitting area in the first gate driving unit can be increased, and the problem of poor curing of the light-curing adhesive positioned at the corner position can be solved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.