阅读说明：本技术 一种显示基板及其制作方法、显示装置 (Display substrate, manufacturing method thereof and display device ) 是由 程磊磊 于 2019-11-19 设计创作，主要内容包括：本发明提供一种显示基板及其制作方法、显示装置，涉及显示技术领域，为解决通过过孔连接双层走线时，容易出现位于顶层的走线在过孔中断裂的问题。所述显示基板包括：沿远离基底的方向，依次层叠设置在基底上的第一导电图形和第二导电图形；位于第一导电图形和第二导电图形之间的第一绝缘层和第二绝缘层，第一绝缘层位于第一导电图形和第二绝缘层之间，第一绝缘层上设置有第一过孔，第二绝缘层上设置有第二过孔，第一过孔在基底上的正投影被第二过孔在基底上的正投影包围，第二过孔在基底上的正投影位于第一导电图形在基底上的正投影的内部，第二导电图形通过第二过孔和第一过孔与第一导电图形耦接。本发明提供的显示基板用于显示画面。(The invention provides a display substrate, a manufacturing method thereof and a display device, relates to the technical field of display, and aims to solve the problem that when double-layer wires are connected through a via hole, the wires on the top layer are prone to being broken in the via hole. The display substrate includes: sequentially stacking a first conductive pattern and a second conductive pattern on the substrate along a direction far away from the substrate; the first insulating layer is located between the first conductive pattern and the second conductive pattern, the first insulating layer is located between the first conductive pattern and the second insulating layer, a first through hole is formed in the first insulating layer, a second through hole is formed in the second insulating layer, the orthographic projection of the first through hole on the substrate is surrounded by the orthographic projection of the second through hole on the substrate, the orthographic projection of the second through hole on the substrate is located inside the orthographic projection of the first conductive pattern on the substrate, and the second conductive pattern is coupled with the first conductive pattern through the second through hole and the first through hole. The display substrate provided by the invention is used for displaying pictures.)

1. A display substrate, comprising:

a substrate, a first electrode and a second electrode,

a first signal line including: sequentially stacking a first conductive pattern and a second conductive pattern on the substrate along a direction far away from the substrate;

at least two layers of insulating layers between the first conductive pattern and the second conductive pattern, the at least two layers of insulating layers comprise a first insulating layer and a second insulating layer, the first insulating layer is located between the first conductive pattern and the second insulating layer, a first via hole is arranged on the first insulating layer, a second via hole is arranged on the second insulating layer, the orthographic projection of the first via hole on the substrate is surrounded by the orthographic projection of the second via hole on the substrate, the orthographic projection of the second via hole on the substrate is located inside the orthographic projection of the first conductive pattern on the substrate, and the second conductive pattern is coupled with the first conductive pattern through the second via hole.

2. The display substrate according to claim 1, further comprising a second signal line, wherein the second signal line is located between the first conductive pattern and the substrate, and an orthogonal projection of the second signal line on the substrate and an orthogonal projection of the first conductive pattern on the substrate have a first overlapping region, and the first overlapping region does not overlap with an orthogonal projection of the second via on the substrate.

3. The display substrate of claim 2, wherein the first overlap region is proximate to a boundary of the second via, and a minimum distance between an orthographic projection of the second via on the base is greater than 0.5 μm.

4. The display substrate according to claim 2, wherein the first signal line comprises a negative power supply signal line, and wherein the second signal line comprises a gate line.

5. The display substrate of claim 1, wherein a minimum distance between a boundary of an orthographic projection of the second via on the base and a boundary of an orthographic projection of the first conductive pattern on the base is greater than a threshold value.

6. The display substrate of claim 5, wherein the threshold is between 0.5 μm and 0.8 μm.

7. The display substrate according to claim 1, wherein the first insulating layer comprises a passivation layer and the second insulating layer comprises a silicone planarization layer.

8. A display device comprising the display substrate according to any one of claims 1 to 7.

9. A manufacturing method of a display substrate is characterized by comprising the step of manufacturing a first signal line and at least two insulating layers on a substrate, and the step specifically comprises the following steps:

manufacturing a first conductive pattern on a substrate;

manufacturing a first insulating layer on one side of the first conductive pattern, which is opposite to the substrate;

manufacturing a second insulating layer on one side, opposite to the substrate, of the first insulating layer, and forming a second via hole on the second insulating layer, wherein a part of the first insulating layer is exposed by the second via hole, and the orthographic projection of the second via hole on the substrate is located inside the orthographic projection of the first conductive pattern on the substrate;

forming a first via on the exposed portion of the first insulating layer, the first via exposing a portion of the first conductive pattern, an orthographic projection of the first via on the substrate being surrounded by an orthographic projection of the second via on the substrate;

and manufacturing a second conductive pattern on the surface of the second insulating layer, which faces away from the substrate, wherein the second conductive pattern is coupled with the first conductive pattern through the second via hole and the first via hole.

10. The method of manufacturing a display substrate according to claim 9, further comprising:

before the first conductive pattern is manufactured, a second signal line is formed on the substrate, a first overlapping area exists between the orthographic projection of the second signal line on the substrate and the orthographic projection of the first conductive pattern on the substrate, and the first overlapping area and the orthographic projection of the second via hole on the substrate do not overlap.

Technical Field

The invention relates to the technical field of display, in particular to a display substrate, a manufacturing method of the display substrate and a display device.

Background

With the increasing demand for display, high-precision display technology has been widely regarded by people. In the related art, a high-precision display device generally has a relatively thick electrode trace, and meanwhile, in order to reduce the voltage drop generated when the electrode trace transmits signals, the electrode trace is set to be a double-layer trace, and the double-layer trace is electrically connected through via holes formed in an insulating layer between the double-layer trace, so that the impedance of the electrode trace is reduced, the voltage drop on a loop is reduced, and the power consumption is reduced. However, in the related art, when the dual-layer traces are connected through the vias, the problem that the traces on the top layer are broken in the vias is likely to occur.

Disclosure of Invention

The invention aims to provide a display substrate, a manufacturing method thereof and a display device, which are used for solving the problem that a routing at the top layer is easy to break in a via hole when a double-layer routing is connected through the via hole.

In order to achieve the above purpose, the invention provides the following technical scheme:

a first aspect of the present invention provides a display substrate comprising:

a substrate, a first electrode and a second electrode,

a first signal line including: sequentially stacking a first conductive pattern and a second conductive pattern on the substrate along a direction far away from the substrate;

at least two layers of insulating layers between the first conductive pattern and the second conductive pattern, the at least two layers of insulating layers comprise a first insulating layer and a second insulating layer, the first insulating layer is located between the first conductive pattern and the second insulating layer, a first via hole is arranged on the first insulating layer, a second via hole is arranged on the second insulating layer, the orthographic projection of the first via hole on the substrate is surrounded by the orthographic projection of the second via hole on the substrate, the orthographic projection of the second via hole on the substrate is located inside the orthographic projection of the first conductive pattern on the substrate, and the second conductive pattern is coupled with the first conductive pattern through the second via hole.

Optionally, the display substrate further includes a second signal line, the second signal line is located between the first conductive pattern and the substrate, an orthogonal projection of the second signal line on the substrate and an orthogonal projection of the first conductive pattern on the substrate have a first overlapping area, and the first overlapping area and an orthogonal projection of the second via hole on the substrate do not overlap.

Optionally, the first overlapping region is close to a boundary of the second via, and a minimum distance between the first overlapping region and an orthographic projection of the second via on the substrate is greater than 0.5 μm.

Optionally, the first signal line includes a negative power supply signal line, and the second signal line includes a gate line.

Optionally, a minimum distance between a boundary of an orthographic projection of the second via hole on the substrate and a boundary of an orthographic projection of the first conductive pattern on the substrate is greater than a threshold.

Optionally, the threshold is between 0.5 μm and 0.8 μm.

Optionally, the first insulating layer includes a passivation layer, and the second insulating layer includes a silicone planarization layer.

In some embodiments, a second aspect of the invention provides a display device comprising the above display substrate.

In some embodiments, a third aspect of the present invention provides a method for manufacturing a display substrate, including a step of manufacturing a first signal line and at least two insulating layers on a substrate, where the step specifically includes:

manufacturing a first conductive pattern on a substrate;

manufacturing a first insulating layer on one side of the first conductive pattern, which is opposite to the substrate;

manufacturing a second insulating layer on one side, opposite to the substrate, of the first insulating layer, and forming a second via hole on the second insulating layer, wherein a part of the first insulating layer is exposed by the second via hole, and the orthographic projection of the second via hole on the substrate is located inside the orthographic projection of the first conductive pattern on the substrate;

forming a first via on the exposed portion of the first insulating layer, the first via exposing a portion of the first conductive pattern, an orthographic projection of the first via on the substrate being surrounded by an orthographic projection of the second via on the substrate;

and manufacturing a second conductive pattern on the surface of the second insulating layer, which faces away from the substrate, wherein the second conductive pattern is coupled with the first conductive pattern through the second via hole and the first via hole.

Optionally, the manufacturing method further includes:

before the first conductive pattern is manufactured, a second signal line is formed on the substrate, a first overlapping area exists between the orthographic projection of the second signal line on the substrate and the orthographic projection of the first conductive pattern on the substrate, and the first overlapping area and the orthographic projection of the second via hole on the substrate do not overlap.

According to the technical scheme provided by the invention, the orthographic projection of the second via hole on the second insulating layer on the substrate is arranged in the orthographic projection of the first conductive pattern on the substrate, so that a section difference cannot be formed between the bottom edge of the formed second via hole and the first insulating layer, and thus when the second via hole is formed by etching, a reaction ion enrichment region cannot be formed at the edge of the second via hole, so that the etching speed at the edge of the second via hole is the same as that at other positions of the second via hole, and the generation of a groove at the edge of the second via hole is avoided, so that the second conductive pattern is not easy to break when the second conductive pattern is formed after the first via hole is manufactured. In addition, in the technical scheme provided by the invention, the groove is not generated at the edge of the second through hole, so that the phenomenon of over-etching the second insulating layer or the insulating layer below the second insulating layer easily generated when the groove is etched is avoided, the problem of short circuit caused by the fact that the insulating layer is broken down by the metal conductive pattern covered below the insulating layer due to the over-etching of the insulating layer is further avoided, and the yield of the display substrate is better ensured.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a schematic top view of a via in the related art;

FIG. 2 is a schematic cross-sectional view taken along line A1A2 in FIG. 1;

FIG. 3 is a schematic cross-sectional view taken along line B1B2 in FIG. 1;

FIG. 4 is a schematic top view of a via provided by an embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view taken along line C1C2 in FIG. 4;

fig. 6 is a schematic cross-sectional view taken along direction D1D2 in fig. 4.

Reference numerals:

10-bottom layer traces, 11-top layer vias,

12-bottom via, 20-second insulating layer

21-second via, 30-first insulating layer,

31-a first via, 40-a second signal line,

50-first conductive pattern, 60-trench,

70-substrate, 80-interlayer insulating layer.

Detailed Description

In order to further explain the display substrate, the manufacturing method thereof and the display device provided by the embodiment of the invention, the following detailed description is made with reference to the accompanying drawings.

Based on the problems existing in the background art, the inventor of the present invention finds, through research, that, in the related art, when a dual-layer trace is connected through a via, the cause of the problem that the trace located on the top layer is easily broken in the via is as follows:

as shown in fig. 1 and fig. 2, taking the example that two insulating layers (not shown in fig. 1) are included between the two layers of traces, the process flow of forming vias on the two insulating layers in the related art includes: firstly, a top layer via hole 11 is manufactured on a second insulating layer 20, and two opposite boundaries included in the orthographic projection of the top layer via hole 11 on a substrate 70 of a display device are not overlapped with the orthographic projection of a bottom layer trace 10 on the substrate 70; then, continuously forming a bottom via hole 12 on the first insulating layer 30 exposed by the top via hole 11 to expose the bottom trace 10; finally, a top layer trace is formed on the second insulating layer 20, so that the top layer trace is electrically connected to the bottom layer trace 10 through the top layer via 11 and the bottom layer via 12.

In the above process, because two opposite boundaries included in the orthographic projection of the top layer via hole 11 on the substrate 70 of the display device are not overlapped with the orthographic projection of the bottom layer trace 10 on the substrate 70, a step difference is formed between the bottom edge of the formed top layer via hole 11 and the first insulating layer 30, when the top layer via hole 11 is formed by etching, a reaction ion enrichment region appears at the edge of the top layer via hole 11, so that the etching speed at the edge of the top layer via hole 11 is increased, a trench 60 is generated at the edge of the top layer via hole 11, and the orthographic projection of the manufactured bottom layer via hole 12 on the substrate 70 is surrounded by the orthographic projection of the top layer via hole 11 on the substrate 70, so that after the manufacturing of the bottom layer via hole 12 is completed, the trench 60 still exists, and thus when the top layer trace is formed, the top layer trace is easy to break.

Based on the above findings, the inventors of the present invention considered to solve the above problems by changing the size of the top-layer via 11 to avoid the generation of the above trench 60.

Referring to fig. 4 and 5, an embodiment of the invention provides a display substrate, including: a substrate 70, a first signal line, and at least two insulating layers; the first signal line includes: sequentially laminating a first conductive pattern 50 and a second conductive pattern provided on the substrate 70 in a direction away from the substrate 70; the at least two insulating layers are located between the first conductive pattern 50 and the second conductive pattern, the at least two insulating layers include a first insulating layer 30 and a second insulating layer 20, the first insulating layer 30 is located between the first conductive pattern 50 and the second insulating layer 20, a first via 31 is provided on the first insulating layer 30, a second via 21 is provided on the second insulating layer 20, an orthographic projection of the first via 31 on the substrate 70 is surrounded by an orthographic projection of the second via 21 on the substrate 70, an orthographic projection of the second via 21 on the substrate 70 is located inside an orthographic projection of the first conductive pattern 50 on the substrate 70, and the second conductive pattern is coupled with the first conductive pattern 50 through the second via 21 and the first via 31.

Specifically, the first conductive pattern 50 and the second conductive pattern may be made of a metal material, and may have the same extending direction, but not limited thereto.

The orthographic projection of the second via 21 on the substrate 70 is located inside the orthographic projection of the first conductive pattern 50 on the substrate 70, and the orthographic projection of the second via 21 on the substrate 70 comprises: an orthographic projection of the second via 21 on the substrate 70 is surrounded by an orthographic projection of the first conductive pattern 50 on the substrate 70; or, a part of the boundary of the orthographic projection of the second via 21 on the substrate 70 is located in an area enclosed by the boundary of the orthographic projection of the first conductive pattern 50 on the substrate 70, and another part of the boundary of the orthographic projection of the second via 21 on the substrate 70 is overlapped with a part of the boundary of the orthographic projection of the first conductive pattern 50 on the substrate 70.

It is noted that the at least two insulating layers may include other insulating layers besides the first insulating layer 30 and the second insulating layer 20, in this case, when forming the via penetrating all the insulating layers, it is to be ensured that when forming the via on the insulating layer farthest from the substrate 70 among all the insulating layers, the orthographic projection of the via on the substrate 70 is located inside the orthographic projection of the first conductive pattern 50 on the substrate 70.

When the display substrate is manufactured, a first conductive pattern 50 is firstly manufactured on a substrate 70, then a first insulating layer 30 and a second insulating layer 20 which are stacked are sequentially formed on one side of the first conductive pattern 50, which faces away from the substrate 70, and then a second via 21 is formed on the second insulating layer 20, wherein a part of the first insulating layer 30 can be exposed by the second via 21, and the orthographic projection of the second via 21 on the substrate 70 is positioned inside the orthographic projection of the first conductive pattern 50 on the substrate 70; then forming a first via 31 on the exposed portion of the first insulating layer 30, wherein the first via 31 can expose a portion of the first conductive pattern 50, and an orthographic projection of the first via 31 on the substrate 70 can be surrounded by an orthographic projection of the second via 21 on the substrate 70; finally, a second conductive pattern is formed on the surface of the second insulating layer 20 facing away from the substrate 70, and the second conductive pattern is coupled to the first conductive pattern 50 through the second via 21 and the first via 31.

According to the specific structure and manufacturing process of the display substrate, in the display substrate provided by the embodiment of the invention, an orthographic projection of the second via 21 on the second insulating layer 20 on the substrate 70 is arranged inside an orthographic projection of the first conductive pattern 50 on the substrate 70, so that no level difference is formed between the bottom edge of the formed second via 21 and the first insulating layer 30, thus, when the second via hole 21 is formed by etching, a reaction ion enrichment region does not appear at the edge of the second via hole 21, so that the etching rate at the edge of the second via 21 is the same as the etching rate at other positions of the second via 21, therefore, the groove 60 is prevented from being generated at the edge of the second via hole 21, so that the second conductive pattern is not easy to break when the second conductive pattern is formed after the first via hole 31 is manufactured.

In addition, in the display substrate provided by the embodiment of the invention, the groove 60 is not generated at the edge of the second via hole 21, so that the phenomenon that the second insulating layer 20 or an insulating layer below the second insulating layer is over-etched easily when the groove 60 is etched is avoided, the problem that the insulating layer is broken down by a metal conductive pattern covered below the insulating layer due to over-etching of the insulating layer to cause short circuit is further avoided, and the yield of the display substrate is better ensured.

As shown in fig. 4 and 6, in some embodiments, the display substrate further includes a second signal line 40, the second signal line 40 is located between the first conductive pattern 50 and the substrate 70, an orthogonal projection of the second signal line 40 on the substrate 70 and an orthogonal projection of the first conductive pattern 50 on the substrate 70 have a first overlapping region, and the first overlapping region does not overlap an orthogonal projection of the second via 21 on the substrate 70.

Specifically, the extending direction of the second signal line 40 may intersect with the extending direction of the first signal line, and the extending direction of the second signal line 40 is perpendicular to the extending direction of the first signal line, for example, but not limited thereto.

The second signal line 40 is disposed at various positions, for example: the second signal line 40 is located between the first conductive pattern 50 and the substrate 70, and an interlayer insulating layer 80 is further disposed between the second signal line 40 and the first conductive pattern 50.

As shown in fig. 6, since the second signal line 40 is located between the first conductive pattern 50 and the substrate 70, and the second signal line 40 overlaps with the first signal line, a step difference is formed at an edge of the first overlapping area of the first conductive pattern 50, that is, a portion of the first conductive pattern 50 located on the second signal line 40 in a direction perpendicular to the substrate 70 is higher than a portion of the first conductive pattern 50 not located on the second signal line 40; further, the first insulating layer 30 formed on the first conductive pattern 50 also has a step difference, so that the second insulating layer 20 formed on the first insulating layer 30 and the first photoresist that needs to be formed on the first insulating layer 30 when the first via hole 31 is formed are uneven in film thickness near the step difference and thin in film thickness near the position where the step difference exists. Illustratively, in a direction perpendicular to the substrate 70, a thickness of a portion of the first insulating layer 30 away from the level difference is 580nm, and a thickness of a portion of the first insulating layer 30 close to the level difference is 350 nm.

In this case, if the orthographic projection of the second via 21 on the substrate 70 is overlapped with the first overlapping area, in the process of forming the second via 21, the second insulating layer 20 and/or the first photoresist layer near the step may be over-etched, which may cause damage (e.g., X in fig. 3) to the first conductive pattern 50 near the step, thereby causing problems of metal oxidation and impedance increase of the first conductive pattern 50, which may further affect the electrical connection performance of the first conductive pattern 50, the electrical characteristics of the thin film transistor electrically connected to the first conductive pattern 50 in the display substrate, and the quality of the display substrate.

In the display substrate provided by the above embodiment, by disposing the first overlapping area not to overlap with the orthographic projection of the second via 21 on the substrate 70, in a direction perpendicular to the substrate 70, neither the second via hole 21 nor the first via hole 31 overlaps with the step difference caused by the second signal line 40, so that in the formation region of the second via hole 21, the thickness of each film layer is uniform, during the formation of said second via 21, the second insulating layer 20 and/or the first photoresist layer are not over-etched, therefore, the problems of damage to the first conductive pattern 50, metal oxidation, impedance increase and the like caused by over-etching are avoided, and the electric connection performance of the first conductive pattern 50, the electric characteristics of a thin film transistor electrically connected with the first conductive pattern 50 in a display substrate and the quality of the display substrate are ensured.

As shown in fig. 4, in some embodiments, the minimum distance (d 3 in fig. 4) between the first overlapping region near the boundary of the second via 21 and the orthographic projection of the second via 21 on the substrate 70 is greater than 0.5 μm.

Specifically, the minimum distance between the first overlapping area and the orthographic projection of the second via hole 21 on the substrate 70 is greater than 0.5 μm when the first overlapping area is close to the boundary of the first via hole 31, so that the thickness of each film layer in the forming area of the second via hole 21 is ensured to be uniform, and the second insulating layer 20 and/or the first photoresist layer are not over-etched in the process of forming the second via hole 21, thereby better avoiding the problems of damage to the first conductive pattern 50, metal oxidation, impedance increase and the like caused by over-etching, ensuring the electrical connection performance of the first conductive pattern 50, and ensuring the electrical characteristics and stability of a thin film transistor electrically connected with the first conductive pattern 50 in a display substrate, and the yield and quality of the display substrate.

In some embodiments, the first signal line includes a negative power supply signal line, and the second signal line 40 includes a gate line.

Specifically, the specific types of the first signal line and the second signal line 40 are various, and illustratively, the first signal line includes a negative power supply signal line, the second signal line 40 includes a gate line, the negative power supply signal line includes a first conductive pattern 50 extending in a first direction, and the second signal line 40 extends in a second direction, the first direction being perpendicular to the second direction.

As shown in fig. 4, in some embodiments, a minimum distance (e.g., d1 or d2 in fig. 4) between a boundary of the orthographic projection of the second via 21 on the substrate 70 and a boundary of the orthographic projection of the first conductive pattern 50 on the substrate 70 is greater than a threshold value.

Specifically, the orthographic projection of the second via hole 21 on the second insulating layer 20 on the substrate 70 is located inside the orthographic projection of the first conductive pattern 50 on the substrate 70, and the orthographic projection boundary of the second via hole 21 on the substrate 70 is set, and the minimum distance between the orthographic projection boundary of the first conductive pattern 50 on the substrate 70 and the orthographic projection boundary of the first conductive pattern 50 is greater than the threshold value, so that it is better ensured that no step difference is formed between the bottom edge of the formed second via hole 21 and the first insulating layer 30, and thus when the second via hole 21 is formed by etching, a reaction ion enriched region does not appear at the edge of the second via hole 21, so that the etching speed at the edge of the second via hole 21 is the same as the etching speed at other positions of the second via hole 21, thereby avoiding the generation of the trench 60 at the edge of the second via hole 21, and making the first via hole 31, when the second conductive pattern is formed, the second conductive pattern is not easily broken.

Moreover, the groove 60 is not generated at the edge of the second via hole 21, so that the phenomenon of over-etching the second insulating layer 20 or the insulating layer below the second insulating layer, which is easily generated when the groove 60 is etched, is avoided, the problem of short circuit caused by the fact that the insulating layer is broken down by the metal conductive pattern covered below the insulating layer due to the over-etching of the insulating layer is further avoided, and the yield of the display substrate is better ensured.

The specific value of the threshold can be set according to actual needs, and exemplarily, the threshold is set to be between 0.5 μm and 0.8 μm; the arrangement mode can not only avoid the generation of the groove 60 at the edge of the second via hole 21, but also ensure that the aperture size of the second via hole 21 is large enough, and further ensure that the aperture size of the subsequently formed first via hole 31 is large enough, so that the first conductive pattern 50 and the second conductive pattern have good electrical connection performance.

Note that, when the thicknesses of the first conductive pattern and the second signal line are between 300nm and 1000nm (inclusive), in the direction perpendicular to the substrate, d1, d2, and d3 may each be greater than or equal to any value between 0.5 μm and 1.5 μm; the thicknesses of the first conductive pattern and the second signal line are different, and the requirements for d1, d2 and d3 are different, and d1, d2 and d3 may not be identical when actually manufactured, and for example, when the thicknesses of the first conductive pattern and the second signal line are 600nm, d1, d2, and d3 may be set to 0.8 μm, 1.2 μm, and 1.0 μm, respectively.

In some embodiments, the first insulating layer 30 may be provided to include a passivation layer, and the second insulating layer 20 may include a silicon on insulator (SOG) layer.

Specifically, the silicone planarizing layer can planarize the step it covers so that the surface of the silicone planarizing layer facing away from the substrate 70 is planar.

The embodiment of the invention also provides a display device which comprises the display substrate provided by the embodiment.

In the display substrate provided by the above embodiment, the orthographic projection of the second via hole 21 on the second insulating layer 20 on the substrate 70 is located inside the orthographic projection of the first conductive pattern 50 on the substrate 70, so that no step difference is formed between the bottom edge of the formed second via hole 21 and the first insulating layer 30, and thus when the second via hole 21 is formed by etching, a reaction ion enriched region does not appear at the edge of the second via hole 21, so that the etching speed at the edge of the second via hole 21 is the same as that at other positions of the second via hole 21, thereby avoiding the generation of the trench 60 at the edge of the second via hole 21, and making the second conductive pattern not easily break when the second conductive pattern is formed after the fabrication of the first via hole 31 is completed. Moreover, in the display substrate provided by the above embodiment, the trench 60 is not generated at the edge of the second via hole 21, so that an over-etching phenomenon of the second insulating layer 20 or an insulating layer below the second insulating layer, which is easily generated when the trench 60 is etched, is avoided, and further, the problem of short circuit caused by the breakdown of the insulating layer by the metal conductive pattern covered below the insulating layer due to the over-etching of the insulating layer is avoided, and the yield of the display substrate is better ensured.

In addition, in the display substrate provided by the above embodiment, by disposing the first overlapping area not to overlap with the orthographic projection of the second via 21 on the substrate 70, in a direction perpendicular to the substrate 70, neither the second via hole 21 nor the first via hole 31 overlaps with the step difference caused by the second signal line 40, so that in the formation region of the second via hole 21, the thickness of each film layer is uniform, during the formation of said second via 21, the second insulating layer 20 and/or the first photoresist layer are not over-etched, therefore, the problems of damage to the first conductive pattern 50, metal oxidation, impedance increase and the like caused by over-etching are avoided, and the electric connection performance of the first conductive pattern 50, the electric characteristics of a thin film transistor electrically connected with the first conductive pattern 50 in a display substrate and the quality of the display substrate are ensured.

Therefore, the display device provided by the embodiment of the invention has the beneficial effects when the display device comprises the display substrate provided by the embodiment, and the description is omitted here.

The display device may be: any product or component with a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer and the like.

The embodiment of the present invention further provides a manufacturing method of a display substrate, which is used for manufacturing the display substrate provided in the above embodiment, the manufacturing method includes a step of manufacturing a first signal line and at least two insulating layers on a substrate 70, and the step specifically includes:

fabricating a first conductive pattern 50 on a substrate 70;

manufacturing a first insulating layer 30 on one side of the first conductive pattern 50, which faces away from the substrate 70;

manufacturing a second insulating layer 20 on a side of the first insulating layer 30 opposite to the substrate 70, forming a second via 21 on the second insulating layer 20, wherein the second via 21 exposes a part of the first insulating layer 30, and an orthographic projection of the second via 21 on the substrate 70 is located inside an orthographic projection of the first conductive pattern 50 on the substrate 70;

forming a first via 31 on the exposed portion of the first insulating layer 30, wherein the first via 31 exposes a portion of the first conductive pattern 50, and an orthographic projection of the first via 31 on the substrate 70 is surrounded by an orthographic projection of the second via 21 on the substrate 70;

a second conductive pattern is formed on a surface of the second insulating layer 20 facing away from the substrate 70, and the second conductive pattern is coupled to the first conductive pattern 50 through the second via 21 and the first via 31.

Specifically, a first conductive film layer is formed on a substrate 70 by using a metal material, and the first conductive film layer is patterned by using a patterning process to form the first conductive pattern 50; then, a first insulating layer 30 is formed on the side, opposite to the substrate 70, of the first conductive pattern 50, and a second insulating layer 20 is formed on the side, opposite to the substrate 70, of the first insulating layer 30; then forming a second photoresist layer on the surface of the second insulating layer 20 opposite to the substrate 70, exposing and developing the second photoresist layer to form a second photoresist layer removal region and a second photoresist layer retention region, wherein the second photoresist layer removal region corresponds to the region where the second via hole 21 is located, the second photoresist retention region corresponds to the other regions except the region where the second via hole 21 is located, etching the second insulating layer 20 located in the second photoresist layer removal region, and removing the second insulating layer 20 located in the second photoresist layer removal region to form a second via hole 21; then, continuously forming a first photoresist layer capable of covering the remaining second insulating layer 20 and the second via hole 21, exposing and developing the first photoresist layer to form a first photoresist layer reserved area and a first photoresist layer removed area, wherein the first photoresist layer removed area corresponds to the area where the first via hole 31 is located, the first photoresist layer reserved area corresponds to other areas except the area where the first via hole 31 is located, and then etching the first insulating layer 30 located in the first photoresist layer removed area to remove the first insulating layer 30 located in the first photoresist layer removed area to form the first via hole 31; and finally, forming a second conductive film layer capable of covering the remaining second insulating layer 20, the second via hole 21 and the first via hole 31, and patterning the second conductive film layer by using a patterning process to form the second conductive pattern, wherein the second conductive pattern is electrically connected with the first conductive pattern 50 through the second via hole 21 and the first via hole 31.

In the display substrate manufactured by the manufacturing method provided by the embodiment of the invention, the orthographic projection of the second via hole 21 on the second insulating layer 20 on the substrate 70 is arranged, and the second via hole is positioned in the orthographic projection of the first conductive pattern 50 on the substrate 70, so that no step difference is formed between the bottom edge of the formed second via hole 21 and the first insulating layer 30, and thus when the second via hole 21 is formed by etching, a reaction ion enrichment region is not generated at the edge of the second via hole 21, and the etching speed at the edge of the second via hole 21 is the same as that at other positions of the second via hole 21, so that a trench 60 is prevented from being generated at the edge of the second via hole 21, and the second conductive pattern is not easy to break when the second conductive pattern is formed after the manufacturing of the first via hole 31 is completed.

In addition, in the display substrate manufactured by the manufacturing method provided by the embodiment of the invention, the groove 60 is not generated at the edge of the second via hole 21, so that the phenomenon of over-etching the second insulating layer 20 or the insulating layer below the second insulating layer, which is easily generated when the groove 60 is etched, is avoided, the problem of short circuit caused by the fact that the insulating layer is broken down by the metal conductive pattern covered below the insulating layer due to the over-etching of the insulating layer is further avoided, and the yield of the display substrate is better ensured.

In some embodiments, the manufacturing method provided in the above embodiments further includes:

before the first conductive pattern 50 is manufactured, a second signal line 40 is formed on the substrate 70, a first overlapping area exists between an orthographic projection of the second signal line 40 on the substrate 70 and an orthographic projection of the first conductive pattern 50 on the substrate 70, and the first overlapping area does not overlap with an orthographic projection of the second via 21 on the substrate 70.

In the display substrate manufactured by the manufacturing method provided by the above embodiment, by setting that the orthographic projections of the first overlapping area and the second via hole 21 on the substrate 70 do not overlap, the second via hole 21 and the first via hole 31 do not overlap with the step difference caused by the second signal line 40 in the direction perpendicular to the substrate 70, so that the thickness of each film layer in the forming area of the second via hole 21 is uniform, and the second insulating layer 20 and/or the first photoresist layer are not over-etched in the process of forming the second via hole 21, thereby avoiding the problems of damage to the first conductive pattern 50, metal oxidation, impedance increase and the like caused by over-etching, ensuring the electrical connection performance of the first conductive pattern 50, and displaying the electrical characteristics of the thin film transistor electrically connected with the first conductive pattern 50 in the substrate, and the quality of the display substrate.

It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the method embodiments, since they are substantially similar to the product embodiments, they are described simply, and reference may be made to the partial description of the product embodiments for relevant points.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected," "coupled," or "connected," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.