阅读说明：本技术 一种存储器的编程方法和系统 (Programming method and system of memory ) 是由 贺元魁 潘荣华 于 2018-08-17 设计创作，主要内容包括：本发明公开了一种存储器的编程方法和系统。存储器的编程方法包括以下步骤：编程时序B1时,向存储单元施加台阶编程电压,所述台阶编程电压具有台阶状上升的电压波形,所述电压波形包括预设数量的电压台阶,每个电压台阶具有预设的台阶宽度,相邻电压台阶之间具有预设的台阶增幅D<Sub>-pgm</Sub>；校验时序Y1时,向存储单元施加校验电压,校验成功则结束；若校验失败,校验时序Y1后再次增加编程电压的幅值以再次进行校验。存储器的编程方法和系统具有提高存储器编程准确性的优点。(The invention discloses a programming method and a system of a memory. The programming method of the memory comprises the following steps: and applying a step programming voltage having a step rising voltage waveform including a preset number of voltage steps, each having a preset step width, and a preset step increase D between adjacent voltage steps to the memory cell when programming the timing sequence B1 ‑pgm (ii) a When the time sequence Y1 is verified, applying verification voltage to the memory cell, and finishing verification if verification is successful; if the verification fails, the magnitude of the program voltage is increased again after the verification timing Y1 to perform the verification again. The programming method and system of the memory have the advantage of improving the programming accuracy of the memory.)

1. A method of programming a memory, comprising the steps of:

and applying a step programming voltage having a step rising voltage waveform including a preset number of voltage steps, each having a preset step width, and a preset step increase D between adjacent voltage steps to the memory cell when programming the timing sequence B1_-pgm；

When the time sequence Y1 is verified, applying verification voltage to the memory cell, and finishing verification if verification is successful;

if the verification fails, the magnitude of the program voltage is increased again after the verification timing Y1 to perform the verification again.

2. The method of programming a memory of claim 1, wherein: when programming the timing sequence B1, the first voltage step of the step program voltage has the preliminary program voltage, the last voltage step of the step program voltage has the target program voltage, and the preliminary program voltage has a value of 20% -70% of the target program voltage.

3. The method of programming a memory of claim 1, wherein: a predetermined step increase D_-pgmThe value of (b) is 5% to 30% of the target programming voltage value.

4. The method of programming a memory of claim 1, wherein: an increase D of the step programming voltage_-pgmRemain unchanged or decrease as the step rises.

5. The method of programming a memory of claim 1, wherein: the preset number of the voltage steps is 2 to 5.

6. The method of programming a memory of claim 2, wherein: the target programming voltage ranges from 12V to 16V.

7. The method of programming a memory of claim 1, wherein: the preset step width is 0.05-0.5 s.

8. The method of programming a memory of claim 1, wherein: at the program timing B1, a step program voltage is applied to the selected word line, a pass voltage is applied to the unselected word line, 0V is applied to the selected bit line, and a positive voltage is applied to the unselected bit line.

9. The method of programming a memory of claim 1, wherein: at the verification timing Y1, a verification voltage is applied to the selected word line, the selected bit line is precharged to the precharge voltage, and a pass voltage is applied to the unselected word line; and then, discharging the selected bit line for the first time, comparing the voltage of the discharged bit line with a first judgment voltage, if the voltage of the discharged bit line is higher than the first judgment voltage, indicating that the verification is successful and the operation can be finished, otherwise, indicating that the verification fails and storing data into the memory again for verification, wherein the verification voltage range is 0V-1V, and the pre-charging voltage range is 1V-1.2V.

10. A programming system for a memory, the programming system comprising:

a programming module for applying a step programming voltage to the memory cell when programming timing B1, the step programming voltage having a step rising voltage waveform including a predetermined number of voltage steps, each voltage step having a predetermined step width, and a predetermined step increase D between adjacent voltage steps_-pgm；

The verification module is used for applying verification voltage to the storage unit when verifying the time sequence Y1, and the verification is finished if the verification is successful;

if the verification fails, after verifying the timing Y1, the program module increases the magnitude of the program voltage again and the verify module verifies again.

Technical Field

The embodiment of the invention relates to the technical field of memories, in particular to a programming method and system of a memory.

Background

The Nand flash memory is a nonvolatile memory and has the advantages of high rewriting speed, large storage capacity and the like. When the Nand flash memory is in programming operation, verification failure occurs, and after each verification failure, the amplitude of the programming voltage needs to be increased. In the prior art, when data is programmed and written for the first time, a higher programming voltage is directly applied to a selected word line of a memory, and the higher programming voltage affects memory cells which do not need to be programmed on the selected word line, so that the threshold of the memory cells which do not need to be programmed is increased, reading errors are caused, and the programming accuracy is low.

Therefore, how to improve the accuracy of programming of the memory becomes a demand in the memory technology field.

Disclosure of Invention

The invention provides a programming method and a programming system of a memory, which aim to solve the technical problem of poor accuracy in programming of the memory.

In a first aspect, an embodiment of the present invention provides a method for programming a memory, including the following steps: and applying a step programming voltage having a step rising voltage waveform including a preset number of voltage steps, each having a preset step width, and a preset step increase D between adjacent voltage steps to the memory cell when programming the timing sequence B1_-pgm(ii) a When the time sequence Y1 is verified, applying verification voltage to the memory cell, and finishing verification if verification is successful; if the verification fails, the magnitude of the program voltage is increased again after the verification timing Y1 to perform the verification again.

Preferably, the first voltage step of the step program voltage has a preliminary program voltage and the last voltage step of the step program voltage has a target program voltage at the time of programming timing B1, and the preliminary program voltage has a value of 20% to 70% of the target program voltage.

Preferably, the step increase D is preset_-pgmThe value of (b) is 5% to 30% of the target programming voltage value.

Preferably, the step programming voltage is increased by an amount D_-pgmRemain unchanged or decrease as the step rises.

Preferably, the preset number of voltage steps is 2 to 5.

Preferably, the target program voltage ranges from 12V to 16V.

Preferably, the preset step width is 0.05-0.5 s.

Preferably, at program timing B1, a step program voltage is applied to the selected word line, a pass voltage is applied to the unselected word lines, 0V is applied to the selected bit line, and a positive voltage is applied to the unselected bit lines.

Preferably, at the verification timing Y1, a verification voltage is applied to the selected word line, the selected bit line is precharged to a precharge voltage, and a pass voltage is applied to the unselected word line; and then, discharging the selected bit line for the first time, comparing the voltage of the discharged bit line with a first judgment voltage, if the voltage of the discharged bit line is higher than the first judgment voltage, indicating that the verification is successful and the operation can be finished, otherwise, indicating that the verification fails and storing data into the memory again for verification, wherein the verification voltage range is 0V-1V, and the pre-charging voltage range is 1V-1.2V.

In a second aspect, the present invention also provides a programming system of a memory, the programming system of the memory including: a programming module for applying a step programming voltage to the memory cell when programming timing B1, the step programming voltage having a step rising voltage waveform including a predetermined number of voltage steps, each voltage step having a predetermined step width, and a predetermined step increase D between adjacent voltage steps_-pgm(ii) a The verification module is used for applying verification voltage to the storage unit when verifying the time sequence Y1, and the verification is finished if the verification is successful; if the verification fails, after verifying the timing Y1, the program module increases the magnitude of the program voltage again and the verify module verifies again.

Compared with the prior art, the invention provides the programming method and the system of the memory, when the time sequence B1 is programmed, the step programming voltage is applied to the memory cell, the step programming voltage has a voltage waveform with step rising, the programming voltage is not increased to the maximum value of the step programming voltage at one time, the impact on the memory cell which is not programmed on the selected word line is reduced, the change of the threshold value of the memory cell which is not programmed on the selected word line is avoided, and the accuracy and the stability of the memory are improved.

Drawings

FIG. 1 is a flow chart illustrating a method for programming a memory according to an embodiment of the invention.

Fig. 2 is a schematic chip structure diagram of a memory cell in embodiment a of the invention.

FIG. 3 is a circuit diagram of a memory array according to an embodiment of the present invention.

FIG. 4 is a waveform diagram of voltages at different times in a programming method of a memory according to embodiment A of the present invention.

FIG. 5 is a graph showing the variation of the magnitude of the program voltage with the increase of the number of verification failures in the embodiment A.

FIG. 6 is a block diagram of a programming system of a memory according to embodiment B of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.