Power semiconductor device
阅读说明:本技术 功率半导体器件 (Power semiconductor device ) 是由 埃迪·黄 尼古拉斯·A·M·科佩尔 马特加兹·罗兹曼 斯蒂芬·D·伍德 章剑峰 于 2019-07-23 设计创作,主要内容包括:本发明提供一种功率半导体器件,包括:具有单极传导结构和双极传导结构的半导体衬底,第一端子和第二端子。单极传导结构包括第一传导类型的第一区、第二区和第三区,其中,第二区的掺杂浓度低于第一区和第三区的掺杂浓度。双极传导结构包括与第一传导类型相反的第二传导类型的第四区、第二区和第五区。单极传导结构可操作以在第一端子和第二端子之间提供第一传导路径。双极传导结构可操作以在第一端子和第二端子之间提供第二传导路径。第一传导路径被配置为在功率半导体器件的导通状态期间,以第一频率接通和断开,并且第二传导路径被配置为在第一传导路径的断开阶段期间接通,在第一传导路径的导通阶段期间被断开。(The invention provides a power semiconductor device, comprising: a semiconductor substrate having a unipolar conductive structure and a bipolar conductive structure, a first terminal and a second terminal. The unipolar conductive structure includes a first region, a second region, and a third region of the first conductivity type, wherein a doping concentration of the second region is lower than a doping concentration of the first region and the third region. The bipolar conductive structure includes a fourth region, a second region, and a fifth region of a second conductivity type opposite the first conductivity type. The unipolar conductive structure is operable to provide a first conductive path between the first terminal and the second terminal. The bipolar conductive structure is operable to provide a second conductive path between the first terminal and the second terminal. The first conductive path is configured to be switched on and off at a first frequency during an on-state of the power semiconductor device, and the second conductive path is configured to be switched on during an off-phase of the first conductive path and switched off during an on-phase of the first conductive path.)
1. A power semiconductor device comprising:
a semiconductor substrate, comprising:
a unipolar conductive structure including a first region of a first conductivity type, a second region of the first conductivity type, and a third region of the first conductivity type, wherein a doping concentration of the second region is lower than doping concentrations of the first region and the third region; and
a bipolar conductive structure including a fourth region of a second conductivity type opposite the first conductivity type, a second region, a fifth region of the second conductivity type;
a first terminal operatively coupled to the first region; and
a second terminal operably coupled to the third region and the fifth region;
wherein the unipolar conductive structure is operable to provide a first conductive path between the first terminal and the second terminal using at least the first region, the second region, and the third region;
wherein the bipolar conductive structure is operable to provide a second conductive path between the first terminal and the second terminal using at least the fourth region, the second region, and the fifth region;
wherein the first conductive path is configured to be switched on and off at a first frequency with application of a control signal during an on-state of the power semiconductor device, and the second conductive path is configured to operate in a high conductivity mode during an off-phase of the first conductive path and in a low conductivity mode during an on-phase of the first conductive path.
2. The power semiconductor device of claim 1, wherein second region is configured to receive conductivity modulation due to at least minority carrier injection from the fifth region into the second region when the second conductive path operates in a high conductivity mode.
3. A power semiconductor device according to claim 1 or 2, wherein the first conductive path is substantially parallel to the second conductive path.
4. A power semiconductor device according to any preceding claim, wherein the power semiconductor device is operable to have an on state during which current flows between the first and second terminals using at least one of the first and second conductive paths, and an off state during which current does not flow between the first and second terminals.
5. A power semiconductor device according to any preceding claim, wherein the power semiconductor device is a power switch.
6. The power semiconductor device of any preceding claim, wherein:
the bipolar conductive structure includes a gate terminal operatively coupled to the fourth region;
the gate terminal is operable to receive a gate signal for activating a current flowing through the bipolar conductive structure; and
the power semiconductor device is configured to enter an on state from an off state upon application of a gate signal and a control signal.
7. A power semiconductor device according to any preceding claim, wherein the duration of the on-phase of the first conduction path is configured to be longer than the duration of the off-phase of the first conduction path during an on-state of the power semiconductor device.
8. A power semiconductor device according to claim 2 or any one of claims 3 to 7 when dependent on claim 2, wherein the duration of the on-phase of the first conduction path in at least one cycle of the control signal is shorter than the duration of disappearance of a portion of the injected carriers by recombination with majority carriers of the second region.
9. A power semiconductor device according to any preceding claim, wherein the fifth and third regions are embedded within the substrate below the second region.
10. The power semiconductor device of any preceding claim, wherein the unipolar conductive structure comprises a Metal Oxide Semiconductor (MOS) gate structure, and wherein the MOS gate structure comprises a channel region of the second conductivity type disposed between the first and second regions; and a gate electrode for generating an electric field in the channel region to invert a conductivity type of the channel region to form a conductive channel between the first region and the second region.
11. The power semiconductor device of claim 10, wherein said gate electrode is configured to receive said control signal to switch on and off said conduction channel of a MOS gate structure to switch on and off said first conduction path.
12. The power semiconductor device of claim 10 or 11, wherein said first region is disposed within said fourth region and said bipolar conductive structure comprises said first region.
13. The power semiconductor device of claim 10, further comprising a switch connectable between the first terminal and the first region, and configured to receive the control signal to turn the first conduction path on and off.
14. The power semiconductor device of claim 13, wherein:
the first zone is arranged in the fourth zone;
the bipolar conductive structure includes a sixth region of the first conductivity type disposed within the fourth region and spaced apart from the first region.
15. A power semiconductor device according to any one of claims 1 to 9, wherein the first region is in direct contact with the second region, and the power semiconductor device further comprises a switch connectable between the first terminal and the first region, and the switch is configured to receive a control signal to switch on and off the first conduction path.
16. The power semiconductor device of claim 15, wherein said bipolar conductive structure comprises a sixth region of the first conductivity type, and said sixth region is disposed within said fourth region.
17. The power semiconductor device of claim 16, wherein:
the bipolar conductive structure includes a plurality of conductive cells connected in parallel between a first terminal and a second terminal,
the sixth region includes a plurality of sixth sub-regions spaced apart from each other,
the fourth region includes a plurality of fourth sub-regions spaced apart from each other,
at least one of the sixth sub-regions being arranged within one of the fourth sub-regions, forming one of the conductive elements with the second and fifth regions; and
at least one of the sixth sub-areas is operatively connected to the first terminal.
18. The power semiconductor device of claim 16 or 17, wherein:
the fifth region includes a plurality of fifth sub-regions spaced apart from each other; and
at least one of the fifth sub-areas is disposed below one of the fourth sub-areas.
19. A power semiconductor device according to claim 17 or 18, wherein the first region comprises at least one first sub-region spaced apart from each other and arranged between adjacent ones of the fourth sub-regions.
20. A power semiconductor device according to claim 17 or 18, wherein the first region comprises at least one first sub-region spaced apart from each other, and wherein the at least one first sub-region is provided within one of the fourth sub-regions and has a boundary substantially aligned with a boundary of one of the fourth sub-regions such that the at least one first sub-region is in direct contact with the second region.
21. A method of operating a power semiconductor device, the power semiconductor device comprising:
a semiconductor substrate comprising:
a unipolar conductive structure including a first region of a first conductivity type, a second region of the first conductivity type, and a third region of the first conductivity type, wherein a doping concentration of the second region is lower than doping concentrations of the first region and the third region; and
a bipolar conductive structure including a fourth region of a second conductivity type opposite the first conductivity type, a second region, a fifth region of the second conductivity type;
a first terminal operatively coupled to the first region; and
a second terminal operably coupled to the third region and the fifth region;
the method comprises the following steps:
providing a first conductive path between the first terminal and the second terminal using the first region, the second region, and the third region;
applying a control signal to switch on and off a first conduction path at a first frequency during an on-state of the power semiconductor device;
providing a second conductive path between the first terminal and the second terminal using the fourth region, the second region, and the fifth region; and
controlling the second conductive path to operate in a high conductivity mode during an off phase of the first conductive path, wherein the second conductive path operates in a low conductivity mode during an on phase of the first conductive path.
Technical Field
The present invention relates to a power semiconductor device. More particularly, but not exclusively, the invention relates to power switches for power electronics applications.
Background
Power semiconductor devices are semiconductor devices used for power electronics applications. Such devices are also referred to as power devices. Typically, power devices have a voltage rating in excess of 20V (i.e., the potential difference that the device must withstand in the OFF state between its main terminals) and conduct in excess of 100mA during its ON state. More commonly, the rating of the power device is higher than 60V and higher than 1A. These values make power devices quite different from low voltage devices, which typically operate at voltages below 5V and conduct currents typically below 1mA, and more typically in the μ a or below μ a range. Another difference between power devices and other types of devices, such as low voltage or Radio Frequency (RF) devices, is that power devices operate primarily on large signals and operate like switches. Exceptions are found in high voltage or power amplifiers, which comprise dedicated power transistors primarily for linear operation. It is not uncommon for a power semiconductor device to carry a current on the order of about 10A to 3000A in its on-state and to block a voltage on the order of about 100V to 10000V in its off-state. Commonly used power semiconductor devices include power diodes, thyristors, Bipolar Junction Transistors (BJTs), power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), and Insulated Gate Bipolar Transistors (IGBTs).
Power semiconductor devices are commonly used as switches or rectifiers in power electronics applications. A switch is an electronic device that can make or break a circuit. The switch has an on state during which current can flow through the switch and an off state during which current cannot flow through the switch. Switches are typically used to conduct current and block voltage in the same direction. In other words, the switch operates such that during an on state, current flows from the first terminal to the second terminal of the switch and the potential at the first terminal is higher than the potential at the second terminal, and during an off state, the switch is capable of withstanding a voltage applied across the switch, wherein the potential at the first terminal is higher than the potential at the second terminal without conducting any significant current between the first terminal and the second terminal. The switch typically has a third terminal which serves as a control terminal for setting and switching the on/off state of the switch. The voltage drop across the switch during the on-state is referred to as the "on-state voltage" of the switch. The on-state voltage is determined by the configuration and material of the switch. Preferably, the on-state voltage should be as low as possible in order to reduce power losses and improve switching efficiency. The current through the switch in the on state should be lower than the rated current of the switch and the voltage applied across the switch in the off state should be lower than the rated voltage of the switch. Otherwise, the switch will be at risk of collapsing.
Currently, the load is switched at dc voltages exceeding 400V, MOSFETs (especially super junction MOSFETs), Insulated Gate Bipolar Transistors (IGBTs), Bipolar Junction Transistors (BJTs) and high voltage thyristors are the options for selection, as well as new technological options such as upcoming silicon carbide (SiC) FETs and gallium nitride (GaN) FETs. Each of these existing power switches has advantages and disadvantages and is therefore directed to different types of applications.
BJTs are a well established technology and are relatively inexpensive to manufacture. Furthermore, BJTs can switch high current loads at high voltages while achieving very low on-state voltages. However, to carry high currents, the BJT must have a relatively large base current, which requires a separate base drive circuit and power supply. Furthermore, BJTs for power electronics applications typically have a large amount of charge stored in the base when the BJT is driven into saturation. The stored charge limits the turn-off time of the BJT, thus limiting its operating frequency in switching applications.
In contrast, MOSFETs are voltage driven and can be controlled directly from the IC. As a majority carrier device, a MOSFET can switch a load at very high frequencies. The super junction technology can realize very low on-state voltage. However, the manufacture of super junction MOSFETs is still relatively expensive and is practically limited to rated voltages below 1000V. Older technology for planar MOSFETs is much less expensive to manufacture and can be used to achieve voltage ratings above 1000V. However, planar MOSFETs typically have a high on-resistance (R) due to the series resistance of the low doped regions required to support high voltagesDS(on)). High on-resistance means that planar MOSFETs can only be used at relatively low current densities and are generally not capable of achieving high current ratings.
IGBTs combine the easy-to-drive advantage of MOSFETs with bipolar functionality to achieve relatively low on-state voltages at moderate to high current densities. The presence of stored charge from bipolar operation reduces the effective series resistance of the lowly doped region. IGBTs are cheaper to manufacture than super junction MOSFETs (while still being much more expensive than high voltage BJTs) and can be used to achieve voltage ratings in excess of 1000V. As with BJTs, the presence of stored charge within IGBTs limits the operating frequency, although recent advances have made these devices suitable for operation at up to 30-50 kHz. The on-state characteristic of the IGBT has an inflection point voltage that cannot be eliminated. Due to this knee voltage, the on-state voltage of the IGBT is never lower than 0.7V, in practice mostly higher than 1V. In contrast, MOSFETs and even BJTs can achieve on-state voltages below 0.5V at suitable current densities. The degree of bipolar action in an IGBT is also typically limited by design to ensure that it can be turned off via the gate of the IGBT. Therefore, IGBTs are not suitable for operating at very high current densities.
High voltage thyristors, including Silicon Controlled Rectifiers (SCRs) and gate turn-off thyristors (GTOs), are popular in industrial motor control applications. They benefit from a very strong bipolar action and can be used at very high current densities, achieving low on-state voltages even at very high nominal voltages (e.g. above 2000V). However, the on-state voltage still has a "knee" as in an IGBT, and the strong bipolar action results in a very high stored charge, which limits the operating frequency of the high-voltage thyristor to about 1 kHz. SCR also has the disadvantage of not being able to cut off via the gate only. Although GTOs can be switched off via the gate, they typically require high power gate drive circuitry to facilitate such switching off.
Compound semiconductor switches such as GaN and SiC FETs have many advantages and overcome many of the disadvantages of the various device types described above, but their high cost currently still limits their use for professional applications.
There is therefore a need for a cost-effective power semiconductor device that can be used as a switch in power electronics applications and that also provides low on-state voltage and high efficiency.
It is an object of the invention to provide such a cost-effective power semiconductor device.
Disclosure of Invention
According to a first aspect of the present invention, there is provided a power semiconductor device comprising: a semiconductor substrate, comprising: a unipolar conductive structure including a first region of a first conductivity type, a second region of the first conductivity type, and a third region of the first conductivity type, wherein a doping concentration of the second region is lower than doping concentrations of the first region and the third region; and a bipolar conductive structure comprising a fourth region of a second conductivity type opposite to the first conductivity type, a second region, a fifth region of the second conductivity type; a first terminal operatively coupled to the first region; and a second terminal operatively coupled to the third region and the fifth region. The unipolar conductive structure is operable to provide a first conductive path between the first terminal and the second terminal using at least the first region, the second region, and the third region. The bipolar conductive structure is operable to provide a second conductive path between the first terminal and the second terminal using at least the fourth region, the second region, and the fifth region. The first conductive path is configured to be switched on and off at a first frequency with application of a control signal during an on-state of the power semiconductor device, and the second conductive path is configured to operate in a high conductivity mode during an off-phase of the first conductive path and in a low conductivity mode during an on-phase of the first conductive path.
By providing a bipolar conducting structure and a unipolar conducting structure on the same semiconductor substrate, both sharing a common low-doped second region designed for achieving a high voltage rating, and by alternating conduction of a first conducting path provided by the unipolar conducting structure and a second conducting path provided by the bipolar conducting structure at a first frequency, conduction of the bipolar conducting structure during an off phase of the first conducting path allows an on-state voltage of the unipolar conducting structure to be reduced during an on phase of the first conducting path. Thus, advantageously, the device may achieve an average on-state voltage that is lower than each of the on-state voltage of the bipolar conducting structure and the original on-state voltage of the unipolar conducting structure. Therefore, the device can achieve high efficiency and low power consumption.
The term "terminal" is used interchangeably with "electrode".
It should be understood that a unipolar conductive structure refers to a semiconductor structure that uses only one type of charge carriers during electron conduction. For example, MOSFETs and schottky diodes are unipolar conductive structures. Since the charge carriers involved are majority carriers, the unipolar conduction structure may also be referred to as a majority carrier conduction structure.
The first conductive path may be a resistive conductive path.
A bipolar conduction structure refers to a semiconductor structure that uses two types of charge carriers (i.e., electrons and holes) during electron conduction. For example, Bipolar Junction Transistors (BJTs), thyristors, IGBTs, and PN junction diodes are bipolar conducting structures. The bipolar conducting structure may also be referred to as a minority carrier conducting structure, since both majority and minority carriers are involved during conduction of the bipolar conducting structure.
The terms "high-conductivity mode" and "low-conductivity mode" may also be referred to as "first conduction mode" and "second conduction mode", respectively, wherein the first conduction mode provides a higher level of conductivity than the second conduction mode. Typically, the level of current flowing through the bipolar conducting structure during the low conductivity mode is much lower than the level of current flowing through the bipolar conducting structure during the high conductivity mode. The current flowing through the bipolar conductive structure during the low conductivity mode is also much lower than the current flowing through the first conductive path during the on-phase of the first conductive path. Thus, the second conductive path and the bipolar conductive structure may also be considered to be "off" during the low conductivity mode.
The second region may be configured to receive conductivity modulation due to at least minority carriers being injected from the fifth region into the second region when the second conductive path is operating in a high conductivity mode.
The first conductive path may be substantially parallel to the second conductive path.
This parallel arrangement allows the unipolar conductive structure to enjoy the benefits of conductivity modulation due to the conduction of the bipolar conductive structure without introducing the knee voltage of the bipolar conductive structure into the conduction characteristics of the overall on-state of the device.
The power semiconductor device is operable to have an on state during which current flows between the first and second terminals using at least one of the first and second conductive paths, and an off state during which current does not flow between the first and second terminals.
The power semiconductor device is a power switch. The power switch may be a bidirectional switch.
The bipolar conductive structure may include a gate terminal operatively coupled to the fourth region. The gate terminal is operable to receive a gate signal for activating a current flowing through the bipolar conductive structure. The power semiconductor device may be configured to enter an on state from an off state upon application of a gate signal and a control signal.
The semiconductor substrate may be a monolithic silicon substrate. The first to fifth regions may be regions of the silicon substrate doped with different types and/or different impurity levels.
The third region may have a first surface and a second surface opposite the first surface. The second terminal may be electrically coupled to the second surface of the third region. The second zone may be disposed on the first surface of the third zone.
The second region may have a first surface and a second surface opposite the first surface and facing the third region.
The fourth region may be disposed within the second region adjacent the first surface of the second region.
The first region may be disposed adjacent to the first surface of the second region.
The fifth region may have a first surface and a second surface opposite the first surface. The second terminal may be electrically coupled to the second surface of the fifth region.
The second region may be disposed on the first surface of the fifth region.
The duration of the on-phase of the first conduction path may be configured to be longer than the duration of the off-phase of the first conduction path during an on-state of the power semiconductor device.
The duration of the on-phase of the first conduction path during at least one period of the control signal may be shorter than the duration of disappearance of a part of the injected carriers by recombination with majority carriers of the second region.
The proportion of injected carriers may be a significant fraction of the injected carriers. Optionally, the fraction may have a value between 50% and 95%.
The first frequency may be between 10KHz and 10 MHz.
The fifth region and the third region may be embedded within the substrate below the second region.
The unipolar conductive structure may include a Metal Oxide Semiconductor (MOS) gate structure. The MOS gate structure may include a channel region of the second conductivity type disposed between the first and second regions; and a gate electrode for generating an electric field in the channel region to invert a conductivity type of the channel region to form a conductive channel between the first region and the second region.
The gate electrode may be configured to receive the control signal to switch on and off the conduction channel of a MOS gate structure to switch on and off the first conduction path.
The first region may be disposed within the fourth region, and the bipolar conductive structure may include the first region.
The power semiconductor device may further include a switch connectable between the first terminal and the first region, and the switch is configured to receive the control signal to turn on and off the first conduction path.
The first zone may be disposed within the fourth zone. The bipolar conductive structure may include a sixth region of the first conductivity type, and the sixth region may be disposed within the fourth region and may be spaced apart from the first region.
The first region may be in direct contact with the second region. The power semiconductor device may further include a switch connectable between the first terminal and the first region, and the switch may be configured to receive a control signal to turn on and off the first conduction path. The bipolar conductive structure may include a sixth region of the first conductivity type, and the sixth region is disposed within the fourth region.
The power semiconductor device may include a first electrode portion electrically connected to the sixth region, and a second electrode portion electrically connected to the first region. The term "electrode portion" is used interchangeably with the term "metallized contact". The first electrode portion may be spaced apart from the second electrode portion. The switch may be electrically connected between the first terminal and the second electrode portion. The first electrode portion may be electrically connected to the first terminal.
The switch may be a low voltage switch. It should be understood that the term "low-voltage switch" means that the voltage rating of the switch is lower than the voltage rating of the power semiconductor devices.
The above switch may be formed on another semiconductor substrate separate from the semiconductor substrate. The semiconductor substrate and the further semiconductor substrate may be encapsulated in a single package.
The bipolar conductive structure may include a plurality of conductive cells connected in parallel between a first terminal and a second terminal. The sixth region may include a plurality of sixth sub-regions spaced apart from each other. The fourth region may include a plurality of fourth sub-regions spaced apart from each other. At least one of the sixth sub-regions may be provided within one of the fourth sub-regions, forming one of the conductive elements with the second and fifth regions. At least one of the sixth sub-areas is operatively connected to the first terminal.
The fourth sub-regions may be spaced apart from each other by a distance configured such that, during an off-state of the device, depletion regions associated with adjacent fourth sub-regions within the second region commonly pinch off the first conduction path before a breakdown of a switch connectable between the first region and the first terminal occurs.
The fifth region may include a plurality of fifth sub-regions spaced apart from each other. At least one of the fifth sub-areas may be disposed below one of the fourth sub-areas.
The first region may include at least one first sub-region spaced apart from each other, and the at least one first sub-region is disposed between adjacent sub-regions of the fourth sub-regions.
Alternatively, the first region may comprise at least one first sub-region spaced apart from each other. The at least one first sub-region may be disposed within one of the fourth sub-regions and may have a boundary substantially aligned with a boundary of one of the fourth sub-regions such that the at least one first sub-region is in direct contact with the second region.
The doping concentration and the thickness of the second region may be configured such that the power semiconductor device is capable of supporting a voltage between the first terminal and the second terminal having, but not limited to, a magnitude of 600V to 800V during the off-state.
According to a second aspect of the present invention, there is provided a method of operating a power semiconductor device comprising: a semiconductor substrate comprising: a unipolar conductive structure including a first region of a first conductivity type, a second region of the first conductivity type, and a third region of the first conductivity type, wherein a doping concentration of the second region is lower than doping concentrations of the first region and the third region; and a bipolar conductive structure comprising a fourth region of a second conductivity type opposite to the first conductivity type, a second region, a fifth region of the second conductivity type; a first terminal operatively coupled to the first region; and a second terminal operably coupled to the third and fifth regions; the method comprises the following steps: providing a first conductive path between the first terminal and the second terminal using the first region, the second region, and the third region; applying a control signal to switch on and off a first conduction path at a first frequency during an on-state of the power semiconductor device; providing a second conductive path between the first terminal and the second terminal using the fourth region, the second region, and the fifth region; and controlling the second conductive path to operate in a high conductivity mode during an off phase of the first conductive path, wherein the second conductive path operates in a low conductivity mode during an on phase of the first conductive path.
Any optional feature described above in relation to aspects of the invention may be applied to another of the aspects of the invention where appropriate.
It should be understood that the power semiconductor device of the present invention is suitable for use in various power electronic applications and is not limited to use as a power switch.
Drawings
For a more complete understanding of the present invention, several embodiments thereof will now be described, by way of example, with reference to the accompanying drawings, in which:
fig. 1 is a schematic diagram of a cross-section of a power semiconductor device according to a first embodiment of the present invention.
Fig. 2 is a schematic diagram of input and output waveforms during the on-state of the power semiconductor device of fig. 1.
Fig. 3 is a schematic diagram of a cross-section of a power semiconductor device according to a second embodiment of the present invention.
Fig. 4 is a schematic diagram of a cross-section of a power semiconductor device according to a third embodiment of the present invention.
Fig. 5 is a schematic diagram of a cross-section of a power semiconductor device according to a fourth embodiment of the present invention.
In the drawings, like parts are denoted by like reference numerals. Further, in each drawing, a component denoted by a reference numeral (format N-i) has the same characteristics as another portion denoted by the reference numeral N.
It is to be understood that the drawings are for illustrative purposes only and are not drawn to scale.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Fig. 1 schematically shows a cross-section of a
Having a thickness t2Is provided on the top surface of the N +
A
The N +
The
Accordingly, when a positive voltage is applied between the
Similar to a typical MOSFET, the first conduction path P1 uses only one type of charge carrier (i.e., electrons) for conduction. The electrons are the predominant carriers for N +
Since the first conduction path P1 is resistive, the on-state characteristic of the unipolar conduction structure has no knee voltage. On-resistance (R) of unipolar conduction structureDS(on)) Including the resistance of the N +
A relatively thick and low doped N-
The P +
The second conduction path P2 may be turned on by applying a positive voltage between the
When path P2 is fully conducting, N-
It should be appreciated that once path P2 is on, it cannot be turned off simply by removing the current provided to
Conduction of path P2 requires diffusion of electrons and holes. Therefore, the second conduction path P2 may be referred to as a bipolar conduction path or a minority carrier conduction path. Therefore, the P +
The
To achieve the open state, paths P1 and P2 must remain closed. Path P1 may be kept off by applying a low voltage (including 0V) to
To achieve the on-state, at least one of the conduction paths P1 and P2 is generally conducted. Path P1 may be conducted by applying a relatively high voltage to
As described above, the voltage drop along path P1 may be large due to the high resistance of N-
Fig. 2 shows the current I supplied to the
As shown in fig. 2, during the whole period t of the on stateONDuring the period, not making the grid electrode16 are constantly biased positive to cause the presence of an N-channel, but will turn a fast on and off (on-off) pulse VGSIs applied to
VGSIs T, which comprises an off-phase T1 switching off the N-channel and an on-phase T2 switching on the N-channel.
During the disconnection phase T1, the first conduction path P1 is disconnected. However, a current pulse I having a duration of T3GIs provided to the
On-state voltage V during off-phase T1 during conduction of path P2ONAbout 1V (i.e., the knee voltage of the on-state characteristic of the bipolar conductive structure). As described above, N-
When the N-channel is turned on during the on-phase T2, both the first conductive path P1 and the second conductive path P2 are conducting at the beginning of the on-phase T2. It will be appreciated that current will tend to flow through paths having lower resistance. Due to the conductivity modulation received by the N-
Because most, if not all, of the current is directed to path P1, the current flowing through path P2 drops below the holding current of the bipolar conducting structure. Path P2 automatically closes or enters a very low conductivity mode. Thus, the current pulse IGMay optionally be shorter than, equal to, or greater than the duration of the disconnection period T1. It should be understood that although fig. 2 shows that the current is pulsed I at the beginning of each off-phase T1GApplied to the
As the on-phase T2 continues, the minority carriers injected into the N-
Typically, the minority carrier lifetime in the N-
By repeating VGSAnd an off-phase T1 and an on-phase T2, and a current pulse I is provided at the beginning of each off-phase T1GOver the entire time period t of the on-state of the deviceONDuring this time, the current flowing from the
Fig. 2 shows that the on-phase T2 has a longer duration than the off-phase T1. The exact ratio of the off-phase T1 and the on-phase T2 can be optimized for maximum benefit. In general, the best performance can be obtained by making the off-phase T1 as short as possible, but long enough to establish a high level of conductivity modulation in the N-
It should be understood that the N-
By using a low defect density silicon structure as the material of the N-
For example, the duration of the off-phase T1 may be from nanoseconds to microseconds. It has been found that there is a minimum duration of the off-phase T1 in order to allow the bipolar conductive structure to conduct, thereby fully modulating the conductivity of the N-
Fig. 2 shows the duration t of the on-state of the
Conductivity modulation is also used for bipolar power devices, such as IGBTs. However, the
The
Fig. 3 schematically shows a cross-section of a
In the
The N +
As with
Similar to
During the on-state of
In particular, when the
When
By providing the N +
During the off state of
The
Fig. 3 shows a second cell of
Each of the
Fig. 4 schematically shows a cross-section of a
The
Similar to
The N +
As shown in fig. 4,
Similar to
During the on-state of the
During the off state of
When the
Fig. 5 schematically shows a cross-section of a
Similar to
Similar to
The operation of
Similar to the
Each of the
It should be understood that although planar MOSFET structures with horizontal channels are used as unipolar conductive structures in the
It should also be understood that although a thyristor-like structure is used as the bipolar conducting structure in the device, other structures, such as BJTs, may also be used.
It should be understood that although each of the
In addition, the unipolar conduction structure within device 100-400 uses electrons to conduct current. It should be understood that a unipolar conductive structure may alternatively use holes to conduct current. However, the mobility of the holes is lower than that of the electrons, and the resistivity of the first conduction path provided by the hole-based unipolar conduction structure may be higher than that provided by the electron-based unipolar conduction structure.
It should be understood that all of the doping polarities described above may be reversed and the resulting device still conform to the present invention. In the present invention, the n-type doping polarity is generally referred to as a first conductivity type, and the p-type doping polarity is referred to as a second conductivity type. However, the skilled person will be able to invert them to form the appropriate devices. The invention also covers all devices formed with reversed doping polarities. Furthermore, it should be understood that the terminals and associated contact regions of the device may be arranged out-of-plane or otherwise aligned such that the direction of the carriers is not exactly as described above, and the resulting device still conforms to the present invention.
It will be appreciated by those skilled in the art that in the foregoing description and appended claims, positional terms such as "top", "bottom", "above", "overlapping", "below", "side", "vertical", and the like, refer to conceptual illustrations of semiconductor devices, such as those shown in standard cross-sectional perspective views and the accompanying drawings. These terms are used for ease of reference, but are not limiting. Accordingly, these terms should be understood to refer to the transistor when in the orientation as shown in the drawings.
While the present invention has been described in terms of the preferred embodiments described above, it should be understood that these embodiments are illustrative only, and the claims are not limited to those embodiments. In view of the present disclosure, those skilled in the art will be able to make modifications and substitutions that are considered to be within the scope of the appended claims. Each feature disclosed or illustrated in this specification, either individually or in any appropriate combination with any other feature disclosed or illustrated herein, may be incorporated in the invention.
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