阅读说明：本技术 半导体装置及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 洪瑟气 全辉璨 金贤洙 安大哲 梁明 于 2019-03-12 设计创作，主要内容包括：提供半导体装置及其制造方法,所述半导体装置包括：基底,包括第一区域和第二区域；有源栅极结构,位于第一区域中的基底上；虚设栅极结构,位于第二区域中的基底上；源极/漏极,在有源栅极结构的相对侧中的每个处位于第一区域中的基底上；多个第一导电接触件,分别连接到有源栅极结构和源极/漏极；电阻结构,位于第二区域中的虚设栅极结构上；多个第二导电接触件,分别连接到所述多个第一导电接触件和电阻结构；蚀刻停止层,位于虚设栅极结构与电阻结构之间。蚀刻停止层包括由不同的材料形成的下蚀刻停止层和上蚀刻停止层。(A semiconductor device and a method of manufacturing the same are provided, the semiconductor device including a substrate including an th region and a second region, an active gate structure on the substrate in the th region, a dummy gate structure on the substrate in the second region, source/drains on the substrate in the th region at each of opposite sides of the active gate structure, a plurality of th conductive contacts connected to the active gate structure and the source/drains, respectively, a resistance structure on the dummy gate structure in the second region, a plurality of second conductive contacts connected to the plurality of th conductive contacts and the resistance structure, respectively, an etch stop layer between the dummy gate structure and the resistance structure, the etch stop layer including a lower etch stop layer and an upper etch stop layer formed of different materials.)

1, kinds of semiconductor devices, the semiconductor device comprising:

a substrate comprising a th region and a second region;

an active gate structure on the substrate in the th region;

a dummy gate structure on the substrate in the second region;

source/drain electrodes on the substrate in the th region at each of opposite sides of the active gate structure;

a plurality of th conductive contacts connected to the active gate structure and the source/drain, respectively;

a resistor structure on the dummy gate structure in the second region;

a plurality of second conductive contacts connected to the plurality of th conductive contacts and the resistive structure, respectively;

and the etching stop layer is positioned between the dummy gate structure and the resistance structure and comprises a lower etching stop layer and an upper etching stop layer, and the material of the lower etching stop layer is different from that of the upper etching stop layer.

2. The semiconductor device according to claim 1,

the material of the lower etch stop layer has a wet etch selectivity with respect to the material of the plurality of th conductive contacts, and

the material of the upper etch stop layer has a dry etch selectivity with respect to the material of the lower etch stop layer.

3. The semiconductor device according to claim 1,

the plurality of second conductive contacts contacting the etch stop layer include sidewalls having a convex portion and a tapered portion,

the lower etch stop layer contacts the raised portions of the sidewalls of the plurality of second conductive contacts, and

the upper etch stop layer contacts the tapered portions of the sidewalls of the plurality of second conductive contacts.

4. The semiconductor device of claim 1, wherein the etch stop layer further comprises a passivation layer between the lower etch stop layer and the upper etch stop layer.

5. The semiconductor device according to claim 4,

the lower etch stop layer comprises a metal nitride,

the passivation layer comprises silicon oxide, and

the upper etch stop layer comprises silicon nitride.

6. The semiconductor device according to claim 1,

the top surfaces of the plurality of th conductive contacts are at the same level as the top surface of the active gate structure, and

the bottom surface of the resistive structure is at a level higher than a level of the top surfaces of the plurality of th conductive contacts.

7. The semiconductor device according to claim 1,

the resistor structure includes an insulating pattern and a resistor element pattern, and

the resistive element pattern is on the insulating pattern.

8. The semiconductor device according to claim 7,

the bottom surface of the lower etch stop layer contacts the top surface of the dummy gate structure, and

the top surface of the upper etch stop layer contacts the bottom surface of the insulating pattern.

9. The semiconductor device of claim 1, wherein bottom surfaces of the plurality of second conductive contacts on the plurality of th conductive contacts are located at different levels than bottom surfaces of the plurality of second conductive contacts on the resistive structure.

10. The semiconductor device of claim 1, wherein bottom surfaces of the plurality of second conductive contacts on the plurality of th conductive contacts are at the same level as bottom surfaces of the plurality of second conductive contacts on the resistive structure.

11, kinds of semiconductor devices, the semiconductor device comprising:

a fin region protruding from the substrate;

a gate structure intersecting the fin region, the gate structure covering a top surface and opposing sidewalls of the fin region;

a source/drain in the fin region at each of opposite sides of the gate structure;

a source/drain contact connected to the source/drain;

a gate contact connected to the gate structure;

an etch stop layer on the gate structure, the etch stop layer including a lower etch stop layer, a passivation layer, and an upper etch stop layer sequentially stacked on one another;

the resistance structure is positioned on the etching stop layer;

a plurality of merged contacts connected to the source/drain contacts or the gate contact, respectively; and

a resistive contact connected to the resistive structure.

12. The semiconductor device of claim 11, wherein the plurality of merged contacts pass through an etch stop layer.

13. The semiconductor device according to claim 12,

the plurality of merged contacts that contact the etch stop layer include sidewalls having a convex portion and a tapered portion,

the lower etch stop layer contacts the raised portions of the sidewalls of the plurality of merged contacts, and

the upper etch stop layer contacts the tapered portion of the sidewall of the plurality of merged contacts.

14. The semiconductor device according to claim 11,

the resistive structure includes an insulating pattern and a resistive element pattern,

the insulating pattern is on the etch stop layer, and

the sidewalls of the insulating pattern and the sidewalls of the resistive element pattern are located on the same plane.

15. The semiconductor device according to claim 11,

the top surfaces of the source/drain contacts, the top surface of the gate contact and the top surface of the gate structure are located at the same level,

the bottom surface of the resistive structure is at a level higher than the level of the top surface of the source/drain contact and the top surface of the gate contact, and

the top surfaces of the plurality of merged contacts and the top surface of the resistive contact are at the same level.

16, a method of manufacturing a semiconductor device, the method comprising:

forming an active gate structure and a dummy gate structure on the substrate, the substrate including an th region and a second region, the active gate structure being formed on the substrate in the th region, the dummy gate structure being formed on the substrate in the second region;

forming source/drains on the substrate in the th region at each of opposite sides of the active gate structure;

forming an interlayer insulating film on the substrate, the interlayer insulating film covering the sidewalls of the active gate structures and the sidewalls of the dummy gate structures, and the interlayer insulating film exposing the top surfaces of the active gate structures and the dummy gate structures;

forming a plurality of th conductive contacts connected to the active gate structure and the source/drain, respectively;

forming an etch stop layer on the lower interlayer insulating film and the plurality of th conductive contacts, the etch stop layer including a lower etch stop layer and an upper etch stop layer;

forming a resistive structure on the etch stop layer in the second region;

forming an upper interlayer insulating film covering the etch stop layer and the resistive structure;

forming a plurality of second conductive contacts connected to the plurality of th conductive contacts while passing through the upper interlayer insulating film and the etch stop layer, and

a plurality of second conductive contacts connected to the resistive structure while passing through the upper interlayer insulating film are formed.

17. The method of claim 16, wherein forming the plurality of second conductive contacts connected to the plurality of -th conductive contacts comprises:

exposing the upper etch stop layer by patterning the upper interlayer insulating film to provide an exposed portion of the upper etch stop layer;

etching the exposed portion of the upper etch stop layer to provide an exposed portion of the lower etch stop layer;

etching the exposed portions of the lower etch stop layer to provide exposed portions of the plurality of th conductive contacts, and

forming the plurality of second conductive contacts connected to the exposed portions of the plurality of th conductive contacts.

18. The method of claim 17, wherein,

the step of etching the exposed portion of the upper etch stop layer is performed by anisotropic etching, and

the step of etching the exposed portion of the lower etch stop layer is performed by isotropic etching.

19. The method of claim 18, wherein,

the step of forming the plurality of second conductive contacts connected to the plurality of th conductive contacts includes forming holes through an etch stop layer over the plurality of th conductive contacts,

the step of forming an aperture through the etch stop layer comprises etching the exposed portion of the upper etch stop layer and etching the exposed portion of the lower etch stop layer,

the sidewall of the upper etch stop layer has a tapered shape in the hole through the etch stop layer, and

the sidewalls of the lower etch stop layer have a concave shape in the hole through the etch stop layer.

20. The method of claim 16, wherein the etch stop layer further comprises a passivation layer between the lower etch stop layer and the upper etch stop layer.

21. The method of claim 20, wherein forming an etch stop layer comprises:

forming a lower etch stop layer on the lower interlayer insulating film and the plurality of th conductive contacts, the lower etch stop layer including a metal nitride;

forming a passivation layer on the lower etch stop layer, the passivation layer including silicon oxide; and

an upper etch stop layer is formed on the passivation layer, the upper etch stop layer comprising silicon nitride.

22. The method of claim 16, wherein the step of forming the plurality of -th conductive contacts comprises:

planarizing top surfaces of the lower interlayer insulating film, the active gate structure, the dummy gate structure, and the plurality of th conductive contacts such that the top surfaces of the lower interlayer insulating film, the active gate structure, the dummy gate structure, and the plurality of th conductive contacts are located at the same level.

23. The method of claim 16, wherein forming the plurality of second conductive contacts comprises:

forming the plurality of second conductive contacts such that bottom surfaces of the plurality of second conductive contacts connected to the plurality of th conductive contacts and bottom surfaces of the plurality of second conductive contacts connected to the resistive structure are located at different levels.

24. The method of claim 16, wherein the step of forming a resistive structure comprises:

forming an initial insulating layer on the etch stop layer;

forming an initial resistive element layer on the initial insulating layer; and

the initial insulating layer and the initial resistive element layer are patterned to form an insulating pattern and a resistive element pattern, the resistive element pattern being on the insulating pattern.

25. The method of claim 24, wherein,

a bottom surface of the insulating pattern is located at a level higher than a level of top surfaces of the plurality of th conductive contacts, and

a bottom surface of the resistive element pattern is located at a level higher than a level of bottom surfaces of the plurality of second conductive contacts.

Technical Field

The present inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a resistive element and a method of manufacturing the same.

Background

In order to increase the degree of integration of semiconductor devices per unit area, the size of semiconductor devices and the distance between semiconductor devices are reduced, thereby increasing the density of semiconductor devices.

Disclosure of Invention

The inventive concept provides semiconductor devices including a resistance element capable of improving electrical characteristics and simplifying a manufacturing process to reduce process difficulty.

The inventive concept also provides methods of manufacturing a semiconductor device including a resistance element capable of improving electrical characteristics and simplifying a manufacturing process to reduce process difficulty.

Other aspects of the inventive concept are not limited thereto and will be clearly understood by those skilled in the art from the following description.

According to aspects of the inventive concept, a semiconductor device includes a substrate including a th region and a second region, an active gate structure on the substrate in the th region, a dummy gate structure on the substrate in the second region, source/drains on the substrate in the th region at opposite sides of the active gate structure, a plurality of conductive contacts connected to the active gate structure and the source/drains, respectively, a resistive structure on the dummy gate structure in the second region, a plurality of second conductive contacts connected to the plurality of conductive contacts and the resistive structure, respectively, and an etch stop layer between the dummy gate structure and the resistive structure.

According to another aspect of the inventive concept, a semiconductor device includes a fin region protruding from a substrate, a gate structure intersecting the fin region, the gate structure covering a top surface and opposing sidewalls of the fin region, source/drains in the fin region at opposing sides of the gate structure, source/drain contacts connected to the source/drains, a gate contact connected to the gate structure, an etch stop layer on the gate structure, a resistive structure on the etch stop layer, a plurality of merged contacts connected to the source/drain contacts or the gate contact, respectively, and a resistive contact connected to the resistive structure.

According to another aspect of the inventive concept, a method of manufacturing a semiconductor device includes forming an active gate structure and a dummy gate structure on a substrate, the substrate including a th region and a second region, the active gate structure being formed on the substrate in the th region, the dummy gate structure being formed on the substrate in the second region, forming source/drains on the substrate in the th region at opposite sides of the active gate structure, forming an underlying interlayer insulating film on the substrate, the underlying interlayer insulating film covering sidewalls of the active gate structure and covering sidewalls of the dummy gate structure, and the underlying interlayer insulating film exposing a top surface of the active gate structure and a top surface of the dummy gate structure, forming a plurality of conductive contacts connected to the active gate structure and the source/drains, respectively, forming an etch stop layer on the underlying interlayer insulating film and the plurality of conductive contacts, the etch stop layer including a lower etch stop layer and an upper etch stop layer, forming a resistive structure on the etch stop layer in the second region, forming an upper interlayer insulating film covering the etch stop layer and the plurality of conductive contacts, and forming a plurality of conductive contacts connected to the second interlayer insulating film and the plurality of conductive contacts simultaneously through the plurality of the second conductive contacts, and forming a plurality of the etch stop layer .

Drawings

Embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a plan view of a layout of a semiconductor apparatus according to an embodiment of the inventive concept;

FIG. 2A is a sectional view taken along line A-A 'of FIG. 1, FIG. 2B is a sectional view taken along line B-B' of FIG. 1, FIG. 2C is a sectional view taken along line C-C 'of FIG. 1, and FIG. 2D is a sectional view taken along line D-D' of FIG. 1;

FIG. 3 is an enlarged view of region III of FIG. 2A;

fig. 4 is a sectional view taken along line C-C' of fig. 1 for explaining a modified example of the second conductive contact;

fig. 5 is a cross-sectional view taken along line C-C' of fig. 1 to explain another modified example of the second conductive contact;

fig. 6 is a cross-sectional view taken along line C-C' of fig. 1 for explaining a modified example of the resistance structure;

fig. 7A to 7C are diagrams showing a modified example of the etching stopper layer, in which fig. 7A is a sectional view taken along line a-a ' of fig. 1, fig. 7B is a sectional view taken along line B-B ' of fig. 1, and fig. 7C is a sectional view taken along line C-C ' of fig. 1;

fig. 8 is a plan view corresponding to the second region of fig. 1, and fig. 9 is a sectional view taken along line E-E' of fig. 8;

fig. 10A to 19C are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept in process order, in which fig. 10A, 11A, … …, and 19A are sectional views taken along line a-a ' of fig. 1, fig. 10B, 11B, … …, and 19B are sectional views taken along line B-B ' of fig. 1, and fig. 10C, 11C, … …, and 19C are sectional views taken along line C-C ' of fig. 1; and

fig. 20 is an enlarged view of the region XX of fig. 18A.

Detailed Description

Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

Fig. 1 is a plan view of a layout of a semiconductor apparatus 10 according to an embodiment of the inventive concept.

Referring to fig. 1, a substrate 100 including an th region R1 and a second region R2 may be provided an active gate structure AGS may be disposed on the substrate 100 in the th region R1 and a dummy gate structure DGS may be disposed on the substrate 100 in the second region R2.

In an embodiment of the inventive concept, the semiconductor device 10 may include resistance structures RS on the substrate 100 in the second region R2, the resistance structures RS being kinds of passive elements on the dummy gate structure DGS.

The resistive structure RS may be provided, for example, in the form of a flat plate having a long axis in the th direction X or in the second direction Y perpendicular to the th direction X, however, the shape of the resistive structure RS is not limited thereto.

At least resistive contacts CR can be electrically connected to the resistive structure RS. can provide the resistive contacts CR for electrical connection between the resistive structure RS and the interlayer wiring.

The dummy gate structures DGS may be in the form of lines extending in the second direction Y, and a plurality of the dummy gate structures DGS may be spaced apart from each other in the th direction X, the dummy gate structures DGS may be arranged to reduce a pattern density difference between the th region R1 in which the memory cells or logic circuits are formed and the second region R2 in which the resistance structures RS are formed in some embodiments, the dummy gate structures DGS may not be arranged under the portions of the resistance contacts CR.

In embodiments, the active pattern AP may be disposed between the substrate 100 and the dummy gate structure DGS, the active pattern AP may be in the form of a line extending in the th direction X, and a plurality of the active patterns AP may be spaced apart from each other in the second direction Y.

Fig. 2A is a sectional view taken along line a-a' of fig. 1. Fig. 2B is a sectional view taken along line B-B' of fig. 1. Fig. 2C is a sectional view taken along line C-C' of fig. 1. Fig. 2D is a sectional view taken along line D-D' of fig. 1.

Referring to fig. 1 and 2A to 2D, a semiconductor apparatus 10 according to an embodiment of the inventive concept may include a resistance structure RS on the dummy gate structure DGS on the substrate 100 in the second region R2.

In embodiments, substrate 100 may comprise a silicon (Si) semiconductor or a germanium (Ge) semiconductor or a compound semiconductor such as a SiGe, SiC, GaAs, InAs, or InP semiconductor, in other embodiments, substrate 100 may have a silicon-on-insulator (SOI) structure and conductive regions such as impurity doped wells or structures.

The th region R1 may be a portion of a logic cell region where a logic transistor of a logic circuit of the semiconductor device 10 is formed or a portion of a memory cell region where a plurality of memory cells are formed to store data, for example, the th region R1 may include a pMOSFET region PR or an nMOSFET region NR, the pMOSFET region PR may be an active region where a p-type transistor is disposed, the nMOSFET region NR may be an active region where an n-type transistor is disposed, in some embodiments, the plurality of pMOSFET regions PR and the plurality of nMOSFET regions NR may be disposed in the second direction Y.

The second region R2 may be a region where passive elements are formed. In the semiconductor apparatus 10 according to an embodiment of the inventive concept, the passive element may be a resistive structure RS. That is, the second region R2 may be a resistance region included in the integrated circuit of the semiconductor apparatus 10.

The th active pattern AP1 and the second active pattern AP2 may be disposed on the substrate 100.

In detail, the th active pattern AP1 may be disposed in an active region of the th region R1. the th active pattern AP1 may be spaced apart from each other in the second direction Y and may be in the form of a line extending in the th direction X. the th active pattern AP1 may be disposed to be spaced apart from each other by substantially the same distance in an active region of the th region R1. the th active pattern AP1 may protrude in a third direction Z perpendicular to the top surface of the substrate 100. the th active pattern AP1 may be a portion of the substrate 100 or may be an epitaxial layer formed on the substrate 100.

The second active patterns AP2 may be disposed on the substrate 100 in the second region R2 the second active patterns AP2 may be disposed in the second direction Y and may be in the form of lines extending in the direction X the second active patterns AP2 may be disposed to be spaced apart from each other by substantially the same distance on the substrate 100 in the second region R2 the second active patterns AP2 may protrude in a third direction Z perpendicular to the top surface of the substrate 100 the second active patterns AP2 may be a portion of the substrate 100 or may be an epitaxial layer formed on the substrate 100.

The separation pattern ST may be disposed on the substrate 100 the separation pattern ST may include th and second separation patterns ST1 and ST2 located in the th region R1 and a third separation pattern ST3 located in the second region R2.

The th separation pattern ST1 may be disposed between the nMOSFET region NR and the pMOSFET region PR, thereby separating the nMOSFET region NR from the pMOSFET region PR.

The second separation pattern ST2 may be disposed at an opposite side of the active pattern AP1, and an upper portion of the active pattern AP1 may be exposed by the second separation pattern ST2 the exposed upper portion of the active pattern AP1 may be defined as the th active fin af1, that is, the th active fin AF1 may be in the form of a fin protruding between the second separation patterns ST 2.

The third separation pattern ST3 may be disposed at the opposite side of the second active pattern AP2, and an upper portion of the second active pattern AP2 may be exposed by the third separation pattern ST 3. The exposed upper portion of the second active pattern AP2 may be defined as a second active fin AF2, and may be in the form of a fin protruding between the third separation patterns ST 3.

The th, second, and third separation patterns ST1, ST2, and ST3 may be connected to each other, that is, may be substantially a portion of the insulating film the th, second, and third separation patterns ST1, ST2, and ST3 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

In embodiments, the thickness of the separation pattern ST1 may be greater than the thicknesses of the second and third separation patterns ST2 and ST3, that is, the top surfaces of the th, second and third separation patterns ST1, ST2 and ST3 may be located at substantially the same level, and the bottom surface of the th separation pattern ST1 may be located at a lower level than the levels of the second and third separation patterns ST2 and ST3, in this case, the th separation pattern ST1 may be formed by a process separate from the second and third separation patterns ST2 and ST3, but the embodiment is not limited thereto.

The active gate structures AGS may be disposed on the substrate 100 in the th region R1 and extend in the second direction Y while crossing the th active pattern AP1 the dummy gate structures DGS may be disposed on the substrate 100 in the second region R2 and extend in the second direction Y while crossing the second active pattern AP 2.

The active gate structures AGS may cross the th active pattern AP1 and cover the top surface and sidewalls of the th active fin AF1 in some embodiments, the active gate structures AGS may extend in the second direction Y and cross both the nMOSFET region NR and the pMOSFET region PR, but the embodiment is not limited thereto.

Each of the plurality of active gate structures AGS may include a gate insulation layer GD, a gate electrode GE, and a gate capping layer GC the gate insulation layer GD may include, for example, silicon oxide, silicon oxynitride, or a high-K dielectric film having a dielectric constant higher than that of silicon oxide, the gate electrode GE may include, for example, at least of conductive metal nitrides (such as titanium nitride and tantalum nitride) and metals (such as aluminum and tungsten), the gate capping layer GC may include, for example, at least of silicon oxide, silicon nitride, and silicon oxynitride.

The gate spacer SP may be disposed on a sidewall of the active gate structure AGS the gate spacer SP may include at least of silicon oxide, silicon nitride, and silicon oxynitride in embodiments, the gate insulation layer GD may extend between the gate electrode GE and the gate spacer SP.

An th active fin AF1 located below the active gate structure AGS and overlapping the active gate structure AGS in a plan view may be defined as the channel CH.

The dummy gate structures DGS may extend in the second direction Y and cross the second active patterns AP2, that is, the dummy gate structures DGS may cover the top surface and the sidewalls of the second active fins AF 2.

The plurality of dummy gate structures DGS may have the same structural features as the active gate structures AGS. For example, each of the plurality of dummy gate structures DGS may include a dummy insulating layer DD, a dummy gate electrode DE, and a dummy capping layer DC sequentially stacked on the substrate 100 in the second region R2. The dummy insulating layer DD may be formed of the same material as the gate insulating layer GD in the same manner as the gate insulating layer GD. The dummy gate electrode DE may be formed of the same material as the gate electrode GE in the same manner as the gate electrode GE. The dummy capping layer DC may be formed of the same material and in the same manner as the gate capping layer GC. The gate spacers SP may be disposed on sidewalls of the dummy gate structure DGS.

The source/drain SD may be disposed on the th active pattern AP1 at the opposite side of the active gate structure AGS in embodiments, as shown in the drawing, the source/drain SD may be an epitaxial layer grown from the th active pattern AP1 as a seed.

In this case, the source/drain SD in the pMOSFET region PR may be configured to apply a compressive strain to the channel CH and the source/drain SD in the nMOSFET region NR may be configured to apply a tensile strain to the channel CH in embodiments, the source/drain SD in the pMOSFET region PR may comprise silicon germanium (SiGe) and the source/drain SD in the nMOSFET region NR may comprise silicon (Si) or silicon carbide (SiC).

Unlike what is shown in the drawings, the source/drain SD may be an impurity region disposed in each of th active fin AF1 at opposite sides of active gate structure AGS, the source/drain SD in pMOSFET region PR may be a p-type impurity region, and the source/drain SD in nMOSFET region NR may be an n-type impurity region, the active gate structure AGS and the source/drain SD may form a transistor in -th region R1.

The lower interlayer insulating film 110 covering the sidewalls of the gate spacers SP and the source/drain electrodes SD may be disposed on the substrate 100. the lower interlayer insulating film 110 may expose the top surfaces of the active gate structures AGS and the dummy gate structures DGS, i.e., the top surfaces of the gate caps GC and the top surfaces of the dummy caps DC. for example, the top surface of the lower interlayer insulating film 110 in the -th region R1 may be located at the same level as the top surface of the active gate structures AGS, and the top surface R2 of the lower interlayer insulating film 110 in the second region R2 may be located at the same level as the top surface of the dummy gate structures DGS.

An upper interlayer insulating film 120 covering the top surfaces of the active gate structures AGS and the dummy gate structures DGS may be disposed on the lower interlayer insulating film 110 each of the lower interlayer insulating film 110 and the upper interlayer insulating film 120 may include at least of silicon oxide and silicon oxynitride.

A source/drain contact CA passing through the lower interlayer insulating film 110 and electrically connected to the source/drain SD may be disposed at the opposite side of the active gate structure AGS the source/drain contact CA may be referred to as an th conductive contact C1.

The source/drain contacts CA may be connected to the source/drains SD, or may be commonly connected to the plurality of source/drains SD. the source/drain contacts CA may be in the form of a bar extending in the second direction Y in plan view.

The source/drain contacts CA may comprise at least of a semiconductor material such as doped polysilicon, metal nitrides such as titanium nitride, tungsten nitride and tantalum nitride, and metals such as tungsten, titanium, tantalum and cobalt although not shown, a metal silicide may be disposed between each source/drain contact CA and each source/drain SD.

A gate contact CB electrically connected to the gate electrode GE may be disposed on each of the active gate structures AGS the gate contact CB may be referred to as an th conductive contact C1.

The gate contact CB, which may pass through the gate capping layer GC and be connected to the gate electrode GE. as shown in the drawing, may be disposed on the th separation pattern ST1, but is not limited thereto.

In embodiments, the top surface of the source/drain contact CA and the top surface of the gate contact CB may be located at substantially the same level as the top surface of the lower interlayer insulating film 110 in the region R1.

The etch stop layer ESL may be disposed on the lower interlayer insulating film 110, and the upper interlayer insulating film 120 may be disposed on the etch stop layer ESL. The upper interlayer insulating film 120 may include silicon oxide, silicon oxynitride, silicon nitride, or a low-K dielectric film having a dielectric constant lower than that of silicon oxide. The etch stop layer ESL will be described in detail below.

The plurality of merged contacts CM passing through the upper interlayer insulating film 120 and the etch stop layer ESL may be disposed in the th region R1 the plurality of merged contacts CM may be referred to as a plurality of second conductive contacts C2. the plurality of merged contacts CM may include at least of a semiconductor material such as doped polysilicon, a metal nitride such as titanium nitride, tungsten nitride, and tantalum nitride, and a metal such as tungsten, titanium, tantalum, and cobalt.

The th wiring Ma and the second wiring Mb may be provided on the upper interlayer insulating film 120 in the th region R1 in the drawing, the second wiring Mb extending forward/backward in the th direction X (X-axis direction) and the th wiring Ma extending forward/backward in the second direction Y (Y-axis direction) are indicated by broken lines.

In embodiments, the 0 th wiring Ma may be electrically connected to source/drain contacts CA via merge contacts CM passing through the upper interlayer insulating film 120 and the etch stop layer ESL in the 1 st region R1 the second wiring Mb may be electrically connected to the gate contacts CB. via merge contacts CM passing through the upper interlayer insulating film 120 and the etch stop layer ESL in the st region R1 so that the th wiring Ma may be electrically connected to source/drain SDs via the merge contacts CM and the source/drain contacts CA, and the second wiring Mb may be electrically connected to gate electrodes GE. th th wiring Ma and the second wiring Mb may include a metal material such as aluminum or copper.

In the semiconductor device 10 according to the embodiment of the inventive concept, the resistance structure RS may be disposed on the etch stop layer ESL in the second region R2 the resistance structure RS is disposed in the upper interlayer insulating film 120 in the second region R2 in embodiments, the resistance structure RS may have a rectangular planar shape having a long axis in a direction (i.e., -direction X) along which the second active pattern AP2 extends, but is not limited thereto.

The resistive structure RS may include a resistive pattern (or resistive element pattern) RP and an insulating pattern DP. the resistive pattern RP may include a metal or a metal compound in embodiments the resistive pattern RP may include a metal material such as tungsten, titanium, or tantalum in other embodiments the resistive pattern RP may include titanium nitride in which case the resistive pattern RP may have a lower specific resistance than when formed of metal alone and thus the resistive pattern RP may have a small thickness.

The insulation pattern DP may be disposed between the resistance pattern RP and the etch stop layer ESL, the insulation pattern DP may have substantially the same planar shape as that of the resistance pattern RP, the insulation pattern DP may include, for example, silicon oxide, the sequentially stacked insulation pattern DP and the resistance pattern RP may be defined as the resistance structure RS. in other embodiments, the bottom surface of the insulation pattern DP. resistance structure RS may be at a higher level than that of the top surface of the conductive contact C1.

The resistance contact CR may be disposed in the second region R2. The resistive contact CR may be referred to as a second conductive contact C2.

The resistance contacts CR may electrically connect the third wirings Mc on the upper interlayer insulating film 120 in the second region R2 with the resistance structure RS, the resistance contacts CR may be disposed in the upper interlayer insulating film 120 in the second region R2 to be electrically connected to the resistance structure RS, the third wirings Mc may be electrically connected to the resistance structure RS. via the resistance contacts CR in some embodiments, a plurality of the resistance contacts CR may be disposed on the resistance structure RS, the plurality of the resistance contacts CR on the resistance structure RS may be commonly connected to the third wirings Mc. of the resistance contacts CR may include the same material as the merge contact CM described above, the third wirings Mc may include the same material as the material of the wiring Ma and the second wiring Mb described above.

In embodiments , the ohmic contact CR may be configured to pass through the resistive pattern RP., that is, the ohmic contact CR may reach the insulating pattern DP. while passing through the upper interlayer insulating film 120 and the resistive pattern RP so that a sidewall of the ohmic contact CR may be in direct contact with the resistive pattern RP.

In embodiments, the resistive contact hole CRH provided with the resistive contact CR may be formed simultaneously with the plurality of merged contact holes CMH provided with the plurality of merged contacts CM the bottom surface of the resistive contact CR may be at a level higher than the level of the bottom surfaces of the plurality of merged contacts CM.

The etch stop layer ESL may be disposed on the lower interlayer insulating film 110, and the upper interlayer insulating film 120 may be disposed on the etch stop layer ESL. Further, the etch stop layer ESL may be disposed between the dummy gate structure DGS and the resistance structure RS in the second region R2.

The etch stop layer ESL may have a multi-layer structure in which a lower etch stop layer L1, a passivation layer LP, and an upper etch stop layer L2 are sequentially stacked, the lower etch stop layer L1, the passivation layer LP, and the upper etch stop layer L2 may be formed of different materials, in embodiments, the lower etch stop layer L1 may be formed of, for example, a metal nitride such as aluminum nitride, the passivation layer LP may be formed of, for example, silicon oxide, and the upper etch stop layer L2 may be formed of, for example, silicon nitride.

Generally, in an interconnect including a th conductive contact (source/drain contact and gate contact) and a second conductive contact (merged contact and resistive contact), the top surface of the th conductive contact may be damaged, and thus, an interface failure may occur when a single layer etch stop layer is formed under the resistive structure, for example, in a patterning process for forming the second conductive contact, a dry etching process may damage the top surface of the metal material of the th conductive contact due to dispersion of the dry etching process and dispersion of the thickness of the etch stop layer.

To limit and/or prevent such damage, the semiconductor device 10 according to an embodiment of the inventive concept includes an etch stop layer esl having a multi-layered structure under the resistance structure RS, the upper etch stop layer L2 limits and/or prevents a contact hole from being recessed downward due to over-etching during a dry etching process for forming the plurality of second conductive contacts C2, the upper etch stop layer L2 may also limit and/or prevent an occurrence of a recess phenomenon in a cleaning process performed to remove etching byproducts generated in the dry etching process, the lower etch stop layer L7 may be formed of a material that is easily removable by wet etching, so that a wet etching process may be performed to expose top surfaces of the plurality of conductive contacts C1 instead of performing the dry etching process.

The passivation layer LP may protect the lower etch stop layer L1 and limit and/or prevent the occurrence of side effects of oxidizing the lower etch stop layer L1, thus enhancing resistance to wet etching.

Accordingly, in the semiconductor device 10 according to the embodiment of the inventive concept, it is possible to limit and/or prevent the occurrence of the interface failure between the plurality of th conductive contacts C1 and the plurality of second conductive contacts C2 by forming the etch stop layer ESL having a multi-layer structure under the resistance structure RS, thereby improving the electrical characteristics and the production efficiency.

Fig. 3 is an enlarged view of a region III of fig. 2A.

Referring to fig. 3, a sidewall of the second conductive contact C2 contacting the lower etch stop layer L1 may have a convex shape, and a sidewall of the second conductive contact C2 contacting the passivation layer LP and the upper etch stop layer L2 may have a tapered shape.

In the semiconductor device 10 according to an embodiment of the inventive concept, the material of the lower etch stop layer L1 may have a wet etch selectivity with respect to the material of the plurality of conductive contacts C1, and the material of the upper etch stop layer L2 may have a dry etch selectivity with respect to the material of the lower etch stop layer L1, the material of the passivation layer LP may limit and/or prevent oxidation of the lower etch stop layer L1.

The lower etch stop layer L1 may be formed of, for example, a metal nitride such as aluminum nitride, the passivation layer LP may be formed of, for example, silicon oxide, and the upper etch stop layer L2 may be formed of, for example, silicon nitride. That is, in order to satisfy different etch selectivity, the lower etch stop layer L1, the passivation layer LP, and the upper etch stop layer L2 of the etch stop layer ESL may be formed of different materials.

As will be described below, the passivation layer LP and the upper etch stop layer L2 are patterned by dry etching of anisotropic etching, and thus the sidewall of the second conductive contact C2, which is in contact with the passivation layer LP and the upper etch stop layer L2, may have a tapered shape. In contrast, the lower etch stop layer L1 is patterned by wet etching of isotropic etching, and thus the sidewall of the second conductive contact C2 contacting the lower etch stop layer L1 may have a convex shape.

Fig. 4 is a sectional view taken along line C-C' of fig. 1 for explaining a modified example of the second conductive contact.

Referring to fig. 4, in a semiconductor device 20 according to another embodiment of the inventive concept, a bottom surface of the resistive contact CR, which is in contact with the resistive structure RS, may be formed to be in contact with a top surface of the resistive pattern RP.

The components of the semiconductor device 20 and the materials thereof are substantially the same as those of the semiconductor device described above with reference to fig. 1 to 2D, and therefore, the following description will focus on differences from fig. 1 to 2D.

The resistance contact CR may be configured to contact the resistance pattern RP while not passing through the resistance structure RS. That is, the resistance contact CR may pass through the upper interlayer insulating film 120 and then reach the resistance pattern RP. Accordingly, the sidewall of the ohmic contact CR may be in direct contact with the upper interlayer insulating film 120, and the bottom surface of the ohmic contact CR may be in direct contact with the top surface of the resistive pattern RP.

Fig. 5 is a cross-sectional view taken along line C-C' of fig. 1 to explain another modified example of the second conductive contact.

Referring to fig. 5, in a semiconductor device 30 according to another embodiment of the inventive concept, a bottom surface of the ohmic contact CR may be formed to be in contact with a top surface of the lower interlayer insulating film 110.

The components of the semiconductor device 30 and the materials thereof are substantially the same as those of the semiconductor device described above with reference to fig. 1 to 2D, and therefore, the following description will focus on the differences from fig. 1 to 2D.

The resistive contact CR may be configured to pass through the resistive structure RS. That is, the resistive contact CR may pass through the upper interlayer insulating film 120, the resistive structure RS, and the etch stop layer ESL, and then reach the lower interlayer insulating film 110. Accordingly, the sidewall of the ohmic contact CR may be in direct contact with the upper interlayer insulating film 120, the resistive structure RS, and the etch stop layer ESL, and the bottom surface of the ohmic contact CR may be in direct contact with the top surface of the lower interlayer insulating film 110. Therefore, the bottom surface of the merged contact CM (see fig. 2A) may be located at substantially the same level as the bottom surface of the resistance contact CR.

Fig. 6 is a sectional view taken along line C-C' of fig. 1 for explaining a modified example of the resistance structure.

Referring to fig. 6, in a semiconductor device 40 according to another embodiment of the inventive concept, a hard mask pattern HP may be disposed on a resistance pattern RP.

The components of the semiconductor device 40 and the materials thereof are substantially the same as those of the semiconductor device described above with reference to fig. 1 to 2D, and therefore, the following description will focus on differences from fig. 1 to 2D.

The resistance structure RS may include an insulation pattern DP, a resistance pattern RP, and a hard mask pattern HP, which are sequentially stacked. The insulation pattern DP and the hard mask pattern HP may have substantially the same planar shape as that of the resistance pattern RP. That is, the sidewalls of the insulation pattern DP, the sidewalls of the resistance pattern RP, and the sidewalls of the hard mask pattern HP may be aligned in the third direction Z perpendicular to the top surface of the substrate 100. The hard mask pattern HP may include, for example, a silicon nitride film or a silicon oxynitride film.

The resistive contact CR may be configured to pass through the resistive structure RS. That is, the resistive contact CR may pass through the upper interlayer insulating film 120, the resistive structure RS, and the etch stop layer ESL, and then reach the lower interlayer insulating film 110. Accordingly, the sidewall of the ohmic contact CR may be in direct contact with the upper interlayer insulating film 120, the resistive structure RS, and the etch stop layer ESL, and the bottom surface of the ohmic contact CR may be in direct contact with the top surface of the lower interlayer insulating film 110. Therefore, the bottom surface of the merged contact CM (see fig. 2A) may be located at substantially the same level as the bottom surface of the resistance contact CR.

Fig. 7A to 7C are diagrams illustrating a modified example of the etching stopper layer. Fig. 7A is a sectional view taken along line a-a' of fig. 1. Fig. 7B is a sectional view taken along line B-B' of fig. 1. Fig. 7C is a sectional view taken along line C-C' of fig. 1.

Referring to fig. 7A through 7C, in a semiconductor device 50 according to another embodiment of the inventive concept, an etch stop layer ESL may have a multi-layer structure in which a lower etch stop layer L1 and an upper etch stop layer L2 are sequentially stacked.

The components of the semiconductor device 50 and the materials thereof are substantially the same as those of the semiconductor device described above with reference to fig. 1 to 2D, and therefore, the following description will focus on the differences from fig. 1 to 2D.

The etch stop layer ESL may not include a passivation layer that limits and/or prevents oxidation of the lower etch stop layer L1, and may have a multi-layered structure in which the upper etch stop layer L2 is directly formed on the lower etch stop layer L1.

The lower etch stop layer L1 and the upper etch stop layer L2 may be formed of different materials. The lower etch stop layer L1 may be formed of, for example, a metal nitride such as aluminum nitride, and the upper etch stop layer L2 may be formed of, for example, silicon nitride.

Fig. 8 is a plan view corresponding to the second region R2 of fig. 1. Fig. 9 is a sectional view taken along line E-E' of fig. 8.

Referring to fig. 8 and 9, in a semiconductor device 60 according to another embodiment of the inventive concept, a dummy gate structure DGS may be disposed below the resistance contact CR.

The components of the semiconductor device 60 and the materials thereof are substantially the same as those of the semiconductor device described above with reference to fig. 1 to 2D, and therefore, the following description will focus on the differences from fig. 1 to 2D.

The dummy gate structure DGS in the second region R2 may be disposed to reduce a step between the th region R1 (see FIG. 1) and the second region R2 due to a difference in pattern density unlike the active gate structure AGS (see FIG. 1) in the th region R1 (see FIG. 1), the dummy gate structure DGS is not an element of a transistor, and thus, has no influence on the characteristics of the semiconductor device 60 even when the resistance contact CR is not located on the dummy gate structure DGS.

Fig. 10A to 19C are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept in a process sequence. Fig. 10A, 11A, and 19A are cross-sectional views taken along line a-a' of fig. 1. Fig. 10B, 11B, and 19B are cross-sectional views taken along line B-B' of fig. 1. Fig. 10C, 11C, and 19C are cross-sectional views taken along line C-C' of fig. 1.

Referring to fig. 10A through 10C, a substrate 100 including an th region R1 and a second region R2 is provided, the substrate 100 may include a semiconductor substrate, the th region R1 may be a portion of a logic cell region or a portion of a memory cell region, the second region R2 may be a region in which a resistive element is formed, that is, the second region R2 may be a resistive region included in an integrated circuit of a semiconductor device.

The th active pattern AP1 may be formed on the substrate 100 in the th region R1, and the second active pattern AP2 may be formed on the substrate 100 in the second region R2 each of the th active pattern AP1 and the second active pattern AP2 may be in the form of a line arranged in the second direction Y and extending in the direction X in some embodiments, the th active pattern AP1 and the second active pattern AP2 may be formed by patterning an upper portion of the substrate 100 in other embodiments, the th active pattern AP1 and the second active pattern AP2 may be formed by forming and patterning an epitaxial layer on the substrate 100, each of the th active pattern AP1 and the second active pattern AP2 may be in the form of a fin protruding in a third direction Z perpendicular to the top surface of the substrate 100.

The th separation pattern ST1 and the second separation pattern ST2 may be formed on the substrate 100 in the th region R1. the th separation pattern ST1 may divide pMOSFET regions and nMOSFET regions in the second direction Y. the second separation pattern ST2 may expose an upper portion of the th active pattern AP 1. the exposed upper portion of the th active pattern AP1 may be defined as a th active fin af1. the third separation pattern ST3 may be formed on the substrate 100 in the second region R2. the third separation pattern ST3 may expose an upper portion of the second active pattern AP 2. the exposed upper portion of the second active pattern AP2 may be defined as a second active fin AF 2.

The th separation pattern ST1 may be formed thicker than the second and third separation patterns ST2 and ST3 in this case, the th separation pattern ST1 may be formed through a process separate from the second and third separation patterns ST2 and ST3, the separate process may include removing a dummy active pattern (i.e., an portion of the th active pattern AP 1) located between a pMOSFET region and an nMOSFET region, and filling an insulating film in a trench formed by removing the dummy active pattern.

Unlike as shown in the drawings, the second active pattern AP2 may be removed, for example, the removal of the second active pattern AP2 may be performed while removing the dummy active pattern in this case, the third separation pattern ST3 may be formed to have substantially the same thickness as that of the th separation pattern ST1 and to have a thickness greater than that of the second separation pattern ST 2.

Referring to fig. 11A through 11C, an active gate structure AGS crossing the th active pattern AP1 and extending in the second direction Y may be formed on the substrate 100 in the th area R1, and a dummy gate structure DGS crossing the second active pattern AP2 and extending in the second direction Y may be formed on the substrate 100 in the second area R2.

Each of the active gate structures AGS may include a gate insulating layer GD, a gate electrode GE, and a gate capping layer GC.

In embodiments, the active gate structure AGS may be formed by a gate-last process using a sacrificial gate structure (not shown). for example, the step of forming the active gate structure AGS may include forming a sacrificial gate structure intersecting the th active pattern AP1, forming gate spacers SP on opposite sidewalls of the sacrificial gate structure, removing the sacrificial gate structure to define gate regions exposing the th active pattern AP1 between the gate spacers SP, and sequentially forming a gate insulating layer GD, a gate electrode GE, and a gate capping layer GC in the gate regions.

Dummy gate structure DGS may be formed in substantially the same manner and of the same material as active gate structure AGS. Thus, the dummy gate structure DGS may have the same structural features as the active gate structure AGS. For example, each dummy gate structure DGS may include a dummy insulating layer DD, a dummy gate electrode DE, and a dummy capping layer DC. The number of dummy gate structures DGS, the length thereof, and/or the area in which the dummy gate structures DGS are arranged may be determined in consideration of the resistance structures RS to be formed.

Source/drain SD. may be formed on th active pattern AP1 at opposite sides of the active gate structure AGS in embodiments, source/drain SD may be formed to apply strain to the channel CH under the active gate structure AGS the step of forming the source/drain SD may include removing th active fin AF1 at opposite sides of the gate spacer SP and performing a selective epitaxial growth process using the th active pattern AP1, an upper portion of which is removed, as a seed.

In embodiments, the source/drain SD in the pMOSFET region may be formed of silicon germanium (SiGe) and the source/drain SD in the nMOSFET region may be formed of silicon carbide (SiC). The source/drain SD may be doped with impurities at the same time or after the epitaxial growth process.

An underlying interlayer insulating film 110 covering sidewalls of the gate spacers SP and the source/drain electrodes SD may be formed on the substrate 100, the underlying interlayer insulating film 110 may be formed in the th region R1 to expose top surfaces of the active gate structures AGS, and the underlying interlayer insulating film 110 may be formed in the second region R2 to expose top surfaces of the dummy gate structures DGS.

For example, the top surface of the lower interlayer insulating film 110 in the th region R1 may be located at substantially the same level as the top surface of the active gate structure AGS, and the top surface of the lower interlayer insulating film 110 in the second region R2 may be located at substantially the same level as the top surface of the dummy gate structure DGS.

Referring to fig. 12A to 12C, source/drain contact holes CAH passing through the lower interlayer insulating film 110 and exposing the source/drains SD and gate contact holes CBH passing through the gate capping layer GC and exposing the gate electrodes GE may be formed in the th region R1.

The source/drain contact hole CAH and the gate contact hole CBH may be formed through separate patterning processes, for example, the source/drain contact hole CAH may be formed through an patterning process, and then the gate contact hole CBH may be formed through a second patterning process, or vice versa.

In detail, the step of forming the source/drain contact CA and the gate contact CB may include filling the inside of the source/drain contact CAH and the gate contact CBH with a conductive material and planarizing the conductive material so that the top surface of the lower interlayer insulating film 110 is exposed.

Referring to fig. 13A to 13C, an etch stop layer ESL may be formed on the lower interlayer insulating film 110 in the th region R1 and the second region R2.

The etch stop layer ESL may be formed such that the lower etch stop layer L1, the passivation layer LP, and the upper etch stop layer L2 are sequentially stacked. The etch stop layer ESL may be formed of an insulating material. The lower etch stop layer L1, the passivation layer LP, and the upper etch stop layer L2 may be formed of different materials.

In embodiments, the lower etch stop layer L1 may be formed of, for example, a metal nitride such as aluminum nitride, the passivation layer LP may be formed of, for example, silicon oxide, and the upper etch stop layer L2 may be formed of, for example, silicon nitride.

Referring to fig. 14A through 14C, an initial insulating layer DL and an initial resistive element layer RL. may be sequentially stacked on the etch stop layer ESL in the th region R1 and the second region R2, for example, the initial insulating layer DL may include silicon oxide and the initial resistive element layer RL may include a metal or a metal compound.In embodiments, the initial resistive element layer RL may include titanium nitride in which case the initial resistive element layer RL may have a low resistivity and thus may be formed to a relatively small thicknessIs measured.

Referring to fig. 15A to 15C, a resistance structure RS may be formed on the etch stop layer ESL in the second region R2. The resistance structure RS may include an insulation pattern DP formed by patterning the initial insulation layer DL (see fig. 14C) and a resistance pattern RP formed by patterning the initial resistance element layer RL (see fig. 14C). The resistance structure RS may be formed in a flat plate shape, but is not limited thereto.

The upper interlayer insulating film 120 may be formed on the etch stop layer ESL, the upper interlayer insulating film 120 in the th region R1 may cover the top surface of the etch stop layer ESL, the upper interlayer insulating film 120 in the second region R2 may cover the etch stop layer ESL, and the resistive structure RS. in embodiments, a process of planarizing the top surface of the upper interlayer insulating film 120 may be performed after the upper interlayer insulating film 120 is formed, a planarization process may be performed to remove a step between the upper interlayer insulating film 120 in the th region R1 and the upper interlayer insulating film 120 in the second region R2 caused by the resistive structure RS.

Although the planarization process is skipped, when the resistance pattern RP is formed of a material having a low resistivity (such as titanium nitride) and thus has a small thickness, the step between the upper interlayer insulating film 120 in the -th region R1 and the upper interlayer insulating film 120 in the second region R2 falls within the process dispersion range.

Referring to fig. 16A to 16C, a -th merged contact hole CMH1 passing through the upper interlayer insulating film 120 and exposing the top surface of the upper etch stop layer L2 and a resistance contact hole CRH sequentially passing through the upper interlayer insulating film 120, the resistance pattern RP and exposing the top surface of the insulating pattern DP may be formed in the -th region R1.

The th merged contact hole CMH1 and the resistive contact hole CRH may be formed through a separate patterning process, for example, the th merged contact hole CMH1 may be formed through the patterning process, and then the resistive contact hole CRH may be formed through the second patterning process, and vice versa the th merged contact hole CMH1 may be formed deeper than the resistive contact hole CRH each of the th patterning process and the second patterning process may include forming a mask pattern (not shown) on the upper interlayer insulating film 120 and performing an anisotropic etching process using the mask pattern as an etching mask.

The upper etch stop layer L2 may be formed of a material having dry etching selectivity with respect to the upper interlayer insulating film 120, and therefore, the upper etch stop layer L2 may be maintained without being etched during the dry etching process of forming the th merged contact hole CMH1 on the upper interlayer insulating film 120.

In addition, the upper etch stop layer L2 limits and/or prevents the th merged contact hole CMH1 from being depressed due to over-etching during the performance of the dry etching process for forming the th merged contact hole CMH1 the upper etch stop layer L2 may also limit and/or prevent the occurrence of a depression phenomenon in the performance of a cleaning process for removing etching byproducts generated in the dry etching process.

The insulating pattern DP may be formed of a material having dry etching selectivity with respect to the upper interlayer insulating film 120 and the resistance pattern RP. Therefore, during the dry etching process for forming the resistance contact hole CRH in the upper interlayer insulating film 120 and the resistance pattern RP is performed, the insulating pattern DP may remain without being etched.

Referring to fig. 17A to 17C, a second merged contact hole CMH2 passing through the upper etch stop layer L2 and the passivation layer LP and exposing the top surface of the lower etch stop layer L1 in the th region R1 may be formed.

The second merged contact hole CMH2 may be formed through a patterning process and a cleaning process the patterning process may include an anisotropic etching process using a mask pattern (not shown) formed on the upper interlayer insulating film 120 or using the upper interlayer insulating film 120 formed by patterning the th merged contact hole CMH1 as an etching mask (see fig. 16C).

The passivation layer LP protects the lower etch stop layer L1 and limits and/or prevents the occurrence of side effects of oxidizing the lower etch stop layer L1, thus enhancing resistance to wet etching, the second merged contact hole CMH2 may be removed in a patterning process and a cleaning process, and the passivation layer LP and the upper etch stop layer L2 may be removed by a dry etching process .

Referring to fig. 18A to 18C, a merged contact hole CMH passing through the lower etch stop layer L1 and exposing the top surface of the conductive contact C1 in the region R1 may be formed.

The merged contact hole CMH may be formed through a patterning process. The patterning process may include performing an isotropic etching process using a mask pattern (not shown) on the upper interlayer insulating film 120 or the upper interlayer insulating film 120 as an etching mask, wherein the interlayer insulating film 120 has the second merged contact hole CMH2 (see fig. 17B) that patterns it.

The merged contact hole CMH is formed by patterning the exposed lower etch stop layer L1 through a wet etching process the lower etch stop layer L1 may be formed of a material that is easily removable through wet etching and a wet etching process may be performed to expose the top surface of the th conductive contact C1 when the merged contact hole CMH is formed, a wet etching process that causes less damage to the top surface of the th conductive contact C1 than the dry etching process may be used.

By the multi-step etching process described above with reference to fig. 16A through 18C, the top surface of the metal material of the th conductive contact C1 can be limited and/or prevented from being damaged by forming the merged contact hole CMH.

Accordingly, in the method of manufacturing the semiconductor device according to the embodiment of the inventive concept, the top surface of the th conductive contact C1 may be limited and/or prevented from being damaged by forming the etch stop layer ESL having a multi-layered structure under the resistance structure RS.

Referring to fig. 19A to 19C, a plurality of merged contacts CM connected to the source/drain contacts CA and the gate contact CB, respectively, and a resistance contact CR connected to the resistance structure RS may be formed.

The plurality of merged contacts CM may sequentially pass through the upper interlayer insulating film 120 and the etch stop layer esl in the -th region R1 the resistance contact CR may sequentially pass through the upper interlayer insulating film 120 and the resistance pattern RP in the second region R2.

In detail, the step of forming the plurality of merged contacts CM and CR may include filling a conductive material in the plurality of merged contact holes CMH and CRH and planarizing the conductive material until the top surface of the upper interlayer insulating film 120 is exposed, and thus, the top surfaces of the plurality of merged contacts CM and CR may be located at substantially the same level as the top surface of the upper interlayer insulating film 120.

Referring back to fig. 2A to 2D, the th wiring Ma, the second wiring Mb, and the third wiring Mc connected to the merging contact CM and the resistance contact CR may be formed on the upper interlayer insulating film 120 the th wiring Ma, the second wiring Mb, and the third wiring Mc may include a metal material such as aluminum or copper, and may be formed through a damascene process.

Fig. 20 is an enlarged view of the region XX of fig. 18A.

Referring to fig. 20, a sidewall forming the lower etch stop layer L1 among sidewalls of the merged contact hole CMH may have a concave shape, and sidewalls forming the passivation layer LP and the upper etch stop layer L2 among sidewalls of the merged contact hole CMH may have a tapered shape.

As described above, the passivation layer LP and the upper etch stop layer L2 are patterned by the dry etching of the anisotropic etching, and thus, the sidewalls forming the passivation layer LP and the upper etch stop layer L2 among the sidewalls of the merged contact hole CMH may have a tapered shape. In contrast, the lower etch stop layer L1 is patterned by wet etching of isotropic etching, and thus, the sidewall forming the lower etch stop layer L1 among the sidewalls of the merged contact hole CMH may have a concave shape.

Although embodiments of the inventive concept have been described above with reference to the accompanying drawings, it will be appreciated by those skilled in the art that the inventive concept can be embodied in many different forms without departing from the scope or essential characteristics thereof. Accordingly, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.