阅读说明：本技术 半导体存储装置及存储器控制器 (Semiconductor memory device and memory controller ) 是由 白川政信 于 2014-09-05 设计创作，主要内容包括：本发明提供一种可提高动作性能的半导体存储装置及存储器控制器。实施方式的半导体存储装置(100)包括：多个串单元SU,其是积层多个存储单元而成并且是NAND串的集合；区块BLK,其包含多个串单元SU,成为数据的抹除单位；以及寄存器(122),其针对每个串单元SU保持抹除特性信息。寄存器(122)可将抹除特性信息输出至存储器控制器(200)。(The invention provides a semiconductor memory device and a memory controller capable of improving operation performance. A semiconductor memory device (100) according to an embodiment includes: a plurality of string units SU which are a set of NAND strings and in which a plurality of memory cells are stacked; a block BLK including a plurality of string units SU as an erase unit of data; and a register (122) that holds erasure characteristics information for each string unit SU. The register (122) may output the erasure flag information to the memory controller (200).)

1. A semiconductor memory device, characterized by comprising:

a plurality of string units which are formed by laminating a plurality of memory units and are a set of NAND strings;

a block including a plurality of the string cells as an erase unit of data; and

a register that holds erasure characteristics information for each of the string cells; and is

The register can output the erasure characteristic information to a memory controller;

when a 1 st command is received from the memory controller, all string units within the block are set as erase verify targets,

when a 2nd command is received from the memory controller, only any string of cells within the block is set as an erase verify target.

2. The semiconductor memory device according to claim 1, wherein:

the register includes a plurality of latch circuits connected in series, and each time any one of the string cells passes erase verification, information indicating the passing string cell and the number of erase cycles at the time of the passing are taken into the latch circuits.

3. The semiconductor memory device according to claim 2, wherein:

the register outputs data in any of the latch circuits to the memory controller in response to an instruction and an address received from the memory controller.

4. The semiconductor memory device according to claim 1, wherein:

when the 1 st command is issued, the unusable NAND strings are removed from the erase verify object.

5. A memory controller, characterized by:

which controls a semiconductor memory device capable of erasing in block units including a plurality of string units that are stacked with a plurality of memory cells and are a set of NAND strings, and the memory controller includes:

a control unit operable to issue a command for reading erase characteristic information of the string cell unit from the semiconductor memory device; and

a storage unit that can hold the erasure characteristics information for each of the string cells;

the memory controller sets all string units in the block as erase verification targets by issuing a 1 st command,

by issuing the 2nd command, only any cell in the block is targeted for erase verification based on the erasure characteristics information.

6. The memory controller of claim 5, wherein:

the erasure characteristics information includes information indicating a string cell that passes the erasure verification and the number of erasure cycles that the string cell passes.

7. The memory controller of claim 6, wherein:

the control unit periodically checks the string unit that is the erase verification target in the 2nd command.

8. The memory controller of claim 7, wherein:

the control unit increases the frequency of rechecking the string unit to be verified as the number of times of erasing the block increases.

Technical Field

Background

A NAND (NOT AND) type flash memory in which memory cells are three-dimensionally arranged is known.

Disclosure of Invention

The invention provides a semiconductor memory device and a memory controller capable of improving operation performance.

Drawings

Fig. 1 is a block diagram of a memory system of embodiment 1.

Fig. 2 is a block diagram of the semiconductor memory device according to embodiment 1.

Fig. 3 is a circuit diagram of the memory cell array of embodiment 1.

Fig. 4 is a cross-sectional view of an example of a NAND string of embodiment 1.

Fig. 5 is a circuit diagram of a part of the latest string register of embodiment 1.

Fig. 6 is a circuit diagram of another part of the latest string register of embodiment 1.

FIG. 7 is a graph showing the relationship between the number of erase cycles and the number of string units according to embodiment 1.

Fig. 8 is a schematic diagram of the latest string register according to embodiment 1.

Fig. 9 is a timing chart of various signals in the latest string register of embodiment 1.

Fig. 10 is a timing chart of various signals at the time of status reading in embodiment 1.

FIG. 11 is a graph showing the relationship between the erase count and the number of bad string occurrences.

FIG. 12 is a flowchart illustrating an erasing operation according to embodiment 2.

Fig. 13 shows the instruction sequence of embodiment 2.

Embodiments relate to a semiconductor memory device and a memory controller.