Erasing multiple blocks in a memory device
阅读说明：本技术 存储器装置中多个块的擦除 (Erasing multiple blocks in a memory device ) 是由 F·罗里 G·卡列洛 于 2019-06-28 设计创作，主要内容包括：本申请案涉及存储器装置中的多个块的擦除。各种应用可包含具有一或多个存储器装置的存储器系统,所述存储器装置能够响应于来自主机的命令而对多个存储器块执行存储器操作。举例来说,可通过若干种方法中的一种擦除多个存储器块来实现擦除性能的改进。这些方法可包含响应于单个命令而进行并行擦除,随后接着进行串行验证。其它方法可包含响应于单个命令而对所述多个块进行依序擦除及验证操作。本发明还揭示额外设备、系统及方法。(The present application relates to the erasure of multiple blocks in a memory device. Various applications may include memory systems having one or more memory devices capable of performing memory operations on a plurality of memory blocks in response to commands from a host. For example, improvements in erase performance may be achieved by erasing multiple memory blocks in one of several ways. These methods may include parallel erase followed by serial verification in response to a single command. Other methods may include performing sequential erase and verify operations on the plurality of blocks in response to a single command. Additional apparatus, systems, and methods are also disclosed.)
1. A system, comprising:
a controller;
a memory device; and
firmware storing instructions executable by the controller to operate the memory device, the instructions including the operations of:
generating an initial set of parameters for erasing a plurality of memory blocks of the memory device; and
the erase and verify operations are performed on the plurality of blocks by sequentially erasing and verifying each block of the plurality of blocks in response to the controller receiving a command to perform the erase and verify operations on the plurality of blocks.
2. The system of claim 1, wherein the operation of generating the initial set of parameters comprises: identifying a first block of the consecutive blocks as a starting block for erasing the plurality of blocks; and identifying a second block of the consecutive blocks as an end block when the plurality of blocks are erased.
3. The system of claim 2, wherein the operation of performing the erase and verify operation includes: generating an erase pulse followed by a verify pulse for each of the successive blocks, then proceeding to a next one of the successive blocks; and terminating the erase and verify operations after erasing the second block.
4. The system of claim 1, wherein the operation of generating the initial set of parameters comprises:
identifying the plurality of blocks by entries in a block list, the list having a number of blocks;
identifying a first block of the number of blocks for erasing; and
a count limit equal to the number of blocks to be erased is generated.
5. The system of claim 4, wherein the operation of performing the erase and verify operation includes:
starting with the first block, generating an erase pulse followed by a verify pulse for each block in the list, and then proceeding to the next block of the list;
after each block is erased and verified, the count of the block counter is incremented by 1; and
terminating the erase and verify operations on the plurality of blocks when the count of the block counter is greater than the count limit.
6. The system of claim 1, wherein the operation of generating the initial set of parameters comprises: a chip erase operation is identified in which a starting block in the sequential erase and verify is a block zero of the memory device and an ending block in the sequential erase is a last block of the memory device.
7. The system of claim 1, wherein the system is a solid state drive.
8. The system of claim 1, wherein the system comprises:
a host operable to generate the command operatively received by the controller; and
a communication interface coupled to the host and the controller, the communication interface arranged to transmit the command from the host to the controller.
9. A method, comprising:
generating an initial set of parameters for erasing a plurality of memory blocks of a memory device; and
the erase and verify operations are performed on the plurality of blocks by sequentially erasing and verifying each block of the plurality of blocks in response to receiving a command to perform the erase and verify operations on the plurality of blocks.
10. The method of claim 9, wherein generating the initial set of parameters comprises: identifying a first block of the consecutive blocks as a starting block for erasing and verifying the plurality of blocks; and identifying a second block of the consecutive blocks as an end block when erasing and verifying the plurality of blocks.
11. The method of claim 10, wherein performing the erase and verify operation includes: generating an erase pulse followed by a verify pulse for each of the successive blocks, then proceeding to a next one of the successive blocks; and terminating the erase and verify operations after erasing the second block.
12. The method of claim 9, wherein generating the initial set of parameters comprises:
identifying the plurality of blocks by entries in a block list, the list having a number of blocks;
identifying a first block of the number of blocks for erase and verification; and
a count limit equal to the number of blocks to be erased and verified is generated.
13. The method of claim 12, wherein performing the erase and verify operation includes:
starting with the first block, generating an erase pulse followed by a verify pulse for each block in the list, and then proceeding to the next block in the list;
incrementing the count of the block counter by 1 after each block is erased and verified; and
terminating the erase and verify operation when the count of the block counter is greater than the count limit.
14. The method of claim 10, wherein generating the initial set of parameters includes identifying a chip erase operation, wherein a starting block in the sequential erase and verify is a block zero and an ending block is a last block of the memory device.
15. A system, comprising:
a controller;
a memory device; and
firmware storing instructions executable by the controller to operate the memory device, the instructions including the operations of:
generating an initial set of parameters for erasing a plurality of memory blocks of the memory device;
simultaneously providing an erase pulse to each of the plurality of blocks; and
after issuing the erase pulse, serially verifying erasure of each of the plurality of blocks.
16. The system of claim 15, wherein the operations comprise operations of: while erasing the plurality of blocks, setting one of the plurality of blocks as unusable to receive another erase pulse in response to determining that the block passes verification.
17. The system of claim 15, wherein the operations comprise operations of: each block that passes verification after erase is marked as a bad block to make the respective block unavailable to receive another erase pulse.
18. The system of claim 17, wherein the operations include an iterator:
maintaining blocks that fail verification after erase as usable blocks to receive another erase pulse;
generating an additional erase pulse for the usable block and serially verifying the usable block after generating the additional erase pulse; and
each available block that passes verification after the additional erase is marked as a bad block to be unavailable to receive another additional erase pulse.
19. The system of claim 18, wherein the iterative procedure is ended immediately after determining that each block of the plurality of blocks is marked as a bad block or after determining that a maximum loop count of the iterative procedure is reached.
20. The system of claim 15, wherein the generating the initial set of parameters comprises: identifying a first block of the consecutive blocks as a starting block for erasing the plurality of blocks; and identifying a second block of the consecutive blocks as an end block of the erasing of the plurality of blocks.
21. The system of claim 15, wherein said generating said initial set of parameters comprises identifying said plurality of blocks for erasure by a list of blocks.
22. The system of claim 15, wherein the generating the initial set of parameters comprises: a chip erase operation is identified, wherein a starting block in the erase is a block zero and an ending block is a last block of the memory device.
23. A method, comprising:
generating an initial set of parameters for erasing a plurality of memory blocks of a memory device;
simultaneously providing an erase pulse to each of the plurality of blocks;
after issuing the erase pulse, serially verifying erasure of each of the plurality of blocks.
24. The method of claim 23, wherein the method includes: while the erasing the plurality of blocks, setting one of the plurality of blocks as unusable to receive another erase pulse in response to determining that the block passes verification.
25. The method of claim 23, wherein the method includes: each block that passes verification after erase is marked as a bad block to make the respective block unavailable to receive another erase pulse after passing the verification.
26. The method of claim 25, wherein the method comprises performing an iterative procedure comprising:
maintaining blocks that fail verification after erase as usable blocks to receive another erase pulse;
generating an additional erase pulse for the usable block and serially verifying the usable block after generating the additional erase pulse; and
each usable block that passes verification after the additional erase pulse is marked as a bad block to be unavailable to receive another additional erase pulse.
27. The method of claim 26, wherein the iterative procedure is ended immediately after determining that each block of the plurality of blocks is marked as a bad block or determining that a maximum loop count of the iterative procedure is reached.
28. The method of claim 23, wherein generating the initial set of parameters comprises: identifying a first block of the consecutive blocks as a starting block for erasing the plurality of blocks; and identifying a second block of the consecutive blocks as an end block of the erasing of the plurality of blocks.
29. The method of claim 23, wherein generating the initial set of parameters includes identifying the plurality of blocks in a block list for erasure.
30. The method of claim 23, wherein generating the initial set of parameters comprises: a chip erase operation is identified in which the starting block in the sequential erase is block zero and the ending block is the last block of the memory device.
Technical Field
The present application relates generally to memory devices.
Background
Memory devices are typically provided in computers or other electronic devices as internal semiconductor integrated circuits. There are many different types of memory, including volatile memory and non-volatile memory. Volatile memory requires power to maintain its data, and examples of volatile memory include random accessMemory (RAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and examples of non-volatile memory include flash memory, Read Only Memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Static RAM (SRAM), Erasable Programmable ROM (EPROM), resistance variable memory such as Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Magnetoresistive Random Access Memory (MRAM), and three-dimensional (3D) XPointTMMemory, and the like.
Flash memory is used as non-volatile memory for a wide variety of electronic applications. Flash memory devices typically include one or more groups of single transistor, floating gate, or charge trapping memory cells that allow for high memory density, high reliability, and low power consumption. Two common types of flash memory array architectures include the NAND (NAND) architecture and the and or (NOR) architecture, which are named in logical form, arranging the basic memory cell configuration of each. The memory cells of a memory array are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row in the array is coupled to an access line (e.g., a word line). In the NOR architecture, the drain of each memory cell in a column in the array is coupled to a data line (e.g., a bit line). In a NAND architecture, memory cells in strings of an array are coupled together in series, source to drain, between a source line and a bit line.
NOR architecture and NAND architecture semiconductor memory arrays are accessed by a decoder that activates a particular memory cell by selecting the word line coupled to the gate of the memory cell. In a NOR architecture semiconductor memory array, once activated, selected memory cells place their data values on bit lines, causing different currents to flow depending on the state in which a particular cell is programmed. In a NAND architecture semiconductor memory array, a high bias voltage is applied to a drain side Select Gate (SGD) line. The word lines coupled to the gates of each group of unselected memory cells are driven at a specified pass voltage (e.g., Vpass) to use each group of unselected memory cells as pass transistors (e.g., to pass current in a manner that is unrestricted by the data values stored by the unselected memory cells). Current then flows from the source line through each series-coupled group to the bit lines, limited only by the selected memory cells of each group, placing the current-encoded data values of the selected memory cells on the bit lines.
Each flash memory cell in a NOR architecture or NAND architecture semiconductor memory array can be programmed individually or collectively to one or a number of program states. For example, a Single Level Cell (SLC) may represent one of two programmed states (e.g., 1 or 0), representing one bit of data. However, flash memory cells can also represent one of more than two program states, allowing higher density memory to be fabricated without increasing the number of memory cells, as each cell can represent more than one binary digit (e.g., more than one bit). These cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In some examples, MLC may refer to a memory cell that may store two data bits per cell (e.g., one of four programmed states), a three-level cell (TLC) may refer to a memory cell that may store three data bits per cell (e.g., one of eight programmed states), and a four-level cell (QLC) may store four data bits per cell. MLC is used herein in its broader context to refer to any memory cell that can store more than one bit of data per cell (i.e., can represent more than two programmed states).
Conventional memory arrays are two-dimensional (2D) structures arranged on a surface of a semiconductor substrate and may be referred to as planar memory arrays. To increase the memory capacity of a given area and to reduce cost, the size of individual memory cells has been reduced. However, there are technical limitations to reducing the size of individual memory cells, and thus, there are technical limitations to the memory density of 2D memory arrays. In response, three-dimensional (3D) memory structures, such as 3D NAND architecture semiconductor memory devices, are being developed to further increase memory density and reduce memory cost.
These 3D NAND devices typically include strings of memory cells coupled in series (e.g., drain to source) between one or more source side Select Gates (SGS) proximate the source and one or more drain side Select Gates (SGD) proximate the bit line. In an example, the SGS or SGD may include one or more Field Effect Transistors (FETs), or Metal Oxide Semiconductor (MOS) structure devices, or the like. In some examples, the strings will extend vertically through multiple vertical spacers containing respective word lines. A semiconductor structure (e.g., a polysilicon structure) may extend adjacent a string of memory cells to form a channel for the memory cells in the string. In the example of a vertical string, the polysilicon structures may be in the form of vertically extending pillars. In some examples, the string may be "folded" and thus arranged relative to the U-shaped post. In other examples, multiple vertical structures may be stacked on top of each other to form a stacked array of memory cell strings.
Memory arrays or devices can be combined together to form a storage volume of a memory system, such as a Solid State Drive (SSD), Universal Flash (UFS)TM) Device, multi-media card (MMC) solid state memory device, embedded MMC device (eMMC)TM) And the like. SSDs can be used as the main storage device for computers, etc., which have benefits over traditional hard disk drives with moving parts, e.g., in terms of performance, size, weight, durability, operating temperature range, and power consumption. For example, SSDs may have shortened search times, latencies, or other delays associated with disk drives (e.g., electromechanical, etc.). SSDs use non-volatile memory cells (e.g., flash memory cells) to eliminate the internal battery supply need, thus allowing the drive to be more versatile and compact.
An SSD may include a number of memory devices, thus a number of dies or logic units (e.g., a number of logic units or LUNs), and may include one or more processors or other controllers that perform the logical functions needed to operate the memory devices or interface with external systems. These SSDs may include one or more flash memory dies on which a number of memory arrays and peripheral circuitry are included. A flash memory array may include a number of block memory cells organized into a number of physical pages. In many examples, an SSD will also include DRAM or SRAM (or other forms of memory die or other memory structures). The SSD can receive commands associated with memory operations from the host, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory device and the host; or an erase operation to erase data from the memory device.
To perform an operation in a memory device, a significant amount of time associated with completing the operation is consumed. The longer it takes for a single operation of a memory device to perform its task, the slower an application using the memory device will run. Thus, the memory industry is being driven toward structural memory devices to perform operations in a manner that shortens the time for many memory operations as much as possible.
Disclosure of Invention
In one aspect, the present application provides a system comprising: a controller; a memory device; and firmware storing instructions executable by the controller to operate the memory device, the instructions including the operations of: generating an initial set of parameters for erasing a plurality of memory blocks of the memory device; and performing erase and verify operations on the plurality of blocks by sequentially erasing and verifying each block of the plurality of blocks in response to the controller receiving a command to perform the erase and verify operations on the plurality of blocks.
In another aspect, the present application provides a method comprising: generating an initial set of parameters for erasing a plurality of memory blocks of a memory device; and performing erase and verify operations on the plurality of blocks by sequentially erasing and verifying each block of the plurality of blocks in response to receiving a command to perform the erase and verify operations on the plurality of blocks.
In another aspect, the present application provides a system comprising: a controller; a memory device; and firmware storing instructions executable by the controller to operate the memory device, the instructions including the operations of: generating an initial set of parameters for erasing a plurality of memory blocks of the memory device; simultaneously providing an erase pulse to each of the plurality of blocks; and serially verifying the erase of each of the plurality of blocks after issuing the erase pulse.
In another aspect, the present application provides a method comprising: generating an initial set of parameters for erasing a plurality of memory blocks of a memory device; simultaneously providing an erase pulse to each of the plurality of blocks; after issuing the erase pulse, serially verifying erasure of each of the plurality of blocks.
Drawings
The drawings, which are not necessarily to scale, illustrate generally the various embodiments discussed in this document by way of example and not by way of limitation.
FIG. 1 illustrates an example of an environment including a memory device, in accordance with various embodiments.
Figures 2 and 3 illustrate schematic diagrams of examples of three-dimensional NAND architecture semiconductor memory arrays, according to various embodiments.
FIG. 4 illustrates an example block diagram of a memory module in accordance with various embodiments.
Fig. 5 is a block diagram illustrating an example machine on which one or more embodiments may be implemented, in accordance with various embodiments.
FIG. 6 is a block diagram illustrating an example system having a host coupled to a memory system, in accordance with various embodiments.
FIG. 7 is a flow diagram of features of an example method of erasing a plurality of memory blocks of a memory device, according to various embodiments.
FIG. 8 is a flow diagram of features of an example method of erasing a plurality of memory blocks of a memory device, according to various embodiments.
FIG. 9 is a flow diagram of features of an example method of sequentially erasing a plurality of memory blocks of a memory device, according to various embodiments.
FIG. 10 is a flow diagram of features of an example method of erasing a plurality of memory blocks of a memory device, the method having parallel erase operations, according to various embodiments.
FIG. 11 is a block diagram illustrating an embodiment of a block disable latch, according to various embodiments.
FIG. 12 is an erase time simulation for two different types of memory components using an example method with parallel erase operations that erases multiple memory blocks of a memory device, according to various embodiments.
FIG. 13 illustrates an example command structure for a list-wise multi-block erase, in accordance with various embodiments.
FIG. 14 illustrates an example command structure for range multi-block erase, in accordance with various embodiments.
Detailed Description
The following detailed description refers to the accompanying drawings that show, by way of illustration, various embodiments of the present invention. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. Other embodiments may be utilized and structural, logical, and electrical changes may be made to these embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments. The following detailed description is, therefore, not to be taken in a limiting sense.
In various embodiments, improvements in memory device capabilities may be achieved by reducing the time it takes for a memory device to perform functions associated with storage elements of the memory device by performing functions on multiple storage elements of the memory device using a single command. For example, improvements in erase performance can be achieved by erasing multiple memory blocks in several ways with respect to multi-block erase (MBE) and with respect to Chip Erase (CE). Each of these methods of operation may include a parallel erase operation in response to a single command or a sequential erase operation in response to a single command. These methods can be implemented with a number of different algorithms. An algorithm is simply a program that performs a task based on performing a certain number of prescribed actions. These algorithms may be executed using firmware operating in a memory device.
The range mbe (rmbe) provides a method of erasing a set of contiguous memory blocks within start and stop limits. A tabular mbe (lmbe) provides a method of erasing a set of memory blocks within a block list. The CE of the memory device provides a method of erasing all storage elements accessible to a user of the memory device, wherein the storage elements used for maintenance and operation of the memory device are effectively masked out of the erase operation. The storage elements may be configured as an array of memory elements. The implementation algorithms of these methods may include sequentially performing erase and verify operations on each block of the memory device in the range for RMBE, in the list for LMBE, or in the user-available blocks to achieve CE. Another implementation algorithm of these methods may include issuing erase pulses in parallel for all blocks of the memory device in the range for RMBE, in the list for LMBE, or in the user-available blocks to achieve CE. After the pulses are issued, the blocks may be sequentially verified, with the verified blocks being prohibited from receiving additional pulses. Inhibiting an operation may include using a flag for a block that passes the verify operation. Feature Addresses (FAs) can be used to enable and manage MBE and CE algorithms.
Systems implementing these or similar algorithms may experience latency improvements with respect to user mode commands. For example, the execution time for an erase device command may be shortened, where all blocks in the user area of the memory device are erased at once. In another example, the execution time for a clear command, a delete command, or a secure erase may be shortened, where all blocks in the garbage list are erased at once. In addition, in a memory system in which the capacity of the memory device is full, performance improvement of the write workload of the memory device can be achieved. Firmware associated with such a memory system may accumulate and erase blocks of useless cells in parallel.
These algorithms, or similar algorithms, to erase multiple memory blocks are easily implemented in memory-based systems. These algorithms for erasing multiple memory blocks in a system can be performed using firmware in response to a single command rather than a series of commands. This may be particularly useful in early software development stages or in the case of testers with slow interfaces and/or sequential access to Devices Under Test (DUTs). In the case of a memory system where multiple memory devices are structured as NAND memory devices, these algorithms coded in the firmware of the memory system can offload the tasks of the host of the memory system to manage the different NAND geometries. In managed NAND applications, this property can be used for ROM implementations. Commands for conducting a CE as taught herein may have hard coded values for the first and last blocks in the NAND.
These or similar algorithms that use firmware associated with a memory controller to erase multiple memory blocks in a system may include an Erase Verify (EV) as part of the algorithm that effectively enables the EV prior to execution of the erase option. This can significantly reduce the task of associating host trace block states. This efficient enabling prior to the erase option enables fast automated inspection and reduces charge buildup. These or similar algorithms allow for an easy implementation of a loop flow that alternates erase and preconditioning phases.
These or similar algorithms that use firmware associated with a memory controller to erase multiple memory blocks in a system may provide test time improvements in manufacturing and when planning a test flow. For example, manufacturing and planning may be performed with a NAND memory system reset to factory settings and including NAND cycles. The MBE method, which involves applying erase pulses in parallel, provides higher parallelism in the erase phase than conventional methods. For a floating gate NAND (FG-NAND) memory array, this approach can provide an estimated improvement of 40%. For a replacement gate NAND (RG-NAND) memory array, this approach can provide an estimated improvement of 90%.
These or similar algorithms that use firmware associated with a memory controller to erase multiple memory blocks in a system may result in less traffic on the memory system bus. The memory bus of a NAND-based memory system may use an Open NAND Flash Interface (ONFI). Less ONFI traffic may be associated with an estimated improvement of 2% to 10%, depending on the tester speed.
These or similar algorithms to erase multiple memory blocks in a system may provide high synchronicity in a multi-die environment. This can be attributed to the time variation of block erase across blocks (tBERS). When issuing a single block erase command, the host waits for each block on a slower die and wastes a number of cycles if a bad block is encountered. Using the MBE or CE method with the corresponding MBE or CE command, the erase time is automatically averaged at the die level, which can provide an estimated improvement of 2 to 10%.
Electronic devices such as mobile electronic devices (e.g., smartphones, tablet computers, etc.), electronic devices used in automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and internet-connected appliances or devices (e.g., internet of things (IoT) devices, etc.) have different storage needs depending on the type of electronic device, the use environment, performance expectations, and so forth.
The electronic device can be broken down into several major components: a processor (e.g., a Central Processing Unit (CPU) or other main processor); memory (e.g., one or more volatile or non-volatile Random Access Memory (RAM) memory devices such as dynamic RAM (dram), mobile or low power double data rate synchronous dram (ddr sdram), etc.); and a storage device (e.g., a non-volatile memory (NVM) device such as flash memory, Read Only Memory (ROM), SSD, MMC or other memory card structure or assembly, etc.). In some examples, the electronic device may include a user interface (e.g., a display, a touchscreen, a keyboard, one or more buttons, etc.), a Graphics Processing Unit (GPU), a power management circuit, a baseband processor, or one or more transceiver circuits, etc.
FIG. 1 illustrates an example of an
One or more communication interfaces may be used to communicate data between the
The
The
The
The
In operation, data is typically written to or read from the
Although a page of data may include a number of bytes of user data (e.g., the data payload includes a number of sectors of data) and their corresponding metadata, the size of a page typically refers only to the number of bytes used to store user data. For example, a page of data having a 4KB page size may include 4KB of user data (e.g., 8 sectors assuming a sector size of 512B) and a number of bytes (e.g., 32B, 54B, 224B, etc.) of metadata corresponding to the user data, such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.
Different types of memory cells or
FIG. 2 illustrates an example schematic diagram of a 3D NAND architecture
Each memory cell string includes a source line (SRC)235 or a source side Select Gate (SGS) (e.g., a first a)0
Within a physical page, each layer represents a row of memory cells and each string of memory cells represents a column. A sub-block may include one or more physical pages. A block may include a number of sub-blocks (or physical pages) (e.g., 128, 256, 384, etc.). Although illustrated herein as having two blocks, each block having two sub-blocks, each sub-block having a single physical page, each physical page having three strings of memory cells, and each string having 8 layers of memory cells, in other examples, the
Each memory cell in
In an example, the
Fig. 3 illustrates an example schematic diagram of a portion of a NAND architecture semiconductor memory array including a plurality of
Each memory cell string is coupled to a source line (SRC)335 using a respective source side Select Gate (SGS) (e.g., first SGS 331-third SGS 333) and to a respective data line (e.g., first Bit Line (BL) BL 0320-third bit line BL2322) using a respective drain side Select Gate (SGD) (e.g., first SGD 326-third SGD 328). Although illustrated in the example of fig. 3 as having 8 layers (e.g., using Word Lines (WL) WL 0310-WL 7317) and three data lines (BL 0326-BL 2328), other examples may optionally include memory cell strings having more or fewer layers or data lines.
In a NAND architecture semiconductor memory array, such as the exemplary memory array 300, the state of a selected
To program or write data to the memory cells, a program voltage (Vpgm) (e.g., one or more program pulses, etc.) may be applied to the selected word line (e.g., WL4), and thus to the control gates of each memory cell coupled to the selected word line (e.g., first Control Gate (CG)341 through
In contrast, a pass voltage (Vpass) may be applied to one or more word lines having memory cells not targeted for programming, or an inhibit voltage (e.g., Vcc) may be applied to data lines (e.g., bit lines) having memory cells not targeted for programming, e.g., to inhibit charge transfer from the channel to the gates of floating these non-targeted memory cells. The channel voltage may vary depending on, for example, the proximity of the applied channel voltage to the word line targeted for programming. The inhibit voltage may include a supply voltage (Vcc) relative to a ground potential (e.g., Vss), such as a voltage from an external source or supply (e.g., a battery, an analog-to-digital converter, etc.).
For example, if a program voltage (e.g., 15V or greater) is applied to a particular word line (e.g., WL4), a channel voltage of 10V may be applied to one or more other word lines (e.g., WL3, WL5, etc.) to inhibit programming of non-target memory cells, or to retain values stored on these memory cells not targeted for programming. As the distance between the applied programming voltage and the non-target memory cells increases, the channel voltage required to inhibit programming of the non-target memory cells may decrease. For example, with a programming voltage of 15V applied to WL4, a channel voltage of 10V may be applied to WL3 and WL5, a channel voltage of 8V may be applied to WL2 and WL6, a channel voltage of 7V may be applied to WL1 and WL7, and so on. In other examples, the channel voltage may be higher or lower, or the number of word lines may be greater or less, etc.
Sense amplifiers or
Between the application of one or more programming pulses (e.g., Vpgm), a verify operation can be performed to determine whether the selected memory cell has reached its intended programmed state. If the selected memory cell has reached its intended programmed state, further programming may be inhibited. Additional programming pulses may be applied if the selected memory cell has not reached its intended programmed state. If the selected memory cells have not reached their intended programmed state after a certain number of programming pulses (e.g., a maximum number), the selected memory cells, or the strings, blocks, or pages associated with these selected memory cells, can be marked as "defective".
To erase a memory cell or group of memory cells (e.g., erase is typically performed in blocks or sub-blocks), an erase voltage (Vers) (e.g., typically Vpgm) may be applied to the substrate (and thus to the channel between the source and drain) of the memory cell targeted for erase (e.g., using one or more bit lines, select gates, etc.) while the word line of the targeted memory cell is held at, for example, a ground potential (e.g., Vss) potential, causing charge to be transferred (e.g., directly such as or fowler-nordheim (FN) tunneling, etc.) from the floating gate of the targeted memory cell to the channel.
Fig. 4 illustrates an example block diagram of a
The
The
One or more devices external to
The
Fig. 5 illustrates a block diagram of an
Examples described herein may include or be operable with logic, components, devices, packages, or mechanisms. A circuit system is a group (e.g., set) of circuits implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). The circuitry composition can be flexibly changed over time and has potential hardware variability. The circuitry includes components that, when operated, may perform particular tasks either individually or in combination. In an example, the hardware of the device circuitry may be permanently designed to implement a particular operation (e.g., hardwired). In an example, hardware of a circuitry may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including computer-readable media physically modified (e.g., magnetically modified, electrically modified, movably placed mass invariant particles, etc.) to encode instructions for a particular operation. When physical components are connected, the underlying electrical properties of the hardware components change, for example, from an insulator to a conductor or vice versa. The instructions enable the participating hardware (e.g., execution units or loading mechanisms) to form components of the circuitry in hardware via the variable connections to perform portions of specific tasks in operation. Thus, when the device is operating, the computer-readable medium is the other component communicatively coupled to the circuitry. In an example, any of the physical components may be used in more than one component of more than one circuitry. For example, in operation, an execution unit may be used at one point in time for a first circuit of a first circuitry, and reused at a different time by a second circuit of the first circuitry or by a third circuit in a second circuitry.
A machine (e.g., computer system) 500 (e.g.,
The
While the machine-
The term "machine-readable medium" may include any medium that is capable of storing, encoding or carrying instructions for execution by the
Instructions 524 (e.g., software, programs, an Operating System (OS), etc.) or other data stored on the
In contrast to virtual memory, virtual memory compression (e.g.,
Storage devices optimized for mobile electronic devices or mobile storage devices typically include MMC solid state storage devices (e.g., micro secure digital (micro SD)TM) Card, etc.). MMC devices include a number of parallel interfaces (e.g., 8-bit parallel interfaces) that connect with a host device, and are typically components that are removable and separable from the host device. In contrast, eMMCTMThe device is attached to a circuit board and is considered as a component of a host device, having a connection to an ATA-basedTMSSD devices (serial AT (advanced technology) attachment or SATA) have comparable read speeds. However, there is an increasing demand for mobile device performance, for example, to fully enable virtual devices or augmented reality devices, take advantage of increasing network speeds, and the like. In response to this request, the memory device has been transitioned from a parallel communication interface to a serial communication interface. A universal flash memory (UFS) device, including a controller and firmware, communicates with a host device using a Low Voltage Differential Signaling (LVDS) serial interface with a dedicated read/write path, further facilitating greater read/write speeds.
The
FIG. 6 is a block diagram of a
The
In various embodiments,
In various embodiments, the erase and verify operations may be performed by the plurality of blocks in response to the
Operations for performing erase and verify operations in sequence based on instructions in
Operations to perform erase and verify operations may include: starting with the first block, generating an erase pulse followed by a verify pulse for each block in the list, and then proceeding to the next block in the list; after each block is erased and verified, the count of the block counter is incremented by "1"; and terminating the erase and verify operations on the plurality of blocks when the count of the block counter is greater than the count limit. Operations for performing erase and verify operations in sequence based on instructions in
Operations to perform erase and verify operations may include: starting with the first block, generating an erase pulse followed by a verify pulse for each block in the list, and then proceeding to the next block of the list; after each block is erased and verified, the count of the block counter is incremented by "1"; and terminating the erase and verify operations on the plurality of blocks when the count of the block counter is greater than the count limit.
The operation of generating the initial set of parameters when performing erase and verify operations in sequence may include: identifying a first block of the consecutive blocks as a starting block for erasing the plurality of blocks; and identifying a second block of the consecutive blocks as an end block when erasing the plurality of blocks. The operation of performing the erase and verify operations while sequentially performing the erase and verify operations includes: generating an erase pulse followed by a verify pulse for each of the successive blocks, then proceeding to a next one of the successive blocks; and terminating the erase and verify operations after erasing the second block.
The operation of generating the initial set of parameters when performing erase and verify operations in sequence may include: a chip erase operation is identified in which the starting block in the sequential erase is block zero of the memory device and the ending block in the sequential erase is the last block of the memory device. The block zero and the end block may be associated with a user accessible memory block.
In various embodiments,
Generating the initial set of parameters may include: multiple blocks for erase are identified in several different formats that can support the method of performing the erase operation. Generating the initial set of parameters may include: a plurality of blocks are identified for erasure by a block list. Generating the initial set of parameters may include: identifying a first block of the consecutive blocks as a starting block for erasing the plurality of blocks; and identifying a second block of the consecutive blocks as an end block of the erasing of the plurality of blocks. Generating the initial set of parameters may include: a chip erase operation is identified, where at erase time, the starting block is block zero and the ending block is the last block of the memory device. The block zero and the end block may be associated with a user accessible memory block.
The operations may include the following operations: in erasing the plurality of blocks, one of the plurality of blocks is set to be unusable in response to determining that the block passes verification to receive another erase pulse. The operations may include the following operations: each block that passes verification after erase is marked as a bad block to make the respective block unavailable to receive another erase pulse. The operations may include the following iterative procedure: maintaining the block that failed verification after erase as a usable block to receive another erase pulse; generating an additional erase pulse for an available block and serially verifying the available block after generating the additional erase pulse; and marking each usable block that passes verification after the additional erase pulse as a bad block to be unavailable to receive another additional erase pulse. The iterative procedure may be ended immediately after determining that each of the plurality of blocks is marked as a bad block or after determining that a maximum loop count for the iterative procedure is reached.
FIG. 7 is a flow diagram of features of an embodiment of an
At 710, an initial set of parameters for erasing a plurality of memory blocks of a memory device is generated. At 720, the erase and verify operations are performed on a plurality of blocks by sequentially erasing and verifying each block of the plurality of blocks in response to receiving a command to perform the erase and verify operations on the plurality of blocks.
FIG. 8 is a flow diagram of features of an embodiment of an
At 810, an initial set of parameters for erasing a plurality of memory blocks of a memory device is generated. At 820, an erase pulse is simultaneously provided for each of the plurality of blocks. At 830, erase of each of the plurality of blocks is serially verified after the erase pulse is issued.
A variation of
FIG. 9 is a flow diagram of features of an embodiment of an
At 905, parameters of the erase operation are initialized. Internal variables are initialized for start and stop limits or for addresses in a list of multiple blocks to be erased. The identification codes of the blocks may be provided with the command to perform the erasure. Initialization may also include arranging for erase operations on the plurality of blocks to use a sequential erase and verify algorithm and/or to choose to use RMBE, LMBE, or CE. In RMBE, the start block address and stop block address can be identified to define the start and stop of RMBE operations. In LMBE, a list of memory blocks to be erased is identified, and the number of blocks in the list is determined, and a block counter is established that sets the number of blocks to a threshold value to define the end of the erase operation using the block counter. In CE, among the algorithms stored in firmware, which consider memory blocks allocated as user memory, the algorithms may have memory addresses starting from zero block to the last block. In a sequential erase operation, the starting block of an erase may be set equal to the "zero" block of the user block and the ending block may be set equal to the last block of the user block. The last block of the user block may be hard-coded in firmware. When running CE, the host is independent of NAND geometry, i.e. number of blocks, since all user blocks are erased.
After initializing the parameters with the sequential erase and verify method selected, execution of the algorithm is done in the algorithm loop for the blocks included in the list, in the range, or for all user blocks. Since the external device or apparatus provides the identification codes of the blocks to the memory system for RMBE or LMBE, the list or range may be referred to as a user list or user range.
At 910, it is determined whether all blocks of the user list, all blocks in the range, or all user blocks have been erased according to the use of RMBE, LMBE, or CE. If the determination is "yes," i.e., all blocks are erased, then at 930, execution of the sequential erase and verify algorithm is ended and the processor returns to performing other functions of the memory system, which may include an additional plurality of block erases or chip erases in response to another command received. During an erase operation in a memory device, the processor may perform other functions of the memory device or functions of other memory devices in a memory system in which the memory device is located. If the determination is "no," the processor continues to execute the loop of the selected algorithm. In some embodiments, if the selected algorithm is the only MBE algorithm in the firmware of the memory system, then this algorithm is the actual choice. In the case of an initial pass through the loop, the block operated on as the first block in the range, or the first block, is associated with the beginning of the block counter in the order in which the range is processed.
At 915, the identification of the block address of the current block to be processed is obtained from the list or range, and this updates the current block for processing. Updating the current block may include marking this current block and/or removing previously processed blocks from the list or range (which for the CE is all user blocks). At 920, the block with the current block address is erased and verified before proceeding to the next block in the list or range.
At 925, the next block that may be processed is marked and the loop proceeds to 910. For RMBE, a block address equal to the next block address in memory may be generated and used to further erase a block of the plurality of blocks, or as an interrupt condition when processing the loop. For LMBE, a block counter may be updated for identifying the next block to be processed, or as an interrupt condition when processing the loop. For a CE, a block address equal to the next block address in memory may be generated and used to further erase a block of the plurality of blocks, or as an interrupt condition when processing the loop. For the CE, if the currently erased block is the last block, the next block may be set to the last block address or to an address beyond the last block address even though the memory may not have such an address, or may be set to an address beyond the address of the last user block if a block address larger than the address of the last block of the user block exists in the memory.
At 910, it is determined whether all blocks in the user list, all blocks in the range, or all user blocks have been erased as part of an iterative process in a loop based on the use of RMBE, LMBE, or CE. This determination provides an interrupt condition to exit the loop. For RMBE, the interrupt condition is to determine that the actual block set at 925 in the loop is greater than the end block of the identified range of the plurality of blocks being erased. That is, the pointers for the blocks in the range indicate the range in terms of the next block set at 925. For LMBE, an interrupt condition occurs when the count in the block counter set at 925 is greater than the threshold count at initialization, where the threshold is the number of block entries in the list of block entries. For the CE, the interrupt condition is to determine that the actual block set at 925 in the loop is the last block of the user block or has an address greater than the address of the last user block.
FIG. 10 is a flow diagram of features of an embodiment of an
In embodiments that include parallel erase operations, erase pulses may be applied simultaneously to a series of blocks (which are multiple blocks designated for erase) so that the blocks are erased in parallel. After the erase pulse is issued, the block may be serially verified. Serial verification is the process of verifying blocks one by one from a start block to an end block. The verified block may be prevented from receiving another erase pulse for verification. Blocks that pass erase verification may be marked as bad. This allows the use of Block Disable Latches (BDLs) in parallel erase operations, similar to some processes that make it impossible to write or read unselected blocks (e.g., bad blocks) while a user is operating. For these blocks that pass erase verification, a BDL may be set for each such block, and the blocks act as unselected blocks, where these blocks do not receive another erase pulse issued for the non-verified blocks. Furthermore, pass-through blocks may still be in the validation loop because their BDL state (e.g., BDL ═ 1) does not allow actions to be performed on these blocks.
The set of initially identified blocks of the plurality of blocks that failed its erase verify process may be given another erase pulse. If one or more BDLs remain zero, allowing the operation to access its corresponding block, the algorithm may continue to loop, where the loop includes applying erase pulses and erase verifications. The algorithm for parallel erase and serial verify may end when all BDLs are set to the disable output state or when the maximum loop count is reached, which may define an interrupt condition for the algorithm. If the algorithm ends due to a timeout condition, the failed verification block may be retrieved by reading back its BDL information.
At 1005, parameters for the erase operation are initialized. Internal variables are initialized for start and stop limits or for addresses in a list of multiple blocks to be erased. The identification codes of the plurality of blocks may be provided with a command to perform an erasure. These restrictions may be used in the serial verify portion of the operation selected for the erase operation on multiple blocks. Initialization may choose to use RMBE, LMBE or CE. In RMBE, start and stop block addresses may be identified to define the start and stop of a range of blocks for which RMBE operations are performed. In LMBE, a list of memory blocks to be erased is identified. In CE, the algorithm considers memory blocks allocated as user memory, which may have memory addresses starting from zero block to the last block. In the CE, the start block for erasure may be set equal to the zero block of the user block, and the end block may be set equal to the last block of the user block. The last block of the user block may be hard-coded in firmware.
At 1007, all blocks are marked as bad, where the block is a user block. In CE, marking all blocks as bad may be skipped since all blocks are erased. At 1009, all blocks in the list of blocks or in the range of blocks are unmarked. Skipping the marking procedure in the CE undoes marking all blocks. During execution of the parallel erase/serial verify algorithm, combining the operations at 1007 and 1009 provides a memory block of the memory device that is not in the erase list or erase range, which is not selected for a memory operation. The marking of the memory block provides an input signal to the BDL of the memory block that deselects the memory block for the memory operation. For example, the BDL of a marked memory block may have a value of "1" in an unselected state, similar to a bad block state in other processes of the memory device.
At 1010, it is determined whether all blocks, blocks of the range, or all user blocks of the user list have been erased. The determination may be based on determining whether all BDLs of all memory blocks not tagged at 1009 are now in a tagged state, which may correspond to a BDL equal to "1". Alternatively, the BDL may be structured as a logic circuit that provides an unselected state corresponding to a "0". All BDLs in the flag state provide an interrupt condition for the algorithm loop. If the determination is "yes," i.e., all blocks are erased, the processor executing the algorithm stored in the firmware may begin operation to end the algorithm. The end of the algorithm may also be initiated by an interrupt condition set into the algorithm, the interrupt condition being the attainment of a maximum loop count. To begin the end of the erase process, the flags on all blocks on the memory device may be reset at 1029 immediately after determining that all blocks identified for erase have been erased. With the reset at 1029 unmarking the memory block, all memory blocks of the memory are placed in a condition of normal use as memory blocks. Beginning at 1019, execution of the parallel erase and serial verify algorithms ends, and the processor returns to performing other functions of the memory system at 1030, which may include additional multiple block erases or chip erases received in response to another command. During an erase operation in a memory device, the processor may perform other functions of the memory device, or of other memory devices of a memory system in which the memory device is located.
If the determination is "no" at 1010, the processor continues to execute the loop of the selected parallel erase/serial verification algorithm. In some embodiments, if the selected algorithm is the only MBE algorithm in the firmware of the memory system, then this algorithm is the actual choice. At 1013, all blocks of memory are selected. At 1014, an erase pulse is applied. Although all blocks are selected at 1013, only the unmarked blocks receive erase pulses applied to them in parallel. After the erase pulse is applied in parallel, it is determined at 1002 whether all blocks that receive the erase pulse have been verified. If the determination is "yes," the algorithm again checks whether all blocks have been erased at 1010.
If the determination as to whether all blocks have been verified is "no" at 1002, then at 1015, the block address of the current block to be processed is obtained from the list or range and this current block is updated for processing. At 1020, the block with the current block address is subjected to erase verification. At 1035, it is determined whether the block At the current block address passes erase verification.
If the determination at 1035 is "yes," i.e., the current block passes erase verification, then the current block is marked so that the current block will not be erase verified. The current block may be marked as a bad block. After marking the current block, at 1045, the current block may be removed from the list subject to erase verification. Beginning at 1045, the next block in the list may be selected to continue the verification process at 1025. Starting at 1025, the algorithm may again determine whether all blocks have been verified at 1002.
If the further determination at 1002 is "yes," the iterative procedure may again determine whether all blocks have been erased at 1010. If the further determination at 1002 is "NO," the iterative procedure proceeds to get the next block address again at 1015 and update the next block address as the current block address for the erase verification at 1020, and determine whether the erase verification was successful at 1035.
FIG. 11 is a block diagram illustrating an embodiment of a block disable
FIG. 12 simulates two using an example method of erasing multiple memory blocks of a memory device having parallel erase operationsErase times for different types of memory components.
FIG. 13 illustrates an embodiment of an
Using the set feature command, a user (e.g., host 605 or other device of fig. 6) that generates data to a memory system (e.g., memory system 610) may populate a
FIG. 14 illustrates an embodiment of an
Using the set feature command, a user (e.g., host 605 or other device of fig. 6) generating data to a memory system (e.g., memory system 610) can fill the scratch space in the memory system with the results of erase operations on a plurality of blocks defined by a range of start and stop block addresses. After the last verify operation, the scratch space may be filled with block addresses of failed verify blocks by instructions that execute the erase algorithm for multiple blocks, which are stored in the form of code in the firmware of the memory system. The flag may be set to a special value if the number of failed verifications exceeds the size of the scratch pad space. This may be an extreme case of a memory device crash, or operating conditions are out of specification and these block addresses of the verification block are not useful for error handling. When the multi-block erase algorithm is finished, the host can retrieve the erase result by accessing the temporary storage space according to the obtained characteristic command.
The firmware may comprise instructions, such as microcode, which when executed by a controller or processor, may cause operations to be performed, including operations associated with multiple block erase operations of a memory device of a memory system coupled to a host associated with any of fig. 1-6, methods 700-1000, methods similar to methods 700-1000, other methods, and associated device structures and data structures taught herein.
In various examples, a component, controller, processor, unit, engine, or table described herein may include physical circuitry or firmware stored on a physical device, and so forth. "processor" as used herein means any type of computational circuitry, such as, but not limited to: a microprocessor, a microcontroller, a graphics processor, a Digital Signal Processor (DSP), or any other type of processor or processing circuit, including a group of processors or multi-core devices.
As used herein, operating a memory cell includes reading, writing, or erasing the memory cell. The operation of placing a memory cell in an intended state is referred to herein as "programming," and may include writing to or erasing from the memory cell (e.g., the memory cell may be programmed to an erased state).
According to one or more embodiments, a memory controller (e.g., processor, controller, firmware, etc.) located inside or outside of a memory device is able to determine (e.g., select, set, adjust, calculate, change, clear, communicate, adapt, derive, define, utilize, modify, apply, etc.) a number of wear cycles or a wear state (e.g., record wear cycles, count operations of the memory device as they occur, track operations of the memory device initiated by the controller, evaluate memory device characteristics corresponding to the wear state, etc.).
According to one or more embodiments, a memory access device may be configured to provide wear cycle information to a memory device with each memory operation. Memory device control circuitry (e.g., control logic) can be programmed to compensate for memory device performance changes corresponding to wear cycle information. The memory device may receive wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.
The method examples described herein may be implemented at least in part by a machine or by a computer. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform the methods described in the above examples. Implementations of such methods may include code, such as microcode, assembly language code, higher level language code, and the like. This code may include computer readable instructions for performing various methods. The code may form part of a computer program product. Further, the code can be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, e.g., during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to: hard disk, removable magnetic disk, removable optical disk (e.g., compact disk and digital video disk), magnetic tape cartridge, memory card or stick, Random Access Memory (RAM), Read Only Memory (ROM), Solid State Drive (SSD), universal flash memory (UFS) device, embedded mmc (emmc), etc.
The following are example embodiments of methods, apparatuses, and systems according to the teachings herein.
Example system 2 may include the features of
Example system 3 may include features of any of the foregoing example systems and may include operations to perform erase and verify operations, including: generating an erase pulse followed by a verify pulse for each of the successive blocks, then proceeding to a next one of the successive blocks; and terminating the erase and verify operations after erasing the second block.
Exemplary system 4 may include features of any of the preceding exemplary systems and may include operations to generate the initial set of parameters, including: identifying the plurality of blocks by entries in a block list, the list having a number of blocks; identifying a first block of the number of blocks for erasing; and generating a count limit equal to the number of blocks to be erased.
Exemplary system 5 may include features of any of the foregoing exemplary systems and may include: starting with the first block, generating an erase pulse followed by a verify pulse for each block in the list, and then proceeding to the next block of the list; after each block is erased and verified, the count of the block counter is incremented by 1; and terminating the erase and verify operations on the plurality of blocks when the count of the block counter is greater than the count limit.
Example system 6 may include features of any of the foregoing example systems and may include operations to generate the initial set of parameters, including: a chip erase operation is identified in which a starting block in the sequential erase and verify is a block zero of the memory device and an ending block in the sequential erase is a last block of the memory device.
Example system 8 may include features of any of the foregoing example systems and may include a system including: a host operable to generate the command operatively received by the controller; and a communication interface coupled to the host and the controller, the communication interface arranged to transmit the command from the host to the controller.
Example method 2 may include the features of
Example method 3 may include features of any of the foregoing example methods and may include performing erase and verify operations including: generating an erase pulse followed by a verify pulse for each of the successive blocks, then proceeding to a next one of the successive blocks; and terminating the erase and verify operations after erasing the second block.
Example method 4 may include features of any of the foregoing example methods and may include generating the set of initial parameters, including: identifying the plurality of blocks by entries in a block list, the list having a number of blocks; identifying a first block of the number of blocks for erase and verification; and generating a count limit equal to the number of blocks to be erased and verified.
Example method 5 may include features of any of the foregoing example methods and may include performing erase and verify operations including: starting with the first block, generating an erase pulse followed by a verify pulse for each block in the list, and then proceeding to the next block in the list; incrementing the count of the block counter by 1 after each block is erased and verified; and terminating the erase and verify operation when the count of the block counter is greater than the count limit.
Example method 6 may include features of any of the foregoing example methods and may include generating the set of initial parameters including identifying a chip erase operation, wherein a starting block in the sequential erase and verify is a block zero and an ending block is a last block of the memory device.
Exemplary system 9 may include: a controller; a memory device; and firmware storing instructions executable by the controller to operate the memory device, the instructions including the operations of: generating an initial set of parameters for erasing a plurality of memory blocks of the memory device; simultaneously providing an erase pulse to each of the plurality of blocks; and serially verifying the erase of each of the plurality of blocks after issuing the erase pulse.
Exemplary system 11 may include features of any of the foregoing
Example system 12 may include features of any of the foregoing example systems 9-11 and may include operations comprising an iterative procedure that is: maintaining blocks that fail verification after erase as usable blocks to receive another erase pulse; generating an additional erase pulse for the usable block and serially verifying the usable block after generating the additional erase pulse; and marking each available block that passes verification after the additional erase as a bad block to be unavailable to receive another additional erase pulse.
Exemplary system 13 may include features of any of the foregoing exemplary systems 9-12 and may include: ending the iterative procedure immediately after determining that each block of the plurality of blocks is marked as a bad block or after determining that a maximum loop count of the iterative procedure is reached.
Exemplary system 14 may include features of any of the foregoing exemplary systems 9-13 and may include generating the initial set of parameters including: identifying a first block of the consecutive blocks as a starting block for erasing the plurality of blocks; and identifying a second block of the consecutive blocks as an end block of the erasing of the plurality of blocks.
Exemplary system 15 may include features of any of the foregoing exemplary systems 9-14 and may include generating the initial set of parameters including identifying the plurality of blocks for erasure by a list of blocks.
Example method 8 may include features of
Example method 9 may include features of any of the foregoing
Example method 11 may include features of any of the foregoing example methods 7-10 and may include: ending the iterative procedure immediately upon determining that each block of the plurality of blocks is marked as a bad block or determining that a maximum loop count of the iterative procedure is reached.
Exemplary method 12 may include features of any of the foregoing exemplary methods 7-11 and may include generating the initial set of parameters, including: identifying a first block of the consecutive blocks as a starting block for erasing the plurality of blocks; and identifying a second block of the consecutive blocks as an end block of the erasing of the plurality of blocks.
Example method 13 may include features of any of the foregoing example methods 7-12 and may include generating the initial set of parameters including identifying the plurality of blocks in a block list for erasure.
Exemplary method 14 may include features of any of the foregoing exemplary methods 7-13 and may include generating the initial set of parameters, including: a chip erase operation is identified in which the starting block in the sequential erase is block zero and the ending block is the last block of the memory device.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiments shown. Various embodiments use permutations and/or combinations of the embodiments described herein. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description. In addition, in the foregoing detailed description, it can be appreciated that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.
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