阅读说明：本技术 集成芯片和形成集成芯片的方法 (Integrated chip and method for forming integrated chip ) 是由 吴伟成 邹百骐 于 2019-06-27 设计创作，主要内容包括：在一些实施例中,本发明涉及集成电路。集成电路包括位于衬底内的第一掺杂区域和第二掺杂区域。FeRAM(铁电随机存取存储器)器件布置在第一掺杂区域和第二掺杂区域之间的衬底上方。该FeRAM器件具有铁电材料和导电电极。铁电材料布置在衬底上方,并且导电电极布置在铁电材料上方并且布置在铁电材料的侧壁之间。本发明的实施例还涉及集成芯片和形成集成芯片的方法。(In some embodiments, the invention relates to integrated circuits. The integrated circuit includes a first doped region and a second doped region within a substrate. A FeRAM (ferroelectric random access memory) device is disposed over the substrate between the first doped region and the second doped region. The FeRAM device has a ferroelectric material and a conductive electrode. A ferroelectric material is disposed over the substrate, and a conductive electrode is disposed over the ferroelectric material and between sidewalls of the ferroelectric material. Embodiments of the invention also relate to integrated chips and methods of forming integrated chips.)

1. An integrated chip, comprising:

a first doped region and a second doped region within the substrate; and

a ferroelectric random access memory (FeRAM) device disposed over the substrate between the first doped region and the second doped region, the ferroelectric random access memory device comprising:

a ferroelectric material disposed over the substrate; and

a conductive electrode over the ferroelectric material and between sidewalls of the ferroelectric material.

2. The integrated chip of claim 1, wherein the chip is a chip,

wherein the substrate has a recessed surface extending between a first sidewall and a second sidewall of the substrate to define a recessed region within an upper surface of the substrate; and

wherein the ferroelectric random access memory device is disposed above the recessed surface and is disposed directly intermediate the first sidewall and the second sidewall.

3. The integrated chip of claim 2, further comprising:

a first isolation structure disposed within a semiconductor substrate and defining a first sidewall of the substrate; and

a second isolation structure disposed within the semiconductor substrate and defining a second sidewall of the substrate.

4. The integrated chip of claim 3, wherein the first sidewall of the substrate is oriented at an angle such that a width of the first isolation structure decreases with increasing height above the recessed surface.

5. The integrated chip of claim 4, wherein the recessed surface of the substrate is defined by a first horizontally extending surface of the first isolation structure, a second horizontally extending surface of the second isolation structure, and a third horizontally extending surface of the semiconductor substrate.

6. The integrated chip of claim 5, further comprising:

a replacement gate residue extending from above the first horizontally extending surface of the first isolation structure to above a third horizontally extending surface of the semiconductor substrate, wherein the replacement gate residue has a metal cap layer disposed between a dielectric film and a sacrificial polysilicon layer.

7. The integrated chip of claim 1, further comprising:

sidewall spacers having one or more dielectric materials disposed on opposite sides of the ferroelectric random access memory device; and

an etch stop layer laterally separated from the ferroelectric random access memory device by the sidewall spacer, the etch stop layer not covering the ferroelectric random access memory device.

8. The integrated chip of claim 1, further comprising:

a transistor device having a gate electrode disposed over the substrate; and

an interlayer dielectric (ILD) layer laterally surrounding the ferroelectric random access memory device and the transistor device, wherein the gate electrode and the ferroelectric random access memory device extend to an upper surface of the interlayer dielectric layer.

9. An integrated chip, comprising:

a substrate having a recessed surface extending between a first sidewall and a second sidewall to define a recessed region recessed below an upper surface of the substrate;

a first doped region and a second doped region disposed within a recessed surface of the substrate;

a ferroelectric material disposed between the first doped region and the second doped region, wherein the ferroelectric material has sidewalls defining a first recess within an upper surface of the ferroelectric material;

a metallic material nested within the first recess, wherein the metallic material has sidewalls defining a second recess within an upper surface of the metallic material; and

a conductive material nested within the second recess.

10. A method of forming an integrated chip, comprising:

forming a sacrificial memory structure over the substrate;

forming an inter-layer dielectric (ILD) layer over the substrate laterally surrounding the sacrificial memory structure;

removing the sacrificial memory structure to form a memory device cavity surrounded by the interlayer dielectric layer;

forming a ferroelectric layer over the interlayer dielectric layer and within the memory device cavity;

forming a metal layer over the ferroelectric layer and within the memory device cavity;

forming a conductive layer over the metal layer and within the memory device cavity; and

removing a portion of the ferroelectric layer, the metal layer, and the conductive layer from over the interlayer dielectric layer to define a ferroelectric random access memory device having a metal disposed between a ferroelectric material and a conductive material.

Technical Field

Embodiments of the invention relate to integrated chips and methods of forming integrated chips.

Background

Many modern electronic devices contain electronic memory configured to store data. The electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data when power is applied, while non-volatile memory is capable of storing data when power is removed. Ferroelectric random access memory (FeRAM) devices are promising candidates for next generation non-volatile storage technologies. This is because FeRAM devices have many advantages, including fast write time, high endurance, low power consumption, and low sensitivity to radiation damage.

Disclosure of Invention

An embodiment of the present invention provides an integrated chip, including: a first doped region and a second doped region within the substrate; and a ferroelectric random access memory (FeRAM) device disposed over the substrate between the first doped region and the second doped region, the ferroelectric random access memory device comprising: a ferroelectric material disposed over the substrate; and a conductive electrode located over the ferroelectric material and between sidewalls of the ferroelectric material.

Another embodiment of the present invention provides an integrated chip, including: a substrate having a recessed surface extending between a first sidewall and a second sidewall to define a recessed region recessed below an upper surface of the substrate; a first doped region and a second doped region disposed within a recessed surface of the substrate; a ferroelectric material disposed between the first doped region and the second doped region, wherein the ferroelectric material has sidewalls defining a first recess within an upper surface of the ferroelectric material; a metallic material nested within the first recess, wherein the metallic material has sidewalls defining a second recess within an upper surface of the metallic material; and a conductive material nested within the second recess.

Yet another embodiment of the present invention provides a method of forming an integrated chip, comprising: forming a sacrificial memory structure over the substrate; forming an inter-layer dielectric (ILD) layer over the substrate laterally surrounding the sacrificial memory structure; removing the sacrificial memory structure to form a memory device cavity surrounded by the interlayer dielectric layer; forming a ferroelectric layer over the interlayer dielectric layer and within the memory device cavity; forming a metal layer over the ferroelectric layer and within the memory device cavity; forming a conductive layer over the metal layer and within the memory device cavity; and removing a portion of the ferroelectric layer, the metal layer, and the conductive layer from over the interlayer dielectric layer to define a ferroelectric random access memory device having a metal disposed between a ferroelectric material and a conductive material.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of some embodiments of an integrated chip having a ferroelectric random access memory (FeRAM) device with nested electrodes.

Fig. 2 shows a cross-sectional view of some additional embodiments of an integrated chip having an embedded FeRAM device with nested electrodes.

Fig. 3 illustrates a cross-sectional view of some alternative embodiments of an integrated chip having an embedded FeRAM device with nested electrodes.

Fig. 4-16 illustrate cross-sectional views of some embodiments of methods of forming integrated chips having embedded FeRAM devices with nested electrodes.

Fig. 17-34 illustrate cross-sectional views of some alternative embodiments of methods of forming integrated chips having embedded FeRAM devices with nested electrodes.

Fig. 35 illustrates a flow diagram of some embodiments of a method of forming an integrated chip having an embedded FeRAM device with nested electrodes.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Embedded memory has become common in modern integrated chips. Embedded memory is an electronic memory device that is located on the same integrated chip die as a logic device (e.g., a processor or ASIC). By embedding the memory device and the logic device on the same integrated chip die, the conductive interconnections between the memory device and the logic device may be shortened, thereby reducing power and improving performance of the integrated chip.

Many modern integrated chips use flash memory in embedded memory systems due to their non-volatility (i.e., their ability to retain stored data states without power), their high density, their fast write speeds, and their compatibility with modern CMOS fabrication processes. However, embedded flash memories are formed by relatively complex processes that may use a large number of masks (e.g., greater than 15 or 20 masks). The complexity of this process results in a high cost of forming embedded flash memories.

In some embodiments, the present invention relates to an integrated chip having an embedded FeRAM device that is formed using a relatively simple fabrication process. A relatively simple fabrication process is performed by replacing the sacrificial memory structure with a FeRAM device prior to forming the high-k metal gate logic device. The process results in a FeRAM device having a nested structure that includes a ferroelectric layer (having sidewalls in an upper surface of the ferroelectric layer defining a recess), and a conductive electrode nested within the recess. Forming the FeRAM device using an alternative process allows the FeRAM device to be formed in an efficient manner (e.g., between 10% and 30% of the photomask used in the embedded flash memory fabrication process may be used to form the embedded FeRAM device), which allows the embedded FeRAM device to be manufactured at low cost.

Fig. 1 illustrates a cross-sectional view of some embodiments of an integrated chip 100 having a ferroelectric random access memory (FeRAM) device with nested electrodes.

The integrated chip 100 includes a substrate 101, the substrate 101 having one or more isolation structures 106 a-106 b disposed within a trench in a semiconductor substrate 102. In some embodiments, the substrate 101 can have a recessed surface 101a extending between the first sidewall 101b and the second sidewall 101c to define a recessed region 104, the recessed region 104 being recessed a non-zero distance d below an upper surface 101u of the substrate 101. In some embodiments (not shown), the first and second sidewalls 101b, 101c may comprise tapered (i.e., angled) sidewalls that cause the width of the recessed region 104 to decrease as the depth of the recessed region 104 increases.

In some embodiments, one or more isolation structures 106 a-106 b may be disposed along an edge of the recessed region 104 of the semiconductor substrate 102. In some such embodiments, the first isolation structure 106a and the second isolation structure 106b may comprise the same isolation structure that extends continuously in a closed loop around the boundary of the recessed region 104. In some embodiments, the one or more isolation structures 106 a-106 b may include shallow trench isolation structures having one or more dielectric materials disposed within trenches in the semiconductor substrate 102.

The FeRAM device 110 is disposed over the substrate 101 between the first doped region 108a and the second doped region 108b within the recessed surface 101 a. The FeRAM device 110 includes a ferroelectric material 112, the ferroelectric material 112 having sidewalls defining a recess within an upper surface of the ferroelectric material 112. The conductive electrode 114 is nested within the recess. In some embodiments, the conductive electrode 114 may directly contact the upper surface and sidewalls of the ferroelectric material 112. In some embodiments, the ferroelectric material 112 and the conductive electrode 114 have uppermost surfaces that are substantially coplanar (e.g., coplanar within the tolerances of a chemical mechanical planarization process).

Nesting the conductive electrode 114 of the FeRAM device 110 within the ferroelectric material 112 allows the FeRAM device 110 to be formed by an efficient manufacturing process using a relatively small number of photomasks (e.g., between 2 and 5 photomasks). Further, while the FeRAM device 110 may have a greater height than the logic devices (e.g., MOSFETs) on the integrated chip 100, positioning the FeRAM device 110 within the recessed region 104 allows the FeRAM device 110 to be formed without affecting the logic devices.

An interlayer dielectric (ILD) structure 118 is disposed over the substrate 101 and laterally surrounds the FeRAM device 110. A conductive contact 120 extends through the ILD structure 118 to contact the first doped region 108a, the second doped region 108b and the conductive electrode 114.

During operation, a bias voltage may be applied to one or more of the first doped region 108a, the second doped region 108b, and/or the conductive electrode 114. For example, in some embodiments, a bias voltage may be applied to the first doped region 108a, the second doped region 108b, and the conductive electrode 114, while in other embodiments, a bias voltage may be applied to the first doped region 108a and the conductive electrode 114 without being applied to the second doped region 108 b. The bias voltage allows data states to be written to and/or read from the FeRAM device 110. For example, during a write operation, one or more bias voltages may be applied to cause charge carriers (e.g., electrons and/or holes) to accumulate between the first and second doped regions 108a and 108 b. The charge carriers generate an electric field that extends through the ferroelectric material 112. The electric field is configured to change the position of the electric dipole within the ferroelectric material 112 according to the bias voltage. If the magnetic polarization of the ferroelectric material 112 has a first polarization for a particular bias voltage, the FeRAM device 110 digitally stores the data state as a first bit value (e.g., a logic "0"). Alternatively, if the magnetic polarization of the ferroelectric material 112 has a second polarization for a different bias voltage than previously, the FeRAM device 110 digitally stores the data state as a second bit value (e.g., a logic "1").

Fig. 2 shows a cross-sectional view of some additional embodiments of an integrated chip 200 having an embedded FeRAM device with nested electrodes.

The integrated chip 200 includes a substrate 101, the substrate 101 having one or more isolation structures 106 a-106 c disposed within a trench in a semiconductor substrate 102. One or more isolation structures 106 a-106 c separate the embedded memory region 201a from the logic region 201 b. Within the embedded memory region 201a, the substrate 101 may have a recessed surface 101a extending between the first sidewall 101b and the second sidewall 101c to define a recessed region 104, the recessed region 104 being recessed below an upper surface 101u of the substrate 101. In some embodiments, one or more isolation structures 106 a-106 c may include Shallow Trench Isolation (STI) structures having a substantially planar bottom surface (i.e., a bottom surface substantially parallel to upper surface 101 u) extending between opposing sidewalls.

In some embodiments, the isolation structures 106 a-106 c may define a first sidewall 101b of the substrate 101 and a second sidewall 101c of the substrate 101. The isolation structures 106 a-106 b may further define a horizontally extending surface 101a connected to the first sidewall 101b or the second sidewall 101 c. Replacement gate residue 202 may be disposed over horizontally extending surface 101 a. In some embodiments, replacement gate residue 202 may include dielectric film 204, metal cap layer 206, and sacrificial layer 208. In some embodiments, the dielectric film 204 comprises a high-k dielectric such as hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, aluminum oxide, zirconium oxide, and the like. In some embodiments, the metal cap layer 206 may comprise titanium nitride, tantalum nitride, or the like. In some embodiments, the sacrificial layer 208 may comprise polysilicon or the like.

In some embodiments, replacement gate residue 202 includes tapered sidewalls facing recessed region 104. For example, in some embodiments, the dielectric film 204 and the metal cap layer 206 may include a horizontally extending segment and a vertically extending segment, respectively, that protrude outward from an upper surface of the horizontally extending segment, while the sacrificial layer 208 has tapered sidewalls that extend between the horizontally extending segment and the vertically extending segment of the metal cap layer 206.

In some embodiments, replacement gate residue 202 extends from directly above the horizontally extending surface of isolation structures 106 a-106 b of substrate 101 to directly above the horizontally extending surface of semiconductor substrate 102. In some such embodiments, the replacement gate residue 202 is disposed over a region 203 of the semiconductor substrate 102 between the first doped region 108a and the first isolation structure 106a and/or between the second doped region 108b and the second isolation structure 106 b.

The FeRAM device 110 is disposed over a recessed surface 101a of the substrate 101 defining the recessed region 104. The FeRAM device 110 includes a ferroelectric material 112 disposed between the first doped region 108a and the second doped region 108 b. The ferroelectric material 112 has sidewalls that define a recess in the uppermost surface of the ferroelectric material 112. The conductive electrode 114 is disposed within the recess.

In some embodiments, conductive electrode 114 includes a metallic material 210 and a conductive material 212. The conductive material 212 is vertically and laterally separated from the ferroelectric material 112 by the metal material 210. In some embodiments, ferroelectric material 112 has sidewalls defining a first recess within an upper surface of ferroelectric material 112, metal material 210 is nested within the first recess and has sidewalls defining a second recess within the upper surface of metal material 210, and conductive material 212 is nested within the second recess. In some embodiments, ferroelectric material 112 has a higher height than metal material 210 and conductive material 212. In some such embodiments, ferroelectric material 112, metallic material 210, and conductive material 212 may have uppermost surfaces that are substantially coplanar.

In various embodiments, ferroelectric material 112 may include lead titanate, lead zirconate titanate (PZT), lead lanthanum zirconate titanate, Strontium Bismuth Tantalate (SBT), lanthanum bismuth titanate (BLT), bismuth neodymium bismuth titanate (BNT), and the like. In some embodiments, the metallic material 210 may include one or more metals, such as aluminum, ruthenium, palladium, hafnium, zirconium, titanium, and the like. In some embodiments, the conductive material 212 may include aluminum, copper, or the like.

Transistor device 214 is disposed within logic region 201 b. Transistor device 214 includes a gate structure 216, gate structure 216 disposed over upper surface 101u of semiconductor substrate 102 between source region 218a and drain region 218 b. The gate structure 216 includes a gate electrode 220 separated from the semiconductor substrate 102 by a gate dielectric 222 and a metal cap 223. In some embodiments, gate electrode 220 may comprise a metal gate electrode (e.g., comprising aluminum, ruthenium, palladium, etc.), and gate dielectric 222 may comprise a high-k dielectric (e.g., comprising aluminum oxide, hafnium oxide, etc.). In other embodiments, the gate electrode 220 may comprise a polysilicon gate electrode and the gate dielectric 222 may comprise an oxide (e.g., silicon dioxide). In some embodiments, metal cap 223 may comprise titanium nitride, tantalum nitride, and the like.

Sidewall spacers 116 are disposed along opposite sides of the FeRAM device 110 and the transistor device 214. In some embodiments, the sidewall spacers 116 may include a first dielectric material 224 and a second dielectric material 226. In some embodiments, the first dielectric material 224 may comprise a different dielectric material (e.g., silicon nitride) than the second dielectric material 226 (e.g., silicon oxide). In some embodiments, the FeRAM device 110 and the transistor device 214 may be separated from the semiconductor substrate 102 by a first dielectric layer 228 extending over the semiconductor substrate 102 and over the one or more isolation structures 106. In some embodiments, the first dielectric layer 228 may include an oxide (e.g., silicon oxide) or other dielectric material.

A first interlayer dielectric (ILD) layer 230 is laterally separated from the FeRAM device 110 and the gate electrode 220 by one or more sidewall spacers 116. Ferroelectric material 112, metal material 210 and conductive material 212 and gate electrode 220 extend to an upper surface of first ILD layer 230. In some embodiments, an Etch Stop Layer (ESL)232 may be disposed between the sidewall spacers 116 and the first ILD layer 230. In some embodiments, the upper surface of ESL 232 may be substantially coplanar with the upper surfaces of ferroelectric material 112, metallic material 210, and conductive material 212. A second ILD layer 234 is situated over the first ILD layer 230. The second ILD layer 234 surrounds the conductive contacts 120, the conductive contacts 120 extending to the FeRAM device 110 and the transistor device 214. In some embodiments, the first ILD layer 230 and/or the second ILD layer 234 may comprise borophosphosilicate glass (BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), or the like. In some embodiments, the conductive contacts 120 may comprise a metal, such as tungsten, copper, or the like.

Fig. 3 illustrates a cross-sectional view of some alternative embodiments of an integrated chip 300 having an embedded FeRAM device with nested electrodes.

The integrated chip 300 includes a substrate 101 having an embedded memory region 201a and a logic region 201 b. Within the embedded memory region 201a, the FeRAM device 110 is disposed over a recessed surface 101a of the substrate 101, the recessed surface 101a extending between the first sidewall 101b and the second sidewall 101 c. The FeRAM device 110 includes a ferroelectric material 112, a metallic material 210, and a conductive material 212. The ferroelectric material 112 has a horizontally extending section extending between first and second vertical protrusions protruding outward from an upper surface of the horizontally extending section. In some embodiments, the height h of the horizontally extending section₁Is greater than the width w of the first vertical protrusion and/or the second vertical protrusion₁。

One or more isolation structures 302 a-302 b are disposed within the semiconductor substrate 102 and define a first sidewall 101b of the substrate 101 and a second sidewall 101c of the substrate 101. In some embodiments, the first sidewall 101b and the second sidewall 101c are oriented at an acute angle θ relative to a line 306 perpendicular to the recessed surface 101a of the substrate 101. In some embodiments, the acute angle θ may be in a range between about 10 ° and about 80 °. In other embodiments, the acute angle θ may be in a range between about 30 ° and about 60 °. In some embodiments, the angled orientation of first sidewall 101b and second sidewall 101c may be such that the width of isolation structures 302 a-302 b, respectively, decreases with increasing height above recessed surface 101 a. In some embodiments, one or more of the isolation structures 302 a-302 b may have an angled lower sidewall 304.

Fig. 4-16 illustrate cross-sectional views 400-1600 of some embodiments of a method of forming an integrated chip having an embedded FeRAM device with nested electrodes. The method forms a FeRAM device using an alternative process performed prior to forming a high-k metal gate device. The method allows for the formation of FeRAM devices using a minimum of photomasks (e.g., between 2 and 5 photomasks). Although fig. 4-16 are described with reference to a method, it should be understood that the structure disclosed in fig. 4-16 may not be limited to such a method, but may exist separately as a structure independent of the method.

As shown in cross-sectional view 400 of fig. 4, a substrate 101 is provided. In various embodiments, the semiconductor substrate 102 may include any type of semiconductor body (e.g., silicon/CMOS body, SiGe, SOI, etc.), such as a semiconductor wafer or one or more dies on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or associated therewith.

One or more isolation structures 106 a-106 c are formed within one or more trenches 402 in the semiconductor substrate 102. In some embodiments, the one or more isolation structures 106 a-106 c are formed by selectively exposing the semiconductor substrate 102 to a first etchant to form the recess 402 according to a first mask layer, the trench 402 being subsequently filled with one or more dielectric materials. In various embodiments, the first mask layer may include photoresist, silicon nitride, silicon carbide, titanium nitride, and the like. One or more isolation structures 106 a-106 c are laterally disposed between the embedded memory region 201a and the logic region 201 b. In various embodiments, the first etchant may include a dry etchant having an etching chemistry including fluorine species (e.g., CF), or a wet etchant including hydrofluoric acid (HF), potassium hydroxide (KOH), or the like₄、CHF₃、C4F₈Etc.).

As shown in the cross-sectional view 500 of fig. 5, the embedded memory region 201a is recessed below the upper surface 102u of the semiconductor substrate 102. The embedded memory region 201a is recessed to form a recessed region 104 within the substrate 101, the recessed region 104 being recessed a non-zero distance d below the upper surface 102u of the semiconductor substrate 102. In some embodiments, the non-zero distance d may be greater than about 10 nm. The recessed region 104 is defined by sidewalls 101b and 101c and a recessed surface 101a of the substrate 101. In some embodiments, the selectivity may be increased by forming a second mask layer 502 over the substrate 101The substrate 101 is exposed to a second etchant to recess the embedded memory regions 201 a. In various embodiments, the second etchant may include a dry etchant or a wet etchant including hydrofluoric acid (HF), potassium hydroxide (KOH), etc. with an etching chemistry including a fluorine species (e.g., CF)₄、CHF₃、C₄F₈Etc.). In some embodiments, second mask layer 502 may comprise photoresist, silicon nitride, silicon carbide, titanium nitride, tantalum nitride, and the like.

As shown in cross-sectional view 600 of fig. 6, a first dielectric layer 228 is formed over the substrate 101. The first dielectric layer 228 is disposed along the horizontally extending surface and the vertically extending surface of the substrate 101. A dielectric film 602 is formed over the first dielectric layer 228, a metal cap layer 604 is formed over the dielectric film 602, and a sacrificial layer 606 is formed over the metal cap layer 604. In some embodiments, the first dielectric layer 228 may include an oxide (e.g., silicon oxide, etc.) formed by a thermal process. In some embodiments, the dielectric film 602 may include a high-k dielectric material such as, for example, aluminum oxide, hafnium oxide, etc., formed by a deposition process (e.g., ALD, CVD, PE-CVD, PVD, etc.). In some embodiments, the metal cap layer 604 may comprise titanium nitride, tantalum nitride, or the like, formed by a deposition process. In some embodiments, the sacrificial layer 606 may comprise polysilicon formed by a deposition process. In some embodiments, the sacrificial layer 606 may have sidewalls that define a recess 608 over the recessed region 104.

As shown in cross-section 700 of fig. 7, a first planarization process is performed on sacrificial layer 702 along line 704. The first planarization process removes a portion of the sacrificial layer (606 of fig. 6) to give the sacrificial layer 702 a flat upper surface 702u, the flat upper surface 702u extending continuously over the embedded memory region 201a and over the logic region 201 b. In some embodiments, the first planarization process may include a Chemical Mechanical Planarization (CMP) process. In some embodiments, a first planarization process may be performed before patterning the sacrificial layer (as shown in fig. 8). In other embodiments (not shown), the first planarization process may be performed after patterning the sacrificial layer (as shown in fig. 8).

As shown in the cross-sectional view 800 of fig. 8, the sacrificial layer (702 of fig. 7), the dielectric film (602 of fig. 7), and the metal cap layer (604 of fig. 7) are patterned to define a sacrificial memory structure 802 within the embedded memory region 201a and a sacrificial gate structure 806 within the logic region 201 b. The sacrificial memory structure 802 includes a sacrificial memory element 804 over a sacrificial dielectric layer 805 and a sacrificial metal cap layer 803. The sacrificial gate structure 806 includes a sacrificial gate electrode 808 located over the gate dielectric 222 (e.g., high-k dielectric) and the metal cap 223. In some embodiments, the sacrificial layer (702 of fig. 7) may be patterned by selectively exposing the sacrificial layer to a third etchant according to a third mask layer (e.g., a photoresist layer) formed over the sacrificial layer (702 of fig. 7).

In some embodiments, the patterning of the sacrificial layer (702 of fig. 7) may leave replacement gate residues 202 along the sidewalls of the recessed region 104. Replacement gate residue 202 may include dielectric film 208 (residue of 602 of fig. 7), metal cap layer 206 (residue of 604 of fig. 7), and sacrificial layer 204 (residue of 702 of fig. 7) remaining after patterning of sacrificial layer memory structure 802 and sacrificial gate structure 806. In some embodiments, replacement gate residue 202 may have tapered sidewalls facing sacrificial memory structure 802.

In some embodiments, the sidewall spacers 116 may be formed along sidewalls of the sacrificial memory structures 802 and the sacrificial gate structures 806. In some embodiments, the sidewall spacers 116 may be formed by depositing one or more dielectric materials over the substrate 101, and then etching the one or more dielectric materials to remove the one or more dielectric materials from horizontal surfaces. In some embodiments, the one or more dielectric materials may include a first dielectric material 224 and a second dielectric material 226 different from the first dielectric material 224. In some embodiments, the first dielectric material 224 and the second dielectric material 226 may each comprise an oxide, nitride, carbide, or the like.

As shown in the cross-sectional view 900 of fig. 9, a first doped region 108a and a second doped region 108b are formed within the memory region 201a of the semiconductor substrate 102. A source region 218a and a drain region 218b are also formed within the logic region 201b of the semiconductor substrate 102. In some embodiments, the first doped region 108a, the second doped region 108b, the source region 218a, and the drain region 218b may be formed by selectively implanting dopant species 902 into the semiconductor substrate 102 using one or more implantation processes. For example, in various embodiments, the first and second doped regions 108a and 108b may be formed by the same implantation process or a different implantation process than the source and drain regions 218a and 218 b. In other embodiments, the first doped region 108a, the second doped region 108b, the source region 218a, and the drain region 218b may be formed by etching the semiconductor substrate 102 to define a cavity and then forming a doped epitaxial material within the cavity. In some embodiments, the replacement gate residue 202 may be used to mask the dopant species 902 from the semiconductor substrate 102 such that the first and second doped regions 108a, 108b are separated from the isolation structures 106 a-106 b by a non-zero distance by the region 203 of the substrate 101.

As shown in cross-sectional view 1000 of fig. 10, a first inter-layer dielectric (ILD) layer 230 is formed over a substrate 101. The first ILD layer 230 laterally surrounds the sacrificial memory structure 802 and the sacrificial gate structure 806. In various embodiments, the first ILD layer 230 may comprise an oxide deposited on the substrate 101 by Chemical Vapor Deposition (CVD) deposition using a high aspect ratio process (i.e., HARP oxide). For example, in some embodiments, the first ILD layer 230 may comprise boron-phosphorous-silicate glass deposited by a CVD process. After forming the first ILD layer 230, a second planarization process may be performed along the lines 1002 to expose the upper surfaces of the sacrificial memory structures 802 and the sacrificial gate structures 806.

As shown in cross-sectional view 1100 of fig. 11, the sacrificial memory elements (804 of fig. 10), the sacrificial dielectric layer (805 of fig. 10), and the sacrificial metal cap layer (803 of fig. 10) are removed from the sacrificial memory structures (802 of fig. 10) to define memory device cavities 1106 disposed between the sidewalls of the sidewall spacers 116. In some embodiments, the sacrificial memory elements (804 of fig. 10), the sacrificial dielectric layer (805 of fig. 10), and the sacrificial metal capping layer (803 of fig. 10) may be removed by selectively exposing the sacrificial memory elements, the sacrificial dielectric layer, and the sacrificial metal capping layer to a fourth etchant 1104. In some embodiments, a fourth masking layer 1102 may be formed over the logic region 201b prior to removing the sacrificial memory elements (804 of fig. 10), the sacrificial dielectric layer (805 of fig. 10), and the sacrificial metal cap layer (803 of fig. 10) to prevent the sacrificial gate electrode 808 from being removed by the fourth etchant 1104.

As shown in cross-sectional view 1200 of fig. 12, ferroelectric layer 1202 is formed over substrate 101, metal layer 1204 is formed over ferroelectric layer 1202, and conductive layer 1206 is formed over metal layer 1204. The ferroelectric layer 1202 lines the interior surfaces of the memory device cavity 1106. The ferroelectric layer 1202 also extends from within the memory device cavity 1106 to above the upper surface of the first ILD layer 230 and the sacrificial gate structure 806. A metal layer 1204 and a conductive layer 1206 also extend from within the memory device cavity 1106 to above the upper surface of the first ILD layer 230 and the sacrificial gate structure 806. In some embodiments, ferroelectric layer 1202, metal layer 1204, and conductive layer 1206 can be formed by a deposition process.

As shown in cross-sectional view 1300 of fig. 13, a third planarization process is performed along line 1304 to define a FeRAM device 110 having nested electrodes. A third planarization process removes a portion of the ferroelectric layer (1202 of fig. 12) to define the ferroelectric material 112 confined within the memory device cavity 1106. The second planarization process also removes the metal layer (1204 of fig. 12) and a portion of the conductive layer 1206 to define a conductive electrode 114 confined within the memory device cavity 1106, the conductive electrode 114 including the gate metal 210 and the conductive material 212. In some embodiments, the third planarization process may include a CMP process.

As shown in cross-section 1400 of fig. 14, the sacrificial gate electrode (808 of fig. 13) is removed from the sacrificial gate structure (806 of fig. 13) to define a gate electrode cavity 1402. In some embodiments, the sacrificial gate electrode (808 of fig. 13) may be removed by selectively exposing the sacrificial gate electrode (808 of fig. 13) to a fifth etchant 1404. In some embodiments, a fifth masking layer 1406 may be formed over the memory region 201a prior to removing the sacrificial gate electrode to prevent the fifth etchant 1404 from damaging the FeRAM device 110. In some embodiments, the removal of the sacrificial gate electrode (808 of fig. 13) may leave the gate dielectric 222 and the metal cap 223 over the semiconductor substrate 102 within the gate electrode cavity 1402.

As shown in cross-sectional view 1500 of fig. 15, gate electrode 220 is formed within gate electrode cavity 1402. In various embodiments, the gate electrode 220 can be formed by forming the metal layer 1502 using a deposition technique (e.g., chemical vapor deposition, physical vapor deposition, etc.) and/or a plating technique (e.g., an electroplating technique). A fourth planarization process is then performed along line 1504 after deposition of metal layer 1502 to define gate electrode 220. In various embodiments, the metal layer 1502 may comprise an n-type metal (e.g., aluminum, tantalum, titanium, hafnium, etc.) or a p-type metal (e.g., nickel, cobalt, molybdenum, platinum, lead, gold, etc.).

As shown in cross-sectional view 1600 of fig. 16, conductive contacts 120 are formed within the second ILD layer 234 formed over the first ILD layer 230. The conductive contacts 120 may be formed by selectively etching the second ILD layer 234 to form openings, and then depositing a conductive material within the openings. In some embodiments, the conductive material may include, for example, tungsten or titanium nitride.

Fig. 17-34 illustrate cross-sectional views 1700-3400 of some alternative embodiments of a method of forming an integrated chip having an embedded FeRAM device with nested electrodes. Although fig. 17-34 are described with reference to a method, it should be understood that the structures disclosed in fig. 17-34 may not be limited to such a method, but may exist separately as a structure independent of the method.

As shown in cross-section 1700 of fig. 17, a liner dielectric 1702 and a protective layer 1704 are formed over semiconductor substrate 102. The liner dielectric 1702 and the protective layer 1704 extend continuously over the embedded memory region 201a and the logic region 201b within the semiconductor substrate 102. The liner dielectric 1702 and the protective layer 1704 may comprise, for example, silicon oxide or the like. The liner dielectric 1702 and the protective layer 1704 may be formed by a thermal process and/or by a deposition process (e.g., CVD, PVD, ALD, etc.).

As shown in the cross-sectional view 1800 of fig. 18, the protective layer 1704 is patterned to remove the protective layer 1704 from over the embedded memory region 201 a. For example, patterning may be performed by selectively exposing the protection layer 1704 to a first etchant according to the first mask layer 1802 over the logic region 201 b. In various embodiments, the first mask layer 1802 may include, for example, a photoresist layer, a hard mask layer, or some other suitable mask material.

As shown in the cross-sectional view 1900 of fig. 19, a thermal oxidation process is performed to oxidize the semiconductor substrate 102 within the embedded memory region 201 a. Oxidizing the semiconductor substrate 102 increases the thickness of the liner dielectric 1902 within the embedded memory region 201a by consuming the semiconductor substrate 102 within the embedded memory region 201 a. The consumption of the semiconductor substrate 102 within the embedded memory region 201a recesses the semiconductor substrate 102 within the embedded memory region 201a such that the semiconductor substrate 102 is recessed a non-zero distance d below the upper surface 102u of the semiconductor substrate 102. In some embodiments, the non-zero distance d may be greater than about 10 nm. In various embodiments, the thermal oxidation process may include, for example, a wet oxidation process and/or a dry oxidation process.

As shown in the cross-sectional view 2000 of fig. 20, the liner dielectric 2002 in the areas not covered by the protective layer 1704 is removed. In some embodiments, the liner dielectric 2002 may be removed by selectively exposing the liner dielectric (1902 of fig. 19) to a second etchant in accordance with the protective layer 1704. In various embodiments, the second etchant may include a wet etchant or a dry etchant.

As shown in cross-sectional view 2100 of fig. 21, protective layer 1704 is removed and a second liner dielectric 2102 is formed over semiconductor substrate 102. In some embodiments, protective layer 1704 may be removed by one or more etching processes and/or some other suitable removal process. In some embodiments, the second liner dielectric 2102 is formed by a thermal process.

As shown in cross-sectional view 2200 of fig. 22, a second protective layer 2202 is formed over the second liner dielectric 2102. The second protective layer 2202 is then etched according to the mask layer 2204 (e.g., photoresist) to reduce the thickness of the second protective layer 2202 in the logic region 201 b. The reduction in thickness of second protective layer 2202 within logic region 201b causes second protective layer 2202 to have substantially equal heights within embedded memory region 201a and logic region 201 b.

As shown in the cross-sectional view 2300 of fig. 23, the semiconductor substrate 102 is patterned to form trenches 2302 a-2302 c within the semiconductor substrate 102. The trenches 2302 a-2302 c are then filled with one or more dielectric materials to form one or more isolation structures 302 a-302 b and 106 c. The one or more isolation structures 302a, 302b, and 106c divide the area of the semiconductor substrate 102 for individual memory cells in fabrication, and the area of the semiconductor substrate 102 for individual logic devices in fabrication.

In some embodiments, the isolation structures 302 a-302 b may have angled lower sidewalls 304 because the isolation structures 302 a-302 b are formed over the edges of the recessed region 104. In some embodiments, the isolation structures 302 a-302 b may further include angled upper sidewalls oriented at an acute angle θ relative to a line 306 perpendicular to the recessed surface 101a of the substrate 101. In some embodiments, the acute angle θ may be in a range between about 10 ° and about 80 °. In other embodiments, the acute angle θ may be in a range between about 30 ° and about 60 °.

As shown in cross-sectional view 2400 of fig. 24, second liner dielectric 2102 and second protective layer 2202 are removed.

As shown in the cross-sectional view 2500 of fig. 25, a first dielectric layer 228 is formed over the substrate 101. The first dielectric layer 228 is disposed along the horizontally extending surface and the vertically extending surface of the substrate 101. A dielectric film 602 is formed over the first dielectric layer 228, a metal cap layer 604 is formed over the dielectric film 602, and a sacrificial layer 702 is formed over the metal cap layer 604. After deposition of the sacrificial layer 702, a first planarization process (e.g., a CMP process) is performed on the sacrificial layer 702 along line 704.

As shown in the cross-sectional view 2600 of fig. 26, the sacrificial layer (702 of fig. 25), the dielectric film (602 of fig. 25), and the metal cap layer (604 of fig. 25) are patterned to define the sacrificial memory structure 802 within the embedded memory region 201a and the sacrificial gate structure 806 within the logic region 201 b. The sacrificial memory structure 802 includes a sacrificial memory element 804 over a sacrificial dielectric layer 805 and a sacrificial metal cap layer 803. The sacrificial gate structure 806 includes a sacrificial gate electrode 808 located over the gate dielectric 222 and the metal cap 223. Sidewall spacers 116 may be formed along sidewalls of the sacrificial memory structures 802 and the sacrificial gate structures 806.

As shown in the cross-sectional view 2700 of fig. 27, the first doped region 108a and the first doped region 108b are formed within the memory region 201a of the semiconductor substrate 102. A source region 218a and a drain region 218b are also formed within the logic region 201b of the semiconductor substrate 102. In some embodiments, the first doped region 108a, the first doped region 108b, the source region 218a, and the drain region 218b may be formed by selectively implanting a dopant species 902 into the semiconductor substrate 102 using two or more implantation processes.

As shown in cross-sectional view 2800 of fig. 28, a first inter-layer dielectric (ILD) layer 230 is formed over the substrate 101. The first ILD layer 230 laterally surrounds the sacrificial memory structure 802 and the sacrificial gate structure 806. After formation of the first ILD layer 230, a second planarization process may be performed along the lines 1002 to expose the upper surfaces of the sacrificial memory structures 802 and the sacrificial gate structures 806.

As shown in cross-sectional view 2900 of fig. 29, the sacrificial memory elements (804 of fig. 28), the sacrificial dielectric layer (805 of fig. 28), and the sacrificial metal cap layer (803 of fig. 28) are removed from the sacrificial memory structures (802 of fig. 28) to define the memory device cavities 1106. In some embodiments, a fourth masking layer 1102 may be formed over the logic region 201b prior to removing the sacrificial memory elements (804 of fig. 28), the sacrificial dielectric layer (805 of fig. 28), and the sacrificial metal cap layer (803 of fig. 28) to prevent the sacrificial gate electrode 808 from being removed by the fourth etchant 1104.

As shown in cross-sectional view 3000 of fig. 30, a ferroelectric layer 1202 is formed over substrate 101, a metal layer 1204 is formed over ferroelectric layer 1202, and a conductive layer 1206 is formed over the metal layer.

As shown in cross-sectional view 3100 of fig. 31, a third planarization process is performed to define the FeRAM device 110. A third planarization process removes a portion of the ferroelectric layer (1202 of fig. 30) to define the ferroelectric material 112. The third planarization process also removes a portion of the metal layer (1204 of fig. 30) and the conductive layer (1206 of fig. 30) to define the conductive electrode 114 including the metal material 210 and the conductive material 212.

As shown in cross-sectional view 3200 of fig. 32, the sacrificial gate electrode (808 of fig. 31) is removed from the sacrificial gate structure (806 of fig. 31) to define a gate electrode cavity 1402.

As shown in cross-sectional view 3300 of fig. 33, a gate electrode 220 is formed within the gate electrode cavity 1402. In various embodiments, the gate electrode 220 may be formed by forming a metal layer using a deposition technique (e.g., chemical vapor deposition, physical vapor deposition, etc.) and/or a plating technique (e.g., an electroplating technique). A fourth planarization process is then performed after deposition of the metal layer to define the gate electrode 220.

As shown in the cross-sectional view 3400 of fig. 34, the conductive contact 120 is formed within the second ILD layer 234 formed above the first ILD layer 230.

Fig. 35 illustrates a flow diagram of some embodiments of a method 3500 of forming an integrated chip having an embedded FeRAM device with nested electrodes.

Although method 3500 is illustrated and described herein as a series of steps or events, it will be appreciated that the illustrated ordering of such steps or events are not to be interpreted in a limiting sense. For example, some steps may occur in different orders and/or concurrently with other steps or events apart from those illustrated and/or described herein. Moreover, not all illustrated steps may be required to implement one or more aspects or embodiments described herein, and one or more steps described herein may be implemented in one or more separate steps and/or stages.

At 3502, a plurality of isolation structures are formed within the substrate. Fig. 4 illustrates a cross-sectional view 400 of some embodiments corresponding to step 3502. Fig. 22-24 show cross-sectional views 2200-2400 of some alternative embodiments corresponding to step 3502.

At 3504, the substrate is recessed to form a recessed region recessed below an upper surface of the substrate. Fig. 5 illustrates a cross-sectional view 500 of some embodiments corresponding to step 3504. Fig. 17-20 show cross-sectional views 1700-2000 of some alternative embodiments corresponding to step 3504.

At 3506, a sacrificial storage structure is formed within the recessed region and a sacrificial gate structure is formed over the upper surface of the substrate. Fig. 6-8 illustrate cross-sectional views 600-800 of some embodiments corresponding to step 3506. Fig. 25-26 show cross-sectional views 2500-2600 corresponding to some alternative embodiments of step 3506.

At 3508, first and second doped regions are formed along opposite sides of the sacrificial storage structure and source and drain regions are formed along opposite sides of the sacrificial gate structure. Fig. 9 illustrates a cross-sectional view 900 of some embodiments corresponding to step 3508. Fig. 27 shows a cross-sectional view 2700 of some alternative embodiments, corresponding to step 3508.

In 3510, a first ILD layer is over the substrate and laterally surrounds the sacrificial memory structures and the sacrificial gate structures. Fig. 10 shows a cross-sectional view 1000 of some embodiments corresponding to step 3510. Fig. 28 shows a cross-sectional view 2800 of some alternative embodiments corresponding to step 3510.

At 3512, the sacrificial memory elements are removed from the sacrificial memory structures to form memory device cavities. Fig. 11 shows a cross-sectional view 1100 of some embodiments corresponding to step 3512. Fig. 29 shows a cross-sectional view 2900 of some alternative embodiments corresponding to step 3512.

At 3514, a ferroelectric layer is formed over the first ILD layer and within the memory device cavity. Fig. 12 illustrates a cross-sectional view 1200 of some embodiments corresponding to step 3514. Fig. 30 shows a cross-sectional view 3000 of some alternative embodiments corresponding to step 3514.

In 3516, a metal layer is formed over the ferroelectric layer and within the memory device cavity. Fig. 12 illustrates a cross-sectional view 1200 of some embodiments corresponding to step 3516. Fig. 30 shows a cross-sectional view 3000 of some alternative embodiments corresponding to step 3516.

At 3518, a conductive layer is formed over the metal layer and within the memory device cavity. Fig. 12 illustrates a cross-sectional view 1200 of some embodiments corresponding to step 3518. Fig. 30 shows a cross-sectional view 3000 of some alternative embodiments corresponding to step 3518.

At 3520, a portion of the ferroelectric layer, the metal layer, and the conductive layer are removed from over the first ILD layer to define a FeRAM device. Fig. 13 shows a cross-sectional view 1300 of some embodiments corresponding to step 3520. Fig. 31 shows a cross-sectional view 3100 of some alternative embodiments, corresponding to step 3520.

At 3522, the sacrificial gate structure is replaced with a metal gate electrode. Fig. 14-15 show cross-sectional views 1400-1500 of some embodiments corresponding to step 3522. Fig. 32-33 show cross-sectional views 3200-3300 of some alternative embodiments corresponding to step 3522.

At 3524, conductive contacts are formed within a second ILD layer formed over the first ILD layer. Fig. 16 shows a cross-sectional view 1600 of some embodiments corresponding to step 3524. Fig. 34 shows a cross-sectional view 3400 of some alternative embodiments corresponding to step 3524.

Accordingly, in some embodiments, the present invention relates to a method of forming an embedded FeRAM device using an alternative process to form a FeRAM device having nested electrodes. The replacement process enables the formation of embedded FeRAM devices by an efficient and low cost manufacturing process.

In some embodiments, the invention relates to an integrated chip. The integrated chip comprises a first doping area and a second doping area which are positioned in the substrate; and a FeRAM (ferroelectric random access memory) device disposed over the substrate between the first doped region and the second doped region, the FeRAM device including a ferroelectric material disposed over the substrate, and a conductive electrode located over the ferroelectric material and between sidewalls of the ferroelectric material. In some embodiments, the substrate has a recessed surface extending between the first sidewall and the second sidewall of the substrate to define a recessed region within the upper surface of the substrate; and the FeRAM device is disposed above the recessed surface and substantially midway between the first sidewall and the second sidewall. In some embodiments, the integrated chip further comprises a first isolation structure and a second isolation structure, the first isolation structure disposed within the semiconductor substrate and defining a first sidewall of the substrate; and a second isolation structure disposed within the semiconductor substrate and defining a second sidewall of the substrate. In some embodiments, the first sidewall of the substrate is oriented at an angle such that a width of the first isolation structure decreases with increasing height above the recessed surface. In some embodiments, the recessed surface of the substrate is defined by a first horizontally extending surface of the first isolation structure, a second horizontally extending surface of the second isolation structure, and a third horizontally extending surface of the semiconductor substrate. In some embodiments, the integrated chip further includes a replacement gate residue extending from above the first horizontally extending surface of the first isolation structure to above a third horizontally extending surface of the semiconductor substrate, the replacement gate residue having a metal cap layer disposed between the dielectric film and the sacrificial polysilicon layer. In some embodiments, the integrated chip further comprises sidewall spacers having one or more dielectric materials disposed on opposite sides of the FeRAM device; and an etch stop layer laterally separated from the FeRAM device by the sidewall spacer, the etch stop layer not covering the FeRAM device. In some embodiments, the integrated chip further comprises a transistor device having a gate electrode disposed over the substrate; and an interlayer dielectric (ILD) layer laterally surrounding the FeRAM device and the transistor device, the gate electrode and the FeRAM device extending to an upper surface of the ILD layer. In some embodiments, the ferroelectric material and the conductive electrode extend to an upper surface of the ILD layer. In some embodiments, the conductive electrode comprises a metal disposed over the ferroelectric material; and a conductive material vertically and laterally separated from the ferroelectric material by a metal.

In other embodiments, the invention relates to an integrated chip. The integrated chip includes a substrate having a recessed surface extending between a first sidewall and a second sidewall to define a recessed region recessed below an upper surface of the substrate; the first doped region and the second doped region are disposed within a recessed surface of the substrate; a ferroelectric material disposed between the first doped region and the second doped region, the ferroelectric material having sidewalls defining a first recess within an upper surface of the ferroelectric material; a metallic material nested within the first recess, the metallic material having sidewalls defining a second recess within an upper surface of the metallic material; and a conductive material nested within the second recess. In some embodiments, the sidewalls of the metal material directly contact the ferroelectric material and the conductive material. In some embodiments, the first height of the ferroelectric material is greater than the second height of the metallic material, and the third height of the conductive material is less than the second height. In some embodiments, the integrated chip further comprises sidewall spacers having one or more dielectric materials disposed on opposite sides of the ferroelectric material, the sidewall spacers having a height substantially equal to the height of the ferroelectric material. In some embodiments, the integrated chip further comprises a transistor device having a gate electrode disposed over the substrate; and an interlayer dielectric (ILD) layer laterally surrounding the ferroelectric material and the transistor device, the gate electrode and the ferroelectric material extending to an upper surface of the ILD layer. In some embodiments, the ferroelectric material has a horizontally extending section extending between the first vertical protrusion and the second vertical protrusion, the first vertical protrusion and the second vertical protrusion protrude outward from an upper surface of the horizontally extending section, and a height of the horizontally extending section is greater than a width of the first vertical protrusion.

In other embodiments, the invention relates to methods of forming integrated chips. The method includes forming a sacrificial memory structure over a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the sacrificial memory structure over the substrate; removing the sacrificial memory structure to form a memory device cavity surrounded by the ILD layer; forming a ferroelectric layer over the ILD layer and within the memory device cavity; forming a metal layer over the ferroelectric layer and within the memory device cavity; forming a conductive layer over the metal layer and within the memory device cavity; and removing a portion of the ferroelectric layer, the metal layer, and the conductive layer from over the ILD layer to define a FeRAM device having a metal disposed between the ferroelectric material and the conductive material. In some embodiments, the method further comprises recessing the storage region of the substrate to form a recessed region recessed below the upper surface of the substrate; and forming a sacrificial memory structure within the recessed region. In some embodiments, the method further comprises implanting the substrate after forming the sacrificial memory structure to form a first doped region along a first side of the sacrificial memory structure and a second doped region along a second side of the sacrificial memory structure. In some embodiments, the sidewalls of the metal layer directly contact the conductive layer and the ferroelectric layer.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.