阅读说明：本技术 记忆性结构 (Memory structure ) 是由 K.布鲁 D.纽恩斯 金世荣 T.S.格肖恩 T.K.托德罗夫 于 2018-06-01 设计创作，主要内容包括：提出了一种用于在电阻状态之间进行对称调制的记忆性结构的制造方法。该方法包括在绝缘基板上形成第一电极和第二电极,形成与第一电极和第二电极接触的阳极,在阳极上方形成离子导体,在离子导体上方形成与阳极相同材料的阴极,在阴极上形成第三电极,使离子能够在阳极和阴极之间双向传输,从而调节记忆性结构的电阻,阳极和阴极由具有离子浓度依赖性的导电性的亚稳混合导电材料形成。(A method of fabricating a memory structure for symmetric modulation between resistance states is presented. The method includes forming a first electrode and a second electrode on an insulating substrate, forming an anode in contact with the first electrode and the second electrode, forming an ion conductor over the anode, forming a cathode of the same material as the anode over the ion conductor, and forming a third electrode on the cathode to enable bi-directional transport of ions between the anode and the cathode to adjust the resistance of the memory structure, the anode and the cathode being formed of a metastable mixed conducting material having an ion concentration dependent conductivity.)

1. A method of fabricating a memory structure for symmetric modulation between resistance states, the method comprising:

forming a first electrode and a second electrode on an insulating substrate;

forming an anode contacting the first and second electrodes;

forming an ion conductor over the anode;

forming a cathode on the ion conductor;

forming a third electrode on the cathode; and

capable of bi-directionally transporting ions between an anode and a cathode, formed of a metastable material, thereby adjusting the resistance of the memory structure.

2. The method of claim 1, wherein the resistance adjustment comprises a resistance switch to maintain a symmetric modulation between the resistance states.

3. The method of claim 1, wherein the first, second and third electrodes are formed from an inert metal.

4. The method of claim 1, wherein the metastable material is a metastable phase-separated mixed ion-electron conductor (MIEC) whose conductivity depends on the concentration of inserted mobile ions.

5. The method of claim 1, wherein an electrical pulse is applied between the first electrode and the third electrode or between the second electrode and the third electrode to effect the write operation.

6. The method of claim 1, wherein an electrical pulse is applied between the first and second electrodes to effect a read operation.

7. The method of claim 1, wherein the movement of ions is achieved by applying a voltage to enable read and write operations to occur simultaneously.

8. The method of claim 1, wherein the chemical potential difference of the ions between the anode and the cathode is maintained near zero.

9. A memory structure for symmetric modulation between resistance states, the structure comprising:

a first electrode and a second electrode formed on an insulating substrate;

an anode in contact with the first and second electrodes;

an ion conductor formed on the anode;

a cathode formed on the ion conductor; and

a third electrode formed on the cathode;

wherein the anode and cathode are formed of metastable materials such that ions can be transported bi-directionally between the anode and cathode, resulting in a resistance modulation of the memory structure.

10. The structure of claim 9, wherein the resistance adjustment comprises a resistance switch to maintain a symmetric modulation between the resistance states.

11. The structure of claim 9, wherein the first, second and third electrodes are formed of an inert metal.

12. The structure of claim 9, wherein the metastable material is a metastable phase-separated Mixed Ion Electron Conductor (MIEC) whose conductivity depends on the concentration of intercalated mobile ions.

13. The structure of claim 9, wherein an electrical pulse is applied between the first electrode and the third electrode or between the second electrode and the third electrode to enable a write operation.

14. The structure of claim 9, wherein an electrical pulse is applied between the first electrode and the second electrode to enable a read operation.

15. The structure of claim 9, wherein the movement of ions is achieved by applying a voltage to enable simultaneous read and write operations.

16. The structure of claim 9, wherein the chemical potential difference of ions between the anode and the cathode remains close to zero.

17. A memory structure for symmetric modulation between resistance states, the structure comprising:

an ionically conductive layer formed between the metastable anode and the metastable cathode. And

an electrode formed adjacent to the metastable anode and the cathode;

wherein the bi-directional transport of ions between the metastable anode and cathode causes a resistance switch to maintain a symmetric modulation between resistance states.

18. The structure of claim 17, wherein the electrodes are formed of an inert metal and the metastable anode and cathode are metastable phase-separated mixed ionic-electronic conductors (MIECs) whose conductivity depends on the concentration of intercalated mobile ions.

19. The structure of claim 17 wherein electrical pulses are applied between the electrodes to effect write operations and read operations.

20. The structure of claim 17, wherein the chemical potential difference of the ions between the metastable anode and cathode remains close to zero.

Technical Field

The present invention relates generally to semiconductor devices and, more particularly, to memory structures of memory devices.

Background

A memory device is an electronic device that can change conductivity. For example, the memory device may provide a high conductivity state when a first voltage is applied to the memory device, and the memory device may provide a low conductivity state when a second voltage is applied to the memory device. Memory devices can be constructed from memory materials that are electroformed or conditioned to provide two or more conductive states. The memory device may be used in a variety of electronic applications such as, but not limited to, non-volatile storage, memory arrays, 3-D memory, switches, reconfigurable and fast tunable bandpass and notch filters, reversible field programmable fuse arrays, sample and hold elements, programmable resistance elements in variable gain amplifiers, and analog-to-digital converters, among others, and may be integrated with other electronic components.

Disclosure of Invention

According to an embodiment, a method of fabricating a memory structure for symmetric modulation between resistance states is provided. The method includes forming a first electrode (e.g., a source) and a second electrode (e.g., a drain) on an insulating substrate, forming an anode in contact with the first and second electrodes, forming an ion conductor on the anode, forming a cathode of the same material as the anode over the ion conductor, forming a third electrode (e.g., a gate electrode) over the cathode, and enabling bi-directional transport of ions between the anode and the cathode formed of the same mixed conductive material, thereby making resistance adjustment of the initial mixed conductor layer, the anode and the cathode being formed of a metastable mixed conductive material having an ion concentration dependent conductivity.

According to an embodiment, a memory structure for symmetric modulation between resistance states is provided. The memory structure includes a first electrode and a second electrode formed on an insulating substrate, an anode contacting the first and second electrodes, an ion conductor formed on the anode, a cathode of the same material as the anode formed on the ion conductor, and a third electrode formed on the cathode. The anode and cathode are formed of a metastable material in which ions are embedded such that bidirectional transport of ions between the anode and cathode results in a resistance adjustment of the initial mixed conductor layer.

According to an embodiment, a memory structure for symmetric modulation between resistance states is provided. The memory structure includes an ionic conductor formed between a metastable anode and a metastable cathode, and an electrode formed adjacent to the metastable anode and the cathode. The symmetric modulation between the resistance states is caused by the bi-directional transfer of ions between the metastable anode and the cathode comprising the same mixed conducting material.

It should be noted that the exemplary embodiments are described with reference to different subject matters. In particular, some embodiments are described with reference to method type claims whereas other embodiments are described with reference to device type claims. However, a person skilled in the art will gather from the above and the following description that, unless other notified, in addition to any combination of features belonging to one type of subject-matter also any combination between features of different subject-matters, in particular between features of the method type claims and features of the device type claims, is considered to be described herein.

These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

Brief description of the drawings

The invention will provide details in the following description of preferred embodiments with reference to the following drawings, in which:

fig. 1 is a cross-sectional view of a three-terminal memory device of the present invention.

FIG. 2 is a cross-sectional view of the memory device of FIG. 1 in which an electrical pulse is applied between the top and bottom electrodes of the three-terminal memory device to effect a write operation, according to the present invention;

FIG. 3 is a cross-sectional view of the memory device of FIG. 1 in which an electrical pulse is applied between the bottom electrodes of the three-terminal memory device to effect a read operation in accordance with the present invention;

FIG. 4 is a physical array of the three-terminal memory device of FIG. 1 for an implementation of a Resistive Processing Unit (RPU) according to the present invention;

FIG. 5 is a graphical representation of resistance switching for an RPU implementation according to the present invention;

FIG. 6 is a graph of asymmetric and symmetric modulation between example resistance states in accordance with the present invention; and

FIG. 7 is a block/flow diagram of a method for fabricating a memory structure for symmetric modulation between resistance states in accordance with the present invention.

Throughout the drawings, the same or similar reference numerals denote the same or similar elements.

Detailed Description

Methods and devices for a three-terminal memory device are provided according to embodiments of the present invention. In general, memory devices are hypothetical non-linear passive electronic components related to charge and flux linkage. The resistance of the memory is not constant but depends on a history of the current previously flowing through the device, e.g. its present resistance depends on the amount of charge that has passed in that direction in the past. Typically, an external switch is required to prevent back discharge in the memory device. The main characteristics of memory devices are analog modulation, decoupled read/write operations, bi-directional modulation and symmetric modulation. The three-terminal memory device of the exemplary embodiments is constructed of layers of metastable material or the same conductive material, thereby achieving symmetric modulation between resistance states without an external switch, since resistance tuning or resistance switching occurs due to the lack of the need to establish an EMF/voltage to transfer or transport ions between metastable layers.

Embodiments in accordance with the present invention provide methods and devices for a three-terminal memory device that achieve symmetric modulation between resistance states. The resistance needs to be symmetrically modulated so that machine learning occurs in the back-propagation training neural network composed of these devices. In order for symmetric modulation to occur, the memory device needs to include metastability, that is, a constant chemical potential must be achieved to move ions between the reservoirs (e.g., metastable anode and cathode layers). Exemplary embodiments introduce a three-terminal memory device in which an electrically insulating electrolyte layer is formed between a metastable anode and a metastable cathode. Ions move reversibly from the cathode into/out of the anode, and source and/or drain (S/D) voltages provide a current according to the ion concentration in the channel. The movement of ions between the metastable anode and metastable cathode provides resistance modulation or switching within the memory device, thereby achieving symmetric modulation. In addition, the chemical potential of the ions between the metastable anode and the metastable cathode remains close to zero.

Embodiments in accordance with the present invention provide methods and devices for a three-terminal memory device in which read and write operations are separated for the memory device, thereby allowing the read and write operations to occur simultaneously, thereby preventing the write operation from being performed simultaneously on the read device.

Memory cells are a common component of integrated circuits. A single memory cell comprises a device that exists in two or more stable memory states. The act of "writing" to the device includes placing the device in the desired memory state, while the act of "reading" the device includes determining which memory state the device is in.

Writing to the device may include applying a programming voltage to the device, where the programming voltage is a voltage sufficient to change the device from one storage state to another storage state. Reading of the device may include measurement of an electrical parameter affected by the memory state of the device, such as measurement of current through the device. It may be desirable to read without changing the memory state of the device so that a read operation does not "write" to the device. The three-terminal memory device of the exemplary embodiment prevents such an undesired operation, and thus prevents a reverse discharge.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments" does not require that all embodiments include the discussed feature, advantage or mode of operation.

As used herein, the term "about" changes the amount of an ingredient, component, or reactant of the present invention used, refers to a change in the numerical value that can occur, for example, by typical measurements and liquid handling procedures used to make concentrates or solutions. Furthermore, variations may arise due to inadvertent errors in the measurement procedure, manufacturing of the composition or ingredients used in carrying out the method, differences in source or purity, and the like. In one aspect, the term "about" means within 10% of the reported numerical value. In another aspect, the term "about" means within 5% of the reported numerical value. In another aspect, however, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported numerical value.

It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features as well as steps and/or block diagrams may be varied within the scope of the present invention. It should be noted that certain features may not be shown in all of the figures for clarity. It is not intended to be construed as a limitation on any particular embodiment, illustration, or scope of the claims.

Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

Fig. 1 is a cross-sectional view of a three-terminal memory device according to the present invention.

The structure 5 includes a substrate 10. A first electrode 12 (or source) and a second electrode 14 (or drain) are formed within the substrate 10. An anode 16 is formed on a portion of the first and second electrodes 12, 14. An ion conductor 18 (or ion conductive layer 18) is formed on the anode 16. The ion conductor 18 may be, for example, an electrolyte. A cathode 20 is then formed on the ion conductor 18. Anode 16 and cathode 20 may be formed from metastable materials. Anode 16 and cathode 20 may be formed from the same metastable material. A third electrode 22 (or gate electrode) is formed over the cathode 20. Thus, structure 5 is a three-terminal memory device. One skilled in the art may consider reversing the order of the electrodes. For example, the first and second electrodes may be positioned or disposed adjacent to the cathode 20, while the third electrode may be positioned or disposed adjacent to the anode 16. Anode 16 and cathode 20 may be referred to as metastable mixed conducting layers. The anode layer 16 and the cathode layer 20 depend on the concentration of the mobile intercalating ions. Anode layer 16 and cathode layer 20 have the same metastable material.

In one or more embodiments, the substrate 10 may be, for example, an insulator or an insulating material.

The first, second and third electrodes 12, 14 and 22 may be formed of an inert metal. The inert metal may be, for example, platinum (Pt), gold (Au), iridium (Ir), or the like. The inert metal does not oxidize during annealing in air at about 500 c. In an exemplary embodiment, lithium cobaltate (LiCoO) is used when in the anode 16 and cathode 20₂) As a metastable material, Pt is preferred because it reduces the formation of metastable phase-separated Mixed Ion Electron Conductors (MIEC) HT-LiCoO₂The temperature required for the film.

Anode 16 and cathode 20 may be formed from metastable materials, such as MIEC. Metastable phases are phases that are locally stable with respect to small fluctuations. Metastable materials have spinodal stability limits between bimodal equilibrium curves that define the metastable region. Within the stability limit, a miscibility gap exists that defines the thermodynamically unstable composition of the material, and thus, the material forms two phases with concentration variations defined by stability and temperature. Metastable MIEC may include, for example, lithium cobaltate (Li)_xCoO₂) Lithium niobate (Li)_xNbO₃) Doped Li_4+xTi₅O₁₂(LTO), lithium titanate (Li)_xTiO₂) Lithium nickelate (Li)_xSmNiO₃) And the like. The thickness of anode 16 and cathode 20 can be, for example, from about 50nm to about 1000nm. Anode 16 and cathode 20 are selected such that they change resistance based on ion concentration as described further below. The initial ion concentrations of anode 16 and cathode 20 are selected or adjusted to ensure that anode 16 and cathode 20 are metastable. Thus, chemical or electrical delithiation may be used to adjust or tune the initial concentrations of metastable anode 16 and metastable cathode 20. Metastability allows for symmetric switching between states and is important for non-volatility. In other words, the symmetric modulation between resistance states is caused by the bi-directional transfer of ions between the metastable anode and the cathode comprising the same mixed conducting material.

The solid electrolyte layer 18 may be formed in contact with the anode layer 16 and the cathode layer 20, and may be configured to electrically isolate the anode layer 16 from the cathode layer 20. In one example, electrolyte layer 18 may be, for example, lithium phosphorous oxynitride (LiPON).

Suitable materials for electrolyte layer 18 may further include, but are not limited to, ethylene carbonate and diethyl carbonate containing lithium ion complexes, as well as other (e.g., acid or base) electrolytes having suitable ion transport properties. In lithium ion applications of the microbattery, the electrolyte 18 is typically non-aqueous to avoid reaction with the lithium metal components in the anode 16 and cathode 20 and further avoid evaporation during cathode annealing.

Suitable anode 16 and cathode 20 materials include, but are not limited to, lithium cobalt oxide, lithium iron phosphate and other lithium metal phosphates, lithium manganese oxide, carbon and graphite or lithium ion implanted graphite.

Each layer (e.g., anode 16, cathode 20, electrolyte 18) may be formed using conventional vacuum deposition techniques, which are capable of encapsulating the reactive layer directly prior to any environmental exposure. Exemplary methods include chemical or physical vapor deposition, flash evaporation, laser ablation, and co-evaporation. Physical Vapor Deposition (PVD) methods may include, for example, reactive or non-reactive sputtering processes. With sputtering, any conventional power source can be used to generate ions (e.g., Ar) that reach the target⁺) Current, e.g. magnetron, DC or pulsed DC power supply. Suitable sputtering targets for the various barrier layer compositions can be formed as either fused powder or pressed powder targets.

Fig. 2 is a cross-sectional view of the memory device of fig. 1. Wherein, according to the present invention, an electric pulse is applied between the top electrode and the bottom electrode of the three-terminal memory device to realize a write operation.

In various embodiments, a voltage source 24 is connected between the second electrode 14 and the third electrode 22 to provide electrical pulses therebetween to effect a write operation. A voltage source 24 may also be connected between the first electrode 12 and the third electrode 22 to provide electrical pulses therebetween to effect a write operation. The electrical pulse causes transfer or ions (or interstitial ions) between anode 16 and cathode 20. Due to the three terminal structure of the memory device, the read and write operations of the device are separated, thus allowing simultaneous read and write operations while preventing accidental reading of the device.

Fig. 3 is a cross-sectional view of the memory device of fig. 1. Wherein, according to the present invention, an electric pulse is applied between bottom electrodes of the three-terminal memory device to realize a read operation.

In various embodiments, a voltage source 26 is connected between the first electrode 12 and the second electrode 14 to provide electrical pulses therebetween to effect a read operation. The electrical pulse causes ion (or interstitial ions) transfer between anode 16 and cathode 20. The relative concentration of ions in anode 16 controls the read resistance of the memory device. Again, due to the three terminal structure of the memory device, the read and write operations of the device are separated, thus allowing the read and write operations to occur simultaneously while avoiding accidental reading of the device.

Thus, as shown in FIGS. 1-3, no external Field Effect Transistor (FET) switch is required to prevent back discharge. In contrast, the bi-directional movement of ions between anode 16 and cathode 20 results in an adjustment of the resistance of memory structure 5. The resistance adjustment includes resistance switching to maintain symmetric modulation between resistance states. Also, the chemical potential of the ions between anode 16 and cathode 20 is kept near zero.

FIG. 4 is a physical array of the three-terminal memory device of FIG. 1. Which is a diagram of a Resistive Processing Unit (RPU) implementation according to the present invention.

Physical array 30 is a rectangular array of memory devices 5, where at each xy intersection, a set of x-lines and a set of y-lines are connected through memory devices 5. The array may be an mxn array configured to be modified accordingly as required by the designer. This constitutes a Resistance Processing Unit (RPU) for use in hardware embodiments such as neural networks.

The first electrode 12 is connected to a current line 34, the second electrode 14 is connected to a voltage line 32, and the third electrode 22 is connected to a voltage line 36. A low read bias is applied to the voltage line 32. A current is induced on line 34.

Fig. 5 is a diagram illustrating resistance switching for an RPU implementation in accordance with the present invention.

The pattern 40 depicts the electrical pulses applied between the electrodes of the memory device 5. Arrow 41 shows the memory device 5 in a first resistive state and arrow 43 shows the memory device 5 switched to a second resistive state. Thus, constant ion motion between anode 16 and cathode 20 results in resistance switching to maintain the chemical potential difference of the ions at or near zero. The reversible modulation at zero EMF of the ion concentration between the layers 16, 20 enables a symmetric resistance state to be maintained during operation of the memory device 5.

Fig. 6 shows a graph of asymmetric and symmetric modulation between resistance states according to the present invention.

The left graph depicts asymmetric modulation 52, while the right graph depicts symmetric modulation 54. The asymmetric curve 51 shows an asymmetric modulation 52. Symmetric curves 55, 57 show symmetric modulation 54. Exemplary embodiments of the present invention achieve symmetric modulation. In order for machine learning to occur on the memory device, the resistance needs to be adjusted symmetrically. In other words, when n positive pulses are provided, the n negative pulses return the device to the same resistance. To achieve symmetric modulation between resistance states, each state of the memory device must have an equal potential. Thus, the memory device needs to include metastability, that is, phase separation is needed to achieve a constant chemical potential of the mobile ions between the reservoirs (e.g., anode 16 and cathode 20).

FIG. 7 is a block/flow diagram of a method for fabricating a memory structure for symmetric modulation between resistance states in accordance with the present invention.

At block 102, a first electrode and a second electrode are formed on an insulating substrate. The first electrode and the second electrode may be formed of an inert metal.

At block 104, an anode is formed in contact with the first electrode and the second electrode, the anode being the metastable MIEC forming the channel.

At block 106, an ion conductor is formed over the MIEC formation channel. The ionic conductor may be, for example, an electrolyte.

At block 108, a cathode of the same material as the anode is formed on the ion conductor, the cathode being a metastable cathode.

At block 110, a third electrode is formed over the cathode. The third electrode may be formed of, for example, an inert metal.

At block 112, ions are enabled to move bi-directionally between the metastable anode and the metastable cathode, thereby causing a resistance adjustment of the memory structure. Resistance regulation involves resistance switching to maintain symmetric modulation between resistance states. The ionic chemical potential difference between the metastable anode and metastable cathode is kept at or near zero to provide symmetric modulation. The anode and cathode may also be referred to as reservoirs of mobile ions, where the ions may drift/diffuse in two directions (e.g., to and from the anode/cathode). Equal potentials and electrolytes prevent back diffusion. Ions move from the anode to the cathode by drift of the ions in the applied electric field. Note that only ions are transferred or transported between the metastable anode and cathode layer. The three-terminal memory structure provides non-volatility of the resistive state without any external FET switching mechanism. The three-terminal memory device may be used, for example, as a neuron in a neural network.

It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other structures, substrate materials, and process features as well as steps and/or blocks may be altered within the scope of the invention.

It will also be understood that when an element such as a layer, region or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

The present embodiments may include a design for an integrated circuit chip that may be created in a graphical computer programming language and stored in a computer storage medium (e.g., a disk, tape, physical hard drive, or virtual hard drive). Such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transfer the resulting design directly or indirectly to such entities by physical mechanisms (e.g., by providing a copy of the storage medium storing the design) or by transmitting the design electronically (e.g., through the Internet). The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers on the wafer) to be etched or otherwise processed.

The methods as described herein may be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (i.e., a single wafer having a plurality of unpackaged chips), bare chip, or packaged form. In the latter case, the chip is mounted on a single chip package (e.g., a plastic carrier with leads attached to a motherboard or higher level carrier) or on a multi-chip package (e.g., with either surface or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product (e.g., a motherboard) or (b) an end product. The end product of (a) may be an integrated circuit chip ranging from toys and other low-end applications having a display, a keyboard or other input device, and a central processor to advanced computer products.

It should also be understood that the material compounds will be described in terms of the listed elements, such as SiGe. These compounds comprise different proportions of the elements in the compound, e.g. SiGe comprises Si_xGe_1-xWhere x is less than or equal to 1, and so on. In addition, other elements may also be included in the compound, and according to the present embodiment. Compounds with additional elements will be referred to herein as alloys.

Reference in the specification to "one embodiment" or "an embodiment" of the present invention, and other variations thereof, is meant to include particular features, structures, characteristics, etc. described in connection with the embodiment. In at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification, and any other variations, are not necessarily all referring to the same embodiment.

It is to be understood that any of the following "/", "and/or" and "at least one" are used, for example, in the case of "a/B", "a and. And/or B "and" at least one of A and B "are intended to encompass the selection of only the first listed option (A) or only the second listed option (B) or both options (A and B). As another example, in the case of "a, B and/or C" and "at least one of a, B and C", such wording is intended to include only the selection of the first listed option (a). Or selecting only the second listed option (B), or selecting only the third listed option (C), or selecting only the first and second listed options (a and B), or selecting only the first and third options (a and C), or selecting only the second and third options (B and C), or selecting all three options (a and B and C). This can be extended for many of the items listed, as will be apparent to those of ordinary skill in this and related arts.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Spatially relative terms, such as "below," "in.. below," "in.. above," "above," etc., may be used herein for ease of description to describe one element or feature's relationship to another element or feature. One or more elements or features as shown. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below … …" can include both an orientation above … … and below … …. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the scope of the present invention.

Having described preferred embodiments for a method of fabricating a memory structure for symmetric modulation between resistance states (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in the following respects. In accordance with the teachings above. It is, therefore, to be understood that changes may be made in the particular embodiments described which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by letters patent is set forth in the appended claims.