阅读说明：本技术 Sram写操作追踪电路 (SRAM write operation tracking circuit ) 是由 史增博 方伟 于 2018-06-25 设计创作，主要内容包括：一种SRAM写操作追踪电路,包括：模拟存储单元电路,与补偿电路耦接,适于模拟SRAM存储单元；补偿电路,输入端与所述模拟存储单元电路的内部存储节点输出端耦接,输出端与时钟产生电路耦接,适于对所述模拟存储单元电路的内部存储节点输出端的输出电压进行补偿,以增加所述内部存储节点输出端的输出电压从高电平跳变至低电平的延时。上述方案可以增加写追踪电路的开启时间,避免出现写电路无法正常写入的情况出现。(An SRAM write operation tracking circuit, comprising: the analog storage unit circuit is coupled with the compensation circuit and is suitable for simulating the SRAM storage unit; and the compensation circuit is suitable for compensating the output voltage of the internal storage node output end of the analog storage unit circuit so as to increase the time delay of the output voltage of the internal storage node output end jumping from a high level to a low level. The scheme can increase the starting time of the writing tracking circuit and avoid the situation that the writing circuit cannot write normally.)

1. An SRAM write operation tracking circuit, comprising:

the analog storage unit circuit is coupled with the compensation circuit and is suitable for simulating the SRAM storage unit;

and the compensation circuit is suitable for compensating the output voltage of the internal storage node output end of the analog storage unit circuit so as to increase the time delay of the output voltage of the internal storage node output end jumping from a high level to a low level.

2. The SRAM write operation tracking circuit of claim 1, further comprising: a delay circuit; the input end of the delay circuit is coupled with the output end of the compensation circuit, and the output end of the delay circuit is coupled with the clock generation circuit.

3. The SRAM write operation tracking circuit of claim 1, further comprising: an inverter circuit;

the inverter circuit includes: second NMOS pipe and first PMOS pipe, wherein:

the grid electrode of the second NMOS tube is coupled with the output end of the compensation circuit, the source electrode of the second NMOS tube is input with low level, and the drain electrode of the second NMOS tube is coupled with the drain electrode of the first PMOS tube;

and the grid electrode of the first PMOS tube is coupled with the output end of the internal storage node of the analog SRAM storage unit circuit, and the source electrode of the first PMOS tube inputs high level.

4. The SRAM write operation tracking circuit of claim 3, wherein the compensation circuit comprises: a first NMOS transistor; the grid electrode of the first NMOS tube inputs high level, the drain electrode of the first NMOS tube is connected with the output end of the internal storage node of the analog SRAM storage unit circuit, the source electrode of the first NMOS tube is coupled with the grid electrode of the second NMOS tube, and the source electrode of the first NMOS tube is the output end of the compensation circuit.

5. The SRAM write operation tracking circuit of claim 4, wherein the compensation circuit further comprises:

and the first end of the energy storage device is coupled with the drain electrode of the first NMOS tube, the second end of the energy storage device is coupled with the source electrode of the first NMOS tube, the energy storage device is suitable for storing electric energy and discharges when the internal working voltage of the chip is detected to be smaller than a preset value.

6. The SRAM write operation tracking circuit of claim 5, wherein the energy storage device is a capacitor.

7. The SRAM write operation tracking circuit of claim 3, wherein a source of the first PMOS transistor is coupled to a substrate of the first PMOS transistor.

8. The SRAM write operation tracking circuit of claim 3, wherein a source of the second NMOS transistor is coupled to a substrate of the second NMOS transistor.

9. The SRAM write operation tracking circuit of claim 1, wherein the analog SRAM memory cell circuit comprises: second PMOS pipe, third PMOS pipe, fourth PMOS pipe, fifth PMOS pipe, third NMOS pipe and fourth NNOS pipe, wherein:

the source electrode of the second PMOS tube is input with high level, the grid electrode of the second PMOS tube is coupled with the grid electrode of the fourth PMOS tube, and the drain electrode of the second PMOS tube is coupled with the source electrode of the fourth PMOS tube;

the source electrode of the third PMOS tube is input with high level, the grid electrode of the third PMOS tube is coupled with the grid electrode of the fifth PMOS tube, and the drain electrode of the third PMOS tube is coupled with the source electrode of the fifth PMOS tube;

the source electrode of the fourth PMOS tube is coupled with the drain electrode of the second PMOS tube, the grid electrode of the fourth PMOS tube is coupled with the grid electrode of the third NMOS tube, and the drain electrode of the fourth PMOS tube is coupled with the drain electrode of the third NMOS tube;

the source electrode of the fifth PMOS tube is coupled with the drain electrode of the third PMOS tube, the grid electrode of the fifth PMOS tube is coupled with the fifth PMOS tube, and the drain electrode of the fifth PMOS tube is coupled with the drain electrode of the fourth NMOS tube;

the source electrode of the third NMOS tube is input with low level, the grid electrode of the third NMOS tube is coupled with the grid electrode of the fourth PMOS tube, and the drain electrode of the third NMOS tube is coupled with the drain electrode of the fourth PMOS tube;

and the source electrode of the fourth NMOS tube is input with low level, the grid electrode of the fourth NMOS tube is coupled with the grid electrode of the fifth PMOS tube, and the drain electrode of the fourth NMOS tube is coupled with the drain electrode of the fifth PMOS tube.

Technical Field

The invention relates to the field of circuits, in particular to a SRAM write operation tracking circuit.

Background

A Static Random Access Memory (SRAM) is a Memory having a Static Access function, and can store data stored therein without a refresh circuit. The SRAM write tracking circuit is used for controlling the turn-on time of a Word Line (WL) in write operation. Currently, the SRAM write tracking circuit is usually implemented by a method of copying a memory cell (bitcell) write operation.

In order to ensure that the write tracking circuit is effective under the condition of minimum working voltage (VCC min), a structure that two pull-up tubes are connected in series is usually adopted, so that the write-in capability of an analog memory cell (reference cell) is enhanced, and the problem of write failure of the reference cell under the minimum working voltage is solved.

In the conventional write tracking circuit, due to the difference between the pull-up transistor of the reference cell and the bitcell, the PVT characteristics between the write tracking circuit and the actual write circuit are greatly different, and the PVT characteristics include a process (process) characteristic, a voltage (voltage) characteristic and a temperature (temperature) characteristic. Under SNFP (slow NMOS Fast PMOS) low-temperature low-voltage, the turn-on time of the write tracking circuit is faster than the time required by the actual write circuit, so that the WL turn-on time is insufficient, and normal write cannot be performed.

Disclosure of Invention

The embodiment of the invention solves the problem of how to increase the starting time of the write tracking circuit under the specific PVT condition so as to avoid the phenomenon that the write circuit cannot normally write.

To solve the above technical problem, an embodiment of the present invention provides a SRAM write tracking circuit, including: the analog storage unit circuit is coupled with the compensation circuit and is suitable for simulating the SRAM storage unit; and the compensation circuit is suitable for compensating the output voltage of the internal storage node output end of the analog storage unit circuit so as to increase the time delay of the output voltage of the internal storage node output end jumping from a high level to a low level.

Optionally, the SRAM write operation tracking circuit further includes: a delay circuit; the input end of the delay circuit is coupled with the output end of the compensation circuit, and the output end of the delay circuit is coupled with the clock generation circuit.

Optionally, the SRAM write operation tracking circuit further includes: an inverter circuit; the inverter circuit includes: second NMOS pipe and first PMOS pipe, wherein: the grid electrode of the second NMOS tube is coupled with the output end of the compensation circuit, the source electrode of the second NMOS tube is input with low level, and the drain electrode of the second NMOS tube is coupled with the drain electrode of the first PMOS tube; and the grid electrode of the second NMOS tube is coupled with the output end of the compensation circuit, the source electrode of the second NMOS tube is input with low level, and the drain electrode of the second NMOS tube is coupled with the drain electrode of the first PMOS tube.

Optionally, the compensation circuit includes: a first NMOS transistor; the grid electrode of the first NMOS tube inputs high level, the drain electrode of the first NMOS tube is connected with the output end of the internal storage node of the analog SRAM storage unit circuit, the source electrode of the first NMOS tube is coupled with the grid electrode of the second NMOS tube, and the source electrode of the first NMOS tube is the output end of the compensation circuit.

Optionally, the compensation circuit further includes: and the first end of the energy storage device is coupled with the drain electrode of the first NMOS tube, the second end of the energy storage device is coupled with the source electrode of the first NMOS tube, the energy storage device is suitable for storing electric energy and discharges when the internal working voltage of the chip is detected to be smaller than a preset value.

Optionally, the energy storage device is a capacitor.

Optionally, the source of the first PMOS transistor is coupled to the substrate of the first PMOS transistor.

Optionally, the source of the second NMOS transistor is coupled to the substrate of the second NMOS transistor.

Optionally, the analog SRAM memory cell circuit includes: second PMOS pipe, third PMOS pipe, fourth PMOS pipe, fifth PMOS pipe, third NMOS pipe and fourth NNOS pipe, wherein: the source electrode of the second PMOS tube is input with high level, the grid electrode of the second PMOS tube is coupled with the grid electrode of the fourth PMOS tube, and the drain electrode of the second PMOS tube is coupled with the source electrode of the fourth PMOS tube; the source electrode of the third PMOS tube is input with high level, the grid electrode of the third PMOS tube is coupled with the grid electrode of the fifth PMOS tube, and the drain electrode of the third PMOS tube is coupled with the source electrode of the fifth PMOS tube; the source electrode of the fourth PMOS tube is coupled with the drain electrode of the second PMOS tube, the grid electrode of the fourth PMOS tube is coupled with the grid electrode of the third NMOS tube, and the drain electrode of the fourth PMOS tube is coupled with the drain electrode of the third NMOS tube; the source electrode of the fifth PMOS tube is coupled with the drain electrode of the third PMOS tube, the grid electrode of the fifth PMOS tube is coupled with the fifth PMOS tube, and the drain electrode of the fifth PMOS tube is coupled with the drain electrode of the fourth NMOS tube; the source electrode of the third NMOS tube is input with low level, the grid electrode of the third NMOS tube is coupled with the grid electrode of the fourth PMOS tube, and the drain electrode of the third NMOS tube is coupled with the drain electrode of the fourth PMOS tube; and the source electrode of the fourth NMOS tube is input with low level, the grid electrode of the fourth NMOS tube is coupled with the grid electrode of the fifth PMOS tube, and the drain electrode of the fourth NMOS tube is coupled with the drain electrode of the fifth PMOS tube.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the SRAM write operation tracking circuit, a compensation circuit is arranged to be coupled with an analog storage unit circuit, and the delay of the output voltage of an output end of an internal storage node jumping from a high level to a low level is increased through the compensation circuit, so that the switching speed of an NMOS under an SNFP is increased, the starting time of the write tracking circuit can be effectively increased, and the situation that the write circuit cannot write normally is avoided.

Furthermore, an energy storage device is connected between the drain electrode and the source electrode of the first NMOS tube in parallel, and the energy storage device discharges when the internal working voltage of the chip is detected to be smaller than a preset value, so that the SRAM can normally work under the low working voltage.

Drawings

FIG. 1 is a schematic diagram of an SRAM write tracking circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another SRAM write tracking circuit according to an embodiment of the present invention.

Detailed Description

In the conventional write tracking circuit, due to the difference between the pull-up transistor of the reference cell and the bitcell, the PVT characteristics between the write tracking circuit and the actual write circuit are greatly different, and the PVT characteristics include a process (process) characteristic, a voltage (voltage) characteristic and a temperature (temperature) characteristic. Under SNFP low temperature and low voltage, the turn-on speed of the write tracking circuit is faster than the time required by the actual write circuit, so that the WL turn-on time is insufficient, and normal writing cannot be performed.

In the embodiment of the invention, in the SRAM write operation tracking circuit, the compensation circuit is coupled with the analog storage unit circuit, and the delay of the output voltage of the output end of the internal storage node jumping from a high level to a low level is increased through the compensation circuit, so that the switching speed of an NMOS under an SNFP is increased, the starting time of the write tracking circuit can be effectively increased, and the situation that the write circuit cannot normally write is avoided.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

The embodiment of the invention provides an SRAM write operation tracking circuit, which comprises: an analog memory cell circuit 11 and a compensation circuit 12.

In a specific implementation, the analog memory cell circuit 11 may be coupled to the compensation circuit 12, the analog memory cell circuit 11 being adapted to analog SRAM memory cells. In practical applications, the specific structure of the analog memory cell circuit 11 can refer to the specific structure of a memory cell (bitcell) in an existing SRAM. The structure of the analog memory cell circuit 11 does not affect the protection scope of the present invention.

In a specific implementation, an input terminal of the compensation circuit 12 may be coupled to an internal storage node output terminal of the analog memory cell circuit 11, and an output terminal of the compensation circuit 12 may be coupled to the clock generation circuit 13. In the embodiment of the present invention, the compensation circuit 12 may compensate the output voltage at the output terminal of the internal storage node of the analog memory cell circuit 11 to increase the delay of the output voltage at the output terminal of the internal storage node of the analog memory cell circuit 11 from the high level to the low level.

In practical applications, the clock generation circuit can be used to generate clock signals inside the SRAM.

In a specific implementation, the SRAM write operation tracking circuit may further include: and a delay circuit 15, wherein an input terminal of the delay circuit 15 may be coupled to an output terminal of the compensation circuit 12, and an output terminal of the delay circuit 15 may be coupled to the clock generation circuit 13.

The output signal of the compensation circuit 12 can be subjected to delay processing by a delay circuit. In a specific application, the delay time of the delay circuit may be set according to an actual application scenario, which is not described herein.

In a specific implementation, the SRAM write operation tracking circuit may further include: and an inverter circuit 14. An input of inverting circuit 14 may be coupled to an output of compensation circuit 12 and an output of inverting circuit 14 may be coupled to an input of delay circuit 15.

Referring to fig. 2, a schematic structural diagram of an SRAM write tracking circuit according to an embodiment of the present invention is shown, and the following description is made in detail with reference to fig. 1.

In a specific implementation, the compensation circuit 12 may include a first NMOS transistor MN 1. The gate of the first NMOS transistor MN1 can input a high level, the drain of the first NMOS transistor MN1 can be connected to the output terminal of the internal storage node of the analog SRAM memory cell circuit, the source of the first NMOS transistor is coupled to the gate of the second NMOS transistor, and the source of the first NMOS transistor is the output terminal of the compensation circuit 12.

In particular implementations, the compensation circuit 12 may also include an energy storage device. The first terminal of the energy storage device may be coupled to the drain of the first NMOS transistor MN1, and the second terminal may be coupled to the source of the first NMOS transistor MN 1.

In the embodiment of the invention, the energy storage device can store electric energy when the chip works normally, and the storage device discharges when the working voltage in the chip is detected to be smaller than the preset value, so that the SRAM can work normally under low working voltage.

In practical application, the energy storage device may be a capacitor, or may be other electronic components or circuit units capable of storing electric energy.

In an embodiment of the invention, referring to fig. 2, the energy storage device is a capacitor C1.

In a specific implementation, the inverter circuit 14 may include a second NMOS transistor MN2 and a first PMOS transistor MP1, wherein: the gate of the second NMOS transistor MN2 may be coupled to the output terminal of the compensation circuit 12, the source of the second NMOS transistor MN2 may input a low level, and the drain of the second NMOS transistor MN2 may be coupled to the drain of the first PMOS transistor MP 1;

the gate of the first PMOS transistor MP1 may be coupled to the internal storage node output terminal of the analog memory cell circuit 11, the source of the first PMOS transistor MP1 may be inputted with a high level, and the drain of the first PMOS transistor MP1 may be coupled to the drain of the second NMOS transistor MN 2.

In the embodiment of the present invention, the source of the second NMOS transistor MN2 may be coupled to the pad of the second NMOS transistor MN2, and the source of the second NMOS transistor MN2 may be connected to the low level VSS. The source of the first PMOS transistor MP1 may be coupled to the pad of the first PMOS transistor MP1, and the source of the first PMOS transistor MP1 may be connected to the high level VDD.

In one embodiment, the source of the first PMOS transistor MP1 may be coupled to the substrate of the first PMOS transistor MP1, and the source of the first PMOS transistor MP1 and the substrate of the first PMOS transistor MP1 are both connected to VDD.

In one implementation, the source of the second NMOS transistor MN2 may be coupled to the substrate of the second NMOS transistor MN2, and the source of the second NMOS transistor MN2 and the substrate of the second NMOS transistor MN2 are both tied to VSS.

In a specific application, the structure of the analog SRAM memory cell in the prior art can be referred to. Referring to fig. 2, a schematic diagram of another SRAM write tracking circuit according to an embodiment of the present invention is shown.

In the embodiment of the present invention, the analog SRAM memory cell circuit 11 may include: a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a third NMOS transistor MN3, and a fourth NMOS transistor MN4, wherein:

the source of the second PMOS transistor MP2 may input a high level VDD, the gate of the second PMOS transistor MP2 may be coupled to the gate of the fourth PMOS transistor MP4, and the drain of the second POMS transistor may be coupled to the source of the fourth PMOS transistor MP 4;

a source of the third PMOS transistor MP3 may input a high level VDD, a gate of the third PMOS transistor MP3 may be coupled to a gate of the fifth PMOS transistor MP5, and a drain of the third PMOS transistor MP3 may be coupled to a source of the fifth PMOS transistor MP 5;

a source of the fourth PMOS transistor MP4 may be coupled to a drain of the second PMOS transistor MP2, a gate of the fourth PMOS transistor MP4 may be coupled to a gate of the third NMOS transistor MN3, and a drain of the fourth PMOS transistor MP4 may be coupled to a drain of the fourth NMOS transistor MN 4;

a source of the fifth PMOS transistor MP5 may be coupled to a drain of the third PMOS transistor MP3, a gate of the fifth PMOS transistor MP5 may be coupled to a gate of the fourth NMOS transistor MN4, and a drain of the fifth PMOS transistor MP5 may be coupled to a drain of the fourth NMOS transistor MN 4;

the source of the third NMOS transistor MN3 may input a low level VCC, the gate of the third NMOS transistor MN3 may be coupled to the gate of the fourth PMOS transistor MP4, and the drain of the third NMOS transistor MN3 may be coupled to the drain of the fourth PMOS transistor MP 4; the gate of the third NMOS transistor MN3 may be coupled to the internal storage node output of the analog memory cell circuit 11;

the source of the fourth NMOS transistor MN4 may input a low VCC, the gate of the fourth NMOS transistor MN4 may be coupled to the gate of the fifth PMOS transistor MP5, and the drain of the fourth PMOS transistor MP4 may be coupled to the drain of the fifth PMOS transistor MP 5.

In practical applications, with continued reference to fig. 2, a bit line Write terminal (DBLW) may be coupled to the drain of the fifth NMOS transistor MN5, a source of the fifth NMOS transistor may be coupled to the gate of the fifth PMOS transistor MP5 and the gate of the fourth NMOS transistor MN4, respectively, a gate of the fifth NMOS transistor may be coupled to the word line Write terminal (DBL _ Write), and a substrate of the fifth NMOS transistor may be coupled to the substrate of the third NMOS transistor MN 3.

The word line write terminal may be coupled to a gate of the sixth NMOS transistor. The source of the sixth NMOS transistor may be coupled to the drain of the fifth PMOS transistor MP5 and the drain of the fourth NMOS transistor MN4, and the drain of the sixth NMOS transistor is the DBLXW output terminal.

In the embodiment of the present invention, the internal storage node output terminal of the analog memory cell circuit 11 may be an RB port.

By adopting the SRAM write operation tracking circuit provided by the embodiment of the invention, the compensation circuit is arranged in the SRAM write operation tracking circuit and is coupled with the analog storage unit circuit, and the delay of the output voltage of the output end of the internal storage node jumping from a high level to a low level is increased through the compensation circuit, so that the switching speed of the NMOS under the SNFP is increased, the starting time of the write tracking circuit can be effectively increased, and the situation that the write circuit cannot normally write is avoided.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.