Integrated circuit with a plurality of transistors
阅读说明:本技术 集成电路 (Integrated circuit with a plurality of transistors ) 是由 叶凌彦 萧孟轩 孙元成 于 2019-06-26 设计创作,主要内容包括:本揭示是关于一种集成电路。所揭示的技术在沟槽内局部地形成磊晶层,此沟槽具有在沟槽的侧壁中堆叠的角形凹陷。控制凹陷大小以控制在沟槽内形成的磊晶层的厚度。凹陷由覆盖层覆盖并且从最底部凹陷开始相继地逐个暴露出。磊晶层在沟槽内逐个形成,磊晶层的晶面边缘部分对准到相应凹陷中,此凹陷是为了磊晶层而相继地暴露的凹陷。(The present disclosure relates to an integrated circuit. The disclosed technique forms an epitaxial layer locally within a trench having a stacked angular recess in a sidewall of the trench. The recess size is controlled to control the thickness of the epitaxial layer formed in the trench. The recesses are covered by a cover layer and successively exposed one after the other starting from the bottommost recess. The epitaxial layers are formed one by one within the trenches with edge portions of the crystal planes of the epitaxial layers aligned in respective recesses that are successively exposed for the epitaxial layers.)
1. An integrated circuit, comprising:
a substrate;
a first device including a first stack of separate nanowire structures of a first semiconductor material over the substrate and a first gate structure surrounding the first stack of separate nanowire structures;
a second device comprising a second stack of discrete nanowire structures of a second semiconductor material over the substrate and a second gate structure surrounding the second stack of discrete nanowire structures; and
a first insulating structure located one or more of laterally between the first device and the second device, or longitudinally between the substrate and the first device.
Technical Field
The present disclosure relates to an integrated circuit.
Background
Complementary Metal Oxide Semiconductor (CMOS) transistors are building blocks for integrated circuits. Faster CMOS switching speeds require higher drive currents, which drives the gate length of CMOS transistors to continue to shrink. The shorter gate length results in an undesirable "short channel effect" in which the current control function of the gate is compromised. FinFET transistors have been developed to overcome short channel effects. As a step to further improve electrostatic control of the channel, transistors have been developed with wrap-around gates, where the gate portions may surround the semiconductor channel or channel strip from the top surface, bottom surface, and sidewalls.
Disclosure of Invention
In one embodiment, an integrated circuit includes a substrate, a first device, a second device, and a first insulating structure. The first device includes a first stack of separate nanowire structures of a first semiconductor material over the substrate and a first gate structure surrounding the first stack of separate nanowire structures. The second device includes a second stack of isolated nanowire structures of a second semiconductor material over the substrate and a second gate structure surrounding the second stack of isolated nanowire structures. The first insulating structure is one or more of laterally between the first device and the second device, or longitudinally between the substrate and the first device.
Drawings
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. In the drawings, like reference numerals identify similar elements or acts unless context dictates otherwise. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 is a cross-sectional view of an example Integrated Circuit (IC);
FIG. 1-1 is an enlarged view of a portion of FIG. 1;
FIG. 2 is a flow chart of an exemplary process; and
fig. 3A-3M are cross-sectional views of a wafer at various stages of an example process of fabricating a nanowire stack.
[ notation ] to show
100 Integrated Circuit Structure (IC)
102 substrate
104N type doped region (N well)
106P type doped region (P well)
110 first device
112 insulating main body
113 insulating layer
114 inclined side wall
115 space
116 is recessed
116a are recessed
116b are recessed
118 upper surface
120 separating nanowire strips
130 grid
132 outer spacer
134 internal spacer
140 source/drain regions
150 second device
152 insulating body
153 insulating layer
154 sloped side wall
156 depression
156a is recessed
156b are recessed
158 upper surface
160 separating nanowire strips
170 grid
172 outer spacer
174 internal spacer
180 source/drain regions
200 process
205 operation
210 operation
215 operation
220 operation
225 operation
230 operation
235 operation
240 operation
250 operation
255 operation
300 wafer
308 upper surface of the container
308C upper surface part
310 sacrificial substrate region
312 groove
312(1) first trench dielectric portion
312(2) alternating sections
312(3) Trench dielectric portion
312(4) alternating sections
312C upper part
314 embankment structure
314C corner portion
316 side wall
316(1) first sidewall portion
316C side wall section
320 cover layer
330(1) recess
330(2) recess
330(3) recess
330(4) recess
332 plane of crystallization
332(4) upper edge
334 crystal plane
336 ridge interface
340(1) first cover layer
340(2) coating layer
340(3) coating layer
340(4) covering layer
350 epitaxial layer
350(1) epitaxial layer
350(2) epitaxial layer
350(3) epitaxial layer
350(4) epitaxial layer
350R crystal face edge part
352(1) edge of crystal plane
352(2) edge portion of crystal plane
352(3) edge portion of crystal plane
352,352(1) edge portion of crystal plane
352,352(2) edge portion of crystal plane
352,352(3) edge portion of crystal plane
352,352(4) edge portion of crystal plane
354(1) upper surface
358 hard mask layer
360 dielectric layer
362 upper surface
370 nanowire stack
370(1) silicon nanowire strip
370(2) silicon germanium nanowire strips
370(3) silicon nanowire strips
370(4) silicon germanium nanowire strips
410 sacrificial substrate region
412 trench
414 embankment structure
416 inclined side wall
460 insulating layer
470 nanowire stack
470(1) silicon germanium nanowire strips
470(2) silicon nanowire strip
470(3) silicon germanium nanowire strips
470(4) silicon nanowire strip
Detailed Description
This disclosure describes techniques for forming gate-all-around devices from stacks of partially formed nanowire semiconductor strips. The inventors have observed that edge portions of the epitaxial layer may degrade the overall quality of the epitaxial layer during local growth of the epitaxial layer in defined spaces, such as trenches. For example, the edge portions of the crystal plane of the lower epitaxial layer cause the upper epitaxial layer to form behind the edge portions of the crystal plane of the lower epitaxial layer that combine with the edge portions of the crystal plane of the upper epitaxial layer to cause further epitaxial growth defects. The disclosed technique forms an epitaxial layer within a trench having a stacked angular recess in a sidewall of the trench. The recess size is selected to control the thickness of the epitaxial layer formed in the trench. The recesses are covered by a cover layer and successively exposed one after the other starting from the bottommost recess. The epitaxial layers are formed one after the other within the trenches with their edge portions aligned into respective recesses, which are recesses to which the epitaxial layers are successively exposed. The epitaxial process includes forming etch features to limit the epitaxial layer from vertically exceeding the exposed recess. Therefore, an epitaxial layer is not formed in the vicinity of the capping layer. Epitaxial formation also includes dynamic feedback control of the thickness to enhance the accuracy of the epitaxial layer thickness. The resulting epitaxial layers each include a facet edge portion aligned into a respective recess and extending substantially flat throughout the trench and having a desired thickness. The locally formed epitaxial layer is patterned to form a nanowire stack. A gate full-loop (GAA) transistor is formed from a partially formed nanowire stack. With the epitaxial layer formed locally, the thickness of the stacked nanowire strips is optimized locally and independently for each type of transistor.
The following disclosure provides many different embodiments, or examples, for implementing different features of the described subject matter. Specific examples of components and arrangements are described below to simplify the present description. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms, such as "below … …," "below … …," "lower," "above … …," "upper," and the like, may be used herein to describe one element or feature's relationship to another element (or elements) or feature (or features) as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the present disclosure. However, it will be understood by those skilled in the art that the present disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and manufacturing techniques have not been described in detail in order to avoid unnecessarily obscuring the description of the embodiments of the present disclosure.
Throughout the specification and the claims which follow, unless the context requires otherwise, the word "comprise", and variations such as "comprises" and "comprising", will be interpreted in an open-ended sense, that is, in an "including, but not limited to".
Use of ordinals (such as first, second and third) does not necessarily imply a ranking meaning for an order, but may merely distinguish between multiple instances of an action or structure.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
As used in this specification and the appended claims, the singular forms "a", "an" and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense including "and/or" unless the context clearly dictates otherwise.
The gate all-around (GAA) transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing for the generation of patterns with pitches that are smaller, for example, than pitches that could otherwise be obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. The spacers are formed using a self-aligned process with the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.
Fig. 1 is a cross-sectional view of an example integrated circuit structure (IC)100 including CMOS components. Referring to fig. 1, an IC 100 includes a
Furthermore, the insulating bodies 112, 152 may be the same layer of dielectric material, e.g., the insulating bodies 112, 152 may be formed by the same deposition process of the same dielectric material. The insulative bodies 112, 152 are labeled with different numbers to indicate that such insulative bodies are associated with the first device 110 or the second device 150, respectively. In other embodiments, the insulating bodies 112, 152 are formed by different processes. The N-well 104 and P-well 106 are optional. In some embodiments, one or more of the devices 110, 150 are not formed within the doped
The first device 110 and the second device 150 each include a vertical stack of multiple (two for illustration) separate nanowire strips 120, 160 and gates 130, 170 surrounding the respective separate nanowire strips 120, 160. The separate nanowire strips 120, 160 are configured as channel regions of the devices 110, 150 and form junctions with the respective source/drain regions 140, 180. The source/drain regions 140, 180 are separated from the respective gates 130, 170 by the inner spacers 134, 174 and/or the outer spacers 132, 172.
In one embodiment, the nanowire strips 120 are silicon germanium or other suitable semiconductor material. The source/drain regions 140 are doped silicon germanium or other suitable semiconductor material. The dopant is an element in group iii such as boron, gallium, indium, and the like. The nanowire strips 160 are silicon or other suitable semiconductor material. Source/drain regions 180 are doped silicon or other suitable semiconductor material. The dopant is an element in group V, such as arsenic, phosphorus, and the like.
Fig. 1 illustrates two embodiments of source/drain structures 140, 180. In the embodiment illustrated with respect to source/drain structures 140, source/drain structures 140 contact nanowire strip 120 through an edge surface of nanowire strip 120. Furthermore, the source/drain structures 140 are patterned to have spaces 115 between the source/drain structures 140 and the sloped sidewalls 114 of the insulating body 112. In the embodiment illustrated with respect to the source/drain structure 180, the source/drain structure 180 extends all the way to the insulating body 152, or specifically into the recess 156 on the sloped sidewall 154. Other structural configurations of the source/drain structures 140/180 and the semiconductor strips 120/160 are also possible and are included in the present disclosure. For example, the source/drain structures 140/180 may surround at least some of the nanowire strips 120/160. The nanowire strips 120, 160 may be retracted (as shown at 120) or extend all the way between the recesses 156 of the insulating body 152 (and/or the recesses 116 of the insulating body 112).
Fig. 1 illustrates an illustrative example of source/drain structures 140, 180 that do not limit the scope of the present disclosure. Other embodiments of the source/drain structures 140, 180 are also possible and are included in the present disclosure.
The
Each of the gate structures 130, 170 is formed as a replacement metal gate. The following description lists examples of materials for the gate structures 130, 170. The gate electrodes of the gates 130, 170 each comprise a conductive material, such as a metal or metal compound. Suitable metal materials for the gate electrodes of gate structures 130, 170 include ruthenium, palladium, platinum, tungsten, cobalt, nickel, and/or conductive metal oxides, as well as other suitable P-type metal materials, and include hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), aluminides, and/or conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), as well as other suitable materials for N-type metal materials. In some examples, the gate electrodes of the gate structures 130, 170 each include a work function layer tailored to have an appropriate work function for enhanced performance of the field effect transistor device. For example, suitable N-type work function metals include Ta, TiAl, TiAlN, TaCN, other N-type work function metals, or combinations thereof, and suitable P-type work function metal materials include TiN, TaN, other P-type work function metals, or combinations thereof. In some examples, a conductive layer (such as an aluminum layer, a copper layer, a cobalt layer, or a tungsten layer) is formed over the work function layer such that the gate electrodes of the gate structures 130, 170 each include a work function layer disposed over the gate dielectric and a conductive layer disposed over the work function layer and under the gate cap (not shown for simplicity). In one example, the gate electrodes of the gate structures 130, 170 each have a thickness in a range from about 5nm to about 40nm, depending on design requirements.
In an exemplary embodiment, the gate dielectric layer comprises an interfacial silicon oxide layer (not separately shown for simplicity), e.g., having a range of about 5 to about 10 angstroms
Thermal or chemical oxide of thickness (v). In example embodiments, the gate dielectric layer further comprises a high dielectric constant (high-k) dielectric material selected from one or more of: hafnium oxide (HfO)2) Hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), combinations thereof, and/or other suitable materials. In some applications, the high-k dielectric material includes a dielectric constant (k) value greater than 6. Dielectric materials having a dielectric constant (k) value of 7 or higher are used depending on design requirements. The high dielectric constant dielectric layer may be formed by Atomic Layer Deposition (ALD) or other suitable techniques. According to embodiments described herein, the high-k dielectric layer of the gate dielectric layer comprises a range of about 10 to about 30 angstromsOr other suitable thickness.In one embodiment, the outer spacers 132, 172 are formed of a low-k dielectric material, such as silicon oxynitride (SiON), silicon monoxide (SiO), silicon oxycarbide (SiONC), silicon oxycarbide (SiOC), vacuum, and other dielectrics or other suitable materials. The outer spacers 132, 172 may be formed by Chemical Vapor Deposition (CVD), high density plasma CVD, spin coating, sputtering, or other suitable methods.
In one embodiment, the inner spacers 134, 174 are formed of a low-k dielectric material (e.g., a dielectric constant value less than 6). The low-k dielectric material of the inner spacers 134, 174 may have a dielectric constant that is different from the dielectric constant of the corresponding outer spacers 132, 172. The low dielectric constant material of the inner spacers 134, 174 may include one or more of the following: silicon monoxide (SiO), silicon oxycarbonitride (SiONC), silicon oxycarbide (SiOC), silicon carbide (SiC), or other suitable low-k dielectric material. In one embodiment, the dielectric constant of the material of the inner spacers 134, 174 is the same as the dielectric constant of the material of the outer spacers 132, 172. In one example, the inner spacers 134, 174 also include one or more air gaps near one or more of the respective gate structures 130, 170 or the respective source/drain structures 140, 180.
The insulating or semiconductor bodies 112, 152 each include generally sloped sidewalls 114, 154 (illustrated in phantom). In an embodiment, the
The insulating body 152 may comprise the same or different dielectric material as the insulating body 112. Semiconductor body 112/152 may include the same or different semiconductor material as
In other embodiments, the insulating body 112 and the insulating body 152 may both be insulating bodies of the same or different dielectric materials or both be semiconductor bodies of the same or different semiconductor materials.
In another embodiment, the insulating bodies 112, 152 may be replaced with a semiconductor material that is the same as or different from the semiconductor material of the nanowire strips 120, 160.
The nanowire ribbon 120 and the nanowire ribbon 160 are formed from a stack of epitaxial layers, each formed by local epitaxial growth. Nanowire strip 120 and nanowire strip 160 can comprise different thicknesses. Furthermore, because the sacrificial strip used in fabricating one of the devices 110, 150 and the nanowire strips 120, 160 of the other of the first and second devices 110, 150 are not fabricated from the same epitaxial layer, the internal spacers 134, 174 of one of the first and second devices 110, 150 may not be laterally aligned with the nanowire strips 160, 120 of the other of the first and second devices 110, 150. Note again that the following will be described in more detail: the nanowire ribbon 120 and the nanowire ribbon 160 are formed from a stack of epitaxial layers, each formed in a local epitaxial growth.
Fig. 1 illustrates that the insulating bodies 112, 152 completely separate the first device 110 and the second device 150 from the
Fig. 1 illustrates that the first device 110 and the second device 150 are each partially embedded in the respective N-well 104 or P-well 106 of the
Moreover, the present disclosure includes that one of the first device 110 and the second device 150 may be formed using other techniques. For example, one of the first device 110 or the second device 150 may not include a respective recess 116, 156 in a sidewall of the insulative body.
Fig. 1 illustrates the use of a dual-tub process, i.e., the formation of both P-
In an embodiment, the spaces 113, 153 between the first means 110, the second means 150 and the respective insulating/semiconductor bodies 112, 152 may be voids, air gaps, may be completely or partially filled with a dielectric material, or may be completely or partially filled with a semiconductor material. The dielectric material in the spaces 113, 153 may be the same dielectric material as the respective insulating bodies 112 or may be a different dielectric material. Furthermore, the spaces 113, 153 may be at least partially filled with a semiconductor material. The semiconductor material in the spaces 113, 153 may be the same semiconductor material as the respective source/drain structures 140, 180 or may be a different semiconductor material. Furthermore, some of the recesses 116, 156 may be at least partially filled with a semiconductor material similar to that of the nanowire strips 120, 160.
In other embodiments, as illustrated in fig. 1 with respect to the first and second devices 110, 150, respectively, the spaces 113, 153 are absent and the recesses 116, 156 are each near the semiconductor nanowire strips 120, 160, the respective source/drain structures 140, 180, or other nanowire strips.
Fig. 2 illustrates an example process of manufacturing an IC device (e.g., the example IC 100 of fig. 1). Fig. 3A-3M illustrate in cross-sectional views different stages of a
In an
Referring back to fig. 2, and also to fig. 3B, in an
In another embodiment, no sacrificial substrate region is formed and subsequent processing is alternatively performed with one or more of the N-
In another embodiment, Shallow Trench Isolation (STI) regions are formed between and/or within the N-
Referring back to fig. 2, also referring to fig. 3C, in an
The
Fig. 3C illustrates that the
As described herein, the
Referring back to fig. 2, and also to fig. 3D, in an
An
In some of the figures described below, only the N-well 104 portion of the
Referring back to fig. 2, and also to fig. 3E, in an
Referring back to fig. 2, and also to fig. 3F, in an
The profile of the angular recesses 330(1) is controlled to conform to or be in line with the edge portions of the angular crystal planes of the epitaxial layers formed within the
It is also contemplated that the first recess 330(1) may have other contours (e.g., semi-elliptical), as are included in the present disclosure. Furthermore, depending on the etch timing, the etch may also terminate before the high etch rate
Referring back to fig. 2, and also to fig. 3G, in an
Referring to fig. 3H, the sequence of
Each of the recesses 330(1), (330), (2), (330), (3), (330), (4) is covered by at least one covering layer 340 (here, 340), (1), (340), (2), (340), (3), and 340 (4)). The higher recesses 330 stacked along the sloped
If the
In one embodiment, the thickness of the dielectric portion (e.g., 312(2)) of the removed
Referring back to fig. 2, and also to fig. 3I, in an
In
Because edge 352(1) of epitaxial layer 350(1) is aligned in angled recess 330(4), upper surface 354(1) of epitaxial layer 350(1) is substantially planar. The epitaxial layer thus extends substantially throughout the space defined by the upper edge 332(4) of the recess 330 (4). By aligning into angled recess 330(4), the crystallographic edge 352(1) of epitaxial layer 350(1) need not fit perfectly into recess 330 (4). In one embodiment, even if edge 352(1) of epitaxial layer 350(1) does not perfectly fit into recess 330(4), the planarity of surface 354(1) may be improved. In another embodiment, as shown in FIG. 3I-1, the profile of recess 330(4) is controlled such that edge portion 352(1) of the crystallographic plane of epitaxial layer 350(1) is completely contained within recess 330 (4). For example, the etch rate difference between
Referring to fig. 3J,
Closely adjacent epitaxial layers 350 (e.g., 350(2) and 350(3)) comprise different semiconductor materials. Alternating epitaxial layers 350 (e.g., 350(2) and 350(4)) comprise the same semiconductor material. In one embodiment, epitaxial layers 350(1) and 350(3) are silicon or other suitable semiconductor material. Epitaxial layers 350(2) and 350(4) are silicon germanium or other suitable semiconductor materials. Epitaxial layers 350(1), 350(3) of silicon include the
Because edge portions of each of
Referring back to fig. 2, and also to fig. 3K, in an
In other embodiments, the "sacrificial"
Fig. 3K illustrates a planarization process (e.g., CMP) performed such that
Referring back to fig. 2, also referring to fig. 3L, in an example operation 255, the stack of
A similar process is also performed in P-well 106 to create nanowire stack 470. As shown in fig. 3M, the nanowire stack 470 includes silicon germanium nanowire strips 470(1), 470(3) and silicon nanowire strips 470(2), 470(4) stacked in an alternating sequence, wherein the silicon nanowire strip 470(4) is stacked as the topmost strip. Since nanowire stack 470 is fabricated separately from
In one example, the
The nanowire stack 470 is used to fabricate NMOS devices having channel regions fabricated from silicon nanowire strips 470(2), 470 (4). The silicon germanium nanowire strips 470(1), 470(3) are removed as sacrificial strips and replaced with gate structures. Thus, in the resulting NMOS transistor, the gate structure surrounds the surface of the silicon nanowire strip.
Fig. 1 illustrates example CMOS components of an integrated circuit fabricated from a
In addition, the disclosed technique for forming an epitaxial layer solves the problems generated by the edge portions of the angular crystal plane of the epitaxial layer. The resulting epitaxial layer is substantially planar and extends in the entire trench of the local epitaxial growth region (i.e., the sacrificial substrate region). Thereby, the product quality can be improved and the size of the space between the devices can be further reduced.
The disclosure may be further understood with reference to the following description of embodiments:
in one embodiment, an integrated circuit includes a substrate, a first device, a second device, and a first insulating structure between the first device and the second device. The first device includes a first stack of isolated nanowire structures of a first semiconductor material over a substrate, and a first gate structure surrounding the first stack of isolated nanowire structures. The second device includes a second stack of isolated nanowire structures of a second semiconductor material over the substrate, and a second gate structure surrounding the second stack of isolated nanowire structures.
In one embodiment, the integrated circuit further comprises a second insulating structure that is one or more of laterally between the first device and the second device, or longitudinally between the substrate and the second device.
In one embodiment, the first stack of split nanowire structures includes a first split nanowire structure and a second split nanowire structure vertically adjacent to the first split nanowire structure, the second split nanowire structure is vertically separated from the first split nanowire structure by a portion of the first gate structure, and a thickness of the portion of the first gate structure is different in a vertical direction from a thickness of a third split nanowire structure of the second stack of split nanowire structures.
In one embodiment, the first semiconductor material is silicon and the second semiconductor material is silicon germanium.
In one embodiment, the first insulating structure is embedded in a first doped region of the substrate.
In one embodiment, the second insulating structure is embedded in a second doped region of the substrate.
In another embodiment, a method includes forming a second substrate region within a first substrate region. A trench is formed in the second substrate region, and a bank structure of the second substrate region is formed around the trench. The bank structure includes sloped sidewall portions and upper corners. The trench is filled with a different material than the second substrate region. The first sidewall portion of the sloped sidewall is exposed. A first recess is formed in the exposed first sidewall portion. A first dielectric capping layer is formed overlying the first recess. Exposing a second sidewall portion of the sloped sidewall. The second sidewall portion is below the first sidewall portion. A second depression is formed in the exposed second sidewall portion below the first angular depression. A second dielectric capping layer is formed overlying the second recess and extending over the first dielectric capping layer. The second recess is exposed while the first recess remains covered. A first semiconductor epitaxial layer is formed in the trench, wherein a crystallographic plane edge portion of the first semiconductor epitaxial layer is aligned into the second recess. Exposing the first angular depression. A second semiconductor epitaxial layer is formed in the trench above the first semiconductor epitaxial layer, wherein a crystallographic edge portion of the second semiconductor epitaxial layer is aligned into the first recess.
In one embodiment, the method further comprises forming a dielectric capping layer covering the upper corners of the trench.
In one embodiment, the method further comprises forming an oxide layer between the dielectric capping layer and an upper surface of the bank.
In one embodiment, the first sidewall portion and the second sidewall portion include a different thickness in a vertical direction.
In one embodiment, the inclined sidewall defines a space that is substantially a convex isosceles trapezoid in a cross-sectional view.
In one embodiment, the method further comprises: forming an aperture by removing a remaining portion of the bank structure; and forming an insulating body by filling the aperture with a dielectric material.
In one embodiment, filling the aperture with a dielectric material comprises: a planarization process is performed to make the insulating body and the second semiconductor epitaxial layer substantially at a same level.
In one embodiment, the method further comprises: forming a vertical stack of a first semiconductor strip and a second semiconductor strip by patterning the first semiconductor epitaxial layer and the second semiconductor epitaxial layer; removing one of the first semiconductor strip or the second semiconductor strip; and forming a gate structure surrounding at least three surfaces of the other of the first semiconductor strip or the second semiconductor strip.
In one embodiment, the method further comprises: removing a portion of the second substrate region under the trench; and forming an insulating body below the trench.
In an embodiment, a trench is formed extending down through the second substrate region and reaching the first substrate region.
In one embodiment, the first substrate region is a doped substrate region.
In a further embodiment, a method includes receiving a wafer including a substrate having a P-well and an N-well. The first substrate body is formed in the P-well, and the second substrate body is formed in the N-well. The first trench is formed in the first substrate body, and the second trench is formed in the second substrate body. The first trench and the second trench have sloped sidewalls. A first recess is formed on the sloped sidewall of the first trench. The second recess is formed on the sloped sidewall of the second trench. The second recess has a different thickness than the first recess. A first epitaxial layer of a first semiconductor material is formed in the first trench with a crystalline surface edge portion of the first semiconductor epitaxial layer extending into the first recess. A second epitaxial layer of the first semiconductor material is formed in the second trench, wherein a crystallographic plane edge portion of the second semiconductor epitaxial layer extends into the second recess. The second epitaxial layer has a different thickness than the first epitaxial layer.
In one embodiment, the first and second epitaxial layers are not aligned with each other in a lateral direction.
In one embodiment, the method further comprises: forming an aperture by removing at least one of the first substrate body or the second substrate body; and forming an insulating body by filling a dielectric material into the void.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
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