阅读说明：本技术 存储器装置的形成方法 (Method for forming memory device ) 是由 卓旭棋 杨政达 于 2018-06-26 设计创作，主要内容包括：本发明提供一种存储器装置的形成方法。存储器装置的形成方法包括在衬底上形成浮栅极,以及在浮栅极上形成控制栅极。存储器装置的形成方法也包含在控制栅极上形成遮罩层,以及在遮罩层的侧壁上形成间隙物,其中间隙物覆盖控制栅极的侧壁和浮栅极的侧壁。存储器装置的形成方法还包括实施离子注入工艺以将掺质注入间隙物的上部,以及实施湿法腐蚀工艺以暴露出控制栅极的侧壁。本发明具有防止湿法腐蚀液沿着氧化物中的孔隙和孔洞向下刻蚀,每一个控制栅极暴露出的侧壁部分具有大抵相同的高度,以及实施离子注入工艺并不会对控制栅极和浮栅极的电性造成影响的有益效果。(The invention provides a forming method of a memory device. The method of forming a memory device includes forming a floating gate on a substrate and forming a control gate on the floating gate. The method also includes forming a mask layer over the control gate, and forming spacers on sidewalls of the mask layer, wherein the spacers cover sidewalls of the control gate and sidewalls of the floating gate. The method for forming the memory device further includes performing an ion implantation process to implant dopants into an upper portion of the spacers, and performing a wet etching process to expose sidewalls of the control gate. The invention has the advantages that wet etching liquid is prevented from etching downwards along the holes and the holes in the oxide, the side wall part exposed by each control grid electrode has the same height, and the electric property of the control grid electrode and the floating grid electrode is not influenced by implementing the ion implantation process.)

1. A method of forming a memory device, comprising:

forming a floating gate on a substrate;

forming a control grid on the floating grid;

forming a mask layer on the control gate;

forming a spacer on the sidewall of the mask layer, wherein the spacer covers a sidewall of the control gate and a sidewall of the floating gate;

performing an ion implantation process to implant a dopant into an upper portion of the spacer; and

a wet etch process is performed to expose the sidewalls of the control gate.

2. The method of claim 1, wherein the ion implantation process further comprises implanting dopants into the mask layer and the control gate.

3. The method of forming a memory device of claim 1, further comprising:

forming a liner layer on the sidewall of the spacer; and

forming a filling dielectric layer on the side wall of the lining layer, wherein the ion implantation process further comprises implanting the dopant into the lining layer and the filling dielectric layer.

4. The method of claim 1, wherein said wet etching process is performed to remove said mask layer and said upper portion of said spacers.

5. The method of forming a memory device of claim 1, further comprising:

forming a metal layer on the control gate; and

an annealing process is performed to perform a silicidation reaction, wherein the silicidation reaction converts an upper portion of the control gate and the metal layer into a silicide layer.

6. A method of forming a memory device, comprising:

forming a floating gate on a substrate;

forming a control grid on the floating grid;

forming a spacer on the sidewall of the control gate;

performing an ion implantation process to implant a dopant into an upper portion of the spacer, wherein the upper portion of the spacer has a conductivity type identical to that of the floating gate after the ion implantation process is performed; and

a wet etch process is performed to remove the upper portion of the spacer.

7. The method of forming a memory device of claim 6, further comprising:

forming a liner layer on the sidewall of the spacer; and

forming a filling dielectric layer on the side wall of the lining layer, wherein the ion implantation process further comprises implanting the dopant into an upper portion of the lining layer and an upper portion of the filling dielectric layer, and the wet etching process further comprises removing the upper portion of the filling dielectric layer.

8. The method of forming a memory device of claim 7, further comprising:

after the wet etching process is performed, a dry etching process is performed to remove the upper portion of the liner layer.

9. A method of forming a memory device, comprising:

providing a substrate comprising a peripheral circuit region and an array region;

forming a first control grid and a second control grid on the peripheral circuit area of the substrate, wherein a first groove is arranged between the first control grid and the second control grid;

forming a spacer on a sidewall of the first trench, wherein a top surface of the spacer is higher than top surfaces of the first control gate and the second control gate;

performing an ion implantation process to implant a dopant into the spacer, the first control gate and the second control gate; and

after the ion implantation process is performed, a wet etching process is performed to expose the sidewall of the first trench.

10. The method of forming a memory device of claim 9, further comprising:

forming a third control gate and a fourth control gate on the array region of the substrate, wherein a second trench is formed between the third control gate and the fourth control gate, and the width of the second trench is smaller than that of the first trench; and

forming a dielectric layer in the second trench, wherein the ion implantation process implants the dopant into the dielectric layer, the third control gate and the fourth control gate,

the dielectric layer of the array area and the spacers of the peripheral circuit area are made of the same material and are formed by the same process, and the side walls of the second grooves are exposed after the wet etching process is carried out.

Technical Field

The present invention relates to a method for manufacturing a memory device, and more particularly, to a method for forming a memory device.

Background

In a non-volatile memory, data in the memory can be rewritten at any time when using a computer, and the non-volatile memory can be divided into two major products, i.e., a read-only memory (ROM) and a flash memory (flash memory). Among them, flash memory is becoming the mainstream technology of non-volatile memory because of its low cost.

Generally, a flash memory includes two gates, a first gate is a floating gate (floating gate) for storing data, and a second gate is a control gate (control gate) for inputting and outputting data. The floating gate is under the control gate and is in a "floating" state. Floating refers to surrounding and isolating the floating gate with an insulating material to prevent charge loss. The control gate is connected to a Word Line (WL) to control the device. One of the advantages of flash memory is that it can be block-by-block erased (blb-block erase). Flash memory is widely used in enterprise servers, storage and network technologies, and a wide range of consumer electronics products, such as flash drive (USB), mobile phones, digital cameras, tablet computers, personal computer cards (PC cards) for notebooks, and embedded controllers, among others.

Although existing methods for forming non-volatile memories are adequate for their intended purposes, they have not been completely satisfactory in every aspect, and thus there is still a need in the art for non-volatile memories.

Disclosure of Invention

According to some embodiments, a method of forming a memory device is provided. A method of forming a memory device includes forming a floating gate on a substrate and forming a control gate on the floating gate. The method also includes forming a mask layer over the control gate, and forming spacers on sidewalls of the mask layer, wherein the spacers cover sidewalls of the control gate and sidewalls of the floating gate. The method further includes performing an ion implantation process to implant dopants into the upper portion of the spacers and performing a wet etching process to expose sidewalls of the control gate.

According to some embodiments, a method of forming a memory device is provided. A method of forming a memory device includes forming a floating gate on a substrate and forming a control gate on the floating gate. The method also includes forming spacers on sidewalls of the control gate, and performing an ion implantation process to implant dopants into upper portions of the spacers, wherein the upper portions of the spacers have a same conductivity type as the floating gate after the ion implantation process is performed. The method further includes performing a wet etch process to remove an upper portion of the spacers.

According to some embodiments, a method of forming a memory device is provided. The method for forming the memory device comprises the steps of providing a substrate comprising a peripheral circuit area and an array area, and forming a first control grid and a second control grid on the peripheral circuit area of the substrate, wherein a first groove is formed between the first control grid and the second control grid. The method also includes forming spacers on sidewalls of the first trench, wherein top surfaces of the spacers are higher than top surfaces of the first and second control gates, and performing an ion implantation process to implant dopants into the spacers, the first and second control gates. The method further includes performing a wet etching process to expose sidewalls of the first trench after performing the ion implantation process.

The invention has the beneficial effects that: by performing the ion implantation process before the wet etching process, the wet etching solution is prevented from etching down along the pores and holes in the oxide. As a result, the exposed sidewall portions of each control gate have substantially the same height after the wet etch process. On the other hand, since the ion implantation process uses the same conductivity type dopant (or the same dopant) as the control gate and the floating gate, the ion implantation process does not affect the electrical properties of the control gate and the floating gate.

In order to make the features and advantages of the present disclosure more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1-9 are cross-sectional views illustrating various stages in forming a memory device, according to some embodiments of the present disclosure.

Reference numerals

11-peripheral circuit area;

12-array area;

100-memory devices;

101-a substrate;

103-tunneling oxide layer;

105-floating grid;

107. 119b, 121-dielectric layers;

109-control grid;

111-an oxide layer;

113 mask layer;

115-first trench;

117 to a second trench;

119 a-spacers;

123-lining layer;

125-filling the dielectric layer;

130-ion implantation process;

131-metal silicide layer;

d1-a first height difference;

d2-second height difference;

t-thickness;

w1, W2-width.

Detailed Description

The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings of embodiments of the disclosure. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings may be exaggerated for clarity. The same or similar reference numbers refer to the same or similar elements, and the following paragraphs will not be repeated.

Fig. 1-9 are cross-sectional views illustrating different stages in forming the memory device 100 of fig. 9, according to some embodiments of the present disclosure.

As shown in fig. 1, a substrate 101 is provided, the substrate 101 including a peripheral circuit region 11 and an array region 12 adjacent to the peripheral circuit region 11. In some embodiments, the material of the substrate 101 may include silicon, gallium arsenide, gallium nitride, germanium silicide, Silicon On Insulator (SOI), other suitable materials, or a combination thereof.

In some embodiments, a tunnel oxide layer 103 is formed on a substrate 101, and then a plurality of floating gates 105, a plurality of dielectric layers 107, and a plurality of control gates 109 are sequentially formed on the tunnel oxide layer 103. The material of the floating gate 105 and the control gate 109 may include polysilicon, and may be formed using a deposition process and a patterning process. In addition, dopants may be selectively implanted into the floating gate 105 and the control gate 109, and in this embodiment, P-type dopants, such as phosphorus (P), may be implanted into the floating gate 105 and the control gate 109. In some embodiments, the floating gate 105 and the control gate 109 may each be one or more layers of structure. In addition, the dielectric layer 107 serves as a dielectric layer between the floating gate 105 and the control gate 109, and may be a multi-layer structure, such as a multi-layer structure formed of oxide-nitride-oxide (ONO).

Referring again to fig. 1, an oxide layer 111 may be formed on sidewalls of each of the floating gates 105, the dielectric layer 107, and the control gates 109 on both sides thereof, and a mask layer 113 may be formed on each of the control gates 109. In some embodiments, the floating gate 105, the dielectric layer 107 and the control gate 109 are formed by patterning using the mask layer 113 as a mask, so that the floating gate 105, the dielectric layer 107 and the control gate 109 have coplanar sidewalls.

Furthermore, in some embodiments, the top surface of the oxide layer 111 and the top surface of the control gate 109 are substantially coplanar, i.e., the oxide layer 111 does not cover the sidewalls of the two sides of the mask layer 113. In addition, the material of the mask layer 113 may be an oxide, such as Tetraethoxysilane (TEOS) oxide.

In peripheral circuit region 11, there is a first trench 115 between two adjacent floating gates 105, dielectric layer 107 and control gate 109, and first trench 115 has a width W1. In array region 12, there is a second trench 117 between two adjacent floating gates 105, dielectric layer 107 and control gate 109, and second trench 117 has a width W2. It is noted that width W1 of first trench 115 is greater than width W2 of second trench 117, and widths of control gate 109, dielectric layer 107 and floating gate 105 of peripheral circuit region 11 are greater than widths of control gate 109, dielectric layer 107 and floating gate 105 of array region 12.

In some embodiments, the control gate 109 and the floating gate 105 in the peripheral circuit region 11 serve as control units (also referred to as select gates) of the memory device 100 to be formed later, and the control gate 109 and the floating gate 105 in the array region 12 serve as storage units of the memory device 100.

Subsequently, as shown in fig. 2, spacers 119a are formed in the first trench 115, and a dielectric layer 119b is formed in the second trench 117. In some embodiments, the spacers 119a and the dielectric layer 119b may comprise the same material and be formed in the same process. For example, the spacers 119a and the dielectric layer 119b may be made of silicon oxide.

The spacers 119a and the dielectric layer 119b are formed by conformably forming a layer of spacer material (not shown) over the mask layer 113, in the first trench 115 and in the second trench 117. Since the width W1 of the first trench 115 is greater than the width W2 of the second trench 117, different cross-sections are formed in the peripheral circuit region 11 and the array region 12 when the gap material layer is formed. Specifically, the gap material layer completely fills the second trenches 117 of the array region 12, but does not completely fill the first trenches 115 of the peripheral circuit region 11.

Subsequently, an etch back process is performed to remove the gap material layer on the mask layer 113, and simultaneously remove a portion of the gap material layer and a portion of the tunnel oxide layer 103 in the first trench 115. After the etch back process, the top surface of the portion of the substrate 101 is exposed. As a result, spacers 119a are formed on the sidewalls of the first trenches 115, and dielectric layers 119b filling the second trenches 117 are formed within the second trenches 117. It is noted that the top surface of the control gate 109 is covered by the mask layer 113, and the top surface of the spacer 119a is higher than the top surface of the control gate 109. In other words, the spacers 119a cover sidewalls of the capping layer 113, sidewalls of the control gate 109, and sidewalls of the floating gate 105.

According to some embodiments, a dielectric layer 121 is formed over the mask layer 113, the dielectric layer 119b, and the exposed top surface of the substrate 101, as shown in FIG. 3. The material of the dielectric layer 121 may be silicon oxide and may be formed using any suitable deposition process. The substrate 101 in the first trench 115 may then be implanted with dopants, such as P-type dopants, using a masking layer (not shown).

Then, as shown in fig. 4, a liner 123 is conformably formed on the dielectric layer 121 and within the first trench 115, and a fill dielectric layer 125 is formed on the liner 123 within the first trench 115. In some embodiments, the material of liner 123 may be silicon nitride, and may be formed using any suitable deposition process. Specifically, the liner 123 covers sidewalls of the spacers 119a in the first trench 115 and a top surface of the dielectric layer 121.

Furthermore, the material of the fill dielectric layer 125 may be silicon oxide, and may be formed using any suitable deposition process. The filling dielectric layer 125 may be formed by forming a dielectric material layer (not shown) on the liner layer 123, and then performing a Chemical Mechanical Polishing (CMP) process to remove the dielectric material layer outside the first trench 115, leaving a portion on the sidewall of the liner layer 123 of the first trench 115, which is the filling dielectric layer 125.

Next, as shown in FIG. 5, an etching process, such as a dry etch, is performed to remove the liner 123, the dielectric layer 121, a portion of the mask layer 113, and a portion of the dielectric layer 119b over the mask layer 113. As a result, the remaining mask layer 113 has a thickness T. In some embodiments, the thickness T is about 25 nm. In this step, a portion of the mask layer 113 is left to ensure that the control gate 109 is not affected by the dry etch.

According to some embodiments, an ion implantation process 130 is performed to implant dopants into the upper portion of the spacers 119a, as shown in fig. 6. In some embodiments, the dopants are implanted into the mask layer 113, the dielectric layer 119b, the spacers 119a, the liner 123, the fill dielectric layer 125, the oxide layer 111, and the control gate 109 globally. Specifically, dopants are implanted into the upper portion of dielectric layer 119b, the upper portion of spacers 119a, the upper portion of liner 123, the upper portion of fill dielectric layer 125, the upper portion of oxide layer 111, and the upper portion of control gate 109.

In some embodiments, the ion implantation process 130 uses dopants of the same conductivity type as the control gate 109 and the floating gate 105. In this embodiment, a P-type dopant, such as phosphorus (P), is used. In addition, the implantation energy of the ion implantation process 130 is in a range of about 30keV to about 50keV, and the dopant amount is in a range of about 2.5x1015 ions/cm 2 to about 5x1015 ions/cm 2. However, in other embodiments, other P-type dopants or other conductive dopants may be used, and the implantation energy and the dopant amount of the ion implantation process 130 may be adjusted according to the actual process requirements, and are not limited to the above ranges.

Next, as shown in fig. 7, a wet etching process is performed to expose a portion of the sidewall of the control gate 109. Specifically, a wet etching process is performed to remove the mask layer 113, and the upper portion of the doped dielectric layer 119b, the upper portion of the spacers 119a, the upper portion of the filling dielectric layer 125 and the upper portion of the oxide layer 111 are implanted in the foregoing processes. In other words, after the wet etching process is performed, a portion of the sidewall of the first trench 115 and a portion of the sidewall of the second trench 117 are exposed.

In this embodiment, the wet etching process uses buffered hydrofluoric acid (BHF) as the etching solution. The mask layer 113 made of oxide and a part of the dielectric layer 119b, the spacers 119a, the filling dielectric layer 125 and the oxide layer 111 are removed by buffered hydrofluoric acid etching. Notably, the buffered hydrofluoric acid does not remove the liner 123 made of silicon nitride. In other embodiments, the wet etching process may use other suitable etching solutions.

After the wet etching process is performed, a first height difference D1 is formed between the top surface of the remaining dielectric layer 119b and the top surface of the adjacent control gate 109, and the first height difference D1 is about 50 nm. In addition, since the top surfaces of the remaining spacers 119a and the top surfaces of the remaining dielectric layers 119b are substantially coplanar, the top surfaces of the remaining spacers 119a and the top surfaces of the adjacent control gates 109 also have a first height difference D1 in the peripheral circuit region 11.

Subsequently, as shown in fig. 8, a dry etching process, such as Reactive Ion Etching (RIE), is performed to remove the upper portion of the liner 123 implanted with the dopant in the foregoing process. Specifically, since the dry etching process has an etching selectivity of 1:1 for oxide and nitride, the dry etching process simultaneously removes portions of the dielectric layer 119b, the spacers 119a, the filling dielectric layer 125, and the oxide layer 111.

In addition, after the dry etching process is performed, a second height difference D2 is formed between the top surface of the remaining dielectric layer 119b and the top surface of the adjacent control gate 109, the second height difference D2 is greater than the first height difference D1, and the second height difference D2 is about 70 nm. In addition, since the top surfaces of the remaining spacers 119a and the top surfaces of the remaining dielectric layers 119b are substantially coplanar, the top surfaces of the remaining spacers 119a and the top surfaces of the adjacent control gates 109 also have a second height difference D2 in the peripheral circuit region 11.

In the present embodiment, a wet etching process and a dry etching process are used to expose a portion of the control gate 109, and the exposed portion (also referred to as a protruding portion) of the control gate 109 has a height of about 70 nm. However, in other embodiments, the dry etch process may be omitted, for example one or more wet etch processes may be used to expose the control gate of about 70 nm.

As described above, the oxide (e.g., the oxide layer 111, the spacers 119a, and the dielectric layer 119b) on the sidewalls of the first trench 115 and the second trench 117 is isotropically (isotropically) removed by performing a wet etching process. By controlling the time of the wet etching process, a planar surface may be formed in the first trench 115 and the second trench 117 after the wet etching process is performed. In other words, in the first trench 115, the top surfaces of the remaining spacers 119a and the oxide layer 111 and the sidewalls of the adjacent control gates 109 have an included angle of about 90 degrees. Similarly, in the second trench 117, the top surfaces of the remaining dielectric layer 119b and the oxide layer 111 have an angle of about 90 degrees with the sidewall of the adjacent control gate 109.

In addition, the ion implantation process 130 is performed before the wet etching process is performed, so that the etching solution is prevented from etching down the pores and holes in the oxide (e.g., the oxide layer 111, the spacers 119a, and the dielectric layer 119 b). As a result, the exposed sidewall portions of each control gate 109 have substantially the same height (e.g., about 70nm) after the wet etch process. On the other hand, since the ion implantation process 130 uses the same conductivity type dopant (or the same dopant) as the control gate 109 and the floating gate 105, the electrical properties of the control gate 109 and the floating gate 105 are not affected by the ion implantation process 130.

According to some embodiments, the protruding portion of the control gate 109 is converted into a metal silicide layer 131, as shown in fig. 9. The formation method of the metal silicide layer 131 includes forming a metal layer (not shown) on the control gate 109, and then performing an annealing process to perform a metal silicidation reaction to convert the metal layer on the upper portion of the control gate 109 and above the control gate into the metal silicide layer 131.

In some embodiments, the material of the metal layer may comprise cobalt (Co), nickel (Ni), or other suitable metal. In addition, a Physical Vapor Deposition (PVD) process, a sputtering process, or other suitable process may be used to form the metal layer. In some embodiments, one or more annealing processes may be used to perform the silicidation reaction. For example, a first annealing process at a temperature in the range of about 400 ℃ to about 600 ℃ and a second annealing process at a temperature in the range of about 600 ℃ to about 800 ℃ may be sequentially used. After performing the annealing process, a metal silicide 131 comprising cobalt disilicide (CoSi2), cobalt silicide (CoSi), or a mixture of the foregoing may be formed.

After performing the annealing process, subsequent process steps may be performed to complete the memory device 100. The subsequent process steps may include, for example, forming contact plugs (not shown) for electrical connection on the metal silicide layer 131 in the peripheral circuit region 11.

It is noted that the bottom surface of the metal silicide 131 is lower than the top surface of the spacer 119a, i.e., the spacer 119a covers a portion of the sidewall of the metal silicide 131. On the other hand, in the array region 12, the top surface of the dielectric layer 119b in the second trench 117 is higher than the bottom surface of the metal silicide 131.

In some embodiments of the present disclosure, a wet etching process is performed to isotropically remove the oxide on the sidewalls of the first trench 115 and the second trench 117, so that the remaining spacers 119a, the dielectric layer 119b, and the oxide layer 111 have a flat top surface. Furthermore, the wet etching process can avoid the problem that the dry etching process is prone to plasma charging damage (plasma damage).

In addition, by performing the ion implantation process 130 before the wet etching process, the wet etching solution is prevented from etching down along the pores and holes in the oxide. As a result, the sidewall portions exposed by each control gate 109 have substantially the same height after the wet etch process. On the other hand, since the ion implantation process 130 uses the same conductivity type dopant (or the same dopant) as the control gate 109 and the floating gate 105, the electrical properties of the control gate 109 and the floating gate 105 are not affected by the ion implantation process 130.

Although the present invention has been described with reference to the above embodiments, it is not intended to limit the invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the claims.