阅读说明：本技术 集成电路及其形成方法 (Integrated circuit and forming method thereof ) 是由 姜慧如 林仲德 曹敏 兰迪·奥斯本 于 2018-10-23 设计创作，主要内容包括：在一些实施例中,本发明的实施例涉及集成电路及其形成方法。集成电路包括布置在衬底上方的第一存储器件和第二存储器件。第一存储器件连接至第一位线。第二存储器件连接至第二位线。共享控制元件布置在衬底内并且被配置为对第一存储器件提供访问并且单独地对第二存储器件提供访问。共享控制元件包括共享一个或多个组件的一个或多个控制器件。(In some embodiments, embodiments of the invention relate to integrated circuits and methods of forming the same. An integrated circuit includes a first memory device and a second memory device disposed over a substrate. The first memory device is connected to a first bit line. The second memory device is connected to the second bit line. The shared control element is disposed within the substrate and is configured to provide access to the first memory device and to provide access to the second memory device separately. A shared control element includes one or more control devices that share one or more components.)

1. An integrated circuit, comprising:

A first memory device disposed over the substrate and connected to a first bit line;

A second memory device disposed over the substrate and connected to a second bit line; and

A shared control element disposed within the substrate and configured to provide access to the first memory device and to provide access to the second memory device individually,

Wherein the shared control element comprises one or more control devices sharing one or more components.

2. The integrated circuit of claim 1, wherein the shared control element comprises a drive transistor having a source region connected to a source line, a drain region connected to the first and second memory devices, and a gate structure connected to first and second word lines.

3. The integrated circuit of claim 2, wherein the first and second transistors are connected in series,

Wherein the gate structure comprises a gate electrode separated from the substrate by a gate dielectric; and

Wherein the first word line is connected to the gate electrode through a first conductive contact provided on the gate electrode, and the second word line is connected to the gate electrode through a second conductive contact provided on the gate electrode.

4. the integrated circuit of claim 2, further comprising:

A third word line connected to the gate structure; and

A third memory device connected between the gate structure and a third bit line.

5. The integrated circuit of claim 1, wherein the first memory device comprises a first Magnetoresistive Random Access Memory (MRAM) device and the second memory device comprises a second magnetoresistive random access memory device.

6. the integrated circuit of claim 1, wherein the shared control element comprises:

a first drive transistor including a first gate structure connected to a first word line and disposed over the substrate between a first source region connected to a first source line and a drain region connected to the first and second memory devices; and

A second drive transistor including a second gate structure connected to a second word line and disposed over the substrate between a second source region connected to a second source line and the drain region.

7. An integrated circuit, comprising:

A memory array comprising a plurality of Magnetoresistive Random Access Memory (MRAM) devices arranged in rows and columns, wherein the plurality of magnetoresistive random access memory devices comprises:

A first magnetoresistive random access memory device connected to a first bit line, which in turn is connected to a first plurality of magnetoresistive random access memory devices within a row of the memory array;

A second magnetoresistive random access memory device connected to a second bit line, which in turn is connected to a second plurality of magnetoresistive random access memory devices within a column of the memory array; and

A drive transistor having a gate structure connected to a word line and disposed between a source region and a drain region connected to the first and second magnetoresistive random access memory devices.

8. The integrated circuit of claim 7, wherein the gate structure is further connected to a second word line.

9. A method of forming an integrated chip, comprising:

forming a shared control element comprising one or more gate structures disposed within a substrate between a drain region and one or more source regions;

Forming one or more interconnect layers within an interlayer dielectric (ILD) structure over the substrate, wherein the one or more interconnect layers define a first word line and a second word line connected to the one or more gate structures;

Forming a first memory device and a second memory device within the interlayer dielectric structure, wherein the first memory device and the second memory device are connected to the drain region; and

One or more additional interconnect layers are formed that define a first bit line connected to the first memory device and a second bit line connected to the second memory device.

10. The method of claim 9, wherein the first bit line is connected to a first plurality of memory devices within a column of a memory array and the second bit line is connected to a second plurality of memory devices within a row of the memory array.

Technical Field

embodiments of the invention relate generally to the field of semiconductors, and more particularly, to integrated circuits and methods of forming the same.

Background

Many modern electronic devices contain electronic memory configured to store data. The electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data when turned on, while non-volatile memory is capable of storing data when power is turned off. Magnetoresistive Random Access Memory (MRAM) is a promising candidate for next generation non-volatile memory technologies.

Disclosure of Invention

according to an aspect of the invention, there is provided an integrated circuit comprising: a first memory device disposed over the substrate and connected to a first bit line; a second memory device disposed over the substrate and connected to a second bit line; and a shared control element disposed within the substrate and configured to provide access to the first storage device and to provide access to the second storage device individually, wherein the shared control element comprises one or more control devices that share one or more components.

According to another aspect of the invention, there is provided an integrated circuit comprising: a memory array comprising a plurality of Magnetoresistive Random Access Memory (MRAM) devices arranged in rows and columns, wherein the plurality of magnetoresistive random access memory devices comprises: a first magnetoresistive random access memory device connected to a first bit line, which in turn is connected to a first plurality of magnetoresistive random access memory devices within a row of the memory array; a second magnetoresistive random access memory device connected to a second bit line, which in turn is connected to a second plurality of magnetoresistive random access memory devices within a column of the memory array; and a drive transistor having a gate structure connected to a word line and disposed between a source region and a drain region connected to the first and second magnetoresistive random access memory devices.

According to yet another aspect of the present invention, there is provided a method of forming an integrated chip, comprising: forming a shared control element comprising one or more gate structures disposed within a substrate between a drain region and one or more source regions; forming one or more interconnect layers within an interlayer dielectric (ILD) structure over the substrate, wherein the one or more interconnect layers define a first word line and a second word line connected to the one or more gate structures; forming a first memory device and a second memory device within the interlayer dielectric structure, wherein the first memory device and the second memory device are connected to the drain region; and forming one or more additional interconnect layers defining a first bit line connected to the first memory device and a second bit line connected to the second memory device.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 illustrates a schematic diagram of some embodiments of a memory circuit having a shared control element configured to provide access to a plurality of memory devices, respectively.

Fig. 2 illustrates a schematic diagram of some additional embodiments of a memory circuit having a shared control element including drive transistors configured to respectively provide access to a plurality of Magnetoresistive Random Access Memory (MRAM) devices.

fig. 3A-3C illustrate some embodiments of an integrated chip having a shared control element configured to provide access to multiple MRAM devices, respectively.

Fig. 4-5 illustrate cross-sectional views of some alternative embodiments of an integrated chip having a shared control element configured to provide access to multiple MRAM devices, respectively.

Fig. 6 shows a schematic diagram of some additional embodiments of a memory circuit having a shared control element configured to provide access to three MRAM devices, respectively.

Fig. 7-8 show schematic diagrams illustrating some embodiments of the operation of a memory circuit having a shared control element configured to provide access to multiple MRAM devices, respectively.

Fig. 9A-9B illustrate some alternative embodiments of an integrated chip having a shared control element configured to provide access to multiple MRAM devices, respectively.

Fig. 10 shows a schematic diagram of some additional embodiments of a memory circuit having a shared control element configured to provide access to three MRAM devices, respectively.

Fig. 11A-11C illustrate some alternative embodiments of an integrated chip having a shared control element configured to provide access to multiple MRAM devices, respectively.

Fig. 12 shows a schematic diagram of some additional embodiments of a memory circuit having a shared control element configured to provide access to three MRAM devices, respectively.

Fig. 13-17 illustrate cross-sectional views of some embodiments of methods of forming an integrated chip having a memory circuit that includes a shared control element configured to provide access to a plurality of MRAM devices, respectively.

FIG. 18 illustrates a flow diagram of some embodiments of a method of forming an integrated chip having memory circuitry including a shared control element configured to provide access to a plurality of memory devices, respectively.

Detailed Description

the following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A Magnetoresistive Random Access Memory (MRAM) device includes a Magnetic Tunnel Junction (MTJ) within a back end of the line (BEOL) of an integrated chip vertically disposed between conductive electrodes. The MTJ includes a fixed layer separated from a free layer by a tunnel barrier layer. The magnetic orientation of the fixed layer is static (i.e., fixed), while the magnetic orientation of the free layer can be switched between a parallel configuration and an anti-parallel configuration relative to the magnetic orientation of the fixed magnetic layer. The parallel configuration provides a low resistance state that is digitally stored as data (e.g., a logic "0") of a first bit value. The anti-parallel configuration provides a high resistance state that is digitally stored as data of a second bit value (e.g., a logic "1").

As the functionality of integrated chips increases, the demand for more memory also increases, thereby necessitating integrated chip designers and manufacturers to increase the amount of memory available while reducing the size and power consumption of the integrated chips. To achieve this goal, the size of memory cell assemblies has been continually shrinking over the past several decades. One advantage of MRAM devices over other memory types is that the MTJ of MRAM devices can be made very small in size. However, in an MRAM cell, a drive transistor (i.e., an access transistor) is used to provide a voltage to the associated MRAM device during a write operation. Because MRAM cells typically use relatively high voltages and/or currents for write operations, the size of the drive transistor may be relatively large. While the MTJs of MRAM can be made with small dimensions, the relatively large size of the drive transistor limits the density of MRAM devices within the memory array.

In some embodiments, the present invention relates to an integrated chip comprising a memory array having a shared control element configured to provide access to a plurality of different MRAM devices, respectively. The shared control element includes one or more control devices (e.g., drive transistors) that share one or more components (e.g., sources, drains, etc.). By using a shared control element to provide access to multiple MRAM devices, the size of the MRAM cells can be reduced because the cells are not limited by the size of the control device (e.g., the drive transistor).

FIG. 1 illustrates a schematic diagram of some embodiments of a memory circuit 100 having a shared control element configured to provide access to a plurality of memory devices, respectively.

The memory circuit 100 includes a memory array 102 having a plurality of memory devices 104 _a,1 through 104 _f,3 (e.g., MRAM devices). The plurality of memory devices 104 _a,1 through 104 _f,3 are arranged within the memory array 102 in rows and columns.A first row of memory devices includes the memory devices 104 _a,1 through 104 _a,3, and a first column of memory devices includes the memory devices 104 _a,1, 104 _c,1, and 104 _e,1, for example.

The memory array 102 also includes a plurality of shared control elements 106 a-106 i configured to provide access to the plurality of memory devices 104 _a,1 -104 _f,3 (e.g., to enable data to be written to a selected one of the plurality of memory devices 104 _a,1 -104 _f,3 and/or read from a selected one of the plurality of memory devices 104 _a,1 -104 _f,3). The respective plurality of shared control elements 106 a-106 i are configured to provide access to two or more of the plurality of memory devices 104 _a,1 -104 _f,3 within the corresponding memory regions 108 a-108 b, respectively.The first shared control element 106a is configured to provide access to a first memory device 104 _a,1 and a second memory device 104 _b,1 within the first memory region 108a, respectively, and the second shared control element 106b is configured to provide access to a third memory device 104 _a,2 and a fourth memory device 104 _b,2, respectively, etc., within the second memory region 108 b.

The plurality of shared control elements 106a to 106i each include one or more individual control devices that share one or more components. In various embodiments, the plurality of shared control elements 106 a-106 i may include one or more transistors sharing source regions, drain regions, and/or gate structures. For example, in some embodiments, the plurality of shared control elements 106a to 106i may each include a single transistor having a drain region connected to the first memory device and the second memory device. In other embodiments, the plurality of shared control elements 106a to 106i may include a first transistor and a second transistor sharing a drain region connected to the first memory device and the second memory device.

the memory array 102 is connected to the control circuit 109 by a plurality of bit lines BL _0x -BL _2x and BL _0y -BL _2y and a plurality of word lines WL _0x -WL _2x and WL _0y -WL _2y in some embodiments, the control circuit 109 includes a bit line decoder 110 and a word line decoder 112 connected to the control unit 114, a plurality of bit lines BL _0x -BL _2x and BL _0y -BL _2y connect the respective plurality of memory devices 104 _a,1 -104 _f,3 to the bit line decoder 110, and a plurality of shared control elements 106 a-106 i are connected to the word line decoder 112 by two or more of the plurality of word lines WL _0x -WL _2x and WL _0y -WL _2y.

In some embodiments, the plurality of shared control elements 106 a-106 i are connected to two or more of a plurality of word lines WL _0x -WL _2x and WL _0y -WL _2y, respectively, extending in different directions, while the memory devices within the respective plurality of memory regions 108 a-108 b are connected to bit lines extending in different directions, for example, a shared control element 106a within a first memory region 108a is connected with a first word line WL _0y extending along a row of shared control elements 106 a-106 c and a second word line WL _0x extending along a column of shared control elements 106a, 106d, and 106 g.

For accessing a memory device (e.g., reading data from or writing data to the memory device), the bit line decoder 110 is configured to selectively provide signals to one or more of the plurality of bit lines BL _0x to BL _2x and BL _0y to BL _2y based on an address S _ADDR1 received from the control unit 114, while the word line decoder 112 is configured to selectively provide signals to one or more of the plurality of word lines WL _0x to WL _2x and WL _0y to WL _2y based on an address S _ADDR2 received from the control unit 114.

the use of shared control elements 106 a-106 i to provide access to more than one of the plurality of memory devices 104 _a,1 -104 _f,3, respectively, allows for a reduction in the size occupied by the control device within the memory array 102. in addition, the size of the memory array 102 may be reduced by reducing the size occupied by the control device within the memory array 102. in some embodiments, the size of the control device may be increased without increasing the size of the memory array 102. by increasing the size of the control device, the current delivered by the control device may be increased and the performance of the memory array 102 may be improved (e.g., increasing the 'read window' (difference between signals "1" and "0" read from the memory devices) of the plurality of memory devices 104 _a,1 -104 _f,3) without increasing the size of the memory array 102.

Fig. 2 illustrates some additional embodiments of a memory array 200 having a shared control element including a shared drive transistor configured to provide access to a plurality of MRAM devices, respectively.

The memory array 200 includes a plurality of MRAM devices 202 arranged in rows and columns. The plurality of MRAM devices 202 each include a Magnetic Tunnel Junction (MTJ) having a fixed (pinned) layer 204 and a free layer 208 separated by a tunnel dielectric layer 206. The magnetic orientation of the fixed layer 204 is static (i.e., fixed), while the magnetic orientation of the free layer 208 can be switched between a parallel configuration and an anti-parallel configuration relative to the magnetic orientation of the fixed layer 204. The parallel configuration provides a low resistance state that is digitally stored as data (e.g., a logic "0") of a first bit value. The anti-parallel configuration provides a high resistance state that is digitally stored as data of a second bit value (e.g., a logic "1"). During operation, the MTJ may change between a low resistance state and a high resistance state through a Tunnel Magnetoresistance (TMR) effect.

for example, within the memory region 108a, a first MRAM device 202a is connected between the shared drive transistor 210a and a first bit line BL _0x extending along a row of the plurality of MRAM devices 202, while a second MRAM device 202b is connected between the shared drive transistor 210a and a second bit line BL _0y extending along a column of the plurality of MRAM devices 202.

The shared drive transistor 210 includes a source terminal (S) connected to a source line SL ₁ or SL ₂, a drain terminal (D) connected to two or more of the plurality of MRAM devices 202, and a gate terminal (G) connected to two or more word lines WL _my and WL _nx (m, n is 0 or 1) extending in different directions-for example, a first drive transistor 210a has a source terminal connected to a first source line SL ₁, drain terminals connected to the first MRAM device 202a and the second MRAM device 202b, and gate terminals connected to a first word line WL _0x extending along rows of the shared drive transistor and a second word line WL _0y extending along columns of the shared drive transistor.

Because the shared drive transistor 210 is shared among multiple MRAM devices 202, the size of the memory array 200 may be reduced. In addition, the size (e.g., gate width) of the shared drive transistor 210 may be increased, thereby increasing the current capability of the shared drive transistor 210. The larger current capacity of the shared drive transistor 210 allows for a higher Tunneling Magnetoresistance (TMR), resulting in a larger read margin and faster read operation.

FIG. 3A illustrates a cross-sectional view of some embodiments of an integrated chip 300 having a plurality of memory devices connected to a shared control element.

integrated chip 300 includes shared control element 212 disposed within substrate 302. In some embodiments, the shared control element 212 may include a single control device including a MOSFET having a gate structure 304g disposed over the substrate 302 and between the source region 304s and the drain region 304 d. Gate structure 304g includes a gate electrode 308 separated from substrate 302 by a gate dielectric 306. In some embodiments, sidewall spacers (not shown) comprising dielectric materials (e.g., oxides, nitrides, carbides, etc.) may be disposed on opposite sides of the gate structure 304 g. In other embodiments, the shared control element 212 may include a Bipolar Junction Transistor (BJT), a High Electron Mobility Transistor (HEMT), or the like. In some embodiments, the shared control element 212 may include a FinFET device having a gate structure 304g extending over a plurality of semiconductor fins extending between source and drain regions. By extending the gate structure 304g over multiple semiconductor fins, the drive current of the FinFET device may be increased over a FinFET device with a single fin.

In some embodiments, gate electrode 308 may comprise polysilicon. In such embodiments, the gate dielectric 306 may comprise a dielectric material such as an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), and the like. In other embodiments, the gate electrode 308 may comprise a metal such as aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, and the like. In such embodiments, the gate dielectric 306 may comprise a high-k dielectric material, such as hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, aluminum oxide, zirconium oxide, and the like.

dielectric structure 312 is disposed over substrate 302 in some embodiments, dielectric structure 312 may include a pre-metal dielectric layer 314 surrounding mid-line-of-line (MEOL) structures 310 a-310 b disposed on source region 304s and drain region 304d, and further surrounding conductive contacts 318 disposed on MEOL structures 310 a-310 b and gate electrodes 308 dielectric structure 312 also includes a plurality of stacked ILD layers 316 disposed over pre-metal dielectric layer 314. the plurality of stacked ILD layers 316 surround a plurality of interconnect layers 321 including alternating layers of interconnect lines 320 and vias 322. the plurality of interconnect layers 321 connect source region 304s to source line SL, gate structure 304g to two or more word lines WL _0x and WL _0y, and drain region 304d to first and second MRAM devices 202a and 202b within dielectric structure 312. in some embodiments, 324 extends continuously from directly under first MRAM device 202a to directly under second MRAM device 202 b. in some embodiments, first and second MRAM devices 202a and 202b may share a plurality of interconnect lines 202, and MRAM devices 202b, and the like, thereby providing a control of the MRAM devices 202a, 202a plurality of MRAM devices 202a, and a plurality of MRAM devices 202 b.

The first MRAM device 202a includes a first Magnetic Tunnel Junction (MTJ) disposed vertically between a bottom electrode via 326 and a top electrode via 328. the first MTJ includes a first fixed layer 204a separated vertically from a first free layer 208a by a first dielectric tunnel barrier 206 a. the first fixed layer 204a has a fixed magnetization, while the first free layer 208a has a magnetization that can be changed to be parallel (i.e., a "P" state) or anti-parallel (i.e., an "AP" state) relative to the magnetization of the first fixed layer 204 a. in some embodiments, the first MRAM device 202a may include an additional layer (e.g., an anti-ferromagnetic layer between the bottom electrode via 326 and the first fixed layer 204 a.) the first fixed layer 204a is connected to the shared control element 212 by a first conductive path that includes a plurality of interconnect layers 321, while the first free layer 208a is connected to a first bit line BL _0x by one or more additional interconnect layers 330 located above the first MRAM device 202 a. in some embodiments, the first fixed layer 204a and the first free layer 208a may be located between the first fixed layer 204a and the first fixed layer 326 a.

The second MRAM device 202b includes a second Magnetic Tunnel Junction (MTJ) disposed vertically between a bottom electrode via 326 and a top electrode via 328 the second MTJ includes a second fixed layer 204b vertically separated from a second free layer 208b by a second dielectric tunnel barrier 206b the second fixed layer 204b is connected to the shared control element 212 by a second conductive path that includes a plurality of interconnect layers 321, and the second free layer 208b is connected to a second bit line BL _0y by one or more additional interconnect layers 330 located above the second MRAM device 202b in some embodiments the positions of the second fixed layer 204b and the second free layer 208b may be reversed.

In some embodiments, the bottom electrode via 326 and the top electrode via 328 may comprise a metal such as titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), tantalum (Ta), etc. in some embodiments, the first fixed layer 204a and the second fixed layer 204B may comprise cobalt (Co), iron (Fe), boron (B), ruthenium (Ru), etc. in some embodiments, the first dielectric tunnel barrier 206a and the second dielectric tunnel barrier 206B may comprise magnesium oxide (MgO), aluminum oxide (Al ₂ O ₃), etc. in some embodiments, the first free layer 208a and the second free layer 208B may comprise cobalt (Co), iron (Fe), boron (B), etc.

Fig. 3B illustrates a cross-sectional view 332 of some embodiments of the integrated chip 300 of fig. 3A.

As shown in cross-sectional view 332, the first word line WL _0x is connected to the gate electrode 308 through a first conductive contact 318a disposed on an upper surface of the gate electrode 308, and the second word line WL _0y is connected to the gate electrode 308 through a second conductive contact 318b disposed on an upper surface of the gate electrode 308. the first conductive contact 318a and the second conductive contact 318b are separated from each other by the pre-metal dielectric layer 314.

Fig. 3C illustrates a top view 336 of some embodiments of the integrated chip 300 of fig. 3A. The cross-sectional view of FIG. 3A is shown along line A-A 'as shown in the top view 336, and the cross-sectional view of FIG. 3B is shown along line B-B' as shown in the top view 336.

In some embodiments, the first word line WL _0x includes a plurality of discrete interconnect lines 342 that extend over the gate structures 304g along the second direction 340 and are separated by a non-zero distance along the first direction 338, respectively, the plurality of discrete interconnect lines 342 are connected together by interconnect lines 320 over the discrete interconnect lines 342 such that the first word line WL _0x is connected to the drive transistors 210a and 210b disposed in the first direction (e.g., along a row of the memory array). the second word line WL _0y includes a complete interconnect line 344 that extends continuously over the plurality of gate structures 304g along the second direction such that the second word line WL _0y is connected to the drive transistors 210a and 210c disposed in the second direction (e.g., along a column of the memory array).

fig. 4 illustrates a cross-sectional view of some alternative embodiments of an integrated chip 400 having multiple MRAM devices connected to a shared control element.

The integrated chip 400 includes a shared control element 212, the shared control element 212 including a mosfet disposed within the substrate 302 and having a source region 304s, a gate structure 304g, and a drain region 304d a dielectric structure 312 located over the substrate 302 surrounds a plurality of interconnect layers 321 including interconnect lines 320 and vias 322 the plurality of interconnect layers 321 connect the source region 304s to a source line SL, the gate structure 304g to two or more word lines WL _0x and WL _0y, and the drain region 304d to the first MRAM device 202a and the second MRAM device 202 b.

The first MRAM device 202a and the second MRAM device 202b are arranged at different heights relative to the substrate 302. For example, the bottom-most surface of the first MRAM device 202a is closer to the substrate 302 than the bottom-most surface of the second MRAM device 202 b. In some embodiments, the first MRAM device 202a and the second MRAM device 202b may be disposed directly above the shared control element 212. In some embodiments, the second MRAM device 202b may be disposed directly above the first MRAM device 202 a. In other embodiments, the second MRAM device 202b and the first MRAM device 202a may be laterally offset from each other. Having the first MRAM device 202a and the second MRAM device 202b in different vertical positions allows the memory array to achieve a smaller footprint.

In some embodiments, the plurality of interconnect layers 321 includes an interconnect line 324 disposed vertically between the first MRAM device 202a and the second MRAM device 202 b. in some such embodiments, the first MRAM device 202a includes a first pinned layer 204a disposed along a lower surface of the interconnect line 324. the first dielectric tunnel barrier 206a separates the first pinned layer 204a from a first free layer 208a connected to a first bit line BL _0x. the second MRAM device 202b includes a second pinned layer 204b disposed along an upper surface of the interconnect line 324. the second dielectric tunnel barrier 206b separates the second pinned layer 204b from a second free layer 208b connected to a second bit line BL _0y.

Fig. 5 shows a cross-sectional view of some additional alternative embodiments of an integrated chip 500 having multiple MRAM devices connected to a shared control element.

The integrated chip 500 includes a shared control element 212, the shared control element 212 including a mosfet disposed within the substrate 302 and having a source region 304s, a gate structure 304g, and a drain region 304d a dielectric structure 312 located over the substrate 302 surrounds a plurality of interconnect layers 321 including interconnect lines 320 and vias 322 the plurality of interconnect layers 321 connect the source region 304s to a source line SL, the gate structure 304g to two or more word lines WL _0x and WL _0y, and the drain region 304d to the first MRAM device 202a and the second MRAM device 202 b.

The plurality of interconnect layers 321 includes interconnect lines 324 that are vertically separated from the first MRAM device 202a and the second MRAM device 202b by at least one interconnect line. For example, the integrated chip 500 includes a first conductive path having one or more interconnect lines and vias extending from the interconnect line 324 to the first MRAM device 202 a. A second conductive path, including one or more interconnect lines and vias, also extends from the interconnect line 324 to the second MRAM device 202 b.

Although fig. 1-5 depict a memory array including a shared control element connected to two memory devices, it should be understood that the disclosed memory circuit is not limited to such an embodiment. Also, in some additional embodiments, the disclosed memory circuit may have a shared control element connected to a greater number of memory devices. For example, in various embodiments, the memory array may include three, four, or more memory devices connected to a shared control element. In some embodiments, the size of the memory array may be optimized by selecting the number of memory devices connected to the shared control element based on the MTJ pitch, fin pitch, and/or metal gate pitch.

Fig. 6 illustrates some additional embodiments of a memory array 600 having shared control elements each configured to provide access to three MRAM devices, respectively.

The memory array 600 includes a plurality of MRAM devices 202 arranged in rows and columns, three of the plurality of MRAM devices 202 are connected to a shared control element 212, the shared control element 212 includes a shared drive transistor 210 configured to provide access to the MRAM devices 202, the shared drive transistor 210 has a source terminal connected to a source line, a gate terminal connected to three word lines, and a drain terminal connected to three MRAM devices (each connected to a separate bit line). for example, the first memory region 108a includes a first drive transistor 210a, the first drive transistor 210a having a source terminal connected to a first source line SL ₁, a gate terminal connected to a first word line WL _0x, a second word line WL _0y, and a third word line WL _0z, and a drain terminal connected to the first MRAM device 202a, the second MRAM device 202b, and the third MRAM device 202 c.

For example, MRAM devices may be accessed by activating bit line BL _nx (n 1,2, 3.) and word line WL _my (m 1,2, 3.), bit line BL _ny (n 1,2, 3), and word line WL _mx (m 1,2, 3.), bit line BL _nz (n 1,2, 3), and word line WL _mz (m 1,2, 3).

Fig. 7 illustrates a schematic diagram 700 showing some embodiments of a write operation to write a data state to an MRAM device. It should be understood that the write operation shown in diagram 700 is one non-limiting example of a method of performing a write operation, and that other methods of performing a write operation may alternatively be used.

As illustrated in the diagram 700, a write operation is performed to the second MRAM device 202 b. In order to write data to an MRAM device, the current provided through the MRAM device must be greater than the switching current (i.e., the critical switching current). A current no greater than the switching current will not produce switching between states and therefore will not write data to the MRAM device.

A write operation is performed by applying a first non-zero bias voltage V ₁ to the word line WL _0x, a second non-zero bias voltage V ₂ to the bit line BL _0y, and a third non-zero bias voltage V ₃ to the source line SL ₁ the first non-zero bias voltage V ₁ turns on the shared drive transistor 210a to form a conductive path between the source line SL ₁ and the second MRAM device 202b the second non-zero voltage V ₂ and the third non-zero voltage V ₃ form a first potential difference that causes a current greater than the switching current to flow through the second MRAM device 202 b.

If the second non-zero bias voltage V ₂ is lower than the third non-zero bias voltage V ₃, then current will travel from the source line SL ₁ to the bit line BL _0y. the current will be polarized by the fixed layer of the second MRAM device 202b, and will cause the free layer of the second MRAM device 202b to have a parallel magnetization that causes the second MRAM device 202b to have a low resistance state that digitally stores data as a first bit value (e.g., a logic "0"). alternatively, if the second non-zero bias voltage V ₂ is higher than the third non-zero bias voltage V ₃, current will travel from the bit line BL _0y to the source line SL ₁.

To prevent undesired leakage current from flowing through the first MRAM device 202a, bit line BL _0x is set to a fourth non-zero bias voltage V ₄, fourth non-zero bias voltage V ₄ is between the second non-zero bias voltage V ₂ and the third non-zero bias voltage V ₃ (i.e., V ₂ < V ₄ < V ₃), by selecting the difference between the fourth non-zero bias voltage V ₄ and the third non-zero bias voltage V ₃ to be sufficiently small, the current provided to the first MRAM device 202a will be less than the switching current, and the data will not be written to the first MRAM device 202 a. similarly, other select lines and bit lines may be biased as shown in fig. 7 to avoid writing undesired data to the unaccessed MRAM device (e.g., the second non-zero bias voltage V ₄ may be less than the second non-zero bias voltage V ₂).

Fig. 8 illustrates a schematic diagram 800 illustrating some embodiments of a read operation to read a data state from an MRAM device.

As illustrated in the diagram 800, a read operation is performed on the second MRAM device 202b by applying a first non-zero bias voltage V ₁ to the word line WL _0x and a second non-zero bias voltage V ₂ to the bit line BL _0y. the first non-zero bias voltage V ₁ turns on the drive transistor 210a, and the second non-zero bias voltage V ₂ will pass a current I _R through the second MRAM device 202 b. the current I _R through the second MRAM device 202b has a value that depends on the resistance state of the second MRAM device 202 b. for example, if the second MRAM device 202b is in a low resistance state (e.g., storing a logic '0'), the current I _R will be greater than if the second MRAM device 202b is in a high resistance state (e.g., storing a logic '1').

The multiplexer 802 is configured to selectively provide a current I _R from the second MRAM device 202b to the sense amplifier 804, the sense amplifier 804 configured to compare the current I _R to a reference current I _REF to determine a data state stored in the second MRAM device 202 b.

Fig. 9A-9B illustrate some alternative embodiments of an integrated chip having a shared control element configured to provide access to multiple MRAM devices, respectively.

As shown in the schematic diagram 900 of fig. 9A, the integrated chip includes a plurality of shared control elements 902 configured to provide access to the first MRAM device 202a and the second MRAM device 202b, respectively. Shared control element 902 includes two separate control devices that share one or more components. For example, the shared control elements 902 each include an individual control device including a first drive transistor 904a and a second drive transistor 904b having a shared drain region.

In some embodiments, as shown in the cross-sectional view 906 of FIG. 9B, the first drive transistor 904a includes a first gate structure 304 _g,1 disposed above the substrate 302 and between the first source region 304 _s,1 and the drain region 304d, the first gate structure 304 _g,1 is connected to a first word line WL _0x, and the first source region 304 _s,1 is connected to a first source line SL _0x, the second drive transistor 904B includes a second gate structure 304 _g,2 disposed above the substrate 302 and between the second source region 304 _s,2 and the drain region 304d, the second gate structure 304 _g,2 is connected to a second word line WL _0y, and the second source region 304 _s,2 is connected to a second source line SL 367, the drain region 304d is connected to the first MRAM device 202a and the second MRAM device 202B through a plurality of interconnect layers 321 including an interconnect line 320 surrounded by a dielectric structure 312 and a via 322, the first MRAM device 202a is further connected to the first MRAM device 202a and the second MRAM device 202B through one or more additional interconnect layers 330 disposed above the first MRAM device 202a, the second MRAM device 202B is further connected to the second MRAM device 202B through one or more additional bit line 632 interconnect layers _0y.

During operation, the first MRAM device 202a may be accessed by activating the first word line WL _0x and biasing the first bit line BL _0x and/or the first source line SL _0x the second MRAM device 202b may be accessed by activating the second word line WL _0y and biasing the second bit line BL _0y and/or the second source line SL _0y in some embodiments, the first source line SL _0x and the second source line SL _0y may include a common source line (i.e., electrically connected together). by sharing the drain region 304d between the first drive transistor 904a and the second drive transistor 904b, the area of the substrate 302 consumed by both the first drive transistor 904a and the second drive transistor 904b is reduced relative to the area of the drive transistors having separate components, allowing for a reduction in the size of the memory array.

It should be understood that in some embodiments, a shared control element including a shared control transistor sharing a drain region (e.g., as shown in fig. 9A-9B) may be connected to a greater number of memory devices (e.g., three, four, or more memory devices may be connected to the shared control element). For example, fig. 10 shows a schematic diagram of some embodiments of a memory array 100 having three memory devices connected to a shared control element 212 including shared drive transistors 210 a-210 c sharing a drain region.

The memory array 1000 includes a plurality of MRAM devices 202 arranged in rows and columns. Within the first memory region 108a, three MRAM devices 202a to 202c of the plurality of MRAM devices 202 are connected to a shared control element 212 that includes three shared drive transistors 210a to 210 c. The three shared drive transistors 210 a-210 c are configured to selectively provide access to the three MRAM devices 202 a-202 c, respectively. For example, the first shared drive transistor 210a is configured to selectively provide access to the first MRAM device 202a, the second shared drive transistor 210b is configured to selectively provide access to the second MRAM device 202b, and the third shared drive transistor 210c is configured to selectively provide access to the third MRAM device 202 c.

The three shared drive transistors 210 a-210 c have source terminals connected to different source lines SL _0x -SL _0z, gate terminals connected to different word lines WL _0x -WL _0z, and shared drain terminals connected to the three MRAM devices 202 a-202 c, the three MRAM devices 202 a-202 c being connected to separate bit lines BL _0x, BL _0z, and BL _0y, respectively, for example, the three shared drive transistors 210 a-210 c may include a first drive transistor 210a, a second drive transistor 210b, and a third drive transistor 210c, the first drive transistor 210a having a first source terminal connected to a first source line SL _0x, a first gate terminal connected to a first word line WL _0x, and a first drain terminal connected to a first bit line BL _0x, the second drive transistor 210b having a second source terminal connected to a second source line SL _0y, a second gate terminal connected to a second word line WL _0y, and a second gate terminal connected to a first source line SL _0y, and a third drain terminal connected to a first source line SL 966 a, the third drive transistor 202b connected to a third source terminal (drain terminal), the third drain terminal) connected to the third drain terminal, the third drain terminal connected to the third drain transistor 202a, the third drain terminal connected to the third drain terminal, the drain terminal connected to the third drain terminal connected to the third drain terminal of the third drain transistor 202b, the third drain transistor 202b 2, the third drain terminal connected to the third drain terminal connected.

Fig. 11A-11C illustrate some alternative embodiments of an integrated chip having a shared control element configured to provide access to multiple MRAM devices, respectively.

As shown in the schematic diagram 1100 of fig. 11A, the integrated chip includes a plurality of shared control elements 1102 configured to provide access to the first MRAM device 202a and the second MRAM device 202b, respectively. Shared control element 1102 includes two separate control devices that share one or more components. For example, the shared control elements 1102 respectively include individual control devices including a first drive transistor 1104a and a second drive transistor 1104b that share source and drain regions.

In some embodiments, as shown in the top view 1106 of FIG. 11B, the first drive transistor 1104a includes a first gate structure 304 _g,1 disposed between the source region 304s and the drain region 304d, the first gate structure 304 _g,1 is connected to a first word line WL _0x, the second drive transistor 1104B includes a second gate structure 304 _g,2 disposed between the source region 304s and the drain region 304d, the second gate structure 304 _g,2 is connected to a second word line WL _0y, the source region 304s is connected to a source line SL ₀, and the drain region 340d is connected to a first MRAM device and a second MRAM device (not shown), FIG. 11C shows a cross-sectional view 1108, the cross-sectional view 1108 showing the first gate structure 304 _g,1 connected to the first word line WL _0x and the second gate structure 304 _g,2 connected to the second word line _0y along the cross-sectional view B-B' of FIG. 11B.

During operation, the first MRAM device 202a may be accessed by activating the first word line WL _0x and biasing the first bit line BL _0x and/or source line SL ₀ the second MRAM device 202b may also be accessed by activating the second word line WL _0y and biasing the second bit line BL _0y and/or source line SL ₀ in some embodiments, the source line SL ₀ may include a common source line (i.e., electrically connected to the source line SL ₁.) by sharing the source region 304s and drain region 304d between the first drive transistor 1104a and the second drive transistor 1104b, the area of the substrate 302 consumed by both the first drive transistor 1104a and the second drive transistor 1104b is reduced relative to drive transistors having separate components, allowing for a reduction in the size of the memory array.

It should be understood that in some embodiments, a shared control element (e.g., as shown in fig. 11A-11C) including a shared control transistor that shares a source region and a drain region may be connected to a greater number of memory devices (e.g., three, four, or more memory devices may be connected to the shared control element). For example, in some embodiments shown in fig. 12, the memory array 1200 may include three memory devices connected to the shared control element 212 including the shared drive transistors 210 a-210 c sharing the source and drain regions.

The memory array 1200 includes a plurality of MRAM devices 202 arranged in rows and columns. Within the first memory region 108a, three MRAM devices 202a to 202c of the plurality of MRAM devices 202 are connected to a shared control element 212 that includes three shared drive transistors 210a to 210 c. The three shared drive transistors 210 a-210 c are configured to selectively provide access to the three MRAM devices 202 a-202 c, respectively. For example, the first shared drive transistor 210a is configured to selectively provide access to the first MRAM device 202a, the second shared drive transistor 210b is configured to selectively provide access to the second MRAM device 202b, and the third shared drive transistor 210c is configured to selectively provide access to the third MRAM device 202 c.

The three shared drive transistors 210 a-210 c each have a source terminal connected to a source line SL ₁, a gate terminal connected to a different word line WL _0x -WL _0z, and a shared drain terminal connected to the three MRAM devices 202 a-202 c, the three MRAM devices 202 a-202 c each being connected to a separate bit line BL _0x, BL _0z, and BL _0y. for example, the three shared drive transistors 210 a-210 c may include a first drive transistor 210a, a second drive transistor 210b, and a third drive transistor 210 c. the first drive transistor 210a has a first source terminal connected to a first source line SL ₁, a first gate terminal connected to a first word line WL _0x, and a first drain terminal connected to a first MRAM device 202a (connected to a first bit line BL _0x). the second drive transistor 210b has a second source terminal connected to the first source terminal (e.g., shared with the source terminal), a second gate terminal connected to the second source line WL ₁, and a second source terminal connected to the first source terminal WL ₁ (e.g., shared source terminal with the first source terminal), and the drain terminal of the first drive transistor 202c, and the third drain terminal connected to the third drive transistor 202 c.

Fig. 13-17 illustrate cross-sectional views 1300-1700 of some embodiments of methods of forming an integrated chip including a memory circuit having a shared control element configured to provide access to a plurality of MRAM devices, respectively. While fig. 13-17 are described in relation to a method, it should be understood that the structure disclosed in fig. 13-17 is not limited to such a method, but may be independent of the method as a separate structure.

As shown in cross-sectional view 1300 of fig. 13, the shared control element 212 is formed within the substrate 302. In various embodiments, the substrate 302 may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), as well as any other type of semiconductor and/or epitaxial layer associated therewith, such as a semiconductor wafer and/or one or more dies located on the wafer. In some embodiments, the shared control element 212 may comprise a MOSFET. In such embodiments, the shared control element 212 may be formed by depositing a gate dielectric film and a gate electrode film over the substrate 302. The gate dielectric film and gate electrode film are then patterned to form a gate structure 304g having a gate dielectric 306 and a gate electrode 308. The substrate 302 may then be implanted to form a source region 304s and a drain region 304d within the substrate 302 and on opposite sides of the gate structure 304 g. In alternative embodiments, the shared control element 212 may include a Bipolar Junction Transistor (BJT), a High Electron Mobility Transistor (HEMT), or the like.

As shown in cross-sectional view 1400 of fig. 14, mid-line-of-line (MEOL) structures 310 a-310 b are formed over source region 304s and drain region 304d, respectively. MEOL structures 310 a-310 b are vertically disposed between substrate 302 and a horizontal plane extending along the top of gate structure 304 g. In some embodiments, MEOL structures 310 a-310 b may directly contact source region 304s and drain region 304 d. In some embodiments, MEOL structures 310 a-310 b may be formed by depositing a conductive material over substrate 302 and then patterning the conductive material to define MEOL structures 310 a-310 b. In other embodiments (not shown), the MEOL structures 310 a-310 b may be formed by a damascene process (e.g., by selectively etching the pre-metal dielectric layer 314 to form openings, depositing conductive material within the openings, and performing a CMP process to define the MEOL structures 310 a-310 b to form the MEOL structures 310 a-310 b).

A pre-metal dielectric layer 314 is formed over the substrate 302 surrounding the MEOL structures 310 a-310 b. In some embodiments, the pre-metal dielectric layer 314 may be formed by a deposition technique. In various embodiments, the pre-metal dielectric layer 314 may include silicon oxynitride, silicon oxide, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), low-k materials, porous dielectric materials, and the like.

After forming pre-metal dielectric layer 314 over substrate 302, pre-metal dielectric layer 314 is patterned to define contact openings 1402 over MEOL structures 310 a-310 b and gate structure 304 g. In some embodiments, the pre-metal dielectric layer 314 may be patterned by forming a patterned masking layer (e.g., a photoresist layer) over the pre-metal dielectric layer 314 and performing an etching process to remove portions of the pre-metal dielectric layer 314 not covered by the patterned masking layer. The contact openings 1402 are filled with a conductive material to form conductive contacts 318 extending from the MEOL structures 310 a-310 b and the gate structure 304g to the upper surface of the pre-metal dielectric layer 314. In some embodiments, the conductive material may include a metal (e.g., tungsten, aluminum, etc.) formed by a deposition process (e.g., CVD, PVD, PE-CVD, ALD, etc.) and/or a plating process (e.g., an electroplating process, an electroless plating process, etc.).

as shown in cross-sectional view 1500 of fig. 15A, a plurality of interconnect layers 321 are formed within a first ILD structure 1502 above the pre-metal dielectric layer 314. In some embodiments, the first ILD structure 1502 includes a plurality of stacked inter-layer dielectric (ILD) layers 1502a through 1502e and a plurality of interconnect layers 321 including alternating layers of interconnect lines 320 and vias 322. In some embodiments, the plurality of stacked ILD layers 1502 a-1502 e may each comprise a dielectric (e.g., oxide, low-k dielectric, ultra-low-k dielectric, etc.). In some embodiments, the interconnect lines 320 and vias 322 may comprise a metal (e.g., copper, aluminum, etc.).

the plurality of interconnect layers 321 connect the source regions 304s to the source lines SL and the gate structures 304g to the first word line WL _nx (n 1,2, 3..) and the second word line WL _my (m 1,2, 3.). the plurality of interconnect layers 321 may be formed by depositing a plurality of stacked ILD layers 1502 a-1502 e over the pre-metal dielectric layer 314, respectively, selectively etching the plurality of stacked ILD layers 1502 a-1502 e to define vias and/or trenches within the ILD layers, forming conductive material within the vias and/or trenches to fill the openings, and performing a planarization process (e.g., a chemical mechanical planarization process).

As shown in the cross-sectional view 1504 of fig. 15B (shown along a section into the page of fig. 15A), the interconnect line 320 is connected to the gate electrode 308 through a first conductive contact 318a and a second conductive contact 318B, the first conductive contact 318a and the second conductive contact 318B being laterally separated by the pre-metal dielectric layer 314 the first conductive contact 318a connects the gate electrode 308 to a first word line WL _nx, and the second conductive contact 318B connects the gate electrode 308 to a second word line WL _my although the first word line WL _nx and the second word line WL _my are shown in the cross-sectional view 1504 as being located on a first interconnect layer, it should be understood that in other embodiments the first word line WL _nx and the second word line WL _my may be located on a higher interconnect layer (e.g., on a second interconnect layer, a third interconnect layer, etc.).

As shown in the cross-sectional view 1600 of fig. 16, the first MRAM device 202a and the second MRAM device 202b are formed over the interconnect line 324 within the first ILD structure 1502. The first MRAM device 202a includes a first MTJ having a first fixed layer 204a separated from a first free layer 208a by a first dielectric tunnel barrier 206 a. The second MRAM device 202b includes a second MTJ having a second fixed layer 204b separated from a second free layer 208b by a second dielectric tunnel barrier 206 b. In some embodiments, the first pinned layer 204a and the second pinned layer 204b may be formed on the bottom electrode via 326 contacting the interconnection line 324. The bottom electrode via 326 is surrounded by a dielectric layer 1402.

_{4 3 4 8}In some embodiments, the first MRAM device 202a and the second MRAM device 202b may be formed at the same time, hi other embodiments, the first MRAM device 202a may be formed at a different time than the second MRAM device 202 b. in some embodiments, the first MRAM device 202a and the second MRAM device 202b may be formed by depositing a magnetic pinned film over the first ILD structure 1502, forming a dielectric barrier film over the magnetic pinned film, and forming a magnetic free film over the dielectric barrier film.

As shown in the cross-sectional view 1700 of FIG. 17, a second ILD structure 1702 is formed over the first MRAM device 202a and the second MRAM device 202 b. the second ILD structure 1702 may be formed by one or more deposition processes (e.g., PVD, CVD, PE-CVD, etc.) one or more additional interconnect layers 330 are formed within the second ILD structure 1702. the one or more additional interconnect layers 330 connect the first MRAM device 202a to a first bit line BL _nx and the second MRAM device 202b to a second bit line BL _my. in some embodiments, the one or more additional interconnect layers 330 may be formed by selectively etching the second ILD 1702 to form openings within the second ILD 1702. thereafter, a conductive material (e.g., copper and/or aluminum) is deposited within the openings.

FIG. 18 illustrates a flow diagram of some embodiments of a method 1800 of forming an integrated chip including memory circuits having shared drive transistors configured to provide access to a plurality of memory devices, respectively.

while the method 1800 is illustrated and described below as a series of steps or events, it will be appreciated that the illustrated ordering of such steps or events are not to be interpreted in a limiting sense. For example, some steps may occur in different orders and/or concurrently with other steps or events apart from those illustrated and/or described herein. Moreover, not all illustrated steps may be required to implement one or more aspects or embodiments described herein, and one or more steps described herein may be implemented in one or more separate steps and/or stages.

In step 1802, a shared control element is formed within a substrate. The shared control element has one or more gate structures disposed within the substrate between the drain region and the one or more source regions. In some embodiments, the shared control element may include a drive transistor having a gate structure disposed between a source region and a drain region within the substrate. In other embodiments, the shared control element may include multiple drive transistors sharing one or more components (e.g., source regions, drain regions, etc.). Fig. 13 illustrates a cross-sectional view 1300 of some embodiments corresponding to step 1802.

At step 1804, a plurality of interconnect layers are formed within the first ILD structure above the substrate. A plurality of interconnect layers connect the source region to a source line and the one or more gate structures to a first word line and a second word line. Fig. 14-15B illustrate cross-sectional views 1400-1504 of some embodiments corresponding to step 1804.

In step 1806, a first MRAM device connected to the drain region is formed. In some embodiments, the first MRAM device is formed with a first pinned layer connected to a drain region. The first pinned layer is separated from the first free layer by a first dielectric barrier layer. Fig. 16 shows a cross-sectional view 1600 of some embodiments corresponding to step 1806.

In step 1808, a second MRAM device connected to the drain region is formed. In some embodiments, the second MRAM device is formed to have a second pinned layer connected to a drain region. The second fixed layer is separated from the second free layer by a second dielectric barrier layer. Fig. 16 shows a cross-sectional view 1600 of some embodiments corresponding to step 1808.

In step 1810, one or more additional interconnect layers are formed to connect the first MRAM device to a first bit line and also to connect the second MRAM device to a second bit line. In some embodiments, the additional interconnect layer is formed to connect the first free layer of the first MRAM device to the first bit line and the second free layer of the second MRAM device to the second bit line. Fig. 17 shows a cross-sectional view 1700 of some embodiments corresponding to step 1810.

Accordingly, in some embodiments, the present invention relates to an integrated chip including a memory array having a shared control element shared among a plurality of memory devices (e.g., MRAM devices).

In some embodiments, the invention relates to an integrated chip. The integrated chip includes a first memory device disposed over the substrate and connected to a first bit line; a second memory device disposed over the substrate and connected to the second bit line; and a shared control element disposed within the substrate and configured to provide access to the first storage device and to provide access to the second storage device separately, the shared control element including one or more control devices sharing one or more components. In some embodiments, the shared control element includes a drive transistor having a source region connected to the source line, a drain region connected to the first and second memory devices, and a gate structure connected to the first and second word lines. In some embodiments, the gate structure includes a gate electrode separated from the substrate by a gate dielectric; the first word line is connected to the gate electrode through a first conductive contact provided on the gate electrode, and the second word line is connected to the gate electrode through a second conductive contact provided on the gate electrode. In some embodiments, the integrated chip further includes a third word line connected to the gate structure and a third memory device connected between the gate structure and the third bit line. In some embodiments, the first memory device comprises a first Magnetoresistive Random Access Memory (MRAM) device and the second memory device comprises a second MRAM device. In some embodiments, the shared control element includes a first drive transistor and a second drive transistor, the first drive transistor having a first gate structure connected to the first word line and disposed over the substrate between a first source region connected to the first source line and a drain region connected to the first and second memory devices; and a second drive transistor having a second gate structure connected to the second word line and disposed over the substrate between a second source region and a drain region connected to the second source line. In some embodiments, the shared control element is connected to a first word line and a second word line. In some embodiments, the integrated chip further comprises: a word line decoder configured to apply a first non-zero voltage to a first word line; and a bit line decoder configured to simultaneously apply a second non-zero voltage to the first bit line and a third non-zero voltage to the second bit line. In some embodiments, the first memory device and the second memory device are disposed within a memory array having a plurality of memory devices arranged in rows and columns; and the first bit line is connected to a first plurality of memory devices within a column and the second bit line is connected to a second plurality of memory devices within a row. In some embodiments, the first bit line and the second bit line extend in different directions.

In other embodiments, the invention relates to an integrated chip. The integrated chip includes a memory array having a plurality of Magnetoresistive Random Access Memory (MRAM) devices arranged in rows and columns, the plurality of MRAM devices including a first MRAM device connected to a first bit line, the first bit line also connected to the first plurality of MRAM devices within a row of the memory array; a second MRAM device connected to a second bit line, the second bit line also connected to a second plurality of MRAM devices within a column of the memory array; and a driving transistor having a gate structure connected to the word line and disposed between the source region and the drain region connected to the first MRAM device and the second MRAM device. In some embodiments, the gate structure is also connected to a second word line. In some embodiments, the word line includes a complete interconnect line extending continuously over the plurality of gate structures along the first direction; and the second word line includes a plurality of discrete interconnect lines each extending over one of the plurality of gate structures and separated by a non-zero spacing along the second direction. In some embodiments, the integrated chip further includes a second drive transistor having a second gate structure connected to a second word line and disposed between a second source region and a drain region. In some embodiments, the integrated chip further includes a second drive transistor having a second gate structure connected to a second word line and disposed between the source region and the drain region. In some embodiments, the first MRAM device includes a first pinned layer and a first free layer electrically connected between the first pinned layer and the drive transistor; and the second MRAM device includes a second pinned layer and a second free layer electrically connected between the second pinned layer and the drive transistor. In some embodiments, the first pinned layer and the second pinned layer are disposed along an upper surface of an interconnect line that extends continuously under the first MRAM device and the second MRAM device. In some embodiments, the first MRAM device includes a first free layer and a first pinned layer electrically connected between the first free layer and the drive transistor; and the second MRAM device includes a second free layer and a second pinned layer electrically connected between the second free layer and the driving transistor.

In yet other embodiments, the invention relates to methods of forming integrated chips. The method includes forming a shared control element having one or more gate structures disposed between a drain region and one or more source regions within a substrate; forming one or more interconnect layers within an interlayer dielectric (ILD) structure over a substrate, wherein the one or more interconnect layers define a first word line and a second word line connected to one or more gate structures; forming a first memory device and a second memory device within the ILD structure, wherein the first memory device and the second memory device are connected to the drain region; and forming one or more additional interconnect layers defining a first bit line connected to the first memory device and a second bit line connected to the second memory device. In some embodiments, the first bit line is connected to a first plurality of memory devices within a column of the memory array and the second bit line is connected to a second plurality of memory devices within a row of the memory array.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.