阅读说明：本技术 一种高低压集成器件及其制造方法 (A kind of high-low pressure integrated device and its manufacturing method ) 是由 乔明 孟培培 张波 于 2019-09-06 设计创作，主要内容包括：本发明提供一种高低压集成器件及其制造方法,所述高低压集成器件包括集成于同一芯片上的高压垂直型恒流器件、低压NMOS器件、低压PMOS器件、低压NPN器件和低压DIODE器件；低压器件均位于介质隔离槽内部,采用介质隔离方式实现高压器件和低压器件完全隔离。本发明采用部分埋氧隔离技术实现高低压器件兼容,完全避免漏电与串扰问题,成本相较传统SOI工艺更低；基于BCD工艺集成技术设计理念,将高压垂直型恒流器件与调流所用的低压器件集成在一起,通过单片集成方式简化恒流器件调流电路设计,降低系统复杂度的同时节约制造成本,可实现恒流器件电流调节的功能,适用于不同电流大小应用场合。(It includes the high pressure vertical-type constant current device being integrated on same chip, low pressure NMOS device, low pressure PMOS device, low pressure NPN device and low pressure DIODE device that the present invention, which provides a kind of high-low pressure integrated device and its manufacturing method, the high-low pressure integrated device,；Low-voltage device is respectively positioned on inside medium isolation channel, realizes that high tension apparatus and low-voltage device are completely isolated using medium isolation method.The present invention buries oxygen isolation technology using part and realizes that high-low voltage device is compatible, avoids electric leakage and cross-interference issue completely, it is lower that cost compares traditional SOI technique；Based on BCD technique integrated technology design concept, high pressure vertical-type constant current device is integrated with the low-voltage device for adjusting stream used, simplify the design of constant current device tune current circuit by single-chip integration mode, manufacturing cost is saved while reducing system complexity, the function of constant current device current regulation can be achieved, be suitable for different size of current applications.)

1. a kind of high-low pressure integrated device, including be integrated on same chip high pressure vertical-type constant current device (101), low pressure NMOS device (102), low pressure PMOS device (103), low pressure NPN device (104) and low pressure DIODE device (105)；

The high pressure vertical-type constant current device (101) is bilateral symmetry, is divided into cellular region and termination environment, cellular region is by multiple The identical cellular of structure connects to be formed with parallel way；The structure cell includes the back side collection being cascading from the bottom to top Electrode metal electrode (40), the first conductivity type substrate (10), the second conductive type epitaxial layer (9), thin-layered medium layer (21), grid Electrode (31) and the first emitter metal electrode (30)；There is the first conduction type first in second conductive type epitaxial layer (9) Well region (3), the second conduction type contact (1), the first conduction type contact (2) and the second conduction type deplection type channel area (6)；

First the first well region of conduction type (3) is located at the upper layer both ends of the second conductive type epitaxial layer (9), and the first conduction type connects Touching (2), the second conduction type contact (1) and the second conduction type deplection type channel area (6) are successively located side by side at the first conductive-type The upper layer side of the first well region of type (3), thin-layered medium layer (21) are located at the contact of the second conduction type of part (1), the second conductive-type On the second conductive type epitaxial layer (9) between type deplection type channel area (6) and first the first well region of conduction type (3), first Emitter metal electrode (30) is located on the second conduction type contact (1), the first conduction type contact (2) and gate electrode (31)；

The termination environment is located at the two sides of cellular region, including the backside collector metal electrode being cascading from bottom to up (40), the first conductivity type substrate (10), the second conductive type epitaxial layer (9), dielectric layer field oxygen (23), pre-metal dielectric (25) With the first emitter metal electrode (30), has in the second conductive type epitaxial layer (9) of the termination environment and equidistantly to arrange First the second well region of conduction type (4)；

The low pressure NMOS device (102), low pressure PMOS device (103), low pressure NPN device (104) and low pressure DIODE device (105) it is sequentially located in the second conductive type epitaxial layer (9) of high pressure vertical-type constant current device (101) side；

It is characterized in that, the low pressure NMOS device (102), low pressure PMOS device (103), low pressure NPN device (104) and low pressure In the area of isolation that DIODE device (105) is also located at media slot (11) and buries oxide layer (13) connect and compose, and be located at it is described every From in first the second well region of conduction type (4) in region, it is internal that polysilicon silicon fill (12) is located at media slot (11)；High-voltage device Part and low-voltage device are isolated by the area of isolation；Table on the second conductive type epitaxial layer (9) between adjacent low-voltage device Face also sets up dielectric layer field oxygen (23).

2. a kind of high-low pressure integrated device according to claim 1, it is characterised in that: first in the area of isolation leads Electric the second well region of type (4) is divided into multiple regions, and quantity is consistent with low-voltage device number, the first adjacent conduction type It is between second well region (4) the second conductive type epitaxial layer (9).

3. a kind of high-low pressure integrated device according to claim 1, it is characterised in that: first in the area of isolation leads Electric the second well region of type (4) is downward and the outside of the area of isolation is extended to two sides, and the first conduction type contacts (2) also position It is connect on the inside of the edge of first the second well region of conduction type (4), and with well region contact electrode (41)；

The second conductive-type in the low pressure PMOS device (103), low pressure NPN device (104) and low pressure DIODE device (105) The first well region of type (5) is in contact with buries oxide layer (13).

4. a kind of high-low pressure integrated device according to claim 1, it is characterised in that: the buries oxide layer (13) is located at the In two conductive type epitaxial layers (9)；Or the buries oxide layer (13) is located in the first conductivity type substrate (10).

5. a kind of high-low pressure integrated device according to claim 1, it is characterised in that: also set up a resistance layer (7), the field Resistance layer (7) is between the first conductivity type substrate (10) and the second conductive type epitaxial layer (9), and the buries oxide layer (13) In the first conductivity type substrate (10).

6. a kind of high-low pressure integrated device according to claim 1, it is characterised in that: high pressure vertical-type constant current device (101) centre of first the first well region of conduction type (3) and first the second well region of conduction type (4) is provided with media slot (11), have in slot polysilicon silicon fill (12), and the bottom of media slot (11) is located under first the second well region of conduction type (4) Side；High pressure vertical-type constant current device (101) termination environment is outermost to be with the second conduction type contact (1) as electric field cut-off ring；Institute The depth of the depth and the media slot (11) in high pressure vertical-type constant current device of stating the media slot (11) in area of isolation keeps one It causes.

7. a kind of high-low pressure integrated device according to claim 1, it is characterised in that: high pressure vertical-type constant current device (101) centre of first the first well region of conduction type (3) and first the second well region of conduction type (4) in is provided with media slot (11), have in slot polysilicon silicon fill (12), in the media slot (11) in the area of isolation and high pressure vertical-type constant current device Media slot (11) extend into the first conductivity type substrate (10), and the depth of the media slot (11) in the area of isolation with The depth of media slot (11) in high pressure vertical-type constant current device is consistent, high pressure vertical-type constant current device (101) termination environment Outermost is provided with the second conduction type contact (1) as electric field and ends ring.

8. a kind of high-low pressure integrated device, including be integrated on same chip high pressure vertical-type constant current device (101), low pressure NMOS device (102), low pressure PMOS device (103), low pressure NPN device (104) and low pressure DIODE device (105)；

The high pressure vertical-type constant current device (101) is bilateral symmetry, is divided into cellular region and termination environment, cellular region is by multiple The identical cellular of structure connects to be formed with parallel way；The structure cell includes the back side collection being cascading from the bottom to top Electrode metal electrode (40), the first conductivity type substrate (10), the second conductive type epitaxial layer (9), thin-layered medium layer (21), grid Electrode (31) and the first emitter metal electrode (30)；There is the first conduction type first in second conductive type epitaxial layer (9) Well region (3), the second conduction type contact (1), the first conduction type contact (2) and the second conduction type deplection type channel area (6)；

First the first well region of conduction type (3) is located at the upper layer both ends of the second conductive type epitaxial layer (9), and the first conduction type connects Touching (2), the second conduction type contact (1) and the second conduction type deplection type channel area (6) are successively located side by side at the first conductive-type The upper layer side of the first well region of type (3), thin-layered medium layer (21) are located at the contact of the second conduction type of part (1), the second conductive-type On the second conductive type epitaxial layer (9) between type deplection type channel area (6) and first the first well region of conduction type (3), first Emitter metal electrode (30) is located on the second conduction type contact (1), the first conduction type contact (2) and gate electrode (31)；

The termination environment is located at the two sides of cellular region, including the backside collector metal electrode being cascading from bottom to up (40), the first conductivity type substrate (10), the second conductive type epitaxial layer (9), pre-metal dielectric (25) and floating metal electrode (42), there is first the first well region of conduction type equidistantly arranged in the second conductive type epitaxial layer (9) of the termination environment (3), there is the first conduction type contact (2), floating metal electrode (42) is located at first in first the first well region of conduction type (3) Conduction type contacts on (2) and pre-metal dielectric (25)；

The low pressure NMOS device (102), low pressure PMOS device (103), low pressure NPN device (104) and low pressure DIODE device (105) it is sequentially located in the second conductive type epitaxial layer (9) of high pressure vertical-type constant current device (101) side；

It is characterized in that, the low pressure NMOS device (102), low pressure PMOS device (103), low pressure NPN device (104) and low pressure DIODE device (105) is also located in the area of isolation that media slot (11) and buries oxide layer (13) connect and compose, polysilicon silicon fill (12) it is internal to be located at media slot (11)；The second conductive type epitaxial layer (9) upper surface between adjacent low-voltage device also sets up Jie Matter layer field oxygen (23).

9. a kind of high-low pressure integrated device according to claim 8, it is characterised in that: the low pressure NMOS device (102), Low pressure PMOS device (103), low pressure NPN device (104) and low pressure DIODE device (105) are also located in the area of isolation In first the second well region of conduction type (4).

10. a kind of high-low pressure integrated device according to claim 8, it is characterised in that: each low-voltage device is respectively positioned on Jie In the area of isolation that matter slot (11) and buries oxide layer (13) connect and compose；

The low pressure NMOS device (102) is located at first the first well region of conduction type (3) inside, first the first well region of conduction type (3) it is located at the upper layer of the second conductive type epitaxial layer (9).

11. a kind of manufacturing method of high-low pressure integrated device, which comprises the following steps:

On the first conductivity type substrate (10), the second conductive type epitaxial layer (9) are formed using epitaxy technique；

Through photoetching and ion implantation technology, after the side of the second conductive type epitaxial layer (9) injection oxonium ion, annealing It is formed buries oxide layer (13)；

Using deep etching technique, the both ends above buries oxide layer (13) form deep trouth and the two sides filled media in deep trouth, It is formed media slot (11), is filled in media slot (11) with polysilicon, formed polysilicon silicon fill (12)；

Using photoetching and ion implantation technology, the first conduction type second is formed on the upper layer of the second conductive type epitaxial layer (9) Well region (4), and carry out well region diffusion；

Oxide layer, shape are grown in the first part upper surface of the second conductive type epitaxial layer (9) using photoetching and thermal growth mode At dielectric layer field oxygen (23)；

Using photoetching and ion implantation technology, on the second conductive type epitaxial layer (9) between dielectric layer field oxygen (23) respectively The first conductive type impurity and the second conductive type impurity are injected, after annealing, on the upper layer of the second conductive type epitaxial layer (9) The other side forms first the first well region of conduction type (3) and the second conduction type deplection type channel area (6), the second conduction type consumption Most type channel region (6) are located at the upper layer side of first the first well region of conduction type (3), form second between media slot (11) and lead Electric the first well region of type (5) and first the first well region of conduction type (3), first the first well region of conduction type (3) are located at part In two the first well regions of conduction type (5)；

By thermal growth mode, oxide layer is grown in the second part upper surface of the second conductive type epitaxial layer (9), forms thin layer Dielectric layer (21) photoetching and is etched and forms gate electrode (31) after depositing polysilicon；

Using photoetching and ion implantation technology, the first conductive type impurity is injected separately on the second conductive type epitaxial layer (9) And second conductive type impurity, in first the first well region of conduction type (3), first the second well region of conduction type (4) after annealing The second conduction type contact (1) is formed with the upper layer of second the first well region of conduction type (5), and (2) are contacted with the first conduction type；

It deposits pre-metal dielectric (25), photoetching simultaneously etches deposited metal after contact hole, then photoetching and etches and form each front gold Belong to electrode；

Deposit back metal forms electrode below the first conductivity type substrate (10).

12. a kind of manufacturing method of high-low pressure integrated device, which comprises the following steps:

On the first conductivity type substrate (10), the second conductive type epitaxial layer (9) are formed using epitaxy technique；

Using photoetching and ion implantation technology, first the second well region of conduction type is formed on the second conductive type epitaxial layer (9) (4), and well region diffusion is carried out；

First the second well region of conduction type by photoetching and ion implantation technology, in the second conductive type epitaxial layer (9) side (4) oxonium ion is injected in, forms buries oxide layer (13) after annealing；

Using deep etching technique, deep trouth is formed in the second conductive type epitaxial layer (9) and in the two sides filled media of deep trouth, It is formed media slot (11), is filled in media slot (11) with polysilicon, formed polysilicon silicon fill (12)；

By thermal growth mode, oxide layer is grown in the first part upper surface of the second conductive type epitaxial layer (9), forms medium Layer field oxygen (23)；

Using photoetching and ion implantation technology, the first conductive type impurity is injected separately on the second conductive type epitaxial layer (9) And second conductive type impurity, after annealing, the first conductive-type is formed on the upper layer of the second conductive type epitaxial layer (9) other side The first well region of type (3) and the second conduction type deplection type channel area (6), the second conduction type deplection type channel area (6) are located at the The upper layer side of one the first well region of conduction type (3), formed between media slot (11) second the first well region of conduction type (5) and First the first well region of conduction type (3), first the first well region of conduction type (3) are located at part the first well region of the second conduction type (5) in；

By thermal growth mode, oxide layer is grown in the second part upper surface of the second conductive type epitaxial layer, thin layer is formed and is situated between Matter layer (21) photoetching and is etched and forms gate electrode (31) after depositing polysilicon；

Using photoetching and ion implantation technology, the first conductive type impurity is injected separately on the second conductive type epitaxial layer (9) And second conductive type impurity, after annealing, in first the first well region of conduction type (3), first the second well region of conduction type (4) The second conduction type contact (1) is formed with the upper layer of second the first well region of conduction type (5), and (2) are contacted with the first conduction type；

It deposits pre-metal dielectric (25), photoetching simultaneously etches deposited metal after contact hole, then photoetching and etches and form each front gold Belong to electrode；

Deposit back metal forms electrode below the first conductivity type substrate (10).

13. a kind of manufacturing method of high-low pressure integrated device, which comprises the following steps:

Through photoetching and ion implantation technology, after the side of the first conductivity type substrate (10) injection oxonium ion, annealing It is formed buries oxide layer (13)；

On the first conductivity type substrate (10), the second conductive type epitaxial layer (9) are formed using epitaxy technique；

Using deep etching technique, deep trouth is formed in the second conductive type epitaxial layer (9) and the first conductivity type substrate (10), And in the two sides filled media of deep trouth, formed media slot (11), filled in media slot (11) with polysilicon, formed polysilicon and fill out Fill object (12)；

Using photoetching and ion implantation technology, first the second well region of conduction type is formed in the second conductive type epitaxial layer (9) (4), and well region diffusion is carried out；

Oxide layer is grown in the first part upper surface of the second conductive type epitaxial layer (9) by thermal growth mode, forms medium Layer field oxygen (23)；

Using photoetching and ion implantation technology, the first conductive type impurity is injected separately on the second conductive type epitaxial layer (9) And second conductive type impurity, after annealing, the first conductive-type is formed in the upper layer other side of the second conductive type epitaxial layer (9) The first well region of type (3) and the second conduction type deplection type channel area (6), the second conduction type deplection type channel area (6) are located at the The upper layer side of one the first well region of conduction type (3), formed between media slot (11) second the first well region of conduction type (5) and First the first well region of conduction type (3), first the first well region of conduction type (3) are located at part the first well region of the second conduction type (5) in；

Oxide layer is grown in the second part upper surface of the second conductive type epitaxial layer by thermally grown mode, thin layer is formed and is situated between Matter layer (21) photoetching and is etched and forms gate electrode (31) after depositing polysilicon；

Using photoetching and ion implantation technology, the first conductive type impurity is injected separately on the second conductive type epitaxial layer (9) And second conductive type impurity, in first the first well region of conduction type (3), first the second well region of conduction type (4) after annealing The second conduction type contact (1) is formed with the upper layer of second the first well region of conduction type (5), and (2) are contacted with the first conduction type；

It deposits pre-metal dielectric (25), photoetching simultaneously etches deposited metal after contact hole, then photoetching and etches and form each front gold Belong to electrode；

Deposit back metal forms electrode below the first conductivity type substrate (10).

Technical field

The invention belongs to semiconductor power device technology fields, and in particular to a kind of high-low pressure integrated device and its manufacturer Method.

Background technique

Constant-current source is a kind of common electronic equipment and device, using fairly common in electronic circuit.Constant-current source is usual For protecting entire circuit, even if occurring spread of voltage in circuit or the case where load resistor value changes greatly, remain to protect Demonstrate,prove the stabilization of entire circuit supply current.Current regulator diode (CRD, Constant Regulating Diode) is a kind of common Semiconductor constant current device replaces common by multiple electronics such as transistor, voltage-stabiliser tube and resistance using diode as constant-current source The constant-current source of element composition realizes that circuit structure is simplified and minimized.Common current regulator diode output electric current is in several millis at present Pacify between tens milliamperes, can be used for directly driving load, due to having the characteristics that device volume is small, device reliability is high, make It has great advantage compared to conventional constant current source.The peripheral circuit of current regulator diode is simple, easy to use, is widely used to certainly The fields such as dynamic control, instrument and meter and protection circuit.But current regulator diode itself output electric current can not be adjusted, can only be by multiple Method in parallel realizes output electric current adjustment, and current value can only be increased by multiple proportional, or be realized by external circuit elements Expand stream output.Both tune stream methods can all cause the increase of number of electronic components used, to cause circuit structure complexity journey The rising of degree and cost.

High-voltage power integrated circuit often utilize the high simulation precision of Bipolar transistor, CMOS high integration and The high power characteristic of DMOS (Double-Diffused MOSFET), by Bipolar analog circuit, CMOS logic circuit, CMOS Analog circuit (abbreviation BCD technique) together with DMOS high voltage power device single-chip integration.BCD technique integrated technology is a kind of normal System power dissipation can be greatly reduced in single slice integration technique, improve system performance, save the encapsulation overhead and tool of circuit There is better reliability.Since part category is numerous in BCD technique, it need to consider each area's particular/special requirement of device, reduce technique system Mask plate quantity is made, every processing step is enable to carry out simultaneously.While the compatibility in order to accomplish high tension apparatus and low-voltage device, it is double The compatibility of pole technique and CMOS technology need to select suitable isolation technology.

Summary of the invention

The technical problem to be solved by the present invention is in view of the problems of the existing technology, provide a kind of high-low pressure integrator Part and its manufacturing method.

In order to solve the above technical problems, the embodiment of the present invention provides a kind of high-low pressure integrated device, including it is integrated in same High pressure vertical-type constant current device, low pressure NMOS device, low pressure PMOS device, low pressure NPN device and low pressure DIODE device on chip Part；

The high pressure vertical-type constant current device is bilateral symmetry, is divided into cellular region and termination environment, cellular region is by multiple The identical cellular of structure connects to be formed with parallel way；The structure cell includes the back side collection being cascading from the bottom to top Electrode metal electrode, the first conductivity type substrate, the second conductive type epitaxial layer, thin-layered medium layer, gate electrode and the first transmitting Pole metal electrode；There is first the first well region of conduction type, the contact of the second conduction type, first in second conductive type epitaxial layer Conduction type contact and the second conduction type deplection type channel area；

First the first well region of conduction type is located at the upper layer both ends of the second conductive type epitaxial layer, and the first conduction type connects Touching, the contact of the second conduction type and the second conduction type deplection type channel area are successively located side by side at first the first well region of conduction type Upper layer side, thin-layered medium floor be located at the second conduction type of part contact, the second conduction type deplection type channel area and first On the second conductive type epitaxial layer between the first well region of conduction type, the first emitter metal electrode is located at the second conduction type On contact, the contact of the first conduction type and gate electrode；

The termination environment is located at the two sides of cellular region, including the backside collector metal electricity being cascading from bottom to up Pole, the first conductivity type substrate, the second conductive type epitaxial layer, dielectric layer field oxygen, pre-metal dielectric and the first emitter metal Electrode has first the second well region of conduction type equidistantly arranged in the second conductive type epitaxial layer of the termination environment；

The low pressure NMOS device, low pressure PMOS device, low pressure NPN device and low pressure DIODE device are sequentially located at described In second conductive type epitaxial layer of high pressure vertical-type constant current device side；

The low pressure NMOS device, low pressure PMOS device, low pressure NPN device and low pressure DIODE device are also located at media slot In the area of isolation connected and composed with buries oxide layer, and in first the second well region of conduction type being located in the area of isolation, Polysilicon silicon fill is located inside media slot；High tension apparatus and low-voltage device are isolated by the area of isolation；Adjacent low-voltage device The second conductive type epitaxial layer upper surface between part also sets up dielectric layer field oxygen.

Based on the above technical solution, the present invention can also be improved as follows.

Further, first the second well region of conduction type in the area of isolation is divided into multiple regions, quantity with it is low Voltage device number is consistent, and is the second conductive type epitaxial layer between first adjacent the second well region of conduction type.

Beneficial effect using above-mentioned further scheme is: by the way that first the second well region of conduction type is divided into multiple areas Domain, makes the junction isolation structure that PNP triode is formed between low-voltage device, and binding medium isolation structure can further prevent low Electric leakage and cross-interference issue between voltage device promote reliability when chip operation.

Further, first the second well region of conduction type in the area of isolation downwards and to two sides extend to it is described every Outside from region, the contact of the first conduction type is also located on the inside of the edge of first the second well region of conduction type, and is connect with well region Touched electrode connection；

Second the first well region of conduction type in the low pressure PMOS device, low pressure NPN device and low pressure DIODE device is equal It is in contact with buries oxide layer.

Further, the buries oxide layer is located in the second conductive type epitaxial layer；Or the buries oxide layer is located at the In one conductivity type substrate.

Further, a resistance layer is also set up, the field resistance layer is located at outside the first conductivity type substrate and the second conduction type Prolong between layer, and the buries oxide layer is located in the first conductivity type substrate.

Further, first the first well region of conduction type and first the second trap of conduction type of high pressure vertical-type constant current device The centre in area is provided with media slot, has polysilicon silicon fill in slot, and the bottom of media slot is located at the first conduction type second Below well region；High pressure vertical-type constant current device termination environment is outermost to be with the contact of the second conduction type as electric field cut-off ring；It is described The depth of media slot in area of isolation and the depth of the media slot in high pressure vertical-type constant current device are consistent.

Further, first the first well region of conduction type and the first conduction type second in high pressure vertical-type constant current device The centre of well region is provided with media slot, there is polysilicon silicon fill in slot, and the media slot in the area of isolation is vertical with high pressure Media slot in type constant current device extends into the first conductivity type substrate, and the depth of the media slot in the area of isolation with The depth of media slot in high pressure vertical-type constant current device is consistent, the setting of high pressure vertical-type constant current device termination environment outermost There is the contact of the second conduction type as electric field and ends ring.

In order to solve the above technical problems, the embodiment of the invention provides a kind of high-low pressure integrated devices, including it is integrated in same High pressure vertical-type constant current device, low pressure NMOS device, low pressure PMOS device, low pressure NPN device and low pressure DIODE on one chip Device；

The high pressure vertical-type constant current device is bilateral symmetry, is divided into cellular region and termination environment, cellular region is by multiple The identical cellular of structure connects to be formed with parallel way；The structure cell includes the back side collection being cascading from the bottom to top Electrode metal electrode, the first conductivity type substrate, the second conductive type epitaxial layer, thin-layered medium layer, gate electrode and the first transmitting Pole metal electrode；There is first the first well region of conduction type, the contact of the second conduction type, first in second conductive type epitaxial layer Conduction type contact and the second conduction type deplection type channel area；

First the first well region of conduction type is located at the upper layer both ends of the second conductive type epitaxial layer, and the first conduction type connects Touching, the contact of the second conduction type and the second conduction type deplection type channel area are successively located side by side at first the first well region of conduction type Upper layer side, thin-layered medium floor be located at the second conduction type of part contact, the second conduction type deplection type channel area and first On the second conductive type epitaxial layer between the first well region of conduction type, the first emitter metal electrode is located at the second conduction type On contact, the contact of the first conduction type and gate electrode；

The termination environment is located at the two sides of cellular region, including the backside collector metal electricity being cascading from bottom to up Pole, the first conductivity type substrate, the second conductive type epitaxial layer, pre-metal dielectric and floating metal electrode, the termination environment There is first the first well region of conduction type equidistantly arranged, first the first well region of conduction type in second conductive type epitaxial layer In have the first conduction type contact, floating metal electrode be located at the first conduction type contact with pre-metal dielectric on；

The low pressure NMOS device, low pressure PMOS device, low pressure NPN device and low pressure DIODE device 105 are sequentially located at institute In the second conductive type epitaxial layer for stating high pressure vertical-type constant current device side；

The low pressure NMOS device, low pressure PMOS device, low pressure NPN device and low pressure DIODE device are also located at media slot In the area of isolation connected and composed with buries oxide layer, polysilicon silicon fill is located inside media slot；Between adjacent low-voltage device Second conductive type epitaxial layer upper surface also sets up dielectric layer field oxygen.

Based on the above technical solution, the present invention can also be improved as follows.

Further, the low pressure NMOS device, low pressure PMOS device, low pressure NPN device and low pressure DIODE device also position In first the second well region of conduction type in the area of isolation.

Further, each low-voltage device is respectively positioned in the area of isolation that media slot and buries oxide layer connect and compose；

The low pressure NMOS device is located inside first the first well region of conduction type, and first the first well region of conduction type is located at The upper layer of second conductive type epitaxial layer.

In order to solve the above technical problems, the embodiment of the invention provides a kind of manufacturing method of high-low pressure integrated device, packet Include following steps:

In the first conductivity type substrate, the second conductive type epitaxial layer is formed using epitaxy technique；

By photoetching and ion implantation technology, oxonium ion, annealing are injected in the side of the second conductive type epitaxial layer After form buries oxide layer；

Using deep etching technique, the both ends above buries oxide layer form deep trouth and the two sides filled media in deep trouth, Media slot is formed, is filled in media slot with polysilicon, polysilicon silicon fill is formed；

Using photoetching and ion implantation technology, the first conduction type second is formed on the upper layer of the second conductive type epitaxial layer Well region, and carry out well region diffusion；

Oxide layer, shape are grown in the first part upper surface of the second conductive type epitaxial layer using photoetching and thermal growth mode At dielectric layer field oxygen；

Using photoetching and ion implantation technology, it is injected separately on the second conductive type epitaxial layer between the oxygen of dielectric layer field First conductive type impurity and the second conductive type impurity, after annealing, in the upper layer other side of the second conductive type epitaxial layer Form first the first well region of conduction type and the second conduction type deplection type channel area, the second conduction type deplection type channel position In the upper layer side of first the first well region of conduction type, second the first well region of conduction type and first is formed between media slot and is led Electric the first well region of type, first the first well region of conduction type are located in the first well region of the second conduction type of part；

By thermal growth mode, oxide layer is grown in the second part upper surface of the second conductive type epitaxial layer, is formed thin Layer dielectric layer photoetching and is etched and forms gate electrode after depositing polysilicon；

Using photoetching and ion implantation technology, the first conductive type impurity is injected separately on the second conductive type epitaxial layer And second conductive type impurity, in first the first well region of conduction type, first the second well region of conduction type and second after annealing The upper layer of the first well region of conduction type forms the contact of the second conduction type and contacts with the first conduction type；

Pre-metal dielectric is deposited, photoetching simultaneously etches deposited metal after contact hole, then photoetching and etches and form each front gold Belong to electrode；

Back metal is deposited below the first conductivity type substrate forms electrode.

In order to solve the above technical problems, the embodiment of the invention provides a kind of manufacturing method of high-low pressure integrated device, packet Include following steps:

In the first conductivity type substrate, the second conductive type epitaxial layer is formed using epitaxy technique；

Using photoetching and ion implantation technology, first the second trap of conduction type is formed on the second conductive type epitaxial layer Area, and carry out well region diffusion；

First the second well region of conduction type by photoetching and ion implantation technology, in the second conductive type epitaxial layer side Middle injection oxonium ion forms buries oxide layer after annealing；

Using deep etching technique, deep trouth is formed in the second conductive type epitaxial layer and fills Jie in the two sides of deep trouth Matter forms media slot, is filled in media slot with polysilicon, forms polysilicon silicon fill；

By thermal growth mode, oxide layer is grown in the first part upper surface of the second conductive type epitaxial layer, is formed and is situated between Matter layer field oxygen；

Using photoetching and ion implantation technology, the first conductive type impurity is injected separately on the second conductive type epitaxial layer And second conductive type impurity, after annealing, the first conduction type is formed on the upper layer of the second conductive type epitaxial layer other side First well region and the second conduction type deplection type channel area, the second conduction type deplection type channel area are located at the first conduction type The upper layer side of one well region forms second the first well region of conduction type and first the first well region of conduction type between media slot, First the first well region of conduction type is located in the first well region of the second conduction type of part；

By thermal growth mode, oxide layer is grown in the second part upper surface of the second conductive type epitaxial layer, is formed thin Layer dielectric layer photoetching and is etched and forms gate electrode after depositing polysilicon；

Using photoetching and ion implantation technology, the first conductive type impurity is injected separately on the second conductive type epitaxial layer And second conductive type impurity, after annealing, in first the first well region of conduction type, first the second well region of conduction type and second The upper layer of the first well region of conduction type forms the contact of the second conduction type and contacts with the first conduction type；

Pre-metal dielectric is deposited, photoetching simultaneously etches deposited metal after contact hole, then photoetching and etches and form each front gold Belong to electrode；

Back metal is deposited below the first conductivity type substrate forms electrode.

In order to solve the above technical problems, the embodiment of the invention provides a kind of manufacturing method of high-low pressure integrated device, packet Include following steps:

Through photoetching and ion implantation technology, after the side of the first conductivity type substrate injection oxonium ion, annealing Form buries oxide layer；

In the first conductivity type substrate, the second conductive type epitaxial layer is formed using epitaxy technique；

Using deep etching technique, deep trouth is formed in the second conductive type epitaxial layer and the first conductivity type substrate, and In the two sides filled media of deep trouth, media slot is formed, is filled in media slot with polysilicon, forms polysilicon silicon fill；

Using photoetching and ion implantation technology, first the second trap of conduction type is formed in the second conductive type epitaxial layer Area, and carry out well region diffusion；

Oxide layer is grown in the first part upper surface of the second conductive type epitaxial layer by thermal growth mode, forms medium Layer field oxygen；

Using photoetching and ion implantation technology, the first conductive type impurity is injected separately on the second conductive type epitaxial layer And second conductive type impurity, after annealing, the first conduction type is formed in the upper layer other side of the second conductive type epitaxial layer First well region and the second conduction type deplection type channel area, the second conduction type deplection type channel area are located at the first conduction type The upper layer side of one well region forms second the first well region of conduction type and first the first well region of conduction type between media slot, First the first well region of conduction type is located in the first well region of the second conduction type of part；

Oxide layer is grown in the second part upper surface of the second conductive type epitaxial layer by thermally grown mode, is formed thin Layer dielectric layer photoetching and is etched and forms gate electrode after depositing polysilicon；

Using photoetching and ion implantation technology, the first conductive type impurity is injected separately on the second conductive type epitaxial layer And second conductive type impurity, in first the first well region of conduction type, first the second well region of conduction type and second after annealing The upper layer of the first well region of conduction type forms the contact of the second conduction type and contacts with the first conduction type；

Pre-metal dielectric is deposited, photoetching simultaneously etches deposited metal after contact hole, then photoetching and etches and form each front gold Belong to electrode；

Back metal is deposited below the first conductivity type substrate forms electrode.

The beneficial effects of the present invention are: the present invention is based on BCD technique integrated technology design concept, by high pressure vertical-type constant current Device is integrated with the low-voltage device for adjusting stream used, simplifies the design of constant current device tune current circuit by single-chip integration mode, Reduce system complexity while save manufacturing cost, it can be achieved that constant current device current regulation function, be suitable for different electric currents Size application.The present invention buries oxygen isolation technology using part and realizes that high-low voltage device is compatible, avoids electric leakage and crosstalk completely Problem, it is lower that cost compares traditional SOI technique.

Detailed description of the invention

Fig. 1 is a kind of the schematic diagram of the section structure for high-low pressure integrated device that the embodiment of the present invention 1 provides；

Fig. 2 is a kind of the schematic diagram of the section structure for high-low pressure integrated device that the embodiment of the present invention 2 provides；

Fig. 3 is a kind of the schematic diagram of the section structure for high-low pressure integrated device that the embodiment of the present invention 3 provides；

Fig. 4 is a kind of the schematic diagram of the section structure for high-low pressure integrated device that the embodiment of the present invention 4 provides；

Fig. 5 is a kind of the schematic diagram of the section structure for high-low pressure integrated device that the embodiment of the present invention 5 provides；

Fig. 6 is a kind of the schematic diagram of the section structure for high-low pressure integrated device that the embodiment of the present invention 6 provides；

Fig. 7 is a kind of the schematic diagram of the section structure for high-low pressure integrated device that the embodiment of the present invention 7 provides；

Fig. 8 is a kind of the schematic diagram of the section structure for high-low pressure integrated device that the embodiment of the present invention 8 provides；

Fig. 9 is a kind of the schematic diagram of the section structure for high-low pressure integrated device that the embodiment of the present invention 9 provides；

Figure 10 is a kind of process flow chart of the manufacturing method for high-low pressure integrated device that the embodiment of the present invention 10 provides；

Figure 11 is a kind of process flow chart of the manufacturing method for high-low pressure integrated device that the embodiment of the present invention 11 provides；

Figure 12 is a kind of process flow chart of the manufacturing method for high-low pressure integrated device that the embodiment of the present invention 12 provides.

In attached drawing, parts list represented by the reference numerals are as follows:

C (1) ... c (i) ... c (n) is structure cell, and i, n are positive integer, indicates cellular number, and 101 is permanent for high pressure vertical-type Device is flowed, 102 be low pressure NMOS device, and 103 be low pressure PMOS device, and 104 be low pressure NPN device, and 105 be low pressure DIODE device Part；1 contacts for the second conduction type, and 2 contact for the first conduction type, and 3 be first the first well region of conduction type, and 4 lead for first Electric the second well region of type, 5 be second the first well region of conduction type, and 6 be the second conduction type deplection type channel area, and 7 be field resistance layer, 9 be the second conductive type epitaxial layer, and 10 be the first conductivity type substrate, and 11 be media slot, and 12 be polysilicon silicon fill, and 13 be to bury Oxide layer, 21 be thin-layered medium layer, and 23 be dielectric layer field oxygen, and 25 be pre-metal dielectric, and 30 be the first emitter metal electrode, 31 It is source metal electrode for gate electrode, 32,33 be drain metal electrode, and 34 be the second emitter metal electrode, and 35 be base stage gold Belong to electrode, 36 be collector electrode metal electrode, and 37 be anode metal electrodes, and 38 be cathodic metal electrode, and 39 contact electrode for body, 40 Electrode is contacted for well region for backside collector metal electrode, 41,42 be floating metal electrode.

Specific embodiment

The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and It is non-to be used to limit the scope of the invention.

As shown in Figure 1, a kind of high-low pressure integrated device that the embodiment of the present invention 1 provides, including be integrated on same chip High pressure vertical-type constant current device 101, low pressure NMOS device 102, low pressure PMOS device 103, low pressure NPN device 104 and low pressure DIODE device 105；

The high pressure vertical-type constant current device 101 is bilateral symmetry, is divided into cellular region and termination environment, cellular region is by more The identical cellular of a structure connects to be formed with parallel way；The structure cell includes the back side being cascading from the bottom to top Collector electrode metal electrode 40, the first conductivity type substrate 10, the second conductive type epitaxial layer 9, thin-layered medium layer 21, gate electrode 31 With the first emitter metal electrode 30；In second conductive type epitaxial layer 9 there is first the first well region of conduction type 3, second to lead Electric types of contacts 1, the contact 2 of the first conduction type and the second conduction type deplection type channel area 6；

First the first well region of conduction type 3 is located at the upper layer both ends of the second conductive type epitaxial layer 9, and the first conduction type connects The contact 1 of the 2, second conduction type of touching and the second conduction type deplection type channel area 6 are successively located side by side at the first conduction type first The upper layer side of well region 3, thin-layered medium layer 21 are located at the second conduction type of part and contact the 1, second conduction type deplection type channel On the second conductive type epitaxial layer 9 between area 6 and first the first well region of conduction type 3, the first 30, emitter metal electrode It is contacted in the 1, first conduction type contact 2 and gate electrode 31 in the second conduction type；

The termination environment is located at the two sides of cellular region, including the backside collector metal electricity being cascading from bottom to up Pole 40, the first conductivity type substrate 10, the second conductive type epitaxial layer 9, dielectric layer field oxygen 23, pre-metal dielectric 25 and the first hair Emitter-base bandgap grading metal electrode 30 has the first conduction type equidistantly arranged in second conductive type epitaxial layer 9 of the termination environment Second well region 4；

The low pressure NMOS device 102, low pressure PMOS device 103, low pressure NPN device 104 and low pressure DIODE device 105 It is sequentially located in the second conductive type epitaxial layer 9 of 101 side of high pressure vertical-type constant current device；

It is characterized in that, the low pressure NMOS device 102, low pressure PMOS device 103, low pressure NPN device 104 and low pressure DIODE device 105 is also located in the area of isolation that media slot 11 and buries oxide layer 13 connect and compose, and is located at the area of isolation In first interior the second well region of conduction type 4, polysilicon silicon fill 12 is located inside media slot 11；High tension apparatus and low-voltage device It is isolated by the area of isolation；9 upper surface of the second conductive type epitaxial layer between adjacent low-voltage device also sets up dielectric layer Field oxygen 23.

In above-described embodiment, in order to have when overleaf collector electrode metal electrode 40 connects high potential between high-low voltage device All low-voltage devices are placed in media slot 11 and buries oxide layer 13 by the way of medium isolation by good electric isolation performance In the area of isolation of composition, prevent electric leakage and cross-interference issue between high pressure vertical-type constant current device and low-voltage device completely.

The low pressure NMOS device 102 include: thin-layered medium layer 21 on first the second well region of conduction type 4 and Gate electrode 31 on thin-layered medium layer 21, two positioned at 31 two sides of gate electrode and in first the second well region of conduction type 4 Second conduction type contact 1, two the second conduction types contact and are respectively provided with source metal electrode 32 and drain metal electrode on 1 33,1 side is contacted positioned at two the second conduction types and the first conduction type being located in first the second well region of conduction type 4 connects Touching 2, the first conduction type contacts on 2, and there is body to contact electrode 39；

The low pressure PMOS device 103 includes: the second conduction type first in first the second well region of conduction type 4 Well region 5, the gate electrode 31 on the thin-layered medium layer 21 and thin-layered medium layer 21 on second the first well region of conduction type 5, Two the first conduction types contact 2 positioned at 31 two sides of gate electrode and in second the first well region of conduction type 5, two first It is respectively provided with drain metal electrode 33 and source metal electrode 32 in conduction type contact 2, is connect positioned at two the first conduction types The the second conduction type contact 1 touching 2 sides and being located in second the first well region of conduction type 5, the second conduction type contacts to be had on 1 There is body to contact electrode 39；

The low pressure NPN device 104 includes: the second conduction type first in first the second well region of conduction type 4 Well region 5, first the first well region of conduction type 3 in second the first well region of conduction type 5 are located at the first conduction type first The second conduction type contact 1 of 3 side of well region, the second conduction type of first the first well region of conduction type, 3 side contacts to be had on 1 Have collector electrode metal electrode 36, positioned at first the first well region of conduction type 3 upper layer and spaced second conduction type connect Touching 1 and the first conduction type contact 2, the contact 1 of the second conduction type and the first conductive-type in first the first well region of conduction type 3 Base metal electrode 35 and the second emitter metal electrode 34 are respectively provided in type contact 2；

The low pressure DIODE device 105 includes: the second conduction type in first the second well region of conduction type 4 One well region 5, positioned at second the first well region of conduction type 5 upper layer and spaced second conduction type contact and 1 and first lead Cathodic metal electrode 38 and sun are respectively provided in electric types of contacts 2, the contact 1 of the second conduction type and the first conduction type contact 2 Pole metal electrode 37.

Semiconductor material used is silicon or silicon carbide, is also applied for other semiconductor materials.

The operation principle of the present invention is that: for the high pressure vertical-type constant current device 101 in actual work, backside collector is golden Belong to electrode 40 and connects high potential, 30 earthing potential of emitter metal electrode, the gate driving circuit control that all low-voltage devices are constituted The current potential of constant current device gate electrode 31.The second conduction type depletion type ditch with the raising of 31 current potential of gate electrode, under it Electronic surface amount of charge in road area 6 is influenced by electric field and is risen, and 6 resistance value of the second conduction type deplection type channel area is dropped It is low, so that constant current device output constant current value increases.By adjusting constant current device gate electrode 31 current potential size, it can be achieved that galvanostat The function that part electric current continuously adjusts is suitable for different size of current applications.

As shown in Fig. 2, the embodiment of the present invention 2 provide a kind of high-low pressure integrated device, be on the basis of embodiment 1, Divide first the second well region of conduction type 4 in the area of isolation and is kept for multiple regions, quantity and low-voltage device number It unanimously, is the second conductive type epitaxial layer between first adjacent the second well region of conduction type 4.By by the first conduction type Two well regions 4 are divided into multiple regions, make between low-voltage device formed PNP triode junction isolation structure, binding medium isolation structure, The electric leakage and cross-interference issue between low-voltage device can be further prevented, reliability when chip operation is promoted.

As shown in figure 3, the embodiment of the present invention 3 provide a kind of high-low pressure integrated device, be on the basis of embodiment 1, Make first the second well region of conduction type 4 in the area of isolation downwards and extend to the outside of the area of isolation to two sides, First conduction type contact 2 is also located on the inside of the edge of first the second well region of conduction type 4, and is connected with well region contact electrode 41 It connects；

The second conduction type in the low pressure PMOS device 103, low pressure NPN device 104 and low pressure DIODE device 105 First well region 5 is in contact with buries oxide layer 13.

A kind of high-low pressure integrated device that the embodiment of the present invention 4 provides is on the basis of embodiment 1, to make described to bury oxygen Change layer 13 to be located in the second conductive type epitaxial layer 9, as shown in Figure 1；Or the buries oxide layer 13 is located at the first conduction type In substrate 10, as shown in Figure 4.

As shown in figure 5, the embodiment of the present invention 5 provide a kind of high-low pressure integrated device, be on the basis of embodiment 1, A resistance layer 7 is also set up, the field resistance layer 7 is between the first conductivity type substrate 10 and the second conductive type epitaxial layer 9, and institute Buries oxide layer 13 is stated to be located in the first conductivity type substrate 10.

As shown in fig. 6, the embodiment of the present invention 6 provide a kind of high-low pressure integrated device, be on the basis of embodiment 1, It is equal in first conduction type the first well region 3 of high pressure vertical-type constant current device 101 and the centre of first the second well region of conduction type 4 It is provided with media slot 11, has polysilicon silicon fill 12 in slot, and the bottom of media slot 11 is located at first the second well region of conduction type 4 Lower section；101 termination environments of high pressure vertical-type constant current device are outermost to be with the second conduction type contact 1 as electric field cut-off ring；It is described The depth of media slot 11 in area of isolation and the depth of the media slot 11 in high pressure vertical-type constant current device are consistent.

In above-described embodiment, by the range for the area of isolation that media slot 11 is surrounded, the first conduction type second should be located at Inside 4 region of well region, well region contact electrode 41 is located between 4 edge of media slot 11 and first the second well region of conduction type, and Closed hoop structure is formed around media slot 11, in order to contact electrode 41 to first the second well region of conduction type 4 by well region Carry out current potential contact.

As shown in fig. 7, the embodiment of the present invention 7 provide a kind of high-low pressure integrated device, be on the basis of embodiment 1, The centre of first conduction type the first well region 3 and first the second well region of conduction type 4 in high pressure vertical-type constant current device 101 is equal It is provided with media slot 11, there is polysilicon silicon fill 12 in slot, the media slot 11 in the area of isolation and the constant current of high pressure vertical-type Media slot 11 in device extends into the first conductivity type substrate 10, and the depth of the media slot 11 in the area of isolation with The depth of media slot 11 in high pressure vertical-type constant current device is consistent, and 101 termination environments of high pressure vertical-type constant current device are outermost It encloses and is provided with the second conduction type contact 1 as electric field cut-off ring.

A kind of high-low pressure integrated device that the embodiment of the present invention 8 provides, the high pressure including being integrated on same chip are vertical Type constant current device 101, low pressure NMOS device 102, low pressure PMOS device 103, low pressure NPN device 104 and low pressure DIODE device 105；

The high pressure vertical-type constant current device 101 is bilateral symmetry, is divided into cellular region and termination environment, cellular region is by more The identical cellular of a structure connects to be formed with parallel way；The structure cell includes the back side being cascading from the bottom to top Collector electrode metal electrode 40, the first conductivity type substrate 10, the second conductive type epitaxial layer 9, thin-layered medium layer 21, gate electrode 31 With the first emitter metal electrode 30；In second conductive type epitaxial layer 9 there is first the first well region of conduction type 3, second to lead Electric types of contacts 1, the contact 2 of the first conduction type and the second conduction type deplection type channel area 6；

First the first well region of conduction type 3 is located at the upper layer both ends of the second conductive type epitaxial layer 9, and the first conduction type connects The contact 1 of the 2, second conduction type of touching and the second conduction type deplection type channel area 6 are successively located side by side at the first conduction type first The upper layer side of well region 3, thin-layered medium layer 21 are located at the second conduction type of part and contact the 1, second conduction type deplection type channel On the second conductive type epitaxial layer 9 between area 6 and first the first well region of conduction type 3, the first 30, emitter metal electrode It is contacted in the 1, first conduction type contact 2 and gate electrode 31 in the second conduction type；

The termination environment is located at the two sides of cellular region, including the backside collector metal electricity being cascading from bottom to up Pole 40, the first conductivity type substrate 10, the second conductive type epitaxial layer 9, pre-metal dielectric 25 and floating metal electrode 42, it is described There is first the first well region of conduction type 3 equidistantly arranged, the first conductive-type in second conductive type epitaxial layer 9 of termination environment There is the first conduction type contact 2, floating metal electrode 42 is located at the first conduction type contact 2 and metal in the first well region of type 3 On preceding medium 25；

The low pressure NMOS device 102, low pressure PMOS device 103, low pressure NPN device 104 and low pressure DIODE device 105 It is sequentially located in the second conductive type epitaxial layer 9 of 101 side of high pressure vertical-type constant current device；

It is characterized in that, the low pressure NMOS device 102, low pressure PMOS device 103, low pressure NPN device 104 and low pressure DIODE device 105 is also located in the area of isolation that media slot 11 and buries oxide layer 13 connect and compose, and polysilicon silicon fill 12 is located at Inside media slot 11；9 upper surface of the second conductive type epitaxial layer between adjacent low-voltage device also sets up dielectric layer field oxygen 23.

Optionally, as shown in figure 8, the low pressure NMOS device 102, low pressure PMOS device 103,104 and of low pressure NPN device Low pressure DIODE device 105 is also located in first the second well region of conduction type 4 in the area of isolation.

As shown in figure 9, the embodiment of the present invention 9 provide a kind of high-low pressure integrated device, be on the basis of embodiment 8, Each low-voltage device is respectively positioned in the area of isolation that media slot 11 and buries oxide layer 13 connect and compose；

The low pressure NMOS device 102 is located inside first the first well region of conduction type 3, first the first well region of conduction type 3 are located at the upper layer of the second conductive type epitaxial layer 9.

The structure can reduce the use of mask plate, reduce production cost, and reasonably optimizing high pressure vertical-type constant current simultaneously The spacing of first the first well region of conduction type 3 in 101 terminal of device, it is ensured that the effect of terminal；Between low-voltage device all It is isolated with slot, better isolation effect may be implemented.

As shown in Figure 10, a kind of manufacturing method for high-low pressure integrated device that the embodiment of the present invention 10 provides, including it is following Step:

In the first conductivity type substrate 10, the second conductive type epitaxial layer 9 is formed using epitaxy technique；

By photoetching and ion implantation technology, oxonium ion, annealing are injected in the side of the second conductive type epitaxial layer 9 Buries oxide layer 13 is formed afterwards；

Using deep etching technique, the both ends above buries oxide layer 13, which form deep trouth and fill in the two sides of deep trouth, to be situated between Matter forms media slot 11, is filled in media slot 11 with polysilicon, forms polysilicon silicon fill 12；

Using photoetching and ion implantation technology, the first conduction type the is formed on the upper layer of the second conductive type epitaxial layer 9 Two well regions 4, and carry out well region diffusion；

Oxide layer is grown in the first part upper surface of the second conductive type epitaxial layer 9 using photoetching and thermal growth mode, Form dielectric layer field oxygen 23；

Using photoetching and ion implantation technology, on the second conductive type epitaxial layer 9 between dielectric layer field oxygen 23 respectively The first conductive type impurity and the second conductive type impurity are injected, it is another on the upper layer of the second conductive type epitaxial layer 9 after annealing Side forms first conduction type the first well region 3 and the second conduction type deplection type channel area 6, the second conduction type depletion type ditch Road area 6 is located at the upper layer side of first the first well region of conduction type 3, and second the first trap of conduction type is formed between media slot 11 Area 5 and first the first well region of conduction type 3, first the first well region of conduction type 3 are located at part the first well region of the second conduction type 5 In；

By thermal growth mode, oxide layer is grown in the second part upper surface of the second conductive type epitaxial layer 9, is formed thin Layer dielectric layer 21 photoetching and is etched and forms gate electrode 31 after depositing polysilicon；

Using photoetching and ion implantation technology, it is miscellaneous on the second conductive type epitaxial layer 9 to be injected separately into the first conduction type Matter and the second conductive type impurity, in first conduction type the first well region 3, first the second well region of conduction type, 4 and after annealing The upper layer of second the first well region of conduction type 5 forms the second conduction type contact 1 and contacts 2 with the first conduction type；

Pre-metal dielectric 25 is deposited, photoetching simultaneously etches deposited metal after contact hole, then photoetching and etches and form each front Metal electrode；

Back metal is deposited below the first conductivity type substrate 10 forms electrode.

As shown in figure 11, a kind of manufacturing method for high-low pressure integrated device that the embodiment of the present invention 11 provides, including it is following Step:

In the first conductivity type substrate 10, the second conductive type epitaxial layer 9 is formed using epitaxy technique；

Using photoetching and ion implantation technology, first the second trap of conduction type is formed on the second conductive type epitaxial layer 9 Area 4, and carry out well region diffusion；

First the second trap of conduction type by photoetching and ion implantation technology, in 9 side of the second conductive type epitaxial layer Oxonium ion is injected in area 4, forms buries oxide layer 13 after annealing；

Using deep etching technique, deep trouth is formed in the second conductive type epitaxial layer 9 and fills Jie in the two sides of deep trouth Matter forms media slot 11, is filled in media slot 11 with polysilicon, forms polysilicon silicon fill 12；

By thermal growth mode, oxide layer is grown in the first part upper surface of the second conductive type epitaxial layer 9, is formed and is situated between Matter layer field oxygen 23；

Using photoetching and ion implantation technology, it is miscellaneous on the second conductive type epitaxial layer 9 to be injected separately into the first conduction type Matter and the second conductive type impurity after annealing, form the first conductive-type on the upper layer of 9 other side of the second conductive type epitaxial layer Type the first well region 3 and the second conduction type deplection type channel area 6, it is conductive that the second conduction type deplection type channel area 6 is located at first The upper layer side of the first well region of type 3 forms second conduction type the first well region 5 and the first conduction type between media slot 11 First well region 3, first the first well region of conduction type 3 are located in part the first well region of the second conduction type 5；

By thermal growth mode, oxide layer is grown in the second part upper surface of the second conductive type epitaxial layer, is formed thin Layer dielectric layer 21 photoetching and is etched and forms gate electrode 31 after depositing polysilicon；

Using photoetching and ion implantation technology, it is miscellaneous on the second conductive type epitaxial layer 9 to be injected separately into the first conduction type Matter and the second conductive type impurity, after annealing, in first conduction type the first well region 3, first the second well region of conduction type, 4 and The upper layer of second the first well region of conduction type 5 forms the second conduction type contact 1 and contacts 2 with the first conduction type；

Pre-metal dielectric 25 is deposited, photoetching simultaneously etches deposited metal after contact hole, then photoetching and etches and form each front Metal electrode；

Back metal is deposited below the first conductivity type substrate 10 forms electrode.

As shown in figure 12, a kind of manufacturing method for high-low pressure integrated device that the embodiment of the present invention 12 provides, including it is following Step:

By photoetching and ion implantation technology, oxonium ion, annealing are injected in the side of the first conductivity type substrate 10 Buries oxide layer 13 is formed afterwards；

In the first conductivity type substrate 10, the second conductive type epitaxial layer 9 is formed using epitaxy technique；

Using deep etching technique, deep trouth is formed in the second conductive type epitaxial layer 9 and the first conductivity type substrate 10, And in the two sides filled media of deep trouth, media slot 11 is formed, is filled in media slot 11 with polysilicon, polysilicon silicon fill is formed 12；

Using photoetching and ion implantation technology, first the second trap of conduction type is formed in the second conductive type epitaxial layer 9 Area 4, and carry out well region diffusion；

Oxide layer is grown in the first part upper surface of the second conductive type epitaxial layer 9 by thermal growth mode, is formed and is situated between Matter layer field oxygen 23；

Using photoetching and ion implantation technology, it is miscellaneous on the second conductive type epitaxial layer 9 to be injected separately into the first conduction type Matter and the second conductive type impurity after annealing, form the first conductive-type in the upper layer other side of the second conductive type epitaxial layer 9 Type the first well region 3 and the second conduction type deplection type channel area 6, it is conductive that the second conduction type deplection type channel area 6 is located at first The upper layer side of the first well region of type 3 forms second conduction type the first well region 5 and the first conduction type between media slot 11 First well region 3, first the first well region of conduction type 3 are located in part the first well region of the second conduction type 5；

Oxide layer is grown in the second part upper surface of the second conductive type epitaxial layer by thermally grown mode, is formed thin Layer dielectric layer 21 photoetching and is etched and forms gate electrode 31 after depositing polysilicon；

Using photoetching and ion implantation technology, it is miscellaneous on the second conductive type epitaxial layer 9 to be injected separately into the first conduction type Matter and the second conductive type impurity, in first conduction type the first well region 3, first the second well region of conduction type, 4 and after annealing The upper layer of second the first well region of conduction type 5 forms the second conduction type contact 1 and contacts 2 with the first conduction type；

Pre-metal dielectric 25 is deposited, photoetching simultaneously etches deposited metal after contact hole, then photoetching and etches and form each front Metal electrode；

Back metal is deposited below the first conductivity type substrate 10 forms electrode.

High-low pressure integrated device of the invention is based on BCD technique integrated technology design concept, by high pressure vertical-type galvanostat Part is integrated with the low-voltage device for adjusting stream used, simplifies the design of constant current device tune current circuit, drop by single-chip integration mode Manufacturing cost is saved while low system complexity.In order to accomplish the compatibility of high tension apparatus and low-voltage device, using partially burying oxygen Isolation technology, by ion implanting and annealing way is realized, cost is lower compared to traditional SOI technique.The high pressure integrated is hung down Without electric leakage and cross-interference issue between straight type constant current device and low-voltage device, smaller chip area is occupied, it can be achieved that constant current device The function of current regulation is suitable for different size of current applications.

In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside", " up time The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on the figure or Positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.

In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three It is a etc., unless otherwise specifically defined.

In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc. Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be mechanical connect It connects, is also possible to be electrically connected；It can be directly connected, can also can be in two elements indirectly connected through an intermediary The interaction relationship of the connection in portion or two elements, unless otherwise restricted clearly.For those of ordinary skill in the art For, the specific meanings of the above terms in the present invention can be understood according to specific conditions.

In the present invention unless specifically defined or limited otherwise, fisrt feature in the second feature " on " or " down " can be with It is that the first and second features directly contact or the first and second features pass through intermediary mediate contact.Moreover, fisrt feature exists Second feature " on ", " top " and " above " but fisrt feature be directly above or diagonally above the second feature, or be merely representative of First feature horizontal height is higher than second feature.Fisrt feature can be under the second feature " below ", " below " and " below " One feature is directly under or diagonally below the second feature, or is merely representative of first feature horizontal height less than second feature.

In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples It closes and combines.

The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.