阅读说明：本技术 存储设备的驱动方法 (Driving method of storage device ) 是由 崔永准 权锡千 于 2018-07-20 设计创作，主要内容包括：本发明的存储设备的驱动方法包括以下步骤：在存储设备的控制器中,根据一个块内的NAND闪存单元的每个保持劣化步骤的阈值电压移位,加载由第一读取基准电压和与一个块内的每个页面组的阈值电压变动对应的第二读取基准电压组成的查找表；在控制器中,使用属于多个块内的每个块的当前劣化步骤的第一读取基准电压和第二读取基准电压中的至少一个读取基准电压,执行读取操作直到每个块均完成读取过程(read pass)。(The driving method of the memory device of the present invention includes the steps of: loading, in a controller of a memory device, a lookup table composed of a first read reference voltage and a second read reference voltage corresponding to a threshold voltage variation of each page group within one block, in accordance with a threshold voltage shift of each retention degradation step of a NAND flash memory cell within one block; in the controller, a read operation is performed until a read process is completed for each block using at least one of the first read reference voltage and the second read reference voltage belonging to the current degradation step for each block of the plurality of blocks.)

1. A driving method of a memory device having a page as a reading or writing unit and a plurality of blocks as an erasing unit composed of a plurality of pages, and forming an N-bit multi-level cell in each NAND flash memory cell so as to be programmed into 2N threshold voltage states corresponding to N bits and perform a read operation on the NAND flash memory with 2N-1 read reference voltages distinguishing threshold voltage sections between the 2N threshold voltage states, and the method comprising the steps of:

Loading, in a controller of the memory device, a lookup table composed of a first read reference voltage and a second read reference voltage corresponding to a threshold voltage variation of each page group within one block, in accordance with a threshold voltage shift of each retention degradation step of the NAND flash memory cells within the one block;

In the controller, a read operation is performed until each of the blocks completes a read process using at least one of a first read reference voltage and a second read reference voltage belonging to a current degradation step of each of the blocks.

2. The driving method of a memory device according to claim 1,

The lookup table is configured to be configured to confirm, by the controller, a read margin based on a positional relationship between the 2N threshold voltage states and the 2N-1 read reference voltages in the NAND flash memory after manufacturing a sales storage device including the NAND flash memory and the controller.

3. The driving method of a memory device according to claim 1,

In the initial judgment of the degradation hold step, the first read reference voltage and the second read reference voltage are sequentially used for the NAND flash memory cells in the one block, the degradation step to which the read reference voltage that is successfully read belongs is adopted, the degradation step for each block is maintained and controlled, and the degradation step is initialized when the block is erased.

4. The driving method of a memory device according to claim 3, further comprising the steps of:

When the reading using the first read reference voltage and the second read reference voltage belonging to the current degradation step fails, the reading is performed using the first read reference voltage and the second read reference voltage belonging to the other degradation steps in order for the blocks within the plurality of blocks.

5. The driving method of a memory device according to claim 1,

For the first reading voltage, in the step of deterioration of the lookup table, a common reading window of the plurality of pages is extracted and lookup is performed within the common reading window.

6. The driving method of a memory device according to claim 3, further comprising the steps of:

And performing soft decision, and when reading fails at all the reference voltages of the lookup table, in the one block, reading is performed by increasing and decreasing the offset reference voltage of the same magnitude with reference to the corresponding first reading reference voltage according to the most recent degradation step and the page position within the one block.

Technical Field

The present invention relates to a driving method of a memory device, which minimizes bit errors suitable for a NAND flash memory by correcting an original read reference voltage between a plurality of threshold voltage states in a threshold voltage distribution of the NAND flash memory in consideration of an external influence (thermal stress or placement time or word line loading effect) generated on the memory device including the NAND flash memory.

Background

In general, a storage device is a memory that plays a secondary role when the storage capacity of a main memory (for example, a core memory, or a ROM, a RAM, or the like of a personal computer) is insufficient. The storage device is mostly a Hard Disk Drive (HDD) or a Solid State Drive (SSD), but the present invention is not limited to the solid state drive for explanation.

The storage device is electrically connected to a user host (user host) and exchanges data in the internal NAND flash memory with an external user host using a controller (controller) provided inside. The NAND flash memory has NAND flash memory cells in a two-dimensional or three-dimensional NAND circuit in order to function as a storage medium. The NAND flash memory has a nonvolatile characteristic of protecting data written therein even in a state where power is turned off.

With the frequent driving of the NAND flash memory, gradual aging of the NAND flash memory cells and/or the influence of external temperature on the NAND flash memory, the storage capacity of the NAND flash memory cells is decreased, and thus the memory device gradually loses electrical reliability. In addition, the reliability degradation of the memory device may be specifically described with reference to fig. 1 and 2.

That is, during driving of the memory device, the NAND flash memory receives an electrical signal from a controller, and repeatedly performs a program (P) operation or an erase (E) operation. During the increase of the program (P)/erase (E) cycle count in the NAND flash memory, the individual NAND flash memory cells may Trap undesired internal parasitic charges (Trap) or rearrange and move target stored charges stored therein as the program (P)/erase (E) cycle count increases, thereby easily shifting (shift) the threshold voltage (Vt).

However, since the data information senses the storage charge of the NAND flash memory cell by a read operation (read operation) of the NAND flash memory cell and is classified into a digital state (digital state), the storage charge is increased or decreased by the parasitic charge, and the data information of the NAND flash memory cell is read as data different from an initial stage during the read operation of the NAND flash memory cell, thereby causing an increase in a raw bit error (raw bit error).

In the graph of fig. 1, the two lower curves 4, 8 represent the raw bit error rate (raw bit error rate) in terms of the number of program/erase cycles in the two NAND flash memories. The raw bit errors gradually increase as the number of program/erase cycles increases. And, according to the influence of the external temperature on the memory device, the NAND flash memory cell accelerates the loss of the stored charge from the inside by the influence of the external temperature, thereby further increasing the original bit error.

In the graph of fig. 1, the two upper curves 14, 18 represent the raw bit error rate according to the number of program/erase cycles after applying a heat-associated bake process (bake process) to the two NAND flash memories associated with the two lower curves 4, 8. The two NAND flashes have lower and upper curves 4, 8, 14, 18 with similar trajectories (lorus) before/after the baking process according to the increase of the number of program/erase cycles.

However, the two NAND flash memories are greatly affected by the external temperature after the baking process compared to the effect of the parasitic charge before the baking process, and thus have a larger original bit error rate after the baking process than before the baking process in view of the same number of program/erase cycles. In order to minimize the original bit error rate, the controller is internally provided with an Error Correction Code (ECC) algorithm, so that a bit error generated during a read operation of the NAND flash memory cell is corrected by the ECC algorithm.

Before explaining the read operation of the NAND flash memory cell, the structure of the NAND flash memory cell is roughly explained, the NAND flash memory cell having a NAND flash memory cell at each intersection point by a bit line (bit line) and a word line (word line). When the NAND flash memory is classified as an N-bit multi-level cell (MLC) NAND flash memory, threshold voltages of the NAND flash memory cells are programmed to 2N threshold voltage states (threshold voltage states) that do not overlap with each other.

In the graph of fig. 2, two threshold voltage states (S1, S2) are illustrated as an example. And, the read operation of the NAND flash memory cell is performed by applying an original read reference voltage (original read reference voltage) to the word line, and distinguishing data information of the threshold voltage into a digital state after comparing the threshold voltage of the NAND flash memory cell with the original read reference voltage through charge and discharge cycles of stored charges received from the NAND flash memory cell in the bit line during a sensing process of the bit line.

When the NAND flash memory is divided into an N-bit multi-level cell (MLC) NAND flash memory, in order to read a threshold voltage of a NAND flash memory cell from the NAND flash memory, 2N-1 original read reference voltages are used between the 2N threshold voltage states. In the graph of fig. 2, the original read reference voltage (V1, solid line) is illustrated as an example between the two threshold voltage states (S1, S2).

The memory device is subject to external temperature during manufacture, and the NAND flash memory accelerates the loss of stored charge from the NAND flash memory cell under the influence of external temperature, and therefore, as shown by the dashed parabola of fig. 2 (hereinafter, referred to as the "dashed threshold voltage state S2"), the NAND flash memory cell shifts (F) one (S2) of the two threshold voltage states (S1, S2) in one direction toward the original read reference voltage (V1).

Wherein a user (user) of the memory device regards an original read reference voltage (V1) when the memory device is first obtained as the optimum, and performs a read operation on the NAND flash memory cell by using the original read reference voltage (V1). In a read operation of the NAND flash memory cell, a tail region of a dotted threshold voltage state (S2) located below the original read reference voltage (V1) is distinguished as a read error.

Since the original read reference voltage (V1) is not adjusted according to the field situation, when the tail region of the dotted threshold voltage state (S2) becomes an original bit error rate exceeding the correction capability of the error correction code of the controller, the read operation of the NAND flash memory is repeated until the original read reference voltage (V1) is shifted to the preliminary read reference voltage (V2, V3, dotted line) and the read process (read pass) is completed to the tail region of the dotted threshold voltage state (S2), and thus the tail region of the dotted threshold voltage state (S2) lowers the electrical performance of the NAND flash memory in terms of the time consumed by the read operation of the NAND flash memory.

And, the controller corrects the tail region of the dotted threshold voltage state (S2) located below the original read reference voltage (V1) using an error correction code algorithm and attempts to relieve by the read process, but when the tail region of the dotted threshold voltage state (S2) exceeds the correction capability of the error correction code, the controller shifts the original read reference voltage (V1) through a read retry algorithm provided in the NAND flash memory, so that the tail region of the process dotted threshold voltage state (S2) can be read.

In the graph of fig. 2, the read retry algorithm is configured to track the trace of the shift of the dashed-line threshold voltage state (S2) while correcting the position of the original read reference voltage (V1) and repeatedly switching the original read reference voltage (V1) to the preliminary read reference voltages (V2, V3), and to repeatedly attempt a read operation using the preliminary read reference voltages (V2, V3) in order to reduce or even completely eliminate read errors at the tail of the dashed-line threshold voltage state (S2). Wherein the original read reference voltage (V1) is changed to an optimal read reference voltage (V3).

For the execution of the read retry algorithm, only one original read reference voltage (V1) and only two preliminary read reference voltages (V2, V3) are used in the graph of fig. 2, but in the N-bit multi-level cell NAND flash memory, more than two preliminary read reference voltages are used in two adjacent threshold voltage states together with 2N-1 original read reference voltages, and thus, in the read operation of the NAND flash memory, a read latency (read latency) is increased and power consumption (power consumption) is increased.

accordingly, when the optimal read reference voltage is searched for by the execution of the read retry algorithm during a read operation of the NAND flash memory cell, the electrical performance of the NAND flash memory cell is excessively degraded, and therefore, the memory device predicts a shift characteristic of a threshold voltage of the NAND flash memory cell and stores a plurality of look-up tables (look-up tables) having the read reference voltage in the NAND flash memory in advance, and the read retry algorithm is executed by the controller reading the look-up tables.

Disclosure of Invention

Technical problem to be solved

The present invention has been made to solve the conventional problems, and an object of the present invention is to provide a method for driving a memory device, which is suitable for performing a read operation of a NAND flash memory without generating a read error by appropriately adjusting the position of an original read reference voltage among a plurality of threshold voltage states in a threshold voltage distribution of the NAND flash memory in consideration of an external influence (thermal stress, a placement time, or a word line loading effect) generated on the memory device including the NAND flash memory.

(II) technical scheme

According to the driving method of a memory device of the present invention, in order to make a plurality of blocks having a page as a unit of reading or writing and an erase unit composed of a plurality of pages, in which individual NAND flash memory cells are composed of N-bit multi-level cells (MLCs), thereby being programmed to 2N threshold voltage states (threshold voltage states) corresponding to N bits, and performing a read operation on the NAND flash memory with 2N-1 read reference voltages that distinguish threshold voltage intervals between the 2N threshold voltage states, loading, in the memory device controller, a lookup table composed of a first read reference voltage and a second read reference voltage corresponding to a threshold voltage variation of each page group within one block, according to a threshold voltage shift of each retention degradation step of the NAND flash memory cell within the one block; in the controller, a read operation is performed until a read process (read pass) is completed for each of the blocks using at least one of a first read reference voltage and a second read reference voltage belonging to a current degradation step for each of the blocks.

The lookup table may be configured to confirm a read margin (read margin) based on a positional relationship between the 2N threshold voltage states and the 2N-1 read reference voltages in the NAND flash memory by the controller after manufacturing a sales storage device including the NAND flash memory and the controller.

In the initial judgment of the degradation holding step, the degradation step to which the read reference voltage that is successfully read (read) belongs may be taken for the NAND flash memory cells in the one block in order, the degradation step may be maintained and controlled for each block, and the degradation step may be initialized when a block is erased.

The driving method of the memory device may further include the steps of: when the reading using the first read reference voltage and the second read reference voltage belonging to the current degradation step fails, the reading is performed using the first read reference voltage and the second read reference voltage belonging to the other degradation steps in order for the blocks within the plurality of blocks.

For the first read voltage, a common read window of the plurality of pages may be extracted and searched within the common read window in the step of degrading the lookup table.

The driving method of the memory device may further include the steps of: performing soft decision (soft decision), and when reading fails at all reference voltages of the lookup table, increasing and decreasing offset (offset) reference voltages of the same magnitude based on a corresponding first read reference voltage in the one block according to a most recent degradation step and a page position within the one block, and reading.

(III) advantageous effects

According to the present invention, in consideration of an external influence (thermal stress or placement time or word line loading effect) generated on a memory device including a NAND flash memory, in a NAND flash memory threshold voltage distribution, a position of an original read reference voltage is appropriately adjusted between a plurality of threshold voltage states, so that position correction based on the original read reference voltage is performed and a read operation of the NAND flash memory is performed according to a field situation without generating a read error, and in the read operation of the NAND flash memory, a read latency is shortened to minimize power consumption.

Drawings

FIG. 1 is a graph of the number of program/erase cycles versus the original bit error rate for a prior art memory device illustrating the degradation of electrical performance of NAND flash memory.

Fig. 2 is a graph illustrating a threshold voltage of a read retry algorithm (read retry algorithm) and the number of NAND flash memory cells in a threshold voltage distribution (threshold voltage distribution) of a NAND flash memory affected by an external temperature in a related art memory device.

Fig. 3 is a block diagram schematically showing a storage device of the present invention.

Fig. 4 and 5 are diagrams and tables illustrating a read retry algorithm of a first embodiment of the present invention in the memory device of fig. 3.

Fig. 6 through 8 are graphs and tables illustrating a read retry algorithm of a second embodiment of the present invention in the memory device of fig. 3.

Fig. 9 through 12 are diagrams, graphs, and tables illustrating a read retry algorithm of a third embodiment of the present invention in the memory device of fig. 3.

Fig. 13 and 14 are diagrams and tables illustrating a read retry algorithm of a fourth embodiment of the present invention in the memory device of fig. 3.

Fig. 15 and 16 are graphs and tables illustrating a read retry algorithm of a fifth embodiment of the present invention in the memory device of fig. 3.

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order that those skilled in the art can easily practice the present invention.

Fig. 3 is a block diagram schematically illustrating a storage device of the present invention.

Referring to fig. 3, the memory device 80 includes a NAND flash memory 50 and a controller 70 electrically connected to each other. The NAND flash memory 50 includes the drive information storage area 44 and the data storage area 48. The information of the drive information storage area 44 contains operation values that initialize various analog circuits required for the operation of the NAND flash memory 50 containing a read reference value by an internal drive circuit of the NAND flash memory 50 when power is applied to the NAND flash memory 50.

And, the one-item manufacturer of the NAND flash memory 50 provides an original look-up table (default look-up table) consisting of an offset (offset) value of the read reference value into yet another storage space of the NAND flash memory 50 to use the original look-up table for the read retry look-up table of the controller 70.

The offset value is a reference for shifting an original read reference voltage (default read reference voltage) to the left or right by an offset degree between two adjacent threshold voltage states in a threshold voltage distribution of the NAND flash memory 50.

For simplicity of explanation of the invention, and in comparison to the original look-up table of the original read reference voltages, the read reference voltages constitute a look-up table that can be arbitrarily formed. The data storage area 48 is an area that can be programmed by the outside of the NAND flash memory 50. In addition, the controller 70 is provided with an Error Correction Code (ECC) algorithm 65.

According to the read retry algorithm, to modify the location of the original read reference voltage, traces of at least one shift (shift) of two adjacent threshold voltage states are tracked in two adjacent threshold voltage states, and to reduce or even completely eliminate read errors for the shifted threshold voltage states, a read operation is repeatedly attempted for the shifted threshold voltage states.

Then, for the purpose of the present invention, the read retry algorithm is described in further detail with reference to fig. 4 to 16.

Fig. 4 and 5 are diagrams and tables illustrating a read retry algorithm of a first embodiment of the present invention in the memory device of fig. 3.

Referring to fig. 4 and 5, the read retry algorithm corrects the position of the original read reference voltages (R1, R2, R3) (refer to fig. 4), which are corrected by the controller 70 based on the threshold voltage distribution table and according to the use site situation of the memory device 80, as shown in fig. 4.

The correction of the original read reference voltage is performed according to the field use condition of the memory device 80, which reflects the pressure (pre-curing stress) applied to the NAND flash memory 50 during the temperature test of the NAND flash memory 50 after the individual manufacturer of the NAND flash memory 50 manufactures the NAND flash memory 50, and the thermal stress (heat stress) applied to the memory device 80 during the surface mounting of the memory device 80 by the finished manufacturer of the memory device 80, and thus reflects the latest condition with respect to the original read reference voltage set by the individual manufacturer of the NAND flash memory 50, thereby setting a more accurate read reference voltage.

In more detail, the correction of the raw read reference voltage comprises the steps of: after a read operation is performed on the NAND flash memory 50 by the controller 70, on the threshold voltage distribution chart, the positional relationship between two adjacent threshold voltage states (P3, P4) and the original read reference voltage (R3) is confirmed, when the original read reference voltage (R3) is spaced from the center between two adjacent threshold voltage states (P3, P4) on the threshold voltage distribution graph, arranging at least one preliminary read reference voltage (R3') at a predetermined voltage value between the peaks of two adjacent threshold voltage states (P3, P4) by the controller 70, and the original read reference voltage (R3) is shifted toward the center between two adjacent threshold voltage states (P3, P4) by at least one preliminary read reference voltage (R3') on the threshold voltage distribution chart by the controller 70, thereby finding the optimal read reference voltage.

Confirming the positional relationship between the two adjacent threshold voltage states (P3, P4) and the original read reference voltage (R3) comprises the steps of: the original read reference voltage (R3) between two adjacent threshold voltage states (P3, P4) is confirmed by the controller 70. At this time, the original read reference voltages (R1, R2, R3) have zero offset values (0, 0).

Finding an optimal read reference voltage (R3') by shifting the original read reference voltage (R3) comprises the steps of: the original read reference voltage (R3) is shifted between two adjacent threshold voltage states (P3, P4) by the controller 70 and an ECC-correctable interval is extracted.

The optimum read reference voltage (R3') is a central value of the extraction section, and takes into account a movement direction and a movement amount of the threshold voltage due to retention degradation of the NAND flash memory cell. The optimum read reference voltage (R3') is set to a value that reduces the original read reference voltage (R3) to the extent of the shift amount of the threshold voltage when the threshold voltage drops, increases the original read reference voltage (R3) to the extent of the shift amount of the threshold voltage when the threshold voltage rises, and reflects the set value in the lookup table.

When the threshold voltage variation of the NAND flash memory 50 for maintaining the target specification exceeds the critical point of the current ECC-correctable read offset and the set read reference value, the retry offset (retry offset) is increased. Generally, the same retention shift occurs regardless of the amount of bit information stored in each of the NAND flash memory cells, and therefore, in a 3-bit cell that is narrower than a 2-bit cell read margin (margin), since there is a high possibility that the threshold voltage shift due to retention greatly exceeds the reference read voltage, it is necessary to cope with a plurality of reference read voltages, and an appropriate reference read voltage should be adopted depending on the degree of retention degradation generation.

Although it is possible to sequentially employ a plurality of reference read voltages and repeat the operation until the read is successful (ECC correction is successful), the performance of the memory device 80 is degraded, and therefore, the tracking hold level is employed and the corresponding reference read voltage is employed, so that the performance degradation of the memory device 80 can be avoided.

The read reference voltage (R3') is represented on the threshold voltage distribution graph as a voltage (R3+ Δ Vt) calculated by adding a threshold voltage increment (Δ Vt) to the original threshold voltage (R3). And, the read reference voltages (R1, R2, R3') have offset values (0, + α). The threshold voltage increment (Δ Vt) corresponds to an offset value (+ α).

In addition, as a variation of the first embodiment of the present invention, the lookup table may be formed by individually shifting the original read reference voltages (R1, R2, R3) by predetermined voltage values.

Fig. 6 to 8 are graphs and tables illustrating a read retry algorithm of a second embodiment of the present invention in the memory device of fig. 3.

Referring to fig. 6 to 8, the read retry algorithm is configured to correct the position of the original read reference voltage (R1, R2, R3, refer to fig. 4), which is performed by the controller 70 according to the read error margin (M) between two adjacent threshold voltage states ((P1, P2) or (P2, P3) or (P3, P4) based on the threshold voltage distribution table, as shown in fig. 4.

For the correction of the original read reference voltage, according to the lapse of the retention time of the one-item manufacturer of the NAND flash memory 50 and the lapse of the retention time of the completed-item manufacturer of the memory device 80, and in consideration of the retention (retentivity) deterioration of the NAND flash memory 50 in the memory device 80, on the threshold voltage distribution chart of fig. 4, it is performed according to the read error margin (M) between two adjacent threshold voltage states (P1, P2) or (P2, P3) or (P3, P4), and thus, by reflecting the case of the retention deterioration with respect to the original read reference voltage set by the one-item manufacturer of the NAND flash memory 50, a more accurate read reference voltage is set.

Before explaining the correction of the original read reference voltage, with respect to the retention degradation of the NAND flash memory 50, in the graph of fig. 6, the retention degradation according to the elapse of the retention time is more serious in the programmed threshold voltage state (programmed threshold voltage states, P2, P3, and P4 of fig. 4) than the erased threshold voltage state (P1 of fig. 4) in view of the threshold voltage shift amount (threshold voltage shift amount).

this is because the programmed threshold voltage state (P2, P3, P4) stores more electrons in the NAND flash memory cell than the erased threshold voltage state (P1). The programmed threshold voltage states (P2, P3, P4) are presented in the threshold voltage distribution graph of FIG. 4 in order of increasing threshold voltage and show successively increasing threshold voltage offsets.

The correction of the raw read reference voltage comprises the steps of: after the read operation is performed on the NAND flash memory 50 by the controller 70, on the threshold voltage distribution graph of fig. 4, confirming a positional relationship between two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4) and an original read reference voltage (R1 or R2 or R3), when the original read reference voltage (R1 or R2 or R3) is spaced apart from the center between the two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4) on the threshold voltage distribution graph of fig. 4, by the controller 70 in the two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4), in the read error margin (M) between the sharp points, dividing the read error margin (M) into half, and confirming an error margin (M) on one side; overlapping, by the controller 70, a threshold voltage variation curve (25 of fig. 7) of the NAND flash memory 50 over a time width between a current usage time point (T0) of the NAND flash memory 50 and a maximum allowable placement time (T3) of the NAND flash memory 50 in the graph of fig. 7, dividing the time width into one-side error margins (m) a plurality of times, and forming subdivided time widths, and setting the individually subdivided time widths to the same threshold voltage variation amount; by the controller 70, on the threshold voltage distribution graph of fig. 4, the original read reference voltage (R1 or R2 or R3) is shifted to the central region between two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4) so that the first read reference voltage (R11/R21/R31 under T1 or R12/R22/R32 under T2 or R13/R23/R33 under T3) is looked up at the boundary time point of the individually subdivided time width (T1 or T2 or T3 of fig. 7).

In the reference numerals of the two adjacent threshold voltage states, the P1/P2 or P2/P3 or P3/P4 represents two adjacent threshold voltage states (P1, P2) or two adjacent threshold voltage states (P2, P3) or two adjacent threshold voltage states (P3, P4). Among the reference numerals of the first read reference voltage, R11/R21/R31 at the T1 denotes the first read reference voltage (R11 or R21 or R31) searched for in the movement of the boundary time point (T1 or T2 or T3) of the original read reference voltage (R1). Under the T2, R12/R22/R32 represents a first read reference voltage (R12 or R22 or R32) found in the movement of the boundary time point (T1 or T2 or T3) of the original read reference voltage (R2).

Under the T3, R13/R23/R33 represents a first read reference voltage (R13 or R23 or R33) found in the movement of the boundary time point (T1 or T2 or T3) of the original read reference voltage (R3). In addition, confirming the positional relationship between the two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4) and the original read reference voltage (R1 or R2 or R3) includes the steps of: the original read reference voltage (R1 or R2 or R3) between two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4) is confirmed by the controller 70.

finding a first read reference voltage (finding R11/R21/R31 under T1 or R12/R22/R32 under T2 or R13/R23/R33 under T3) by moving the original read reference voltage (R1 or R2 or R3) comprises the steps of: by the controller 70, during the movement of the original read reference voltage (R1 or R2 or R3) to the central region between two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4), the original read reference voltage (R1 or R2 or R3) passes through the time width of the individual subdivision, and reaches the threshold voltage variation amount to exceed the one-side error margin (m), the threshold voltage corresponding to the boundary time (T1 or T2 or T3) of the time width of the individual subdivision is read as the optimum read reference voltage (R11/R21/R31 under T1 or R12/R22/R32 under T2 or R13/R23/R33 under T3), the lookup table of fig. 8 containing the optimum read reference voltage (R11/R21/R31 under T1 or R12/R22/R32 under T2 or R13/R23/R33 under T3) is formed, and the lookup table is stored in the data storage area 48 of the NAND flash memory 50.

Fig. 9 to 12 are diagrams, graphs and tables illustrating a read retry algorithm of a third embodiment of the present invention in the memory device of fig. 3.

Referring to fig. 9 to 12, the read retry algorithm is configured to correct the position of an original read reference voltage (R1, R2, R3, refer to fig. 4), which is performed by the controller 70 based on the threshold voltage distribution table according to the read error margin (M) between two adjacent threshold voltage states (P1, P2 or P2, P3 or P3, P4) and the position of each Word Line (WL) group of the NAND flash memory 50, as shown in fig. 4.

The correction of the original read reference voltage is performed in consideration of the retention deterioration of the NAND flash memory 50 in the memory device according to the lapse of the retention time of the NAND flash memory 50 by the single manufacturer and the lapse of the retention time of the memory device 80 by the completed manufacturer, and is performed according to the read error margin M between two adjacent threshold voltage states (P1, P2 or P2, P3 or P3, P4) in the threshold voltage distribution diagram in fig. 4 and the position of each word line group of the NAND flash memory 50, and thus, a more accurate read reference voltage is set by reflecting the retention deterioration condition with respect to the original read reference voltage set by the single manufacturer of the NAND flash memory 50.

Before explaining the correction of the raw read reference voltage, the reason why the retention (retention) of the NAND flash memory 50 is deteriorated is that, in the schematic diagram of fig. 9, the NAND flash memory 50 is regarded as a two-dimensional (2D) structure, and when one string (string) in one block (block) is observed, word lines (WL1) having different sizes by position are provided on the semiconductor substrate (W1), or in the schematic diagram of fig. 10, the NAND flash memory 50 is regarded as a three-dimensional structure, and when one string in one block is observed, word lines (WL2) having different sizes by position are provided on the semiconductor substrate (W2).

This is because the word line (WL1 or WL2) is composed of a floating gate (floating gate) and a control gate (control gate) in the NAND flash memory cell, and electrons are inserted into the floating gate or discharged from the floating gate in a program/erase operation of the NAND flash memory 50, and a threshold voltage is maintained by the floating gate. Among them, the electric characteristic difference of each word line (WL1) is caused by the variation of the resistance of the position of each cell (cell) in the NAND cell string connected in series in the NAND flash memory 50, and the loading effect (loading effect) etching and doping characteristic difference of the discontinuous pattern of the cells located at the periphery of the string in the manufacturing step, unlike most cells having the repetitive pattern.

The reason why each of the word lines (WL2) has different sizes from each other is that the word line (WL2) surrounds the active region AR2 formed vertically and tapered (taper) on the semiconductor substrate (W2), and thus has a larger width (width) of the word line (WL2) as it goes away from the semiconductor substrate (W2). Accordingly, the electrical characteristic difference of each word line (WL2) is caused by a phenomenon that, in the case of a three-dimensional cell of a stacked structure, an upper cell has a larger vertical hole (hole) accommodating an active region (AR2) than a lower cell, and thus, has a slower programming speed according to a voltage density difference in the upper cell than the lower cell.

The NAND flash memory 50 considers the variation of the threshold voltage in accordance with the position of the word line on the semiconductor substrate (W1 or W2) as viewed from one character string in one block, so that the Word Line (WL) can be divided into 3 word line groups (G1, G2, G3) based on the threshold voltage curve 35.

The correction of the raw read reference voltage comprises the steps of: confirming a positional relationship between two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4) and an original read reference voltage (R1 or R2 or R3) on the threshold voltage distribution graph of fig. 4 after performing a read operation on the NAND flash memory 50 through the controller 70, and when the original read reference voltage (R1 or R2 or R3) is spaced apart from a center between the two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4) on the threshold voltage distribution graph of fig. 4, dividing the read error margin (M) into half in the read error margin (M) between the two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4) through the controller 70, and confirming an error margin (M) on one side; overlapping, by the controller 70, the threshold voltage variation curve 25 of the NAND flash memory 50 in a time width between a current use time point (T0) of the NAND flash memory 50 and a maximum allowable placing time (T3) of the NAND flash memory 50 in the graph of fig. 7, dividing the time width into one-side error margins (m) a plurality of times, and forming subdivided time widths, and setting the individually subdivided time widths to the same threshold voltage variation amount; by the controller 70, on the threshold voltage distribution graph of fig. 4, the original read reference voltage (R1 or R2 or R3) is shifted to the central region between two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4) so as to search for the first read reference voltage (search for R11/R21/R31 under T1 or R12/R22/R32 under T2 or search for R13/R23/R33 under T3) at the boundary time point (T1 or T2 or T3) of the individually subdivided time width; by the controller 70, in the NAND flash memory 50, the first read reference voltage (shift R11/R21/R31 under T1 or shift R12/R22/R32 under T2 or shift R13/R23/R33 under T3) is shifted according to the position of each word line group (G1 or G2 or G3), and the second read reference voltage (search for R111/R211/R311 in one of G1 to G3 or search for R122/R222/R322 in one of G1 to G3 or search for R133/R233/R333 in one of G1 to G3) is searched in the threshold voltage variation between the word line groups (G1, G2, G3).

In the reference numerals of the two adjacent threshold voltage states, the P1/P2 or P2/P3 or P3/P4 represents two adjacent threshold voltage states (P1, P2) or two adjacent threshold voltage states (P2, P3) or two adjacent threshold voltage states (P3, P4). In the reference numerals of the first read reference voltage, at the time point of T1, R11/R21/R31 denotes the first read reference voltage (R11 or R21 or R31) searched for in the movement of the boundary time point (T1 or T2 or T3) of the original read reference voltage (R1). At the time point of T2, R12/R22/R32 represents a first read reference voltage (R12 or R22 or R32) found in the movement of the boundary time point (T1 or T2 or T3) of the original read reference voltage (R2).

And, at the T3 time point, R13/R23/R33 represents a first read reference voltage (R13 or R23 or R33) searched for in the movement of the boundary time point (T1 or T2 or T3) of the original read reference voltage (R3). In the reference numerals of the second read reference voltage, R111/R211/R311 in one of the G1 through G3 denotes the second read reference voltage (R111 or R211 or R311) found in one (G1 or G2 or G3) of the word line groups (G1, G2, G3). In one of the G1-G3, R122/R222/R322 represents a second read reference voltage (R122 or R222 or R322) found in one (G1 or G2 or G3) of the word line groups (G1, G2, G3). In one of the G1-G3, R133/R233/R333 represents a second read reference voltage (R133 or R233 or R333) looked up in one (G1 or G2 or G3) of the word line groups (G1, G2, G3).

In addition, confirming the positional relationship between the two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4) and the original read reference voltage (R1 or R2 or R3) includes the steps of: the original read reference voltage (R1 or R2 or R3) between two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4) is confirmed by the controller 70.

Finding a first read reference voltage (finding R11/R21/R31 under T1 or R12/R22/R32 under T2 or R13/R23/R33 under T3) by moving the original read reference voltage (R1 or R2 or R3) comprises the steps of: by the controller 70, during the movement of the original read reference voltage (R1 or R2 or R3) to the central region between two adjacent threshold voltage states (P1/P2 or P2/P3 or P3/P4), the original read reference voltage (R1 or R2 or R3) passes through the time width of the individual subdivision, and reaches the threshold voltage variation amount to exceed the one-side error margin (m), the threshold voltage corresponding to the boundary time (T1 or T2 or T3) of the time width of the individual subdivision is read as the optimum read reference voltage (R11/R21/R31 under T1 or R12/R22/R32 under T2 or R13/R23/R33 under T3), a lookup table (refer to fig. 12) containing the optimum read reference voltage (R11/R21/R31 under T1 or R12/R22/R32 under T2 or R13/R23/R33 under T3) is formed, and the lookup table is stored in the data storage area 48 of the NAND flash memory 50.

Finding a second read reference voltage (finding R111/R211/R311 in one of G1 to G3 or finding R122/R222/R322 in one of G1 to G3 or finding R133/R233/R333 in one of G1 to G3) by moving the first read reference voltage (moving R11/R21/R31 in T1 or R12/R22/R32 in T2 or R13/R23/R33 in T3) comprises the steps of: reading the threshold voltage of the NAND flash memory cell of each word line WL in the individual word line group (G or G) according to the first read reference voltage (R/R under T or R/R under T) during shifting the first read reference voltage (R/R under T or R/R under T) according to the word line group (G, G) at the boundary time point (T or T) by the controller 70, and confirming whether the read error occurs or not when the read error does not occur in the word line group (G, G) and the threshold voltage amount exists between the word line groups (G, G), adding the first read reference voltage (T under T plus R/R/R or R under T plus R/R/R under T or R under T plus R/R/R) and reading the word line group (G, G) on the threshold voltage amount Taking as an optimum read reference voltage (reading R111/R211/R311 in one of G1 to G3 or reading R122/R222/R322 in one of G1 to G3 or reading R133/R233/R333 in one of G1 to G3), inserting the optimum read reference voltage (inserting R111/R211/R311 in one of G1 to G3 or inserting R122/R222/R322 in one of G1 to G3 or inserting R133/R233/R333 in one of G1 to G3) in the first lookup table, forming a second lookup table (refer to fig. 12), and storing the second lookup table in the data storage region 48 of the NAND flash memory 50.

Fig. 13 and 14 are diagrams and tables illustrating a read retry algorithm of a fourth embodiment of the present invention in the memory device of fig. 3.

Referring to fig. 13 and 14, the read retry algorithm is configured to correct the position of the original read reference voltages (R1, R2, R3, refer to fig. 4) that are performed by grouping the readable sections by similar word lines. A reference voltage providing the maximum read margin is set for each group. In this case, although an optimal read margin is secured for the page belonging to each group, in the pages belonging to the other groups, the ECC correction fails due to lack of read margin, and other voltages are used in the lookup table for read retries, thereby degrading the performance of the memory device 80.

In the initial placement section where degradation of the NAND flash memory cell has not occurred, the interval between adjacent threshold voltage states is wide, so that the common read window as shown in CR1-3 of fig. 13 can be secured. Therefore, in the correction of the original read reference voltage, the common read reference value extracted from the common read window is additionally set in the look-up table for read retry in the optimum reference voltage item for each word line group and is performed earlier than the read reference value for each word line group, thereby omitting the read retry for each word line group, further improving the performance of the memory device 80. Accordingly, the correction of the original read reference voltage is an unnecessary operation in the case of performing the placement in which the number of common read windows is greatly reduced, and therefore, is not included in the look-up table of the read retry.

In more detail, as shown in fig. 4 or 13, the correction of the original read reference voltage is performed by the controller 70 based on the threshold voltage distribution table at the same position illustrated on the X-axis of each individual page ((bottom page, BP) or (center page, CP) or (top page, TP)) in one block of the NAND flash memory 50 according to a common read window (CRW1 or CRW2 or CRW3) set between two adjacent threshold voltage states (P1, P2 or P2, P3 or P3, P4).

The correction of the original read reference voltage is performed according to a common read window (CRW1 or CRW2 or CRW3) set between two adjacent threshold voltage states (P1, P2 or P2, P3 or P3, P4) in consideration of a word line loading effect and a word line resistance according to a position of a page (TP, CP, BP) in one block within the NAND flash memory 50, the same position of each individual page (TP or CP or BP) illustrated on the threshold voltage distribution graph of fig. 4 or 13.

the correction of the raw read reference voltage comprises the steps of: after a read operation is performed on the NAND flash memory 50 by the controller 70, when the original read reference voltages (R1, R2, R3) are spaced from the center between two adjacent threshold voltage states (P1, P2 or P2, P3 or P3, P4) on the threshold voltage distribution graph of fig. 4 or 13, each individual page (BP or CP or TP) of the pages (BP, CP, TP) confirms a read error margin (M) between the plurality of threshold voltage states (P1, P2, P3, P4) illustrated on the threshold voltage distribution graph, each individual page (BP or CP or TP) is at the same position on the threshold voltage distribution graph by the controller 70, a common read window (CRW1, CRW 87458, P3668672) between the two adjacent threshold voltage states (P9, P2 or P2, P3 or P3, P4) is set by the controller 70, and the original read reference voltages (R3, R3) are moved to the common read window (CRW 368747, CRW 72, R3) by the controller 70, R2, R3) such that the original read reference voltages are located between common read windows (CRW1, CRW2, CRW3) to find first read reference voltages (CR1, CR2, CR3) between common read windows (CRW1, CRW2, CRW 3).

Setting the common read window (CRW1, CRW2, CRW3) comprises the steps of: as seen from the threshold voltage distribution graph of fig. 4 or 13, the controller 70 searches the common read windows (CRW1, CRW2, and CRW3) formed in a straight shape through the two adjacent threshold voltage potentials (P1, P2, P2, P3, P3, and P4) at the same position in the individual page (BP, CP, and TP) without generating a read error and along the page BP, CP, and TP, thereby forming a first lookup table (see fig. 14) having the common read windows (CRW1, CRW2, and CRW3), and stores the first lookup table in the data storage region 48 of the NAND flash memory 50.

Finding the first read reference voltage (CR1, CR2, CR3) comprises the steps of: as seen on the threshold voltage distribution graph of fig. 4 or 13, the controller 70 causes the original read reference voltages (R1, R2, R3) to be located in a central region between the common read windows (CRW1, CRW2, CRW3) while moving the original read reference voltages (R1, R2, R3) to the common read windows (CRW1, CRW2, CRW3), reads the threshold voltage having the largest read error margin between the common read windows (CRW1, CRW2, CRW3) as the optimal read reference voltages (CR1, CR2, CR3), inserts the optimal read reference voltages (CR1, CR2, CR3) into the original table to form a second lookup table (refer to fig. 14), and stores the second lookup table in the data storage region 48 of the flash NAND 50.

Fig. 15 and 16 are graphs and tables illustrating a read retry algorithm of a fifth embodiment of the present invention in the memory device of fig. 3.

Referring to fig. 15 and 16, the read retry algorithm is configured to correct the position of the original read reference voltage (R1, R2, R3, refer to fig. 4), and the correction of the original read reference voltage (R1, R2, R3) is performed by the controller 70 according to the degradation step (T1 or T2 or T3 of fig. 8) of the NAND flash memory cells in one threshold voltage state distribution (P1 or P2 or P3 or P4 distribution (distribution)) of two adjacent threshold voltage states (P1, P2 or P2, P3 or P3, P4) based on the threshold voltage distribution graph, as shown in fig. 4 or fig. 15.

For the sake of simplifying the present invention, the two adjacent threshold voltage states are defined as two individual threshold voltage states (P1, P2). The correction of the original read reference voltage is performed by the controller 70 according to the elapse of the retention time of the individual manufacturer of the NAND flash memory 50 and the elapse of the retention time of the finished manufacturer of the storage device 80, and in consideration of the retention deterioration of the NAND flash memory 50 in the storage device 80, in two adjacent threshold voltage states (P1, P2) of the threshold voltage distribution chart of fig. 15, according to one-side threshold voltage state distribution (P1 or P2 or P3 or P4 distribution (distribution)) of the first read reference voltages (R11/R21/R31 under T1 or R12/R22/R32 under T2 or R13/R23/R33 under T3) of the NAND flash memory cells within the threshold voltage distribution chart of fig. 8.

In more detail, the correction of the raw read reference voltage comprises the steps of: after performing a read operation on the NAND flash memory 50 using the controller 70, on the threshold voltage distribution graph of fig. 15, when the original read reference voltage (R1) is spaced from the center between two adjacent threshold voltage states (P1, P2) by the extent of the first read reference voltage (e.g., R11 spaced at T1), offset read reference voltages (-R110, + R110) of the same distance (L) are set to both sides from the center between the two adjacent threshold voltage states (P1, P2) and the first read reference voltage (R11) is shifted to the offset read reference voltages (-R110, + R110), a lookup table is formed by inserting the offset read reference voltage (-R110 or + R110) in the original lookup table associated with the original read reference voltage (R1), and the lookup table is stored in the data storage region 48 of the NAND flash memory 50.

The correction of the raw read reference voltages (R2, R3) may also be performed in the same manner as described above. The above-described original read reference voltages (R1, R2, R3) may be changed to offset read reference voltages (R110, R210, R310).

next, the driving method of the memory device of the present invention is performed as follows with reference to the first to fifth embodiments (refer to fig. 1 to 16).

Referring to fig. 1 to 16, the memory device 80 has a page as a read or write unit and a plurality of blocks as an erase unit composed of a plurality of pages, and is composed of N-bit multi-level cells (MLCs) in individual NAND flash memory cells so as to be programmed into 2N threshold voltage states corresponding to N bits, and can perform a read operation on the NAND flash memory 50 using 2N-1 read reference voltages that distinguish threshold voltage sections between the 2N threshold voltage states.

The driving method of the memory device 80 includes the steps of: loading, in the controller 70, a lookup table (individual table or integrated one table of fig. 5, 8, 12, 14 and 16) composed of a first read reference voltage and a second read reference voltage corresponding to a threshold voltage variation of each page group within one block according to a threshold voltage shift of each retention degradation step of the NAND flash memory cells within the one block; in the controller 70, a read operation is performed until a read process (read pass) is performed for each of the blocks using at least one of the first read reference voltage and the second read reference voltage belonging to the current degradation step for each of the blocks.

Therefore, the driving method of the memory device 80 reads with a reference read voltage that conforms to the current degradation step of the NAND flash memory cell, and thus, the performance of the memory device 80 can be improved compared to performing the entire contents of the look-up table including all the degradation steps.

The initial judgment of the retention degradation step is to adopt a first reading reference voltage and a second reading reference voltage in sequence for the NAND flash memory cells in one block, adopt the degradation step to which the reading reference voltage which is successfully read belongs, retain and control the degradation step of each block, and can initialize the degradation step when the block is erased.

The driving method of the memory device 80 may further include the steps of: and when the reading using the first read reference voltage and the second read reference voltage belonging to the current degradation step fails, sequentially using the first read reference voltage and the second read reference voltage belonging to the other degradation steps for each of the blocks, and reading.

For the first read voltage, a common read window of the plurality of pages may be extracted and searched within the common read window in the step of degrading the lookup table.

The driving method of the memory device 80 may include the steps of: performing soft decision (soft decision), upon a read failure at all reference voltages of the lookup table, increasing and decreasing offset (offset) reference voltages of the same magnitude based on the most recent degradation step in the one block and a page position within the one block with reference to the corresponding first read reference voltage, and reading.