阅读说明：本技术 显示面板及制造方法 (Display panel and manufacturing method ) 是由 奚苏萍 于 2019-08-26 设计创作，主要内容包括：本发明公开一种显示面板,包括有效显示区域、公共电极、走线区域及电路板。有效显示区域包括薄膜晶体管及多个像素电极。薄膜晶体管包括源极、栅极及漏极,栅极设置在源极和漏极之间,源极及漏极之间具有通道。在源极、通道及漏极的上方设置钝化层。在钝化层上方设置氧化铟锡层。氧化铟锡层覆盖在通道上方以和栅极一起来形成双栅极作用。(The invention discloses a display panel, which comprises an effective display area, a common electrode, a wiring area and a circuit board. The effective display area comprises a thin film transistor and a plurality of pixel electrodes. The thin film transistor comprises a source electrode, a grid electrode and a drain electrode, wherein the grid electrode is arranged between the source electrode and the drain electrode, and a channel is arranged between the source electrode and the drain electrode. And arranging a passivation layer above the source electrode, the channel and the drain electrode. An indium tin oxide layer is disposed over the passivation layer. An ito layer overlies the channel to form a dual gate action with the gate.)

1. a display panel, comprising:

The display device comprises an effective display area and a plurality of pixel electrodes, wherein the effective display area comprises a thin film transistor and a plurality of pixel electrodes, the thin film transistor comprises a source electrode, a grid electrode and a drain electrode, the grid electrode is arranged between the source electrode and the drain electrode, a channel is arranged between the source electrode and the drain electrode, a passivation layer is arranged above the source electrode, the channel and the drain electrode, an indium tin oxide layer is arranged above the passivation layer, and the indium tin oxide layer covers the channel.

2. The display panel of claim 1, further comprising a common electrode, a routing area, and a circuit board.

3. The display panel according to claim 2, wherein an indium tin oxide signal line is provided over the common electrode.

4. The display panel of claim 2, wherein the circuit board comprises a control circuit board and a driving circuit board, the control circuit board is electrically connected to the driving circuit board, the driving circuit board is electrically connected to the trace area, and the trace area is electrically connected to the active display area.

5. The display panel of claim 1, wherein the plurality of pixel electrodes comprise normal pixel electrodes and dummy pixel electrodes.

6. The display panel of claim 5, wherein the dummy pixel electrode is connected to an ITO signal line on the common electrode through at least one via, and the ITO signal line is connected to the driving circuit through a dummy data signal line and a via.

7. The display panel according to claim 4, wherein the control circuit board controls potentials of the plurality of pixel electrodes through data signal lines.

8. The display panel according to claim 5, wherein the dummy pixel electrode and the common electrode are at the same potential.

9. The display panel of claim 5, wherein the dummy pixel electrode is not electrically connected to the thin film transistor.

10. The display panel according to claim 1, wherein the thin film transistor further comprises: a substrate;

A gate insulating layer;

An amorphous silicon layer; and

A doped amorphous silicon layer;

The gate is disposed on the substrate, the gate insulating layer covers the gate, the amorphous silicon layer covers the gate insulating layer, the doped amorphous silicon layer is disposed on the amorphous silicon layer, and the source and the drain are disposed on the doped amorphous silicon layer, respectively.

Technical Field

the present invention relates to a display panel and a manufacturing method thereof, and more particularly, to a display panel capable of effectively reducing threshold voltage offset of a thin film transistor and a manufacturing method thereof.

Background

in recent years, since the thin film transistor in the gate driver circuit board circuit region is exposed to a forward voltage for a long time, a forward shift in the threshold voltage of the thin film transistor in the circuit region is likely to occur. The thin film transistor in the effective display area is under negative voltage for a long time, so that the threshold voltage of the thin film transistor in the effective display area is easy to generate negative deviation. The threshold voltage deviation of the thin film transistor in the circuit area and the threshold voltage deviation of the thin film transistor in the effective display area are opposite to each other, so that the function of the panel is abnormal, and the service life of the panel is influenced.

Therefore, there is a need for an improved display panel and a method for manufacturing the same to solve the problems of the prior art.

Disclosure of Invention

Compared with the prior art, the display panel can effectively reduce the offset of the threshold voltage of the thin film transistor, thereby prolonging the service life of the display panel.

A display panel comprises an effective display area, wherein the effective display area comprises a thin film transistor and a plurality of pixel electrodes, the thin film transistor comprises a source electrode, a grid electrode and a drain electrode, the grid electrode is arranged between the source electrode and the drain electrode, a channel is arranged between the source electrode and the drain electrode, a passivation layer is arranged above the source electrode, the channel and the drain electrode, an indium tin oxide layer is arranged above the passivation layer, and the indium tin oxide layer covers the channel.

In an embodiment of the invention, the display panel further includes a common electrode, a routing area and a circuit board.

in an embodiment of the invention, an ito signal line is disposed on the common electrode.

In an embodiment of the invention, the circuit board includes a control circuit board and a driving circuit board, the control circuit board is electrically connected to the driving circuit board, the driving circuit board is electrically connected to the routing area, and the routing area is electrically connected to the effective display area.

In an embodiment of the invention, the plurality of pixel electrodes include a normal pixel electrode and a dummy pixel electrode.

In an embodiment of the invention, the dummy pixel electrode is connected to the ito signal line on the common electrode through at least one via, and the ito signal line is connected to the driving circuit through the dummy data signal line and the via.

In an embodiment of the invention, the control circuit board controls the potentials of the plurality of pixel electrodes through the data signal lines.

In an embodiment of the invention, the dummy pixel electrode and the common electrode are at the same potential.

In an embodiment of the invention, the dummy pixel electrode is not electrically connected to the thin film transistor.

In an embodiment of the invention, the thin film transistor further includes a substrate, a gate insulating layer, an amorphous silicon layer, and a doped amorphous silicon layer. The grid is arranged on the substrate, the grid insulating layer covers the grid, the amorphous silicon layer covers the grid insulating layer, the doped amorphous silicon layer is arranged on the amorphous silicon layer, and the source electrode and the drain electrode are respectively arranged on the doped amorphous silicon layer.

Drawings

FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present invention;

FIG. 2 is a cross-sectional view of a thin film transistor disposed in an active display area according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a channel of an ITO layer crossing a TFT according to an embodiment of the present invention; and

FIG. 4 shows voltage waveforms of scan lines and dummy data lines according to an embodiment of the present invention.

Detailed Description

Referring to fig. 1, an embodiment of the invention provides a display panel 10, where the display panel 10 includes an effective display area 20, a common electrode 30, a trace area 40, and a circuit board 50. Specifically, the effective display area 20 includes a thin film transistor and a plurality of pixel electrodes including a normal pixel electrode and a dummy pixel electrode. The normal pixel electrode is electrically connected with the thin film transistor, and the virtual pixel electrode is not electrically connected with the thin film transistor. The circuit board 50 includes a control circuit board 52 and a drive circuit board 51. The control circuit board 52 is electrically connected to the driving circuit board 51, and the control circuit board 52 can control the potentials of the plurality of normal pixel electrodes through the driving circuit board 51 and the data signal lines 80. In addition, the control circuit board 52 can also control the potentials of the plurality of virtual pixel electrodes through the virtual data signal lines 70, specifically, the control circuit board 52 is electrically connected to the routing area 40 through the driving circuit board 51 and the virtual data signal lines 70, the through holes in the routing area 40 are connected to the ito signal lines 60 on the common electrode, the ito signal lines 60 are further connected to the virtual pixel electrodes, so that the control circuit board 52 controls the potentials of the plurality of virtual pixel electrodes through the virtual data signal lines 70. Preferably, the dummy pixel electrode is at the same potential as the common electrode.

With reference to fig. 2, the thin film transistor disposed in the effective display area is further described. The thin film transistor 100 includes a substrate 101, a gate electrode 102, a gate insulating layer 103, an amorphous silicon layer 104, a doped amorphous silicon layer 105, a source electrode 106, a drain electrode 107, a passivation layer 108, and an ito layer 109. Specifically, a gate electrode 102 is disposed on a substrate 101, a gate insulating layer 103 covers the gate electrode 102, an amorphous silicon layer 104 covers the gate insulating layer 103, a doped amorphous silicon layer 105 is disposed on the amorphous silicon layer 104, a source electrode 106 and a drain electrode 107 are respectively disposed on the doped amorphous silicon layer 105, a channel is formed between the source electrode 106 and the drain electrode 107, a passivation layer 108 is disposed over the source electrode 106, the channel, and the drain electrode 107, and an ito layer 109 is disposed over the passivation layer 108.

Referring to fig. 3, the ito layer 109 between the upper pixel 250 and the lower pixel 200 crosses the channel of the tft 100, and the ito signal layer 109 electrically connected to the ito signal line is located on the common electrode line and 3 tfts 100. In other words, the ito layer 109 spans the tft 100, and the electrode made of ito is equivalent to another gate electrode, so that the tft 100 has dual gate electrodes, which can effectively reduce the offset of the threshold voltage of the tft, thereby improving the lifetime of the display panel.

Since the thin film transistor in the gate driver circuit board is always at a forward voltage, a forward shift in threshold voltage is likely to occur. Referring to fig. 4, it can be seen from the waveforms of the output scan lines G1 through G2160 of the gate driver circuit substrate that the gate electrodes of the tfts in the effective display area are only a positive voltage for a short time, and are mostly at a relatively low voltage for the rest of the time, so that a negative bias is easily generated. The thin film transistors in the effective display area are in a relatively low potential voltage for a long time, so that the threshold voltage of the thin film transistors in the effective display area is easy to generate negative deviation. In the embodiment of the present invention, the voltage waveforms of the dummy data lines 70 and the ITO signal lines 60 electrically connected thereto are given negative voltages only during the blanking time (blanking time)300 and are at relatively high voltages at other times, so that the problem that the threshold voltages of the TFTs in the active display area are prone to negative shifts can be improved.

the display panel and the manufacturing method thereof provided by the embodiment of the invention can effectively reduce the offset of the threshold voltage of the thin film transistor, thereby prolonging the service life of the display panel.

while the invention has been described in conjunction with specific embodiments thereof, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims.