阅读说明：本技术 高电子迁移率晶体管芯片及其制备方法 (High electron mobility transistor chip and preparation method thereof ) 是由 李瑶 吴志浩 王江波 于 2021-06-30 设计创作，主要内容包括：本发明公开了一种高电子迁移率晶体管芯片及其制备方法,属于半导体光电技术领域。高电子迁移率晶体管芯片包括衬底与n个相互间隔地层叠在衬底上的外延结构,衬底包括依次层叠的绝缘导热层、导电金属层及衬底主体。n个外延结构中存在相互独立的两个外延结构之间的互联。衬底主体起到支撑及源极连接作用。导电金属层导电并键合到绝缘导热层,便于制备。绝缘导热层、导电金属层及衬底主体的制备要求以及成本较低。导电金属层用于引出引脚,不需要额外从高电子迁移率晶体管芯片上剥离衬底,也可以后续封装等操作。减少制备手续,可以降低最终得到的HEMT的成本的同时保证HEMT的质量。(The invention discloses a high electron mobility transistor chip and a preparation method thereof, belonging to the technical field of semiconductor photoelectricity. The high electron mobility transistor chip comprises a substrate and n epitaxial structures which are mutually spaced and stacked on the substrate, wherein the substrate comprises an insulating heat conduction layer, a conductive metal layer and a substrate main body which are sequentially stacked. And the n epitaxial structures are interconnected between the two independent epitaxial structures. The substrate body serves as a support and source connection. The conductive metal layer is conductive and bonded to the insulating and heat conducting layer, and preparation is facilitated. The preparation requirements and the cost of the insulating heat conduction layer, the conductive metal layer and the substrate main body are lower. The conductive metal layer is used for leading out pins, the substrate does not need to be additionally stripped from the high electron mobility transistor chip, and the subsequent packaging and other operations can be carried out. The preparation procedures are reduced, the cost of the finally obtained HEMT can be reduced, and the quality of the HEMT can be ensured.)

1. A high electron mobility transistor chip comprising a substrate and n epitaxial structures stacked on the substrate at intervals, n being an integer and n being greater than or equal to 2, each of the epitaxial structures comprising an epitaxial layer, a source electrode, a gate electrode and a drain electrode stacked on the substrate, the epitaxial layer comprising a dislocation blocking layer, a channel layer, a cap layer and an insulating protective layer stacked on the substrate in this order, an orthographic projection of the dislocation blocking layer on a surface of the substrate being located within an orthographic projection of the channel layer on the surface of the substrate, the insulating protective layer covering a surface of the channel layer and a part of a surface of the cap layer, the gate electrode being located on the insulating protective layer and communicating with the cap layer, the source electrode and the drain electrode being located on both sides of the gate electrode, respectively, and the source electrode and the drain electrode both communicating with the channel layer,

the drain of one of the epitaxial structures of the n epitaxial structures is in communication with the source of the other epitaxial structure,

characterized in that the substrate comprises an insulating heat conduction layer, a conductive metal layer and a substrate main body which are sequentially stacked in the direction from the substrate to the epitaxial structure,

the source electrode of each epitaxial structure is communicated to the substrate main body, and the insulating protection layer of each epitaxial structure extends to the insulating heat conduction layer.

2. The hemt chip of claim 1, wherein a ratio of a thickness of the substrate body to a thickness of the conductive metal layer is 50:1 to 200: 1.

3. The hemt chip of claim 1, wherein a ratio of a thickness of the conductive metal layer to a thickness of the insulating and heat conducting layer is 1:100 to 1: 200.

4. The high electron mobility transistor chip of any one of claims 1 to 3, wherein the thickness of the substrate main body is 100um to 300um, the thickness of the conductive metal layer is 0.5um to 6um, and the thickness of the insulating and heat conducting layer is 50um to 1200 um.

5. The hemt chip of any one of claims 1 to 3, wherein the material of the substrate body is one of Si, SiC and GaN, the conductive metal layer comprises a bonding metal portion and a bonding metal portion which are sequentially stacked in a direction from the substrate to the epitaxial structure, the material of the bonding metal portion comprises one or more of Ti, Ni, Au, Al and Sn, the material of the bonding metal portion is Au, and the material of the insulating and heat conducting layer is one of high-resistivity silicon, aluminum oxide and aluminum nitride.

6. The HEMT chip as claimed in any one of claims 1 to 3, wherein the source of each epitaxial structure is connected to the conductive metal layer.

7. A method for manufacturing a high electron mobility transistor chip, the method being used for manufacturing the high electron mobility transistor chip as claimed in any one of claims 1 to 6, the method comprising:

providing a base substrate;

sequentially growing a dislocation blocking layer, a channel layer and a film layer on the base substrate, wherein the film layer comprises a plurality of mutually-spaced cap layers;

forming a grid electrode on each cap layer, and respectively forming a source electrode and a drain electrode on two sides of each cap layer, wherein the source electrode and the drain electrode are positioned on the channel layer;

forming (n-1) parallel grooves extending to the base substrate on the channel layer, the (n-1) grooves dividing the channel layer into n independent structures, n being an integer and n being greater than or equal to 2;

forming a connection groove extending to the base substrate on each of the independent structures;

thinning one surface of the base substrate far away from the independent structure to obtain a substrate main body;

forming a conductive metal layer on one surface of the substrate main body far away from the independent structure;

bonding the insulating heat conduction layer on the conductive metal layer;

extending the groove to the insulating and heat conducting layer;

forming an insulating protection layer on each independent structure, wherein the insulating protection layer covers the surface of the channel layer and part of the surface of the cap layer in each independent structure, and fills the grooves to obtain n epitaxial structures laminated on the substrate main body;

communicating the drain of one of the n epitaxial structures with the source of the other epitaxial structure, and filling the connecting groove with the source of the other epitaxial structure.

8. The method of claim 7, wherein after forming an insulating protective layer on each of the individual structures, before communicating the drain of one of the n epitaxial structures with the source of another one of the epitaxial structures, the method further comprises:

extending the connecting grooves to a surface of the conductive metal layer.

9. The method of claim 7, wherein after forming the connection grooves extending to the base substrate on each of the independent structures, before thinning a surface of the base substrate away from the independent structure to obtain a substrate main body, the method further comprises:

covering a passivation layer on the surface of each independent structure far away from the base substrate, wherein holes for exposing the surface of the source electrode, the surface of the grid electrode and the surface of the drain electrode are reserved on the passivation layer.

10. The method according to claim 9, wherein the thickness of the passivation layer is 1um to 8 um.

Technical Field

The invention relates to the technical field of semiconductor photoelectricity, in particular to a high-electron-mobility transistor chip and a preparation method thereof.

Background

A HEMT (High Electron Mobility Transistor) is a heterojunction field effect Transistor, which is widely used in various electric appliances. The HEMT chip is a foundation for preparing electronic power devices, and different circuit logics can be formed by different interconnection among pins among a plurality of HEMT chips. The interconnected HEMT chip generally comprises a substrate and a plurality of mutually-spaced epitaxial structures stacked on the substrate, wherein each epitaxial structure comprises an epitaxial layer, a source electrode, a grid electrode and a drain electrode stacked on the substrate, the epitaxial layer comprises a dislocation blocking layer, a channel layer and a cap layer which are sequentially stacked on the substrate, the source electrode and the drain electrode are distributed on the channel layer at intervals, the grid electrode is located between the source electrode and the drain electrode, and the grid electrode is located on the cap layer.

The source and the substrate are connected in a part of the HEMT epitaxial structure so as to inhibit the back gate effect which can exist in the high electron mobility transistor. In the HEMT epitaxial structure in which the source electrode is connected with the substrate, the substrate used is generally an SOI substrate, but the SOI substrate has high preparation cost, high requirements on an epitaxial preparation process, incapability of preparing a thick epitaxial layer, unstable heat dissipation and great influence on the performance of the finally obtained high electron mobility transistor.

Disclosure of Invention

The embodiment of the invention provides a high electron mobility transistor chip and a preparation method thereof, which can reduce the cost of a HEMT and ensure the device performance of the HEMT. The technical scheme is as follows:

the embodiment of the invention provides a high electron mobility transistor chip, which comprises a substrate and n epitaxial structures which are mutually and alternately laminated on the substrate, wherein n is an integer and is more than or equal to 2, each epitaxial structure comprises an epitaxial layer, a source electrode, a grid electrode and a drain electrode which are laminated on the substrate, the epitaxial layer comprises a dislocation blocking layer, a channel layer, a cap layer and an insulating protective layer which are sequentially laminated on the substrate, the orthographic projection of the dislocation blocking layer on the surface of the substrate is positioned in the orthographic projection of the channel layer on the surface of the substrate, the insulating protective layer covers the surface of the channel layer and part of the surface of the cap layer, the grid electrode is positioned on the insulating protective layer and is communicated with the cap layer, the source electrode and the drain electrode are respectively positioned at two sides of the grid electrode, and the source electrode and the drain electrode are both communicated with the channel layer,

the drain of one of the epitaxial structures of the n epitaxial structures is in communication with the source of the other epitaxial structure,

the substrate comprises an insulating heat conduction layer, an electric conduction metal layer and a substrate main body which are sequentially stacked in the direction from the substrate to the epitaxial structure,

the source electrode of each epitaxial structure is communicated to the substrate main body, and the insulating protection layer of each epitaxial structure extends to the insulating heat conduction layer.

Optionally, a ratio of a thickness of the substrate body to a thickness of the conductive metal layer is 50:1 to 200: 1.

Optionally, the ratio of the thickness of the conductive metal layer to the thickness of the insulating and heat conducting layer is 1:100 to 1: 200.

Optionally, the ratio of the thickness of the conductive metal layer to the thickness of the insulating and heat conducting layer is 1:100 to 1: 200.

Optionally, the thickness of the substrate main body is 100 um-300 um, the thickness of the conductive metal layer is 0.5 um-6 um, and the insulating and heat conducting layer is 50 um-1200 um.

Optionally, the substrate main body is made of one of Si, SiC and GaN, the conductive metal layer includes an adhesion metal portion and a bonding metal portion stacked in sequence in a direction from the substrate to the epitaxial structure, the adhesion metal portion is made of one or more of Ti, Ni, Au, Al and Sn, the bonding metal portion is made of Au, and the insulating and heat conducting layer is made of one of high-resistance silicon, aluminum oxide and aluminum nitride.

Optionally, the source of each epitaxial structure is connected to the conductive metal layer.

The embodiment of the present disclosure provides a method for manufacturing a high electron mobility transistor chip, where the method is used to manufacture the high electron mobility transistor chip, and the method includes:

providing a base substrate;

sequentially growing a dislocation blocking layer, a channel layer and a film layer on the base substrate, wherein the film layer comprises a plurality of mutually-spaced cap layers;

forming a grid electrode on each cap layer, and respectively forming a source electrode and a drain electrode on two sides of each cap layer, wherein the source electrode and the drain electrode are positioned on the channel layer;

forming (n-1) parallel grooves extending to the base substrate on the channel layer, the (n-1) grooves dividing the channel layer into n independent structures, n being an integer and n being greater than or equal to 2;

forming a connection groove extending to the base substrate on each of the independent structures;

thinning one surface of the base substrate far away from the independent structure to obtain a substrate main body;

forming a conductive metal layer on one surface of the substrate main body far away from the independent structure;

bonding the insulating heat conduction layer on the conductive metal layer;

extending the groove to the insulating and heat conducting layer;

forming an insulating protection layer on each independent structure, wherein the insulating protection layer covers the surface of the channel layer and part of the surface of the cap layer in each independent structure, and fills the grooves to obtain n epitaxial structures laminated on the substrate main body;

communicating the drain of one of the n epitaxial structures with the source of the other epitaxial structure, and filling the connecting groove with the source of the other epitaxial structure.

Optionally, after forming an insulating protection layer on each of the independent structures, before communicating the drain of one of the n epitaxial structures with the source of another one of the n epitaxial structures, the preparation method further includes:

extending the connecting grooves to a surface of the conductive metal layer.

Optionally, after forming the connection grooves extending to the base substrate on each of the independent structures, before thinning a surface of the base substrate away from the independent structure to obtain a substrate main body, the preparation method further includes:

covering a passivation layer on the surface of each independent structure far away from the base substrate, wherein holes for exposing the surface of the source electrode, the surface of the grid electrode and the surface of the drain electrode are reserved on the passivation layer.

Optionally, the thickness of the passivation layer is 1um to 8 um.

The technical scheme provided by the embodiment of the invention has the following beneficial effects:

the high electron mobility transistor chip comprises a substrate and n epitaxial structures which are mutually spaced and stacked on the substrate, wherein the substrate is used as a growth base of the epitaxial structures and plays a supporting role for the epitaxial structures. Each epitaxial structure includes a common epitaxial layer, a gate, a source, and a drain. In the direction from the substrate to the epitaxial structure, the substrate comprises an insulating heat conduction layer, a conductive metal layer and a substrate main body which are sequentially stacked. The insulating protection layer of each epitaxial structure extends to the insulating heat conduction layer, the insulating protection layer extending to the insulating heat conduction layer isolates the connection between the epitaxial structures, the drain electrode of one epitaxial structure in the n epitaxial structures is communicated with the source electrode of the other epitaxial structure, and then the interconnection between the two mutually independent epitaxial structures is realized, so that certain circuit logic is formed in the high electron mobility transistor chip. The substrate main body in the substrate plays a good supporting role, the substrate main body can be isolated into n parts corresponding to the n epitaxial structures one by the insulating protection layer, the source electrode in each epitaxial structure can be connected with the corresponding part of the substrate main body, and the back gate effect possibly existing in all the epitaxial structures can be well inhibited. The conductive metal layer can conduct electricity and is bonded to the insulating heat conduction layer, and the preparation of the high-electron-mobility transistor chip is facilitated. The preparation requirements and the cost of the insulating heat conduction layer, the conductive metal layer and the substrate main body are low, the overall cost of the high-electron-mobility transistor chip can be effectively controlled, the conductive metal layer can be used for leading out pins, and the subsequent packaging and other operations of the high-electron-mobility transistor chip can be carried out without additionally stripping the substrate from the high-electron-mobility transistor chip. The preparation procedures of the high electron mobility transistor chip can be reduced, the cost of the finally obtained HEMT can be reduced, and the quality and the performance of the HEMT can be ensured.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a high electron mobility transistor chip according to an embodiment of the present invention;

fig. 2 is a flowchart illustrating a method for manufacturing a high electron mobility transistor chip according to an embodiment of the disclosure;

fig. 3 is a flowchart illustrating a method for manufacturing a high electron mobility transistor chip according to an embodiment of the disclosure;

fig. 4 to fig. 10 are schematic diagrams illustrating a manufacturing process of another high electron mobility transistor chip according to an embodiment of the disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a high electron mobility transistor chip according to an embodiment of the present invention, and as shown in fig. 1, the high electron mobility transistor chip according to an embodiment of the present invention includes a substrate 1 and n epitaxial structures 2 stacked on the substrate 1 at intervals, where n is an integer and n is greater than or equal to 2, each epitaxial structure 2 includes an epitaxial layer 21, a source 22, a gate 23, and a drain 24 stacked on the substrate 1, the epitaxial layer 21 includes a dislocation blocking layer 211, a channel layer 212, a cap 213, and an insulating protection layer 214 stacked on the substrate 1 in sequence, an orthogonal projection of the dislocation blocking layer 211 on a surface of the substrate 1 is located in an orthogonal projection of the channel layer 212 on the surface of the substrate 1, the insulating protection layer 214 covers a surface of the channel layer 212 and a partial surface of the cap 213, the gate 23 is located on the insulating protection layer 214 and is in communication with the cap 213, the source 22 and the drain 24 are respectively located at two sides of the gate 23, and both the source 22 and the drain 24 are communicated with the channel layer 212.

The drain 24 of one epitaxial structure 2 of the n epitaxial structures 2 is in communication with the source 22 of the other epitaxial structure 2. The substrate 1 includes an insulating and heat conducting layer 11, an electrically conductive metal layer 12, and a substrate main body 13, which are sequentially stacked in a direction from the substrate 1 toward the epitaxial structure 2. The source 22 of each epitaxial structure 2 is connected to the substrate body 13, and the insulating protective layer 214 of each epitaxial structure 2 extends to the insulating heat conducting layer 11.

The high electron mobility transistor chip comprises a substrate 1 and n epitaxial structures 2 which are stacked on the substrate 1 at intervals, wherein the substrate 1 is used as a growth base of the epitaxial structures 2 to support the epitaxial structures 2. Each epitaxial structure 2 comprises a common epitaxial layer 21, a gate 23, a source 22 and a drain 24. The substrate 1 includes an insulating and heat conducting layer 11, an electrically conductive metal layer 12, and a substrate main body 13, which are sequentially stacked in a direction from the substrate 1 toward the epitaxial structure 2. The insulating protective layer 214 of each epitaxial structure 2 extends to the insulating heat conduction layer 11, the insulating protective layer 214 extending to the insulating heat conduction layer 11 isolates the connection between the epitaxial structures 2, and if the drain electrode 24 of one epitaxial structure 2 in the n epitaxial structures 2 is communicated with the source electrode 22 of the other epitaxial structure 2, the two independent epitaxial structures 2 are interconnected, so that a certain circuit logic is formed in the high-electron-mobility transistor chip. The substrate body 13 in the substrate 1 plays a good role in supporting, and the substrate body 13 can be isolated by the insulating protection layer 214 into n portions corresponding to the n epitaxial structures 2 one by one, and the source 22 in each epitaxial structure 2 can be connected with the corresponding portion of the substrate body 13, so that the back gate effect which may exist in all the epitaxial structures 2 can be well suppressed. And the conductive metal layer 12 can perform the functions of conducting electricity and bonding to the insulating and heat conducting layer 11, so as to facilitate the preparation of the high electron mobility transistor chip. The preparation requirements and the cost of the insulating heat conduction layer 11, the conductive metal layer 12 and the substrate main body 13 are low, the overall cost of the high-electron-mobility transistor chip can be effectively controlled, the conductive metal layer 12 can be used for leading out pins, and the subsequent packaging and other operations of the high-electron-mobility transistor chip can be carried out without additionally stripping the substrate 1 from the high-electron-mobility transistor chip. The preparation procedures of the high electron mobility transistor chip can be reduced, the cost of the finally obtained HEMT can be reduced, and the quality and the performance of the HEMT can be ensured.

Moreover, the insulating heat conduction layer 11 and the conductive metal layer 12 both have good heat dissipation effects, and can also reduce the influence of heat on the service life of the finally obtained high-electron-mobility transistor, thereby prolonging the service life of the finally obtained high-electron-mobility transistor.

It should be noted that, between two epitaxial structures 2, the insulating protective layer 214 plays a role of insulation and isolation, and a part of the insulating protective layer 214 extends to the insulating and heat conducting layer 11 for isolation.

Optionally, the ratio of the thickness of the substrate body 13 to the thickness of the conductive metal layer 12 is 50:1 to 200: 1.

When the ratio of the thickness of the substrate main body 13 to the thickness of the conductive metal layer 12 is within the above range, the substrate main body 13 can realize good support and connection, the conductive metal layer 12 can effectively realize bonding and connection, and the overall manufacturing cost is not very high.

Illustratively, the ratio of the thickness of the conductive metal layer 12 to the thickness of the insulating and heat conducting layer 11 is 1:100 to 1: 200.

When the ratio of the thickness of the conductive metal layer 12 to the thickness of the insulating heat conduction layer 11 is within the above range, the thickness of the insulating heat conduction layer 11 is reasonable, the extension structure 2 can be well supported, heat can be effectively conducted, the cost of the finally obtained high-electron-mobility transistor is controlled to be reasonable, and the service life of the high-electron-mobility transistor is long.

Optionally, the thickness of the substrate main body 13 is 100um to 300um, the thickness of the conductive metal layer 12 is 0.5um to 6um, and the thickness of the insulating and heat conducting layer 11 is 50um to 1200 um.

When the thickness of the substrate main body 13, the thickness of the conductive metal layer 12 and the thickness of the insulating and heat conducting layer 11 are within the above ranges, the preparation cost required for the substrate 1 itself is low, and the method can also be applied to the growth of most epitaxial materials with different thickness specifications. The preparation cost of the HEMT is controlled, and the overall quality of the HEMT is ensured.

Illustratively, the material of the substrate body 13 is one of Si, SiC, and GaN, the conductive metal layer 12 includes a bonding metal portion and a bonding metal portion stacked in sequence in a direction from the substrate toward the epitaxial structure, the material of the bonding metal portion includes one or more of Ti, Ni, Au, Al, and Sn, the material of the bonding metal portion is Au, and the material of the insulating and heat conducting layer 11 is one of high-resistance silicon, aluminum oxide, and aluminum nitride.

The material of the substrate main body 13, the material of the conductive metal layer 12 and the material of the insulating and heat conducting layer 11 are respectively selected from the above materials, so that the preparation cost of the whole substrate 1 is low, the connection condition between the materials is good in the preparation process of the substrate 1, the quality of the substrate 1 is good, and the service life of the whole substrate is long. The high-resistance silicon is a material of the high-resistance silicon substrate.

Optionally, the source 22 of each epitaxial structure 2 is connected to the conductive metal layer 12.

The source electrode 22 of each epitaxial structure 2 is communicated with the conductive metal layer 12, the resistance of the metal is very small, the voltage between the source electrode 22 and the conductive metal layer 12 can be basically kept consistent, the situation that the potential of the source electrode 22 is different from the potential of a grounding point is smaller, and the quality of the finally obtained HEMT can be effectively ensured.

In one implementation provided by the present disclosure, the dislocation blocking layer 211, the channel layer 212, and the cap layer 213 may be a GaN layer, an AlGaN barrier layer, and a GaN cap layer, respectively. And the preparation and the acquisition of the HEMT are facilitated.

In other implementations provided by the present disclosure, the dislocation blocking layer 211, the channel layer 212 and the cap layer 213 may also be made of other different materials, and the epitaxial structure 2 may further include other layers besides the dislocation blocking layer 211, the channel layer 212 and the cap layer 213, such as buffer layers, etc., which is not limited by the present disclosure.

For ease of understanding, the metal material connecting the source 22 and drain 24 is identified as 25.

Fig. 2 is a flowchart of a method for manufacturing a high electron mobility transistor chip according to an embodiment of the present disclosure, where the method for manufacturing a high electron mobility transistor chip is used to manufacture the high electron mobility transistor chip, and the method for manufacturing the high electron mobility transistor chip includes:

s101: a base substrate is provided.

S102: a dislocation blocking layer, a channel layer and a film layer are sequentially grown on a base substrate, and the film layer comprises a plurality of mutually spaced cap layers.

S103: and forming a grid electrode on each cap layer, respectively forming a source electrode and a drain electrode on two sides of each cap layer, and positioning the source electrode and the drain electrode on the channel layer.

S104: forming (n-1) grooves in parallel extending to the base substrate on the channel layer, the (n-1) grooves dividing the channel layer into n independent structures, n being an integer and n being greater than or equal to 2.

S105: connecting grooves extending to the base substrate are formed on each of the individual structures.

S106: and thinning one surface of the base substrate far away from the independent structure to obtain a substrate main body.

S107: and forming a conductive metal layer on one surface of the substrate body far away from the independent structure.

S108: and bonding an insulating heat conduction layer on the conductive metal layer.

S109: the groove extends to the insulating heat conduction layer.

S110: and forming an insulating protection layer on each independent structure, wherein the insulating protection layer covers the surface of the channel layer and part of the surface of the cap layer in each independent structure, and the insulating protection layer of each independent structure extends to the insulating heat conduction layer to obtain n epitaxial structures laminated on the substrate main body.

S111: and communicating the drain electrode of one epitaxial structure in the n epitaxial structures with the source electrode of the other epitaxial structure, wherein the source electrode of the other epitaxial structure is filled with the connecting groove.

The high electron mobility transistor chip comprises a substrate and n epitaxial structures which are mutually spaced and stacked on the substrate, wherein the substrate is used as a growth base of the epitaxial structures and plays a supporting role for the epitaxial structures. Each epitaxial structure includes a common epitaxial layer, a gate, a source, and a drain. In the direction from the substrate to the epitaxial structure, the substrate comprises an insulating heat conduction layer, a conductive metal layer and a substrate main body which are sequentially stacked. The insulating protection layer of each epitaxial structure extends to the insulating heat conduction layer, the insulating protection layer extending to the insulating heat conduction layer isolates the connection between the epitaxial structures, the drain electrode of one epitaxial structure in the n epitaxial structures is communicated with the source electrode of the other epitaxial structure, and then the interconnection between the two mutually independent epitaxial structures is realized, so that certain circuit logic is formed in the high electron mobility transistor chip. The substrate body in the substrate plays a good role in supporting, and communication with each source electrode in the n epitaxial structures can be carried out, and the back gate effect which possibly exists in all the epitaxial structures can be well suppressed. The conductive metal layer can conduct electricity and is bonded to the insulating heat conduction layer, and the preparation of the high-electron-mobility transistor chip is facilitated. The preparation requirements and the cost of the insulating heat conduction layer, the conductive metal layer and the substrate main body are low, the overall cost of the high-electron-mobility transistor chip can be effectively controlled, the conductive metal layer can be used for leading out pins, and the subsequent packaging and other operations of the high-electron-mobility transistor chip can be carried out without additionally stripping the substrate from the high-electron-mobility transistor chip. The preparation procedures of the high electron mobility transistor chip can be reduced, the cost of the finally obtained HEMT can be reduced, and the quality and the performance of the HEMT can be ensured.

In addition, the substrate main body is obtained by thinning the base substrate in the preparation process, so that the cost cannot be greatly increased on the basis of the base substrate. The basic level of the epitaxial structure is obtained by growing on the basis of the basic substrate, the bottom layer quality of the epitaxial structure can be guaranteed to be good, and the quality of the finally obtained epitaxial structure and the HEMT is good. Meanwhile, the depth of the insulating protection layer and the depth of the groove are controlled, the insulating protection layer and the groove are prepared after the conductive metal layer and the insulating heat conduction layer are formed, the substrate is basically formed at the moment, the insulating protection layer and the groove only need to be locally operated to obtain a final HEMT chip, the operation required by the whole HEMT chip in the preparation process is small, and the whole preparation cost is low.

Fig. 3 is a flowchart of another method for manufacturing a high electron mobility transistor chip according to an embodiment of the disclosure, and referring to fig. 3, the method includes:

s201: a base substrate is provided.

Illustratively, the base substrate may be a common silicon substrate. Is convenient for preparation and acquisition.

S202: a dislocation blocking layer, a channel layer and a film layer are sequentially grown on a base substrate, and the film layer comprises a plurality of mutually spaced cap layers.

In step S202, the dislocation blocking layer and the channel layer may be grown by a metal organic vapor deposition apparatus.

In step S202, the forming of the film layer may include: forming a base layer on the channel layer; and etching a plurality of mutually spaced cap layers on the base layer by using a photoetching process to obtain the film layer. The preparation of the cap layer is convenient, and the preparation steps required by the whole process are fewer.

S203: and forming a grid electrode on each cap layer, respectively forming a source electrode and a drain electrode on two sides of each cap layer, and positioning the source electrode and the drain electrode on the channel layer.

The gate, the source and the drain may be formed by photolithography.

Illustratively, the forming of, for example, a gate electrode, includes: coating photoresist on the surface of a structure grown on a base substrate; forming a through hole corresponding to the grid on the photoresist, wherein the through hole is communicated with the cap layer; evaporating a grid into the through hole; and removing the photoresist. Thereby obtaining the grid electrode. The formation process of the source and the drain is similar to that of the gate, and therefore, the detailed description thereof is omitted.

The gate, source and drain are formed prior to using the recess to divide the structure grown on the base substrate. The photoresist and part of metal can be prevented from being filled in the groove in the process of preparing the grid electrode after the groove. The preparation process of the whole HEMT is simple.

To facilitate understanding, FIG. 4 is provided herein, and with reference to FIG. 4, a blocking layer 211, a channel layer 212, and a plurality of spaced apart capping layers 213 are grown on base substrate 100; the source 22, gate 23 and drain 24 are also fabricated.

S204: forming (n-1) grooves in parallel extending to the base substrate on the channel layer, the (n-1) grooves dividing the channel layer into n independent structures, n being an integer and n being greater than or equal to 2.

It should be noted that the grooves may be formed by etching or etching. The present disclosure is not so limited.

S205: connecting grooves extending to the base substrate are formed on each of the individual structures.

The connection trenches are used for connection between the source 22 and the substrate.

S206: and covering a passivation layer on the surface of each independent structure far away from the base substrate, wherein holes for exposing the surface of the source electrode, the surface of the grid electrode and the surface of the drain electrode are reserved on the passivation layer.

The addition of the passivation layer can effectively protect the surface of the base substrate and reduce the influence of the thinning of the subsequent base substrate on the epitaxial material.

Optionally, the thickness of the passivation layer is 1um to 8 um.

The thickness of the passivation layer is within the range, so that the interior of the epitaxial material can be effectively protected, and meanwhile, the integral cost of the HEMT can not be greatly improved.

Illustratively, the material of the passivation layer is silicon oxide or silicon nitride. Is convenient to prepare and obtain and has good protection effect.

For ease of understanding, the structure after performing steps S204 to S206 may refer to fig. 5, in which the groove S1 extends from the channel layer 212 to the surface of the base substrate 100, and the connection groove S2 extends from the channel layer 212 to the surface of the base substrate 100. The passivation layer 200 covers the surface of the epitaxial material grown on the base substrate 100, and the source electrode 22, the gate electrode 23 and the drain electrode 24 are exposed by the via hole on the passivation layer 200.

S207: and thinning one surface of the base substrate far away from the independent structure to obtain a substrate main body.

Alternatively, the base substrate may be thinned by a chemical mechanical polishing process. The surface quality of the obtained substrate main body is better.

The structure after thinning of the base substrate can be seen in fig. 6, the base substrate being thinned to obtain the substrate body 13.

S208: and forming a conductive metal layer on one surface of the substrate body far away from the independent structure.

The conductive metal layer may be obtained by magnetron sputtering. A conductive metal layer of better quality can be obtained.

S209: and bonding an insulating heat conduction layer on the conductive metal layer.

The conductive metal layer and the insulating heat conduction layer can be connected through bonding. The preparation process is simple while the connection quality of the two is ensured.

Illustratively, the bonding pressure of the conductive metal layer and the insulating and heat conducting layer is 900-1100 kg; the bonding temperature of the conductive metal layer and the insulating heat conduction layer is 200-300 ℃. The connection quality of the conductive metal layer and the insulating heat-conducting layer can be better, and the integral connection interface is smoother.

For the sake of understanding, referring to fig. 7, the structure after steps S208 to S209 are performed is that the substrate main body 13 is formed with the conductive metal cart 12 and the insulating and heat conducting layer 11.

S210: the groove extends to the insulating heat conduction layer.

The grooves extending to the insulating heat conducting layer can be obtained by etching.

The structure after step S210 is completed can refer to fig. 8, and the groove S1 extends to the insulating and heat conducting layer 11.

S211: and forming an insulating protection layer on each independent structure, wherein the insulating protection layer covers the surface of the channel layer and part of the surface of the cap layer in each independent structure, and the insulating protection layer fills the groove to obtain n epitaxial structures laminated on the substrate main body.

It should be noted that the insulating protection layer does not fill the connection groove in step S211. The material of the insulating protective layer can be the same as that of the passivation layer, and the passivation layer and the insulating protective layer are overlapped to form the final insulating protective layer.

S212: the connecting trenches are extended to the surface of the conductive metal layer.

In step S212, the original positions of the connection grooves may be etched to obtain the connection grooves extending to the surface of the conductive metal layer.

After the step S212 is performed, referring to fig. 9, the groove S1 is filled with the insulating protection layer 214, the insulating protection layer 214 covers most of the surface of the epitaxial structure 2, and the connecting groove S2 extends to the surface of the conductive metal layer 12.

S213: and communicating the drain electrode of one epitaxial structure in the n epitaxial structures with the source electrode of the other epitaxial structure, wherein the source electrode of the other epitaxial structure is filled with the connecting groove.

Communicating the drain of one of the n epitaxial structures with the source of the other epitaxial structure may be accomplished by depositing a metal material between the source and the drain. Is convenient for preparation. The shape of the metal material can be obtained by matching with a photoetching process.

The structure of the HEMT chip after step S213 is performed can be referred to fig. 10.

The invention is not to be considered as limited to the particular embodiments shown and described, but is to be understood that various modifications, equivalents, improvements and the like can be made without departing from the spirit and scope of the invention.