阅读说明：本技术 阵列基板及其制作方法 (Array substrate and manufacturing method thereof ) 是由 赵玲 张伟闵 肖军城 于 2021-08-09 设计创作，主要内容包括：本发明提供一种阵列基板及其制作方法。阵列基板包括衬底基板层、第一走线层、绝缘层以及应力平衡层；所述第一走线层设于所述衬底基板层上；所述第一走线层包括第一走线；所述绝缘层设于所述第一走线层上且覆盖在所述第一走线上方；所述应力平衡层设于所述绝缘层上方且围绕所述衬底基板层边缘,其中,所述应力平衡层的边缘与所述衬底基板层的所述边缘切齐,所述应力平衡层具有与所述第一走线方向相反的弯曲应力,所述应力平衡层弯曲的曲率小于1.2mm/m。本发明通过在间隔区、边框区或第一走线和/或第二走线上设置应力平衡层,利用应力平衡层材质的压应力平衡走线的拉翘应力,改善阵列基板在制备过程中的翘曲破片问题。(The invention provides an array substrate and a manufacturing method thereof. The array substrate comprises a substrate layer, a first wiring layer, an insulating layer and a stress balance layer; the first wiring layer is arranged on the substrate layer; the first routing layer comprises a first routing; the insulating layer is arranged on the first wiring layer and covers the first wiring; the stress balance layer is arranged above the insulating layer and surrounds the edge of the substrate layer, wherein the edge of the stress balance layer is flush with the edge of the substrate layer, the stress balance layer has bending stress opposite to the first wiring direction, and the bending curvature of the stress balance layer is smaller than 1.2 mm/m. According to the invention, the stress balance layer is arranged on the spacer area, the frame area or the first routing and/or the second routing, and the tensile stress of the routing is balanced by utilizing the compressive stress of the material of the stress balance layer, so that the problem of warping and breaking of the array substrate in the preparation process is solved.)

1. An array substrate, comprising:

a substrate layer;

the first wiring layer is arranged on the substrate base layer; the first routing layer comprises a first routing;

the insulating layer is arranged on the first wiring layer and covers the first wiring; and

the stress balance layer is arranged above the insulating layer and surrounds the edge of the substrate layer, wherein the edge of the stress balance layer is flush with the edge of the substrate layer, the stress balance layer has bending stress opposite to the first wiring direction, and the bending curvature of the stress balance layer is smaller than 1.2 mm/m.

2. The array substrate of claim 1, wherein the material of the first trace layer comprises copper, and the thickness of the first trace is greater than or equal to 5500 angstroms; the stress balance layer is made of any one of arsenic, polysilicon, SINx, SiQx and IGZO; the stress-balancing layer has a thickness greater than or equal to 900 angstroms.

3. The array substrate of claim 1, wherein the stress balance layer covers the first trace.

4. The array substrate of claim 3, wherein the array substrate is divided into a display area and a frame area surrounding the display area, and the stress balance layer is disposed in the frame area.

5. The array substrate of claim 1, further comprising:

the second routing layer is arranged on the stress balance layer; and

and the passivation layer is arranged on the second routing layer.

6. The manufacturing method of the array substrate is characterized by comprising the following steps:

manufacturing a plurality of groups of same first routing layer patterns on a substrate layer, wherein each group of first routing layer patterns comprises first routing, and the plurality of groups of first routing layer patterns are arranged in an array and spaced from each other on the substrate layer;

manufacturing an insulating layer to cover the plurality of groups of first routing layer patterns and the substrate base layer;

manufacturing a stress balance layer on the insulating layer, wherein the stress balance layer covers the interval regions among the multiple groups of first routing layer patterns; the stress balance layer has bending stress opposite to the first routing direction, and the curvature of the bending of the stress balance layer is less than 1.2 mm/m; and

and cutting the substrate layer along the spacing area to form a plurality of array substrates.

7. The method for manufacturing the array substrate of claim 6, wherein the material of the first trace layer pattern comprises copper, and the thickness of the first trace is greater than or equal to 5500 angstroms; the stress balance layer is made of any one of arsenic, polysilicon, SINx, SiQx and IGZO; the stress-balancing layer has a thickness greater than or equal to 900 angstroms.

8. The method for manufacturing the array substrate according to claim 6, wherein the stress balance layer covers the first trace.

9. The manufacturing method of the array substrate is characterized by comprising the following steps:

manufacturing a plurality of groups of same first routing layer patterns on a substrate layer, wherein each group of first routing layer patterns comprises first routing, and the plurality of groups of first routing layer patterns are arranged in an array and spaced from each other on the substrate layer;

manufacturing an insulating layer to cover the plurality of groups of first routing layer patterns and the substrate base layer;

manufacturing a stress balance layer on the insulating layer, wherein the stress balance layer covers the interval regions among the multiple groups of first routing layer patterns; the stress balance layer has bending stress opposite to the first routing direction, and the curvature of the bending of the stress balance layer is less than 1.2 mm/m;

manufacturing a second routing layer pattern which is arranged on the stress balance layer;

manufacturing a passivation layer arranged on the second routing layer pattern; and

and cutting the substrate layer along the spacing area to form a plurality of array substrates.

10. The method for manufacturing the array substrate according to claim 9, wherein the array substrate is divided into a display area and a frame area surrounding the display area, and the stress balance layer covers the frame area from the spacing area.

Technical Field

The invention relates to the field of display, in particular to an array substrate and a manufacturing method thereof.

Background

With the progress of science and technology and the development of times, people have higher and higher requirements on mobile phone display screens. Currently mainstream hard screen displays have failed to meet market demands.

In the prior art, an array substrate includes conductive layer structures such as data lines or gate lines, and in order to improve a Charge Ratio (CR) to reduce capacitance delay, current 8K display device products need to use a thicker conductive material to prepare the conductive layer structures such as the data lines or the gate lines, and the thicker the adopted material is, the greater the stress is, which causes that glass for preparing the array substrate is easily subjected to tensile stress of the conductive layer structures such as the data lines or the gate lines and warped or even broken in a display area or an edge area.

Therefore, when the conductive layer structures such as data lines or gate lines are manufactured, the problem of array substrate warpage and even fragment caused by the tensile stress of the material needs to be solved urgently.

Disclosure of Invention

The invention aims to provide an array substrate and a manufacturing method thereof, which are used for solving the technical problem of array substrate warping and even chipping caused by tensile stress of materials when conducting layer structures such as data lines or gate lines are prepared.

In order to solve the above problems, an embodiment of the present invention provides an array substrate, including a substrate layer, a first wiring layer, an insulating layer, and a stress balance layer; the first wiring layer is arranged on the substrate layer; the first routing layer comprises a first routing; the insulating layer is arranged on the first wiring layer and covers the first wiring; the stress balance layer is arranged above the insulating layer and surrounds the edge of the substrate layer, wherein the edge of the stress balance layer is flush with the edge of the substrate layer, the stress balance layer has bending stress opposite to the first wiring direction, and the bending curvature of the stress balance layer is smaller than 1.2 mm/m.

In an embodiment of the array substrate, a material of the first trace layer includes copper, and a thickness of the first trace is greater than or equal to 5500 angstroms; the stress balance layer is made of any one of arsenic, polysilicon, SINx, SiQx and IGZO; the stress-balancing layer has a thickness greater than or equal to 900 angstroms.

In an embodiment of the array substrate, the stress balance layer covers the first trace.

In an embodiment of the present application, the array substrate is divided into a display area and a frame area surrounding the display area, and the stress balance layer is disposed in the frame area.

In an embodiment of the present invention, the array substrate further includes a second routing layer and a passivation layer; the second routing layer is arranged on the stress balance layer; the passivation layer is arranged on the second routing layer.

In another embodiment of the present invention, a method for manufacturing an array substrate is provided, including the following steps:

manufacturing a plurality of groups of same first routing layer patterns on a substrate layer, wherein each group of first routing layer patterns comprises first routing, and the plurality of groups of first routing layer patterns are arranged in an array and spaced from each other on the substrate layer;

manufacturing an insulating layer to cover the plurality of groups of first routing layer patterns and the substrate base layer;

manufacturing a stress balance layer on the insulating layer, wherein the stress balance layer covers the interval regions among the multiple groups of first routing layer patterns; the stress balance layer has bending stress opposite to the first routing direction, and the curvature of the bending of the stress balance layer is less than 1.2 mm/m; and

and cutting the substrate layer along the spacing area to form a plurality of array substrates.

In an embodiment of the present invention, a material of the first trace layer pattern includes copper, and a thickness of the first trace is greater than or equal to 5500 angstroms; the stress balance layer is made of any one of arsenic, polysilicon, SINx, SiQx and IGZO; the stress-balancing layer has a thickness greater than or equal to 900 angstroms.

In an embodiment of the present invention, the stress balance layer covers the first trace.

The application also provides a manufacturing method of the array substrate, which comprises the following steps:

manufacturing a plurality of groups of same first routing layer patterns on a substrate layer, wherein each group of first routing layer patterns comprises first routing, and the plurality of groups of first routing layer patterns are arranged in an array and spaced from each other on the substrate layer;

manufacturing an insulating layer to cover the plurality of groups of first routing layer patterns and the substrate base layer;

manufacturing a stress balance layer on the insulating layer, wherein the stress balance layer covers the interval regions among the multiple groups of first routing layer patterns; the stress balance layer has bending stress opposite to the first routing direction, and the curvature of the bending of the stress balance layer is less than 1.2 mm/m;

manufacturing a second routing layer pattern which is arranged on the stress balance layer;

manufacturing a passivation layer arranged on the second routing layer pattern; and

and cutting the substrate layer along the spacing area to form a plurality of array substrates.

In an embodiment of the present application, the array substrate is divided into a display area and a frame area surrounding the display area, and the stress balance layer covers the frame area from the spacer area.

The array substrate and the manufacturing method thereof have the beneficial effects that the stress balance layer is arranged on the interval area, the frame area or the first routing and/or the second routing, the tensile stress of the routing is balanced by utilizing the compressive stress of the material of the stress balance layer, and the warping and breaking problems of the array substrate in the preparation process are improved.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1a is a schematic cross-sectional view of an array substrate according to an embodiment of the invention;

fig. 1b is a schematic top view of an array substrate according to an embodiment of the invention;

FIG. 2 is a schematic cross-sectional view of another array substrate according to an embodiment of the invention;

FIG. 3 is a schematic diagram of a planar structure of a large plate structure before being cut into a small plate structure to form an array substrate according to an embodiment of the present invention;

fig. 4 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention.

Fig. 5 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the invention.

The components in the figure are identified as follows:

a substrate base layer 1, a first wiring layer 2, an insulating layer 3,

a stress balance layer 4, a second routing layer 5, a passivation layer 6,

an array substrate 10, a large plate structure 11, a small plate structure 12,

the first trace 21, the display area 101, the frame area 102,

a gap region 103.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1a, fig. 1b and fig. 2, an array substrate 10 is provided in one embodiment of the present invention; the array substrate 10 comprises a substrate layer 1, a first routing layer 2, an insulating layer 3 and a stress balance layer 4; the first wiring layer 2 is arranged on the substrate base layer 1; the first wire layer 2 comprises a first wire 21; the insulating layer 3 is arranged on the first routing layer 2 and covers the first routing 21; the stress balance layer 4 is arranged above the insulating layer 3 and surrounds the edge of the substrate layer 1, wherein the edge of the stress balance layer 4 is aligned with the edge of the substrate layer 1; the direction of the bending stress of the stress balance layer 4 is opposite to that of the first routing wire 21, and the curvature of the bending stress of the stress balance layer 4 is smaller than 1.2mm/m, so that the bending stress is mutually offset, and the prepared array substrate 10 is ensured to be a straight structure.

In an embodiment of the present application, the substrate layer 1 is preferably a glass substrate or a structure including a glass substrate. The material of the first trace 21 includes copper (Cu), a thickness Dm of the first trace 21 is greater than or equal to 5500 angstroms, and preferably Dm is 5500 angstroms to 15500 angstroms; the material of the insulating layer 3 comprises silicon oxide and/or silicon nitride; the stress balance layer 4 is made of any one of arsenic, polysilicon, SINx, SiQx and IGZO; the thickness Da of the stress-balancing layer 4 is greater than or equal to 900 angstroms, preferably Da is 900 angstroms to 5600 angstroms. The stress balance layer 4 covers the first trace 21. When the stress balance layer 4 is made of any one of polysilicon, SINx, SiQx and IGZO, the H content in the deposited polysilicon, SINx, SiQx and IGZO formed stress balance layer 4 is lower than the H content in the case of preparing a semiconductor layer with the same material to form an active layer structure, specifically, the temperature, the H content and the nitrogen-silicon ratio in the preparation process are adjusted to make the formed film layer be compressive stress, for example, SiH is reduced₄Flow rate, reduction of NH₃Flow, increase N₂And (4) flow rate. At present, the warpage of the stress balance layer 4 is controlled below 1.2mm, and the warpage (i.e. curvature) of the stress balance layer 4 is specifically determined according to the toughness of the glass substrate in the substrate layer 1 and the processing equipment.

As shown in fig. 1a and fig. 2, preferably, the first trace 21 is a gate trace (scan line), and the insulating layer 3 is a gate insulating layer. Referring to fig. 3, it is preferable that a plurality of small plate structures 12 are included in a large plate structure 11 for manufacturing an array substrate 10, each small plate structure 12 is cut to form the array substrate 10 with a complete driving function, the array substrate 10 of each small plate structure 12 includes a display area 101 and a frame area 102 disposed around the display area 101, a gap area 103 is disposed at an edge position between two adjacent small plate structures 12, and the large plate structure 11 forms a plurality of small plate structures 12 by cutting at the gap area 103 position. Wherein the stress balance layer 4 is disposed in the frame region 102.

Since the first trace 21 is made of copper, the principle that the array substrate is warped due to the copper tensile stress is analyzed as follows: after the first wire 21 is formed by a Physical Vapor Deposition (PVD) method and a copper material, a thin film of the first wire 21 and the substrate layer 1 are transferred from a hot state to a cold state by patterning, the substrate layer 1 contains glass, the thermal expansion coefficient of the glass is smaller than that of copper, which causes tensile stress of the first wire 21 to the substrate layer 1, so that two ends of the substrate layer 1 are tilted upwards and bent, and even glass in the substrate layer 1 is broken when the stress is too large. Moreover, the thicker the film layer of the first trace 21 is, the greater the stress is, so that no matter the display area 10 or the frame area 102 of the glass for manufacturing the array substrate is easily warped or even broken due to the tensile stress of the first trace 21. Therefore, the stress balance layer 4 is arranged on the first routing wire 21, the tensile stress of the first routing wire 21 is balanced by the compressive stress of the material of the stress balance layer 4, and the problem of warping and breaking of the large plate structure 11 of the array substrate 10 in the preparation process is solved.

Referring to fig. 2, in an embodiment of the present invention, the array substrate 10 further includes a second routing layer 5 and a passivation layer 6; the second routing layer 5 is arranged on the stress balance layer 4; the second routing layer 5 is arranged corresponding to the first routing layer 2; the passivation layer 6 is disposed on the insulating layer 3 and covers the second wiring layer 5. Preferably, the second wiring layer 5 is a source/drain wiring (data line). The material of second routing layer 5 includes copper, and the thickness of second routing layer 5 is greater than or equal to 5500 angstroms, preferably 5500 angstroms to 15500 angstroms.

It can be understood that another stress balance layer may be disposed on the passivation layer 6 corresponding to the second routing layer 5, and the two stress balance layers may effectively increase the stress balance effect on the array substrate, thereby effectively improving the warpage and fragment problem of the array substrate in the preparation process.

Referring to fig. 4 in combination with fig. 1a to fig. 3, an embodiment of the invention provides a method for manufacturing an array substrate, including the following steps S11 to S16:

s11, a step of fabricating first routing layers, in which multiple sets of the same first routing layer 2 patterns are fabricated on a substrate layer 1 (large board structure 11), each set of the first routing layer 2 patterns includes a first routing 21, and the multiple sets of the first routing layer 2 patterns are arranged in an array and spaced from each other on the substrate layer 1;

s12, manufacturing an insulating layer, namely manufacturing an insulating layer 3 to cover the patterns of the multiple groups of first wiring layer 2 and the substrate base plate layer 1;

s13, a step of forming a stress balance layer, wherein a stress balance layer 4 is formed on the insulating layer 3, and the stress balance layer 4 covers the spacers 103 between the plurality of patterns of the first wiring layer 2; when the stress balance layer 4 is made of any one of polysilicon, SINx, SiQx and IGZO, the H content in the deposited polysilicon, SINx, SiQx and IGZO formed stress balance layer 4 is lower than the H content in the case of preparing a semiconductor layer with the same material to form an active layer structure, specifically, the temperature, the H content and the nitrogen-silicon ratio in the preparation process are adjusted to make the formed film layer be compressive stress, for example, SiH is reduced₄Flow rate, reduction of NH₃Flow, increase N₂Flow rate; at present, the warpage of the stress balance layer 4 is stuck and controlled below 1.2mm, and the warpage (i.e. curvature) of the stress balance layer 4 is specifically determined according to the toughness of a glass substrate in the substrate layer 1 and processing equipment; and

and S14, cutting to form an array substrate, namely cutting the substrate layer 1 (large plate structure 11) along the spacing area 103 to form a plurality of array substrates 10.

Referring to fig. 5 in combination with fig. 1a to fig. 3, a method for fabricating an array substrate according to another embodiment of the present invention includes the following steps S21 to S26:

s21, a step of fabricating first routing layers, in which multiple sets of the same first routing layer 2 patterns are fabricated on a substrate layer 1 (large board structure 11), each set of the first routing layer 2 patterns includes a first routing 21, and the multiple sets of the first routing layer 2 patterns are arranged in an array and spaced from each other on the substrate layer 1;

s22, manufacturing an insulating layer, namely manufacturing an insulating layer 3 to cover the patterns of the multiple groups of first wiring layer 2 and the substrate base plate layer 1;

s23, a step of forming a stress balance layer, wherein a stress balance layer 4 is formed on the insulating layer 3, and the stress balance layer 4 covers the spacers 103 between the plurality of patterns of the first wiring layer 2;

s24, a step of manufacturing a second routing layer, namely manufacturing a second routing layer 5 pattern which is arranged on the stress balance layer 4;

s25, manufacturing a passivation layer, namely manufacturing a passivation layer 6 which is arranged on the second routing layer 5 pattern; and

and S26, cutting to form an array substrate, namely cutting the substrate layer 1 (large plate structure 11) along the spacing area 103 to form a plurality of array substrates 10.

In the cut array substrate 10, the stress balance layer 4 is arranged above the insulating layer 3 and surrounds the edge of the substrate layer 1, wherein the edge of the stress balance layer 4 is aligned with the edge of the substrate layer 1; the direction of the bending stress of the stress balance layer 4 is opposite to that of the first routing line 21, so that the bending stresses are mutually offset, and the prepared array substrate 10 is ensured to be a straight structure.

In an embodiment of the present application, the substrate layer 1 is preferably a glass substrate or a structure including a glass substrate. The material of the first trace 21 includes copper (Cu), a thickness Dm of the first trace 21 is greater than or equal to 5500 angstroms, and preferably Dm is 5500 angstroms to 15500 angstroms; the material of the insulating layer 3 comprises silicon oxide and/or silicon nitride; the thickness Da of the stress-balancing layer 4 is greater than or equal to 900 angstroms, preferably Da is 900 angstroms to 5600 angstroms. The stress balance layer 4 covers the first trace 21. When the stress balance layer 4 is made of any one of polysilicon, SINx, SiQx and IGZO, the H content in the deposited polysilicon, SINx, SiQx and IGZO formed stress balance layer 4 is lower than the H content in the case of preparing a semiconductor layer with the same material to form an active layer structure, specifically, the temperature, the H content and the nitrogen-silicon ratio in the preparation process are adjusted to make the formed film layer be compressive stress, for example, SiH is reduced₄Flow rate, reduction of NH₃Flow, increase N₂And (4) flow rate. The warpage of the stress balance layer 4 is controlled to be 1.2mm at presentIn the following, the warpage (i.e. curvature) of the stress balance layer 4 is specifically determined according to the toughness of the glass substrate in the substrate layer 1 and the processing equipment.

Referring to fig. 3, a plurality of small plate structures 12 are included in a large plate structure 11 before the array substrate 10 is cut and manufactured, each small plate structure 12 is cut to form the array substrate 10 with a complete driving function, the array substrate 10 of each small plate structure 12 includes a display area 101 and a frame area 102 surrounding the display area 101, a gap area 103 is disposed at an edge position between two adjacent small plate structures 12, and the large plate structure 11 forms a plurality of small plate structures 12 by cutting at the gap area 103 position and cutting. Wherein the stress balance layer 4 is disposed in the frame region 102.

Since the first trace 21 is made of copper, the principle that the array substrate is warped due to the copper tensile stress is analyzed as follows: after the first wire 21 is formed by a Physical Vapor Deposition (PVD) method and a copper material, a thin film of the first wire 21 and the substrate layer 1 are transferred from a hot state to a cold state by patterning, the substrate layer 1 contains glass, the thermal expansion coefficient of the glass is smaller than that of copper, which causes tensile stress of the first wire 21 to the substrate layer 1, so that two ends of the substrate layer 1 are tilted upwards and bent, and even glass in the substrate layer 1 is broken when the stress is too large. Moreover, the thicker the film layer of the first trace 21 is, the greater the stress is, so that no matter the display area 101 or the frame area 102 of the glass for preparing the array substrate 10 is easily warped or even broken due to the tensile stress of the first trace 21. Therefore, the stress balance layer 4 is arranged on the first routing wire 21, the tensile stress of the first routing wire 21 is balanced by the compressive stress of the material of the stress balance layer 4, and the problem of warping and breaking of the large plate structure 11 of the array substrate 10 in the preparation process is solved.

It can be understood that another stress balance layer may be disposed on the passivation layer 6 corresponding to the second routing layer 5, and the two stress balance layers can effectively increase the stress balance effect on the array substrate 10, and effectively improve the problem of warpage and fragment of the large plate structure 11 in the manufacturing process of the array substrate 10.

The array substrate and the manufacturing method thereof have the beneficial effects that the stress balance layer is arranged on the interval area, the frame area or the first routing and/or the second routing, and the warping and breaking problems of the array substrate in the preparation process are improved by utilizing the tensile stress balanced by the compressive stress of the material of the stress balance layer.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.