阅读说明：本技术 闪存阵列的擦除方法 (Erasing method of flash memory array ) 是由 蒋家勇 石振东 于 2021-08-26 设计创作，主要内容包括：本公开提供了一种闪存阵列的擦除方法。该闪存阵列包括：多个闪存单元,沿行方向和列方向排列；多个字线组,沿行方向延伸；以及多个位线组,沿列方向延伸；在字线组和位线组的交点处设置有闪存单元对,其包括在行方向上相邻的共享同一个位线组的第一闪存单元和第二闪存单元。根据本公开的擦除方法包括将各擦除电压施加到被选中的闪存单元的第一和第二电极以及晶体管的栅电极,其中施加到与被擦除的存储晶体管连接的电极的擦除电压高于衬底与存储晶体管的栅介质叠层之间的界面处的空穴势垒高度。本公开的闪存阵列的擦除方法能够改善阈值电压窗口并且提高存储可靠性,同时还具有操作功耗低和擦除速度快的优点。(The present disclosure provides a method of erasing a flash memory array. The flash memory array includes: a plurality of flash memory cells arranged in a row direction and a column direction; a plurality of word line groups extending in a row direction; and a plurality of bit line groups extending in a column direction; at the intersections of the word line groups and the bit line groups, flash memory cell pairs are provided, which include first and second flash memory cells sharing the same bit line group that are adjacent in the row direction. An erase method according to the present disclosure includes applying erase voltages to first and second electrodes of a selected flash memory cell and a gate electrode of a transistor, wherein the erase voltage applied to an electrode connected to the memory transistor being erased is higher than a hole barrier height at an interface between a substrate and a gate dielectric stack of the memory transistor. The erasing method of the flash memory array can improve the threshold voltage window and improve the storage reliability, and meanwhile has the advantages of low operation power consumption and high erasing speed.)

1. A method of erasing a flash memory array, the flash memory array comprising:

a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction;

a plurality of word line groups extending in the row direction; and

a plurality of bit line groups extending in the column direction,

wherein a flash memory cell pair is provided at an intersection of the word line group and the bit line group, the flash memory cell pair including a first flash memory cell and a second flash memory cell sharing the same bit line group which are adjacent in the row direction,

wherein each of the first flash memory cell and the second flash memory cell includes a first storage transistor, a gating transistor, and a second storage transistor sequentially connected in series in the column direction,

wherein in each of the first flash memory cell and the second flash memory cell, a source region of the first memory transistor is connected to a first electrode of the flash memory cell, a drain region of the second memory transistor is connected to a second electrode of the flash memory cell,

wherein each set of bit lines comprises a first bit line connected to the first electrode of a first flash memory cell of the pair of flash memory cells, an intermediate bit line connected to the second electrode of a second flash memory cell of the pair of flash memory cells, and a second bit line connecting the second electrode of the first flash memory cell and the first electrode of the second flash memory cell, and

wherein each bit line group includes a first control line connected to the gate electrode of the first memory transistor, a word line connected to the gate electrode of the gating transistor, and a second control line connected to the gate electrode of the second memory transistor,

the erasing method includes a first erasing step of:

performing an erase operation on first memory transistors of the first and second flash memory cells by applying a first erase voltage to the first bit line, the middle bit line, and the second bit line, applying a second erase voltage to the first control line, applying a second power supply voltage to the word line and the second control line, or floating the word line and the second control line;

performing an erase operation on second memory transistors of the first and second flash memory cells by applying the first erase voltage to the first bit line, the middle bit line, and the second bit line, applying the second power supply voltage to the word line and the first control line, or floating the word line and the first control line, applying the second erase voltage to the second control line;

wherein the first erasing voltage is higher than a preset voltage, the second erasing voltage is equal to or lower than the second power supply voltage, an

Wherein the preset voltage is preset according to a carrier barrier height at an interface between the substrate and the gate dielectric stack of the first storage transistor and the second storage transistor.

2. The erasing method according to claim 1,

the second power supply voltage is a ground voltage,

the first erasing voltage is in a range of 3V to 6V, an

The second erase voltage is in a range of-8V to 0V.

3. The erasing method of claim 1, further comprising a second erasing step of:

applying the second erase voltage to the first control line and the second control line by applying the first erase voltage to the first bit line, the middle bit line, and the second bit line, applying the second power supply voltage to the word line or floating the word line while performing an erase operation on the first flash memory cell and the second flash memory cell.

4. The erasing method according to claim 1 or 3,

during an erase operation of the flash memory cell, performing an erase operation on the first storage transistor or the second storage transistor through a band-to-band tunneling hot carrier injection mechanism.

5. The erasing method of claim 1, further comprising a third erasing step of:

applying a second power supply voltage to the word line or floating the word line while performing an erase operation on the first flash memory cell and the second flash memory cell by applying a second erase voltage to the substrate of the flash memory array, the first bit line, the middle bit line, and the second bit line, applying a second erase voltage to the first control line and the second control line, applying a second power supply voltage to the word line, or floating the word line,

wherein the third erase voltage is in a range of 0V to 20V, and the fourth erase voltage is in a range of-10V to 0V.

6. The erasing method according to claim 5,

performing an erase operation on the first memory transistor or the second memory transistor by a Fowler-Nordheim tunneling mechanism during an erase operation of the flash memory cell.

7. The erasing method of claim 5, further comprising:

firstly, the erasing operation is carried out on the whole flash memory array through the third erasing step, and then, the erasing operation is carried out on a part of flash memory units in the flash memory array through the first erasing step or the second erasing step.

8. The erasing method according to claim 5,

the third erase voltage is the same as or different from the first erase voltage; and

the fourth erase voltage is the same as or different from the second erase voltage.

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to an erase method for a flash memory array.

Background

Flash memory, flash memory for short, is a non-volatile memory, i.e. the stored data will not be lost even if the power is off, especially suitable for the fields of mobile communication and computer memory parts. In addition, some flash memories also have high-density storage capability, and are suitable for applications in large-capacity mobile storage media and the like.

Conventional flash memories employ a floating gate type cell structure. The floating gate type nonvolatile memory originates from a MIMIS (Metal-Insulator-Semiconductor) structure proposed by d.kahng and s.sze in 1967. The structure is additionally provided with a Metal floating gate and an ultrathin tunneling Oxide layer on the basis of a traditional Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), so that charges are stored by utilizing the Metal floating gate. Based on this, Masuoka et al first proposed the concept of Flash Memory in 1984, namely, to implement high-speed erase capability by erasing erase bits by blocks (sectors) and to eliminate the necessary select pipes in EEPROM (Erasable Programmable Read-only Memory) so as to have a smaller Memory cell size. With the advent of flash memory, flash memory has rapidly been developed with its high erase speed, high integration, and superior performance. An ETOX flash memory cell (Electron Tunneling Oxide device) is proposed by Intel corporation in 1988, and becomes the basis of most floating gate type flash memory cell structures so far.

However, the floating gate type flash memory has the following disadvantages: the process is relatively complex; the existence of the floating gate structure in the flash memory unit increases the longitudinal height of the gate structure, which is not beneficial to reducing the process size and the unit area in proportion; meanwhile, because of the conductivity of the floating gate, the stored charges can move freely in the floating gate, which is not favorable for improving the reliability of the memory. In order to solve the problems of complex process, poor reliability and the like of the floating gate type flash Memory, researchers propose a Charge-Trapping-Memory (CTM) which stores charges by using a Silicon Nitride medium and is also called a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) type flash Memory. Based on this, b.eitan et al proposed a two-bit Memory cell structure NROM (Nitride-Read-Only-Memory) in 2000, but the structure has the disadvantages that two Memory bits (i.e. two Memory transistors) interfere with each other, and the device size cannot be reduced.

However, the conventional floating gate ETOX flash memory and SONOS NROM flash memory have the problems that the process size cannot be reduced, the cell area is large, the erase power consumption is large, and the array area overhead is large, and cannot realize high-density integration above gigabit (Gb) capacity.

In addition, existing flash memory arrays require bit lines, word lines, and source lines to be provided to enable selection and operation of the flash memory cells. However, the source lines of the conventional flash memory array are formed in the active region, and the sheet resistance of the active region is much higher than that of metal. Therefore, to reduce the series resistance of the source lines, active area source lines need to be shorted together by a common source line of metal every several rows or columns in the row direction or the column direction, resulting in an increase in area overhead of the flash memory array.

With the rapid development of applications such as mobile intelligent terminals, wearable devices, and intelligent sensor networks, higher requirements are put forward on power consumption, storage capacity, and cost of flash memories, and therefore a flash memory technology with the advantages of low power consumption, small unit area, small process size, high array integration density, large capacity, and the like is required.

Disclosure of Invention

The above information disclosed in this background section is only for background understanding of the inventive concept and therefore it may contain information that does not constitute prior art.

In order to solve the above problems in the prior art, the present disclosure provides an erasing method of a flash memory array.

According to one aspect of the present disclosure, a method of erasing a flash memory array is provided. The flash memory array includes: a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction; a plurality of word line groups extending in a row direction; and a plurality of bit line groups extending in the column direction, wherein a flash memory cell pair is provided at an intersection of the word line group and the bit line group, the flash memory cell pair including a first flash memory cell and a second flash memory cell adjacent in the row direction sharing the same bit line group. Each of the first flash memory cell and the second flash memory cell includes a first storage transistor, a gate transistor, and a second storage transistor sequentially connected in series in a column direction. In each of the first flash memory cell and the second flash memory cell, a source region of the first memory transistor is connected to a first electrode of the flash memory cell, and a drain region of the second memory transistor is connected to a second electrode of the flash memory cell. Each bit line group includes a first bit line connected to the first electrode of the first flash memory cell of the pair of flash memory cells, an intermediate bit line connected to the second electrode of the second flash memory cell of the pair of flash memory cells, and a second bit line connected to the second electrode of the first flash memory cell and the first electrode of the second flash memory cell. Each bit line group includes a first control line connected to the gate electrode of the first memory transistor, a word line connected to the gate electrode of the gating transistor, and a second control line connected to the gate electrode of the second memory transistor. The erasing method comprises the following first erasing step: performing an erase operation on the first memory transistors of the first and second flash memory cells by applying a first erase voltage to the first bit line, the middle bit line, and the second bit line, applying a second erase voltage to the first control line, applying a second power supply voltage to the word line and the second control line, or floating the word line and the second control line; an erase operation is performed on the second memory transistors of the first and second flash memory cells by applying a first erase voltage to the first bit line, the middle bit line, and the second bit line, applying a second power supply voltage to the word line and the first control line, or floating the word line and the first control line, applying a second erase voltage to the second control line. The first erase voltage is higher than a preset voltage, and the second erase voltage is equal to or lower than a second power supply voltage. The preset voltage is preset according to the carrier barrier height at the interface between the substrate and the gate dielectric stack of the first memory transistor and the second memory transistor.

According to the erasing method of the flash memory array, the threshold voltage window of the erasing operation can be improved, the storage reliability is improved, and meanwhile, the advantages of low operation power consumption and high erasing speed are achieved.

However, the effects of the present disclosure are not limited to the above effects, and it is to be understood that various extensions may be made without departing from the spirit and scope of the present disclosure that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention.

Fig. 1 is a cross-sectional view illustrating a flash memory cell according to an embodiment of the present disclosure.

Fig. 2 shows an equivalent circuit diagram of a flash memory cell according to an embodiment of the present disclosure.

Fig. 3 shows a circuit schematic of a flash cell pair according to an embodiment of the present disclosure.

FIG. 4 shows a circuit schematic of a flash memory array according to an embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of the erase operation performed on the first memory transistor by the first erase step according to an embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of a principle of simultaneously performing an erase operation on a first memory transistor and a second memory transistor through a second erase step according to an embodiment of the present disclosure.

Fig. 7 shows a schematic diagram of a principle of performing an erase operation on a first memory transistor and a second memory transistor through a third erase step according to an embodiment of the present disclosure.

Fig. 8 illustrates a schematic diagram of performing an erase operation on first memory transistors of first and second flash memory cells by a first erase step according to an embodiment of the present disclosure.

Fig. 9 illustrates a schematic diagram of performing an erase operation on the second memory transistors of the first and second flash memory cells by a first erase step according to an embodiment of the present disclosure.

Fig. 10 illustrates a schematic diagram of performing an erase operation on a first flash memory cell and a second flash memory cell by a second erase step according to an embodiment of the present disclosure.

Fig. 11 illustrates a schematic diagram of performing an erase operation on a first flash memory cell and a second flash memory cell by a third erase step according to an embodiment of the present disclosure.

FIG. 12 shows a flow chart of a method of erasing a flash memory array according to an embodiment of the present disclosure.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiments" and "implementations" are interchangeable words, and are non-limiting examples of apparatuses or methods that employ one or more of the inventive concepts disclosed herein. It may be evident, however, that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the exemplary embodiments. Moreover, the exemplary embodiments may be different, but not necessarily exclusive. For example, the particular shapes, configurations and characteristics of the exemplary embodiments may be used or implemented in other exemplary embodiments without departing from the inventive concept.

Unless otherwise indicated, the illustrated exemplary embodiments should be understood as providing exemplary features of varying detail of some ways in which the inventive concepts may be practiced. Thus, unless otherwise specified, features, components, modules, layers, films, panels, regions, and/or aspects and the like (hereinafter referred to individually or collectively as "elements") of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the spirit of the invention.

The use of cross-hatching and/or shading in the figures is typically provided for clarifying the boundaries between adjacent elements. As such, the presence or absence of cross-hatching or shading is not intended to convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonality between the illustrated elements, and/or any other characteristic, attribute, shape, etc., of an element, unless otherwise specified. Further, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. When the exemplary embodiments may be implemented differently, a specific order of processing may be performed differently from that described. For example, two processes described in succession may be executed substantially concurrently or in reverse order to that described. Also, like reference numerals refer to like elements.

When an element such as a layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. For purposes of this specification, the term "connected" may refer to physical, electrical, and/or fluid connections, with or without intervening elements. Further, the D1, D2, and D3 axes are not limited to three axes of a rectangular coordinate system, such as the x, y, and z axes, and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y, and Z" may be construed as X only, Y only, Z only, or any combination of two or more of X, Y and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the terms first, second, etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

Spatial relational terms, such as "under," "below," "under," "lower," "over," "upper," "higher," and "side" (e.g., as in a "sidewall") and the like may be used herein for descriptive purposes to describe the relationship of one element to another element as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. Furthermore, the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It should also be noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms rather than degree terms, and thus are utilized to account for inherent deviations in the measured, calculated, and/or provided values as recognized by those of ordinary skill in the art.

Some example embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units and/or modules, as is conventional in the art. Those skilled in the art will appreciate that the blocks, units and/or modules are physically implemented by electronic (or optical) circuitry, such as logic circuitry, discrete components, microprocessors, hardwired circuitry, memory elements, wired connections, and so forth, which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where the blocks, units, and/or modules are implemented by a microprocessor or other similar hardware, they may be erased and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and/or software. It is also contemplated that each block, unit, and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more microprocessors and associated circuitry that are erased) for performing other operations. Furthermore, each block, unit and/or module of some example embodiments may be physically separated into two or more interactive and discrete blocks, units and/or modules without departing from the scope of the present inventive concept. Furthermore, the blocks, units and/or modules of some example embodiments may be physically combined into more complex blocks, units and/or modules without departing from the scope of the inventive concept.

Embodiments are described herein with reference to cross-sectional and/or exploded views, which are schematic illustrations of idealized embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments disclosed herein are not necessarily to be construed as limited to the particular illustrated shapes of regions but are to include deviations in shapes that result, for example, from manufacturing. In this manner, the regions illustrated in the figures may be schematic in nature and the shapes of these regions may not reflect the actual shape of a region of a device, and thus this is not necessarily intended to be limiting.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 illustrates a cross-sectional view of a flash memory cell MC100 according to an embodiment of the present disclosure.

As shown in fig. 1, a flash memory cell MC100 according to an embodiment of the present disclosure may include a substrate 101 including a deep well region DNW103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103.

Although the first doping type is defined as P-type and the second doping type is defined as N-type in fig. 1 as an example, one skilled in the art will recognize that the present disclosure is not limited thereto and the first doping type may also be N-type, in which case the second doping type may be P-type.

According to an embodiment of the present disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

Further, the flash memory cell MC100 includes a first memory transistor MS110, a gate transistor MG120, and a second memory transistor MD 130 connected in series in this order. The first memory transistor MS110 may be disposed on the well region PW 102 and stores the first DATA 1. The second memory transistor MD 130 may be disposed on the well region PW 102 and stores second DATA 2. The gate transistor MG120 is disposed between the first and second memory transistors MS110 and MD 130 in the horizontal direction DR1 on the well region PW 102, for isolating the first and second memory transistors MS110 and MD 130 and performing a gate operation on the first and second memory transistors MS110 and MD 130.

According to an embodiment of the present disclosure, the flash memory cell MC100 includes two memory transistors MS110 and MD 130, and thus the flash memory cell MC100 can implement a function of two-bit storage, i.e., storing the first DATA1 and the second DATA2 at the same time.

Further, as shown in fig. 1, the source region of first memory transistor MS110 is connected to first electrode S of flash memory cell MC100, which may also be referred to as source S of flash memory cell MC100, and the drain region of second memory transistor MD 130 is connected to second electrode D of flash memory cell MC100, which may also be referred to as drain D of flash memory cell MC 100.

Those skilled in the art will recognize that the source and drain of a flash memory cell are defined herein for ease of description, however the definition of source and drain of a flash memory cell is relative and the terms "source" and "drain" may be used interchangeably under different operating conditions.

Further, as shown in fig. 1, the first memory transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask barrier 117 sequentially disposed in a vertical direction DR 2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 sequentially stacked in a vertical direction. In addition, the second memory transistor MD 130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask barrier 137 sequentially disposed in the vertical direction DR 2. The gate dielectric stack 132 has a first oxide layer 133, a storage dielectric layer 134, and a second oxide layer 135 sequentially stacked in a vertical direction.

According to the embodiment of the present disclosure, the flash memory cell MC100 includes two memory transistors MS110 and MD 130, and thus a function of two-bit storage can be implemented.

According to an embodiment of the present disclosure, as shown in fig. 1, a flash memory cell MC100 for two-bit storage may be composed of three closely arranged transistors, namely, a gate transistor MG120 located in the middle of the flash memory cell MC100, a first memory transistor MS110 located at a first end of the flash memory cell MC100, and a second memory transistor MD 130 located at a second end of the flash memory cell MC 100.

As shown in fig. 1, flash memory cell MC100 may be formed over well region PW 102 in semiconductor substrate 101. Furthermore, to isolate well region PW 102 from substrate 101 for applying voltages to well region PW 102 under certain operating conditions, well region PW 102 may be formed in deep well region DNW103 as shown in fig. 1.

As shown in fig. 1, a source region 140 formed by N-type doping is disposed at a first end of the flash memory cell MC100, and a drain region 150 formed by N-type doping is also disposed at a second end of the flash memory cell MC 100. The source region 140 is connected to the metal source 142, i.e., the first electrode S, located at an upper layer through the contact hole 141, and the drain region 150 is connected to the metal drain 152, i.e., the second electrode D, located at an upper layer through the contact hole 151.

According to an embodiment of the present disclosure, the first and second electrodes S and D may include a metal or highly doped polysilicon. When the first electrode S and the second electrode D are formed of a metal, it may include at least one of the following materials: aluminum, titanium nitride, copper, tungsten, cobalt, and manganese.

As described above, the gate structure of the first memory transistor MS110 may have, in order from bottom to top, the channel region 111, the gate dielectric stack 112, the gate electrode 116, and the hard mask barrier 117 for sidewall self-alignment, as shown in fig. 1. According to embodiments of the present disclosure, the gate electrode 116 may comprise, for example, polysilicon, a metal gate, a metal silicide material, or a combination thereof. According to an embodiment of the present disclosure, the hard mask barrier 117 may include, for example, silicon oxide, silicon nitride, a silicon glass material, or a combination thereof.

Further, as shown in fig. 1, the gate dielectric stack 112 has a first oxide layer (tunnel oxide layer) 113, a storage dielectric layer (charge storage layer) 114, and a second oxide layer (blocking oxide layer) 115, which are sequentially stacked in a vertical direction. According to an embodiment of the present disclosure, the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide or aluminum oxide, etc.

According to embodiments of the present disclosure, the storage medium layer 114 may include one or more layers of storage media. In addition, according to an embodiment of the present disclosure, the storage medium forming the storage medium layer 114 may include: mono-or multi-component oxides such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide; mono-or poly-nitrides such as silicon nitride; mono-or poly-oxynitrides such as silicon oxynitride; polycrystalline silicon or nanocrystalline materials; or a combination of the above materials.

According to an embodiment of the present disclosure, when the storage dielectric layer 114 is formed of, for example, a silicon nitride material, the first oxide layer 113, the storage dielectric layer 114, and the second oxide layer 115 may form the gate dielectric stack 112 as an ONO (oxide-nitride-oxide) composite storage dielectric. At this time, the first memory transistor MS110 may be a SONOS type memory transistor.

Further, according to an embodiment of the present disclosure, the first memory transistor MS110 may be another trap charge trapping type memory transistor having a similar operation mechanism as the SONOS type memory transistor, which employs a high-K material rich in charge traps, such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, etc., instead of the silicon nitride material in the SONOS memory as the memory dielectric layer 114.

In addition, according to an embodiment of the present disclosure, the first memory transistor MS110 may also be a floating gate type memory transistor, which uses a polysilicon material instead of a silicon nitride material in a SONOS memory to form a floating gate for storing charges as the storage medium layer 114.

In addition, according to the embodiment of the present disclosure, the first memory transistor MS110 may also be a nano-crystal memory transistor (nano-crystal memory), which uses a nano-crystal material with quantum dots (quantum dots) instead of a silicon nitride material in a SONOS memory as the memory medium layer 114.

According to an embodiment of the present disclosure, the length of the gate electrode 116 of the first memory transistor MS110 may be defined by the length of the hard mask barrier 117 disposed on the gate electrode 116 through a self-aligned process. It should be noted by those skilled in the art that reference herein to "length" is intended to refer to the dimension of the stated object in the horizontal direction DR 1.

According to the embodiment of the present disclosure, the second memory transistor MD 130 has the same structure as the first memory transistor MS110 except disposed at the opposite side of the gate transistor MG120 and may be manufactured through the same process as the first memory transistor MS110, and thus a detailed description of the structure of the second memory transistor MD 130 will be omitted herein for the sake of brevity.

The gate structure of the gating transistor MG120 may include a channel region 121, a gate dielectric layer 122, and a gate electrode 123 in this order from bottom to top. According to the embodiment of the present disclosure, the gate electrode 123 of the gate transistor MG120 is connected to a word line, and the length of the gate electrode 123 thereof is defined by the process size of the photolithography process. According to an embodiment of the present disclosure, the gate dielectric layer 122 may include materials such as silicon oxide, silicon oxynitride, hafnium oxide, and the like. Further, according to an embodiment of the present disclosure, the gate electrode 123 may include, for example, polysilicon, a metal gate, a metal silicide material, or a combination thereof.

According to an embodiment of the present disclosure, the channel regions 111, 131, and 121 of the first memory transistor MS110, the second memory transistor MD 130, and the gate transistor MG120 may each have a first doping type, and the doping concentration of the channel regions 111 and 131 of the first memory transistor MS110 and the second memory transistor MD 130 may be lower than the doping concentration of the channel region 121 of the gate transistor MG 120.

Further, according to an embodiment of the present disclosure, the channel regions 111 and 131 of the first and second memory transistors MS110 and MD 130 may have a second doping type or be an undoped intrinsic channel region, and the channel region 121 of the gate transistor MG120 may have a first doping type different from the second doping type.

For example, as shown in fig. 1, in the case where the first doping type is a P-type and the second doping type is an N-type, the doping concentration of the P-type channels 111 and 131 of the first and second memory transistors MS110 and MD 130 is lower than that of the P-type channel 121 of the gate transistor MG 120. Furthermore, according to an embodiment of the present disclosure, the channel regions 111 and 131 may also be undoped intrinsic channels or N-type doped channel regions.

According to an embodiment of the present disclosure, the flash memory cell MC100 further includes: a first isolation portion 124 provided between the first memory transistor MS110 and the gate transistor MG120 in the horizontal direction DR1 for isolating the gate electrode 116 of the first memory transistor MS110 and the gate electrode 123 of the gate transistor MG 120; and a second isolation portion 125 disposed between the gate transistor MG120 and the second memory transistor MD 130 in the horizontal direction DR1 for isolating the gate electrode 123 of the gate transistor MG120 and the gate electrode 136 of the second memory transistor MD 130.

Specifically, as shown in fig. 1, the gate electrode 123 of the gate transistor MG120 is provided at both sides with a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls for electrically isolating from the gate electrode 116 of the first memory transistor MS110 and the gate electrode 136 of the second memory transistor MD 130, respectively, by a certain isolation gap length. According to an embodiment of the present disclosure, the first isolation portion 124 and the second isolation portion 125 may include the same material as the gate dielectric layer 122.

According to the flash memory unit disclosed by the embodiment of the disclosure, two storage transistors can be realized in one flash memory unit, so that the equivalent area of each storage bit can be greatly reduced, and further lower cost and higher integration density can be obtained.

In addition, the memory transistor in the flash memory cell according to the embodiment of the present disclosure may adopt a SONOS-type device structure with a simple structure, and has advantages of a simple process, a low gate electrode operating voltage, and good data retention reliability.

In addition, in the flash memory unit according to the embodiment of the disclosure, the mutual influence of two storage bits is isolated through the gating transistor, and the distribution width and the lateral diffusion of the storage charges are suppressed, so that a higher storage charge density can be obtained in the silicon nitride storage layer, the problems of wide charge distribution, large mutual interference, incapability of reducing the gate length and the like of the existing NROM storage unit which also adopts two-bit storage are avoided, and the storage window and the data reliability are remarkably improved.

In particular, the equivalent channel length of the flash memory cell according to the embodiment of the present disclosure is the sum of the lengths of the gate electrodes of the first storage transistor, the gate transistor, and the second storage transistor. As described above, the gate electrode length of the gate transistor is defined by the process Feature Size of the photolithography process, typically about equal to or slightly larger than the Critical Feature Size (Critical Feature Size), which is typically denoted as F (or CF). In addition, the gate electrode lengths of the first and second memory transistors are defined by the lengths of the self-aligned sidewall hard mask barriers, respectively, and thus may be smaller than F in size. Therefore, according to the embodiments of the present disclosure, a smaller channel length of the flash memory cell can be obtained under the same process feature size, thereby achieving the purpose of reducing the area and manufacturing cost of the flash memory cell.

In addition, in the flash memory array composed of the flash memory cells according to the embodiments of the present disclosure, for the flash memory cells that are not selected for operation, the gate electrodes of the gating transistor and the first and second storage transistors are grounded, so that the entire series channel of the flash memory cells is completely turned off, and the equivalent channel length is extended, thereby preventing the source-drain punch-through of the flash memory cells under the condition of high operating voltage under a smaller process feature size, and overcoming the problem that the gate electrode length of the existing flash memory cells cannot be reduced along with the reduction of the process feature size. Therefore, the flash memory cell according to the embodiment of the present disclosure has better process scaling capability, and thus can achieve smaller cell area and manufacturing cost by reducing the process feature size.

In addition, in the flash memory cell according to the embodiment of the present disclosure, by reducing the doping concentration of the P-type channel region of the first memory transistor and the second memory transistor or designing them as the N-type doped channel region, the threshold voltage of the memory transistor and the gate electrode operating voltage in the erasing and reading operations can be reduced, and thus the reliability of the memory transistor can be improved. Meanwhile, the punch-through resistant voltage of the flash memory unit can be improved by improving the doping concentration of the P-type channel region of the gating transistor, and the leakage current between the source region and the drain region of the non-selected flash memory unit is reduced.

Fig. 2 illustrates an equivalent circuit diagram of the flash memory cell MC100 according to an embodiment of the present disclosure.

Specifically, as shown in fig. 2, the flash memory cell MC100 includes a first memory transistor MS110, a gate transistor MG120, and a second memory transistor MD 130 connected in series in this order. The gating transistor MG120 may isolate the first and second memory transistors MS110 and MD 130 and perform a gating operation on the first and second memory transistors MS110 and MD 130.

Fig. 3 shows a circuit schematic of a flash cell pair 200 according to an embodiment of the present disclosure. FIG. 4 shows a circuit schematic of a flash memory array according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, a flash memory array may include: a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction; a plurality of word line groups extending in a row direction; and a plurality of bit line groups extending in the column direction, wherein a flash memory cell pair is provided at an intersection of the word line group and the bit line group, the flash memory cell pair including a first flash memory cell and a second flash memory cell adjacent in the row direction sharing the same bit line group.

As shown in fig. 3 and 4, according to an embodiment of the present disclosure, a flash memory array may include a plurality of flash memory cells as shown in fig. 2, which may be arranged in an array of m × 2n in a row direction and a column direction perpendicular to the row direction, where m and n are natural numbers greater than 1. Thus, a plurality of flash memory cells form a flash memory array of m rows by 2n columns.

As shown in fig. 3, two flash memory cells adjacent in the row direction may constitute one flash memory cell pair 200 including a first flash memory cell 210 and a second flash memory cell 220 according to an embodiment of the present disclosure. For example, the first flash cell 210 may be a flash cell located in row 0, column 0 of the flash array, and the second flash cell 220 may be a flash cell located in row 0, column 1 of the flash array. Thus, according to embodiments of the present disclosure, a flash memory array may include pairs of flash memory cells arranged in m rows by n columns.

The first flash memory cell 210 includes a first storage transistor 211, a gating transistor 212, and a second storage transistor 213 sequentially connected in series in a column direction. The second flash memory cell 220 includes a first storage transistor 221, a gating transistor 222, and a second storage transistor 223 sequentially connected in series in a column direction.

According to an embodiment of the present disclosure, in the first flash memory cell 210, the source region of the first memory transistor 211 is connected to the first electrode S1 of the first flash memory cell 210, and the drain region of the second memory transistor 213 is connected to the second electrode D1 of the first flash memory cell 210.

Further, according to an embodiment of the present disclosure, in the second flash memory cell 220, the source region of the first memory transistor 221 is connected to the first electrode S2 of the second flash memory cell 220, and the drain region of the second memory transistor 223 is connected to the second electrode D2 of the second flash memory cell 220.

Further, according to an embodiment of the present disclosure, the pair of flash memory cells 200, i.e., the pair of the first and second flash memory cells 210 and 220, share a bit line group extending in a column direction, the bit line group including the first bit line BSL0, the middle bit line BLM0, and the second bit line BLD 0. According to the first embodiment of the present disclosure, the first bit line BSL0 may be connected to the first electrode S1 of the first flash memory cell 210, the second bit line BLD0 may be connected to the second electrode D2 of the second flash memory cell 220, and the middle bit line BLM0 may connect the second electrode D1 of the first flash memory cell 210 and the first electrode S2 of the second flash memory cell 220.

As described above, according to the embodiment of the present disclosure, the first and second flash memory cells 210 and 220 adjacent in the row direction are connected to the same first bit line BSL0, middle bit line BLM0, and second bit line BLD 0. That is, according to embodiments of the present disclosure, pairs of flash memory cells share the same set of bit lines in a flash memory array. For example, column 0 and column 1 flash memory cells share a group of bit lines including first bit line BLS0, middle bit line BLM0, and second bit line BLD0, and column 2 and column 3 flash memory cells share a group of bit lines including first bit line BLS1, middle bit line BLM1, and second bit line BLD1, up to column 2n-2 and column 2n-1 flash memory cells share a group of bit lines including first bit line BLS < n-1>, middle bit line BLM < n-1>, and second bit line BLD < n-1 >.

Further, according to an embodiment of the present disclosure, the flash memory array further includes a plurality of word line groups extending in the row direction, each of the word line groups including a first control line, a word line, and a second control line, wherein the first control line is connected to the gate electrode of the first memory transistor of the flash memory cell pair, the word line is connected to the gate electrode of the gating transistor of the flash memory cell pair, and the second control line is connected to the gate electrode of the second memory transistor of the flash memory cell pair.

According to an embodiment of the present disclosure, in a flash memory array, flash memory cells (pairs) of the same row share the same word line group, i.e., a first control line, a word line, and a second control line.

As shown in fig. 3 and 4, taking the flash memory cell pair 200 as an example, the flash memory cell pair 200, i.e., the first flash memory cell 210 and the second flash memory cell 220, is located in the 0 th row and shares the same word line group, i.e., the first control line MS0, the word line WL0, and the second control line MD0, with other flash memory cells (pairs) in the 0 th row. The first control line MS0 is connected to the gate electrodes of the first memory transistors 211 and 221 of the first and second flash memory cells 210 and 220, the word line WL0 is connected to the gate electrodes of the gate transistors 212 and 222 of the first and second flash memory cells 210 and 220, and the second control line MD0 is connected to the gate electrodes of the second memory transistors 213 and 223 of the first and second flash memory cells 210 and 220.

Similarly, the gate electrodes of the first memory transistors in the flash memory cell (pair) of the 1 st row are commonly connected to the first control line MS1, the gate electrodes of the gate transistors in the flash memory cells of the 1 st row are commonly connected to the word line WL1, and the gate electrodes of the second memory transistors in the flash memory cells of the 1 st row are commonly connected to the second control line MD 1. Similarly, the gate electrodes of the first memory transistors in the flash memory cells of the m-2 th row are commonly connected to a first control line MS < m-2>, the gate electrodes of the gate transistors in the flash memory cells of the m-2 th row are commonly connected to a word line WL < m-2>, and the gate electrodes of the second memory transistors in the flash memory cells of the m-2 th row are commonly connected to a second control line MD < m-2 >. Similarly, the gate electrodes of the first memory transistors in the flash memory cells of the m-1 th row are commonly connected to a first control line MS < m-1>, the gate electrodes of the gate transistors in the flash memory cells of the m-1 th row are commonly connected to a word line WL < m-1>, and the gate electrodes of the second memory transistors in the flash memory cells of the m-1 th row are commonly connected to a second control line MD < m-1 >.

Those skilled in the art will recognize that the flash memory cells according to the embodiments of the present disclosure have a symmetrical structure, and thus the flash memory cells adjacent in the column direction are oppositely disposed based on the connection relationship of the first control line, the word line, the second control line, the first bit line, the middle bit line, and the second bit line as described above, i.e., the first memory transistor of the flash memory cell of the current row is adjacent to the first memory transistor of the flash memory cell of the previous row in the column direction, and the second memory transistor of the flash memory cell of the current row is adjacent to the second memory transistor of the flash memory cell of the next row in the column direction; or, the second storage transistor of the flash memory cell of the current row is adjacent to the second storage transistor of the flash memory cell of the previous row in the column direction, and the first storage transistor of the flash memory cell of the current row is adjacent to the first storage transistor of the flash memory cell of the next row in the column direction.

Fig. 5 shows a schematic diagram of the erase operation performed on the first memory transistor by the first erase step according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, when performing an erase operation on the flash memory cell MC100, the well region PW 102 of the flash memory cell MC100 may be grounded.

Specifically, according to the embodiment of the present disclosure, as shown in fig. 5, when an erase operation is performed on the first memory transistor MS110 of the flash memory cell MC100 through the first erase step, the second power supply voltage VSS is applied to the well region PW 102, the first erase voltage VE1 is applied to the first electrode S and the second electrode D, the second power supply voltage VSS is applied to the gate electrode 123 of the gate transistor MG120 and the gate electrode 136 of the second memory transistor MD 130 or the gate electrode 123 of the gate transistor MG120 and the gate electrode 136 of the second memory transistor MD 130 are floated (floating is denoted by FLT in the drawing), and the second erase voltage VE2 is applied to the gate electrode 116 of the first memory transistor MS 110. For example, the second power supply voltage VSS may be a ground voltage, e.g., 0V.

According to an embodiment of the present disclosure, the first erase voltage VE1 is higher than a preset voltage VP, wherein the preset voltage VP is preset according to a carrier barrier height at an interface between the substrate and the gate dielectric stack 112 of the first storage transistor MS 100. For example, in the flash memory cell MC100 shown in fig. 1, the preset voltage VP1 may enable holes to cross a hole barrier at the interface between the P-type channel region 111 and the lower first oxide layer (tunnel oxide) 113 in the gate dielectric stack 112. For example, in the case where the P-type channel region 111 includes silicon and the first oxide layer 113 includes silicon dioxide, the barrier height is 4.8 electron volts (eV). In this case, the first erase voltage VE1 is typically greater than 4 volts (V). For example, the first erase voltage VE1 may be in the range of 3V to 6V. For example, the first erase voltage VE1 may be 4V.

According to an embodiment of the present disclosure, the second erase voltage VE2 is equal to or lower than the second power supply voltage VSS, which may be the ground voltage GND. Further, according to an embodiment of the present disclosure, the second erase voltage VE2 may be in the range of-8V to 0V. For example, the second erase voltage VE2 may be-6V.

Similarly, according to the embodiment of the present disclosure, when the erase operation is performed on the second memory transistor MD 130 of the flash memory cell MC100 through the first erase step, the first erase voltage VE1 is applied to the first electrode S and the second electrode D, the second power supply voltage VSS is applied to the gate electrode 123 of the gate transistor MG120 and the gate electrode 116 of the first memory transistor MS110 or the gate electrode 123 of the gate transistor MG120 and the gate electrode 116 of the first memory transistor MS110 are floated, and the second erase voltage VE2 is applied to the gate electrode 116 of the second memory transistor MD 130.

It can be seen that due to the symmetrical structure of flash cell MC100, there is also a symmetrical relationship for the respective erase voltages VE1 and VE2 applied during the erasing of first memory transistor MS110 and second memory transistor MD 130 using the first erase step. Therefore, for the sake of brevity, the erase voltage applied during the erase operation of the second memory transistor MD 130 will not be repeatedly described here.

Further, according to the embodiment of the present disclosure, it is also possible to simultaneously perform the erase operation on the first memory transistor MS110 and the second memory transistor MD 130 of the flash memory cell MC100 through the second erase step. Fig. 6 shows a schematic diagram of a principle of simultaneously performing an erase operation on a first memory transistor and a second memory transistor through a second erase step according to an embodiment of the present disclosure.

According to the embodiment of the present disclosure, as shown in fig. 6, when the erase operation is simultaneously performed on the first memory transistor MS110 and the second memory transistor MD 130 through the second erase step, the first erase voltage VE1 is applied to the first electrode S and the second electrode D, the second power supply voltage VSS is applied to the gate electrode 123 of the gate transistor MG120 or the gate electrode 123 of the gate transistor MG120 is floated, and the second erase voltage VE2 is applied to the gate electrode 116 of the first memory transistor MS110 and the gate electrode 136 of the second memory transistor MD 130.

According to an embodiment of the present disclosure, the erase operations performed on the first and second memory transistors MS110 and MD 130 through the first and second erase steps described above employ a band-to-band tunneling hot carrier injection mechanism. Taking the example of performing the erase operation on the first memory transistor MS110, the junction at the first electrode S of the flash memory cell MC100 is under a high voltage reverse bias state, so that under the action of the second erase voltage VE2 (negative gate voltage) applied on the gate electrode 116, the depletion region of the junction will have a band-to-band tunneling physical effect, and hot holes generated by the band-to-band tunneling will be injected into the storage medium layer 114, such as silicon nitride. The hot holes neutralize electrons stored during a write (program) operation of the flash memory cell MC100, so that the threshold voltage of the first memory transistor MS110 is lowered. In addition, since the flash memory cell MC100 is in an off state at this time, the erase operation does not cause an on current, and thus has an advantage of low power consumption.

Fig. 7 shows a schematic diagram of a principle of performing an erase operation on a first memory transistor and a second memory transistor through a third erase step according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, an erase operation may also be simultaneously performed on the first memory transistor MS110 and the second memory transistor MD 130 of the flash memory cell MC100 through a third erase step. According to the embodiment of the present disclosure, in performing the erase operation on the first memory transistor MS110 and the second memory transistor MD 130 at the same time, the third erase voltage VE3 is applied to the well region PW 102, the first electrode S and the second electrode D, the second power supply voltage VSS is applied to the gate electrode 123 of the gate transistor MG120, and the fourth erase voltage VE4 is applied to the gate electrode 116 of the first memory transistor MS110 and the gate electrode 136 of the second memory transistor MD 130.

According to an embodiment of the present disclosure, the third erase voltage VE3 may be in a range of 0V to 20V. For example, the third erase voltage VE3 may be 6V. According to an embodiment of the present disclosure, the fourth erase voltage VE4 may be in the range of-10V to 0V. For example, the fourth erase voltage VE4 may be-6V.

Further, according to the embodiment of the present disclosure, the third erase voltage VE3 used in the third erase step may be the same as or different from the first erase voltage VE1 used in the first and second erase steps described above, and the fourth erase voltage VE4 used in the third erase step may be the same as or different from the second erase voltage VE2 used in the first and second erase steps described above.

According to an embodiment of the present disclosure, the erase operation performed on the first memory transistor MS110 and the second memory transistor MD 130 through the third erase step described above employs a FN (Fowler-Nordheim) tunneling mechanism. Taking as an example the erasing operation performed on the first memory transistor MS110, the third erasing voltage VE3 of a relatively high voltage is applied to the first electrode S of the flash memory cell MC100 and the well region PW 102 (substrate), the fourth erasing voltage VE4 of a negative voltage or a ground voltage is applied to the gate electrode 116 (control gate) of the first memory transistor MS110, and under the action of the gate reverse electric field, the written (programmed) electron charges stored in the storage medium layer 114 are pulled out by the substrate through the FN tunneling mechanism, so that the threshold voltage of the first memory transistor MS110 is lowered. In addition, since the flash memory cell MC100 is in an off state at this time and there is no voltage difference between the first electrode S and the second electrode D thereof, the erase operation does not cause on-current, and thus the erase method of the flash memory cell according to the present disclosure has an advantage of low power consumption.

It should be noted that the erase operation of the third erase step based on the FN tunneling scheme according to the present disclosure has a lower operation current than the first erase step and the second erase step based on the band-to-band tunneling hot hole injection scheme, and thus can be applied to simultaneously perform the erase operation on more rows of flash memory cells, and thus can support the erase operation of a larger capacity flash memory array. However, due to the trapping effect of the written (programmed) electron charges in the storage dielectric layer, such as silicon nitride, it is difficult for the trapped electrons to be excited away from the electron traps by the longitudinal reverse electric field to be injected into the substrate by tunneling. In this way, the erase operation of the third erase step based on the FN tunneling mechanism has a higher erase voltage, a slower operation speed, and a smaller erase window than the erase operation of the first erase step and the second erase step based on the band-to-band tunneling hot carrier injection mechanism.

Fig. 8 illustrates a schematic diagram of performing an erase operation on the first memory transistors 211 and 221 of the first and second flash memory cells 210 and 220 through a first erase step according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, as shown in fig. 8, in performing an erase operation on the first memory transistors 211 and 221 of the first and second flash memory cells 210 and 220, a first erase voltage VE1, for example, 4V, is applied to the first bit line BLS0, the middle bit line BLM0, and the second bit line BLD0, a second erase voltage VE2, for example, -6V, is applied to the first control line MS0 connected to the gate electrodes of the first memory transistors 211 and 221, a second power supply voltage VSS is applied to the word line WL0 connected to the gate electrodes of the gate transistors 212 and 222 and the second control line MD0 connected to the gate electrodes of the second memory transistors 213 and 223, or the word line WL0 and the second control line MD0 are floated.

Fig. 9 illustrates a schematic diagram of performing an erase operation on the second memory transistors 213 and 223 of the first and second flash memory cells 210 and 220 through a first erase step according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, as shown in fig. 9, when an erase operation is performed on the second memory transistors 213 and 223 of the first and second flash memory cells 210 and 220 through the first erase step, a first erase voltage VE1 of, for example, 4V is applied to the first bit line BLS0, the middle bit line BLM0, and the second bit line BLD0, a second erase voltage VE2 of, for example, -6V is applied to the second control line MD0 connected to the gate electrodes of the second memory transistors 213 and 223, a second power supply voltage VSS is applied to the word line WL0 connected to the gate electrodes of the gate transistors 212 and 222 and the first control line MS0 connected to the gate electrodes of the first memory transistors 211 and 221 or the word line WL0 and the first control line MS0 are floated.

According to an embodiment of the present disclosure, as shown in fig. 8 and 9, a first erase step may be used to simultaneously erase a first memory transistor or a second memory transistor in one or more rows of flash memory cells. Further, according to an embodiment of the present disclosure, when an erase operation is performed through the first erase step, all bit line groups of the flash memory array may be connected to the first erase voltage VE 1. For a row of flash memory cells for which an erase operation is not performed, the word line group thereof may be connected to the second power supply voltage VSS or floated.

Fig. 10 illustrates a schematic diagram of performing an erase operation on the first flash memory cell 210 and the second flash memory cell 220 through a second erase step according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, as shown in fig. 10, when the erase operation is simultaneously performed on the first and second memory transistors 211 and 221 and 213 and 223 of the first and second flash memory cells 210 and 220 through the second erase step, a first erase voltage VE1 of, for example, 4V is applied to the first bit line BLS0, the intermediate bit line BLM0, and the second bit line BLD0, a second erase voltage VE2 of, for example, -6V is applied to the first control line MS0 connected to the gate electrodes of the first memory transistors 211 and 221 and the second control line MD0 connected to the gate electrodes of the second memory transistors 213 and 223, and the second power supply voltage VSS is applied to the word line WL0 connected to the gate electrodes of the gate transistors 212 and 222 or the word line WL0 is floated.

According to an embodiment of the present disclosure, as shown in fig. 10, the first and second memory transistors in the flash memory cells of one or more rows may be simultaneously erased using a second erase step. Further, according to an embodiment of the present disclosure, when an erase operation is performed through the second erase step, all bit line groups of the flash memory array may be connected to the first erase voltage VE 1. For a row of flash memory cells for which an erase operation is not performed, the word line group thereof may be connected to the second power supply voltage VSS or floated.

According to the embodiments of the present disclosure, as shown in fig. 8 to 10, by the first erasing step or the second erasing step, the erasing operation may be simultaneously performed on the selected row or rows of memory cells or on the first memory transistors or the second memory transistors in the flash memory cells of the selected row.

According to an embodiment of the present disclosure, as shown in fig. 8 to 10, when an erase operation of a flash memory array is performed through a first erase step or a second erase step, a first erase voltage VE1 is applied to a first bit line BLS <0: n-1>, an intermediate bit line BLM <0: n-1>, and a second bit line BLD <0: n-1> of the flash memory array.

According to the embodiment of the present disclosure, as shown in fig. 8 to 10, for a flash memory cell on which an erase operation is not performed, the first control line, the word line, and the second control line thereof are applied with the second power supply voltage VSS or floated.

Fig. 11 illustrates a schematic diagram of performing an erase operation on a first flash memory cell and a second flash memory cell by a third erase step according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, as shown in fig. 11, when an erase operation is simultaneously performed on the first and second memory transistors 211 and 221 and 213 and 223 of the first and second flash memory cells 210 and 220 through the third erase step, a third erase voltage VE3, for example, 6V, is applied to the well region PW 102, the first bit line BLS0, the middle bit line BLM0, and the second bit line BLD0 of the flash memory array, a fourth erase voltage VE4, for example, -6V, is applied to the first control line MS0 connected to the gate electrodes of the first memory transistors 211 and 221 and the second control line MD0 connected to the gate electrodes of the second memory transistors 213 and 223, and a second power supply voltage VSS is applied to the word line WL0 connected to the gate electrodes of the gate transistors 212 and 222 or the word line WL0 floats.

According to an embodiment of the present disclosure, as shown in fig. 11, by the third erase step, an erase operation may be simultaneously performed on the entire flash memory array.

Further, as described above, according to the embodiment of the present disclosure, the third erase voltage VE3 used in the third erase step may be the same as or different from the first erase voltage VE1 used in the first and second erase steps described above, and the fourth erase voltage VE4 used in the third erase step may be the same as or different from the second erase voltage VE2 used in the first and second erase steps described above.

According to an embodiment of the present disclosure, as shown in fig. 11, in performing an erase operation on the entire flash memory array, a third erase voltage VE3 is applied to a well region PW 102, a first bit line BLS <0: n-1>, a middle bit line BLM <0: n-1> and a second bit line BLD <0: n-1>, a fourth erase voltage VE4 is applied to a first control line MS <0: m-1> and a second control line MD <0: m-1>, and a second power supply voltage VSS is applied to a word line WL <0: m-1> or the word line WL <0: m-1> is floated.

As described above, the erase operation of the third erase step based on the FN tunneling scheme is suitable for simultaneously performing the erase operation on more rows and even the entire flash memory array, but the erase voltage is higher, the operation speed is slower, and the erase window is smaller, compared to the erase operation of the first erase step and the second erase step based on the band-to-band tunneling hot carrier injection scheme. Thus, according to embodiments of the present disclosure, the first (second) erase step may be used in combination with the third erase step to achieve an optimal trade-off of erase speed and erase effect. Specifically, the erase operation may be first performed on the entire flash memory cells or on the flash memory cells of more rows using the third erase step based on the FN tunneling mechanism, so that the threshold voltage of the selected flash memory cell to be erased is erased to a lower state by using the characteristic of small operation current of the FN tunneling effect while selecting the flash memory cells of more rows to perform the erase operation. Subsequently, an erase operation may be performed on one or fewer rows of flash memory cells using a first erase step or a second erase step based on a band-to-band tunneling hot carrier injection mechanism, thereby utilizing neutralization of the injected holes to erase selected flash memory cells to be erased to a lower threshold voltage state.

FIG. 12 shows a flow diagram of a method 1200 of erasing a flash memory array according to an embodiment of the present disclosure.

The erasing method 1200 starts in step S1201. Subsequently, in step S1202, an erase operation is performed on all rows of the flash memory array through the third erase step. Subsequently, in step S2103, one or more rows of flash memory cells of the flash memory array are selected and an erase operation is performed on the selected rows of flash memory cells by the first erase step or the second erase step. Further, in step S1203, the row address of the flash memory cell row on which the first erasing step or the second erasing step has been performed may also be stored. Subsequently, in step S1204, it is determined whether the first erasing step or the second erasing step has been performed on all the rows of the flash memory cells. If so, the erase method 1200 ends at step S1205. Otherwise, the erasing method 1200 returns to step S1203, and according to the previously stored row address, an erasing operation is performed on the flash memory cells of the row on which the first erasing step and the second erasing step are not performed.

By the multi-step combined erasing method of the flash memory array according to the embodiment of the present disclosure, the first erasing step and/or the second erasing step can be combined with the third erasing step to obtain a lower erasing threshold voltage while reducing the erasing voltage and the erasing time, thereby improving the erasing operation speed and improving the erasing operation threshold voltage window of the flash memory unit and the reliability of storage.

Those skilled in the art will recognize that although the erase method of the flash memory array of the present disclosure is described above in connection with the flash memory cell MC100 shown in fig. 1, the erase method of the flash memory array of the present disclosure is not limited to the flash memory cell MC100 shown in fig. 1. It is contemplated by those skilled in the art having the benefit of the present disclosure that the erase method of the flash memory array of the present disclosure may be applied to other types of flash memory cells, such as flash memory cells including only one memory transistor or flash memory cells storing two bits of data using one memory transistor, and all such variations are intended to be within the scope of the present disclosure.

Although the present disclosure has been described with reference to the embodiments thereof, those skilled in the art will appreciate that various modifications and changes can be made to the present disclosure without departing from the spirit and scope of the present disclosure disclosed in the appended claims.