阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 黄致凡 沈香谷 王良玮 陈殿豪 陈燕铭 于 2021-08-10 设计创作，主要内容包括：半导体结构包括位于第二金属层正上方的第三金属层,该第二金属层位于第一金属层上方。该第二金属层包括位于存储区中的磁隧道结(MTJ)器件和位于逻辑区中的第一导电部件。每个MTJ器件包括位于底电极和底电极上方的MTJ堆叠件。该第三金属层包括电连接至第一导电部件的第一通孔、以及位于MTJ器件的MTJ堆叠件上方并电连接至该MTJ堆叠件的槽通孔。该槽通孔占据从MTJ器件中的第一个向MTJ器件中的最后一个连续横向延伸的空间。该第一通孔与槽通孔一样薄或更薄。该第三金属层还包括分别电连接至第一通孔和槽通孔的第二导电部件和第三导电部件。本申请的实施例还涉及形成半导体结构的方法。(The semiconductor structure includes a third metal layer directly over the second metal layer, which is over the first metal layer. The second metal layer includes a Magnetic Tunnel Junction (MTJ) device in the storage region and a first conductive feature in the logic region. Each MTJ device includes an MTJ stack located above a bottom electrode and a bottom electrode. The third metal layer includes a first via electrically connected to the first conductive component, and a slot via over and electrically connected to a MTJ stack of the MTJ device. The slot via occupies a space that extends continuously laterally from a first one of the MTJ devices to a last one of the MTJ devices. The first via is as thin or thinner as the slotted via. The third metal layer also includes a second conductive feature and a third conductive feature electrically connected to the first via and the trench via, respectively. Embodiments of the present application also relate to methods of forming semiconductor structures.)

1. A semiconductor structure, comprising:

a first metal layer;

a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of Magnetic Tunnel Junction (MTJ) devices in a memory device region and a first conductive feature in a logic device region, wherein each of the magnetic tunnel junction devices includes a bottom electrode and a magnetic tunnel junction stack disposed over the bottom electrode; and

a third metal layer disposed directly over the second metal layer, wherein the third metal layer includes a first via disposed over the first conductive means and electrically connected to the first conductive means and a trench via disposed over the magnetic tunnel junction devices and electrically connected to the magnetic tunnel junction stack of each of the magnetic tunnel junction devices, wherein the trench via occupies a space that extends continuously laterally from a first one of the magnetic tunnel junction devices to a last one of the magnetic tunnel junction devices, wherein a first thickness of the first via is equal to or less than a second thickness of the trench via directly over the magnetic tunnel junction stack of one of the magnetic tunnel junction devices, wherein the third metal layer further includes a second conductive means disposed over the first via and electrically connected to the first via and a third conductive means disposed over the trench via and electrically connected to the trench via.

2. The semiconductor structure of claim 1, wherein the trench via and the first via each comprise copper.

3. The semiconductor structure of claim 2, wherein the second and third conductive features each comprise copper.

4. The semiconductor structure of claim 1, wherein the second metal layer comprises a dielectric feature disposed laterally between two adjacent ones of the magnetic tunnel junction devices, and a third thickness of the slot via directly above the dielectric feature is greater than the second thickness.

5. The semiconductor structure of claim 4, wherein the third thickness is about 5nm to about 50nm greater than the second thickness.

6. The semiconductor structure of claim 1, wherein one of the magnetic tunnel junction devices further comprises a top electrode vertically between the trench via and the magnetic tunnel junction stack of the one of the magnetic tunnel junction devices.

7. The semiconductor structure of claim 1, wherein each of the magnetic tunnel junction devices further comprises a spacer on a sidewall of the magnetic tunnel junction stack of the respective magnetic tunnel junction device and a protective layer on a sidewall of the spacer, wherein a portion of the trench via is disposed in a space laterally between the protective layers of two adjacent ones of the magnetic tunnel junction devices.

8. The semiconductor structure of claim 7, wherein a bottom surface of the portion of the trench via is substantially planar.

9. A method of forming a semiconductor structure, comprising:

providing a structure having a first metal layer and a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of Magnetic Tunnel Junction (MTJ) devices in a memory device region and a first conductive feature in a logic device region, wherein each of the magnetic tunnel junction devices includes a bottom electrode, a magnetic tunnel junction stack disposed over the bottom electrode, and a top electrode disposed over the magnetic tunnel junction stack;

forming one or more dielectric layers over the second metal layer;

forming a first etch mask over the one or more dielectric layers, wherein the first etch mask defines a first aperture over the first conductive means and a second aperture over and continuously extending from a first one of the magnetic tunnel junction devices to a last one of the magnetic tunnel junction devices;

etching the one or more dielectric layers through the first and second holes to form first and second trenches, respectively, in the one or more dielectric layers, wherein the first trench exposes the first conductive feature and the second trench exposes a portion of each of the magnetic tunnel junction devices;

depositing a first metallic material into the first and second trenches and over the one or more dielectric layers; and

a chemical mechanical planarization process is performed on the first metal material such that a first portion of the first metal material remains in the first trench, a second portion of the first metal material remains in the second trench, and the first metal material is removed from a top surface of the one or more dielectric layers.

10. A method of forming a semiconductor structure, comprising:

providing a structure having a first metal layer and a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of Magnetic Tunnel Junction (MTJ) devices in a memory device region and a first conductive feature in a logic device region, wherein each of the magnetic tunnel junction devices includes a bottom electrode, a magnetic tunnel junction stack disposed over the bottom electrode, and a top electrode disposed over the magnetic tunnel junction stack;

forming a first dielectric layer over the second metal layer and a second dielectric layer over the first dielectric layer;

forming a first trench and a second trench in the first dielectric layer, wherein the first trench exposes the first conductive means and the second trench exposes a portion of each of the magnetic tunnel junction devices;

forming a third trench and a fourth trench in the second dielectric layer, wherein the third trench is directly over the first conductive feature and the fourth trench is directly over the magnetic tunnel junction device;

depositing a first metal material into the first, second, third, and fourth trenches and over the second dielectric layer; and

performing a chemical mechanical planarization process on the first metal material such that a first portion of the first metal material remains in the first and third trenches, a second portion of the first metal material remains in the second and fourth trenches, and the first metal material is removed from a top surface of the second dielectric layer.

Technical Field

Embodiments of the present application relate to semiconductor structures and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each of which has smaller, more complex circuits than the previous generation. In the course of IC development, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component (or line) that can be fabricated using the fabrication process) has decreased. Such a scale-down process generally results in benefits by improving production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing the IC.

One advance IN the design and manufacture of some ICs is the development of non-volatile memories (NVMs), IN particular Magnetic Random Access Memories (MRAMs). MRAM provides comparable performance to volatile Static Random Access Memory (SRAM), and has lower power consumption and comparable density compared to volatile Dynamic Random Access Memory (DRAM). MRAM can provide faster access times and can degrade performance over time compared to NVM flash memory. MRAM cells are formed from a Magnetic Tunnel Junction (MTJ) that includes two ferromagnetic layers separated by a thin insulating barrier and operating with tunneling of electrons between the two ferromagnetic layers through the insulating barrier. Scaling of MRAM cells in advanced technology nodes is limited by the resolution limits of lithography and etching techniques. As MRAM cells shrink, the series resistance of the MRAM cells may increase in some cases, resulting in higher power consumption. While existing methods in the formation of MRAM devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. Accordingly, there is a need for improvement in this field.

Disclosure of Invention

Some embodiments of the present application provide a semiconductor structure comprising: a first metal layer; a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of Magnetic Tunnel Junction (MTJ) devices in a memory device region and a first conductive feature in a logic device region, wherein each of the magnetic tunnel junction devices includes a bottom electrode and a magnetic tunnel junction stack disposed over the bottom electrode; and a third metal layer disposed directly above the second metal layer, wherein the third metal layer includes a first via disposed above the first conductive means and electrically connected to the first conductive means and a trench via disposed above the magnetic tunnel junction devices and electrically connected to the magnetic tunnel junction stack of each of the magnetic tunnel junction devices, wherein the trench via occupies a space that continuously extends laterally from a first one of the magnetic tunnel junction devices to a last one of the magnetic tunnel junction devices, wherein a first thickness of the first via is equal to or less than a second thickness of the trench via directly above the magnetic tunnel junction stack of one of the magnetic tunnel junction devices, wherein the third metal layer further includes a second conductive means disposed above the first via and electrically connected to the first via and a third conductive portion disposed above the trench via and electrically connected to the trench via And (3) a component.

Other embodiments of the present application provide a method of forming a semiconductor structure, comprising: providing a structure having a first metal layer and a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of Magnetic Tunnel Junction (MTJ) devices in a memory device region and a first conductive feature in a logic device region, wherein each of the magnetic tunnel junction devices includes a bottom electrode, a magnetic tunnel junction stack disposed over the bottom electrode, and a top electrode disposed over the magnetic tunnel junction stack; forming one or more dielectric layers over the second metal layer; forming a first etch mask over the one or more dielectric layers, wherein the first etch mask defines a first aperture over the first conductive means and a second aperture over and continuously extending from a first one of the magnetic tunnel junction devices to a last one of the magnetic tunnel junction devices; etching the one or more dielectric layers through the first and second holes to form first and second trenches, respectively, in the one or more dielectric layers, wherein the first trench exposes the first conductive feature and the second trench exposes a portion of each of the magnetic tunnel junction devices; depositing a first metallic material into the first and second trenches and over the one or more dielectric layers; and performing a chemical mechanical planarization process on the first metal material such that a first portion of the first metal material remains in the first trench, a second portion of the first metal material remains in the second trench, and the first metal material is removed from a top surface of the one or more dielectric layers.

Still other embodiments of the present application provide a method of forming a semiconductor structure, comprising: providing a structure having a first metal layer and a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of Magnetic Tunnel Junction (MTJ) devices in a memory device region and a first conductive feature in a logic device region, wherein each of the magnetic tunnel junction devices includes a bottom electrode, a magnetic tunnel junction stack disposed over the bottom electrode, and a top electrode disposed over the magnetic tunnel junction stack; forming a first dielectric layer over the second metal layer and a second dielectric layer over the first dielectric layer; forming a first trench and a second trench in the first dielectric layer, wherein the first trench exposes the first conductive means and the second trench exposes a portion of each of the magnetic tunnel junction devices; forming a third trench and a fourth trench in the second dielectric layer, wherein the third trench is directly over the first conductive feature and the fourth trench is directly over the magnetic tunnel junction device; depositing a first metal material into the first, second, third, and fourth trenches and over the second dielectric layer; and performing a chemical mechanical planarization process on the first metal material such that a first portion of the first metal material remains in the first and third trenches, a second portion of the first metal material remains in the second and fourth trenches, and the first metal material is removed from a top surface of the second dielectric layer.

Drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A and 1B show perspective views of a semiconductor device in which an MRAM is integrated. Fig. 1C illustrates a cross-sectional view of the semiconductor device in fig. 1A and 1B, according to an embodiment.

Fig. 2A and 2B illustrate a flow diagram of a method for forming a semiconductor device having an MRAM array integrated therein, in accordance with an embodiment of the present invention.

Fig. 2C shows a flow diagram of a method for forming a semiconductor device having an MRAM integrated therein, in accordance with an alternative embodiment of the present invention.

Fig. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K-1, 3L, 3M-1, 3N, 3O, 3P, and 3Q illustrate semiconductor structures during a fabrication process according to the method of fig. 2A-2B, according to some embodiments.

Fig. 4A, 4B, 4C, 4D, 4E, 5A, and 5B illustrate cross-sectional views of a semiconductor structure during a fabrication process according to the method of fig. 2C, according to some embodiments.

Fig. 6, 7, 8, and 9 illustrate cross-sectional views of semiconductor structures according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Further, when a value or range of values is described by "about", "approximately", etc., unless otherwise stated, the term encompasses the values within certain variations (such as +/-10% or other variations) of the described values in light of the particular techniques disclosed herein, but in accordance with the knowledge of one of ordinary skill in the art. For example, the term "about 5 nm" may encompass the size range of 4.5nm to 5.5nm, 4.0nm to 5.0nm, and the like.

The present invention generally relates to semiconductor devices and methods of manufacture. More particularly, the present invention relates to providing a semiconductor device having MRAM and logic devices integrated therein. The MRAM is disposed in an MRAM device region (or MRAM region) of the semiconductor device, and the logic device is disposed in a logic device region (or logic region) of the semiconductor device. MRAM includes an array of MRAM cells arranged in rows and columns. MRAM cells in the same row are connected to a common word line, while MRAM cells in the same column are connected to a common bit line. The trench vias are provided as part of the bit lines to reduce the series resistance on the bit lines. The manufacturing process of the trench via is the same as the process of forming the via in the logic region to simplify the manufacturing process.

Fig. 1A and 1B illustrate perspective views of a device (or semiconductor device or structure) 200 having an MRAM array 250. In particular, fig. 1A shows a building block of MRAM array 250 — MRAM cell 249 with MTJ 150 (or MTJ stack 150). The MTJ 150 includes an upper ferromagnetic plate 152 and a lower ferromagnetic plate 154 separated by a thin insulating layer 156 (also referred to as a tunnel barrier layer). One of the two ferromagnetic plates (e.g., the lower ferromagnetic plate 154) is a magnetic layer (also referred to as a pinned or fixed layer 154) that is pinned to an antiferromagnetic layer, while the other ferromagnetic plate (e.g., the upper ferromagnetic plate 152) is a "free" magnetic layer that can change its magnetic field to one of two or more values to store one of two or more corresponding data states (also referred to as a free layer 152).

The MTJ 150 uses Tunnel Magnetoresistance (TMR) to store a magnetic field on an upper ferromagnetic plate 152 and a lower ferromagnetic plate 154. For a sufficiently thin insulating layer 156 (e.g., about 10nm or less in thickness), electrons can tunnel from the upper ferromagnetic plate 152 to the lower ferromagnetic plate 154. Data may be written to a cell in a variety of ways. In one approach, a current is passed between the upper ferromagnetic plate 152 and the lower ferromagnetic plate 154, which induces a magnetic field that is stored in the free magnetic layer (e.g., the upper ferromagnetic plate 152). In another approach, Spin Transfer Torque (STT) is utilized, wherein a flow of spin-aligned or polarized electrons is used to alter the magnetic field within the free magnetic layer relative to the fixed magnetic layer. Other methods of writing data may be used. However, all data writing methods involve changing the magnetic field within the free magnetic layer relative to the fixed magnetic layer.

Due to the magnetic tunneling effect, the resistance of the MTJ 150 varies according to the magnetic field stored in the upper ferromagnetic plate 152 and the lower ferromagnetic plate 154. For example, when the magnetic fields of the upper ferromagnetic plate 152 and the lower ferromagnetic plate 154 are aligned (or in the same direction), the MTJ 150 is in a low resistance state (i.e., a logic "0" state). When the magnetic fields of the upper ferromagnetic plate 152 and the lower ferromagnetic plate 154 are in opposite directions, the MTJ 150 is in a high resistance state (i.e., a logic "1" state). The magnetic field direction of the upper ferromagnetic plate 152 can be changed by passing a current through the MTJ 150. By measuring the resistance between the upper ferromagnetic plate 152 and the lower ferromagnetic plate 154, a read circuit coupled to the MTJ 150 can distinguish between "0" and "1" states. FIG. 1A also shows that the upper ferromagnetic plate 152 of the MTJ 150 is coupled to a bit line, the lower ferromagnetic plate 154 of the MTJ 150 is coupled to the source (or drain) of a transistor in the transistor structure 101, the drain (or source) of the transistor is coupled to a power Supply Line (SL), and the gate of the transistor is coupled to a Word Line (WL). The MTJ 150 can be accessed (such as read or write) by a bit line, a word line, and a power supply line.

Fig. 1B shows an MRAM array 250 comprising M rows (words) and N columns (bits) of MRAM cells (or MRAM devices) 249. Each MRAM cell 249 includes an MTJ 150. Word line WL₁、WL₂……WL_MExtend across a respective row of MRAM cells 249, and bit lines BL₁、BL₂……BL_NExtending along columns of MRAM cells 249.

FIG. 1C illustrates a cross-sectional view of device 200 along the bit line direction of MRAM array 250 (i.e., the B-B line in FIG. 1B), while showing both MRAM array 250 and logic device 252 of the same figure, according to some embodiments of the invention. Referring to fig. 1C, an MRAM array 250 is disposed in the MRAM region 100A and a logic device 252 is disposed in the logic region 100B. The logic device 252 may be used to implement write/read logic for accessing the MRAM array 250 or performing other functions. The MRAM region 100A and the logic region 100B have a common transistor structure 101 in or on the semiconductor substrate 100.

In some embodiments, the semiconductor substrate 100 may be, but is not limited to, a silicon substrate (such as a silicon wafer). Optionally, the semiconductor substrate 100 comprises another elemental semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. In yet another alternative, the semiconductor substrate 100 is a semiconductor-on-insulator (SOI). In other alternatives, the semiconductor substrate 100 may include a doped epitaxial layer, a graded semiconductor layer, and/or a semiconductor layer overlying a different type of another semiconductor layer, such as a silicon layer on a silicon germanium layer. The semiconductor substrate 100 may or may not include doped regions such as p-type wells, n-type wells, or a combination thereof.

The semiconductor substrate 100 also includes heavily doped regions, such as a source 103 and a drain 105, located at least partially in the semiconductor substrate 100. The gate 107 is located above the top surface of the semiconductor substrate 100 and between the source 103 and the drain 105. Contact plug 108 is formed in interlayer dielectric (ILD)109 and may be electrically coupled to transistor structure 101. In some embodiments, ILD 109 is formed on semiconductor substrate 100. ILD 109 may be formed by various techniques for forming such layers, such as Chemical Vapor Deposition (CVD), low pressure CVD (lpcvd), plasma enhanced CVD (pecvd), sputtering and Physical Vapor Deposition (PVD), thermal growth, and the like. ILD 109 may be formed from a variety of dielectric materials, such as oxides (e.g., Ge oxide), oxynitrides (e.g., GaP oxynitride), silicon dioxide (SiO)₂) Nitrogen-containing oxides (e.g., nitrogen-containing SiO)₂) Nitrogen-doped oxide (e.g., N)₂Implanted SiO₂) Silicon oxynitride (Si)_xO_yN_z) And the like. The transistors in the transistor structure 101 may be planar transistors or non-planar transistors, such as fin field effect transistors (finfets).

In some embodiments, Shallow Trench Isolation (STI)111 is provided to define and electrically isolate adjacent transistors. A plurality of STIs 111 are formed in the semiconductor substrate 100. STI 111 may include, for example, an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (SiO)₂) Nitrogen-containing oxides (e.g., nitrogen-containing SiO)₂) Nitrogen-doped oxide (e.g., N)₂Implanted SiO₂) Silicon oxynitride (Si)_xO_yN_z) And the like. STI 111 may also be formed of any suitable "high dielectric constant" or "high-K" material (where K is greater than or equal to about 8), such as titanium oxide (Ti)_xO_yFor example TiO₂) Tantalum oxide (Ta)_xO_yE.g. Ta₂O₅) And the like. Alternatively, STI 111 may be formed from any suitable "low dielectric constant" or "low-k" dielectric material, where k is less than or equal to about 4.

FIG. 1C further illustrates a package of devices 200Including an interconnect structure 308 over the transistor structure 101. Interconnect structure 308 includes three adjacent metal layers 302, 304, and 306, as well as other metal layers not shown. Metal layer 302 is the nth metal layer on the top surface of transistor structure 101, and metal layers 304 and 306 are the (N +1) th and (N +2) th metal layers, respectively. Thus, in some embodiments, metal layers 302, 304, and 306 are also referred to as metal layer M_N、M_N+1And M_N+2. The value N may be any natural number. For example, N may be 3, 4, 5, 6, or other natural number. In this embodiment, MRAM cell 249 is implemented in metal layer 304.

Metal layer 302 includes inter-metal dielectric (IMD) layer 206 and metal line 208 in both MRAM region 100A and logic region 100B. IMD layer 206 may be an oxide such as silicon dioxide, a low-k dielectric material such as a carbon-doped oxide, or a very low-k dielectric material such as porous carbon-doped silicon dioxide. The metal lines 208 may be made of a metal such as aluminum, copper, or a combination thereof.

Metal layer 304 includes a dielectric layer 210 (also referred to as a dielectric barrier layer (SBL)) that extends through both MRAM region 100A and logic region 100B. For example, in various embodiments, the dielectric layer 210 may comprise one or more dielectric materials, such as Si₃N₄SiON, SiC, SiCN or combinations thereof. In MRAM region 100A, metal layer 304 also includes MRAM cell 249 surrounded by one or more dielectric layers 210, 212, 214, 216, and 226. In logic region 100B, metal layer 304 also includes metal via 213 and metal line 217 surrounded by one or more dielectric layers 210 and 215. The various components in the metal layer 304 are described further below.

In an embodiment, the dielectric layer 212 comprises a metal-based dielectric material, such as aluminum oxide (i.e., AlO)_xSuch as Al₂O₃). In an embodiment, the dielectric layer 214 comprises a low-k dielectric material, such as a silicon oxide based low-k dielectric material. For example, the dielectric layer 214 may include Undoped Silicate Glass (USG) or doped silicon oxide, such as borophosphosilicate glass (BPSG), Fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. In an embodiment, the dielectric layer 216 comprisesOne or more oxide-based dielectric materials, such as an oxide formed from Tetraethylorthosilicate (TEOS), an undoped silicate glass, or a doped silicon oxide such as borophosphosilicate glass (BPSG), fluoride-doped quartz glass (FSG), phosphosilicate glass (PSG), fused silica glass (BSG), and/or other suitable dielectric materials. In an embodiment, the dielectric layer 226 includes a dielectric material that is different from the material in the dielectric layer 216 and the material in the top electrode 228 (discussed below). For example, the dielectric layer 226 may comprise a metal-based dielectric material, such as aluminum oxide (i.e., AlO)_xSuch as Al₂O₃)。

In the present embodiment, each MRAM cell 249 includes a Bottom Electrode Via (BEVA)220 and a conductive barrier layer 218 on the sidewalls and bottom surface of BEVA 220. The conductive barrier layer 218 may be disposed directly on one of the metal lines 208 in the metal layer 302 that is connected to a via on one of the source and drain features of a transistor in the transistor structure 101 (such connection is not shown in fig. 1C, but see fig. 1A). BEVA 220 may include tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, combinations thereof, or other suitable metals or metal compounds. The barrier layer 218 may comprise titanium nitride, tantalum nitride, or other suitable conductive diffusion barrier layer. The barrier layer 218 is disposed between the BEVA 220 and the surrounding dielectric layers 210, 221, and 214.

In this embodiment, each MRAM cell 249 further includes a Bottom Electrode (BE)222 disposed above BEVA 220, an MTJ (or MTJ stack) 150 disposed above BE 222, and a Top Electrode (TE)228 disposed above MTJ 150. In embodiments, each of BE 222 and TE 228 can comprise a metal nitride, such as TaN, TiN, Ti/TiN, TaN/TiN, Ta, or combinations thereof. In some embodiments, MTJ 150 may include ferromagnetic layers, MTJ spacers, and capping layers. A capping layer is formed on the ferromagnetic layer. Each of the ferromagnetic layers may include a ferromagnetic material, which may be a metal or metal alloy, e.g., Fe, Co, Ni, CoFeB, FeB, CoFe, FePt, FePd, CoPt, CoPd, CoNi, TbFeCo, CrNi, and the like. The MTJ spacer may include a non-ferromagnetic metal, such as Ag, Au, Cu, Ta, W, Mn, Pt, Pd, V, Cr, Nb, Mo, Tc, Ru, and the like. Another MTJ spacer may also include an insulatorRims, e.g. Al₂O₃MgO, TaO, RuO, etc. The capping layer may comprise a non-ferromagnetic material, which may be a metal or an insulator, such as Ag, Au, Cu, Ta, W, Mn, Pt, Pd, V, Cr, Nb, Mo, Tc, Ru, Ir, Re, Os, Al₂O₃MgO, TaO, RuO, etc. The capping layer may reduce the write current of its associated MRAM cell. A ferromagnetic layer may serve as the free layer 152 (fig. 1A), whose magnetic polarity or magnetic orientation may be changed during a write operation of the MRAM cell 249 associated therewith. The ferromagnetic layers and MTJ spacers may function as fixed layers 154 (fig. 1A) whose magnetic direction may not change during operation of their associated MRAM cell 249. It is contemplated that according to other embodiments, the MTJ 150 can include an antiferromagnetic layer.

In this embodiment, each MRAM cell 249 further includes a dielectric spacer 224 located on sidewalls of MTJ 150 and BE 222. Spacers 224 may comprise one or more dielectric materials, such as silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Silicon oxynitride (Si)_xO_yN_z) And the like. In the present embodiment, a dielectric layer 226 is disposed over the spacers 224 and over the sidewalls of the TEs 228.

In the present embodiment, the metal layer 304 in the logic area 100B includes a metal via 213, a metal line 217, and dielectric layers 210 and 215. Metal vias 213 are electrically connected to some of metal lines 208 in metal layer 302. The dielectric layer 215 may be an oxide such as silicon dioxide, a low-k dielectric material such as a carbon-doped oxide, or a very low-k dielectric material such as porous carbon-doped silicon dioxide. The metal vias 213 and metal lines 217 may be made of a metal such as aluminum, copper, or a combination thereof.

The metal layer 306 includes metal features 260A, 260B, 262A, and 262B surrounded by one or more dielectric layers 230, 232, 234, and 236. Dielectric layers 230, 232, 234, and 236 extend across MRAM region 100A and logic region 100B. Metal features 260A and 262A are disposed in MRAM region 100A. Metal features 260B and 262B are disposed in logic area 100B. The various components in the metal layer 306 are described further below.

In one embodiment, the dielectric layer 230 includes a dielectric materialThe material in layer 210 is the same or similar material. For example, the dielectric layer 230 may include one or more dielectric materials, such as Si₃N₄SiON, SiC, SiCN or combinations thereof. In an embodiment, the dielectric layer 232 includes the same or similar material as in the dielectric layer 212. For example, the dielectric layer 232 may comprise a metal-based dielectric material, such as aluminum oxide (i.e., AlO)_xSuch as Al₂O₃) Or other metal oxides. In an embodiment, the dielectric layer 234 comprises a low-k dielectric material, such as a silicon oxide based low-k dielectric material. For example, the dielectric layer 234 may include Undoped Silicate Glass (USG) or doped silicon oxide, such as borophosphosilicate glass (BPSG), Fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. In an embodiment, dielectric layer 236 comprises one or more oxide-based dielectric materials, such as an oxide formed from Tetraethylorthosilicate (TEOS), an undoped silicate glass, or a doped silicon oxide such as borophosphosilicate glass (BPSG), fluoride-doped quartz glass (FSG), phosphosilicate glass (PSG), fused silica glass (BSG), and/or other suitable dielectric materials.

In the present embodiment, the metal parts 260B and 262B are metal vias and metal lines, respectively. The metal vias 260B and the metal lines 262B may be made of a metal, such as aluminum, copper, or a combination thereof. In the present embodiment, metal feature 260A is a trench via formed in the same process as via 260B and comprising the same material as via 260B, and metal feature 262A is a metal line formed in the same process as metal line 262B and comprising the same material as metal line 262B. The slotted via 260A and metal line 262A are part of a bit line of the MRAM array 250. A tub via 260A is disposed over a column of MRAM cells 249 that share the same bit line (see fig. 1B). In some embodiments, the tub via 260A is disposed over a plurality of consecutive MRAM cells 249 (which may be a subset of a column of MRAM cells 249) that share the same bit line. When referring to a column of MRAM cells 249, the following discussion applies to both cases (either the column or a subset of the column). In this embodiment, the slot via 260A is disposed directly on the TE 228 of each MRAM cell 249 in the column and is electrically connected to the TE 228. In some embodiments, the slot via 260A is disposed directly over the MTJ 150 of each MRAM cell 249 in the column and is electrically connected to that MTJ 150. The slot via 260A extends laterally in a column from a first one 249 of the MRAM cells 249 to a last one 249 (along the "x" direction or bit line direction). Contacting the tub via 260A with a column of MRAM cells 249 advantageously reduces the series resistance of the bit lines compared to a method in which a single via is provided over each MRAM cell 249.

Further, as shown in fig. 1C, the portion of the trench via 260A disposed between adjacent MTJs 150 extends below the top surface of the TE 228, and in some embodiments even below the top surface of the MTJ 150 (as will be discussed later). This advantageously increases the volume of the trench via and further reduces the series resistance of the bit line. In the present embodiment, via 260B has a thickness d1, the portion of slot via 260A directly above MTJ 150 has a thickness d2, and the portion of slot via 260A laterally between two adjacent MTJs 150 has a thickness d 3. In an embodiment, thickness d2 is equal to or greater than thickness d1, and thickness d3 is greater than thickness d 1. In some embodiments, thickness d3 is equal to or greater than thickness d 2. For example, in some embodiments, the thickness d3 is about 5nm to about 50nm greater than the thickness d 2. In some examples, the thickness d2 is in a range of 40nm to 80nm, and the thickness d3 is in a range of 45nm to 130 nm. The above thicknesses d1, d2, and d3 are measured from the bottom surface of the respective vias 260A and 260B to the top surface of the dielectric layer 234. Further, in some embodiments, the length of the trench vias (i.e., along the "x" direction) is in the range of about 100nm to about 10,000nm, while the width of the trench vias (i.e., extending into and out of the page of fig. 1C along the "y" direction) is in the range of 20nm to about 100 nm. In an embodiment, the metal lines 262A and 262B have substantially the same thickness.

Fig. 2A and 2B illustrate a flow diagram of a method 500 for forming a semiconductor device 200 with an integrated MRAM array and logic device, according to an embodiment. Fig. 2C shows a flow diagram of certain operations of method 500 in an alternative embodiment. The method 500 is an example only and is not intended to limit the invention, not as explicitly recited in the claims. Additional operations may be provided before, during, and after method 500, and some of the operations described may be replaced, eliminated, or relocated for additional embodiments of the method. Method 500 is described below in conjunction with fig. 3A-8, which illustrate various cross-sectional views of semiconductor device 200 during fabrication steps according to method 500.

At operation 502, the method 500 (fig. 2A) provides or is equipped with a device 200 having a metal layer 302 and respective dielectric layers 210, 212, and 214 disposed over the metal layer 302, such as shown in fig. 3A. Although not shown in fig. 3A, device 200 also includes a transistor structure (such as transistor structure 101 in fig. 1C) disposed in or above a substrate (such as semiconductor substrate 100 in fig. 1C). Metal layer 302 is the nth metal layer above the transistor structure, where N is a natural number. The device 200 includes an MRAM region 100A for forming an MRAM array therein and a logic region 100B for forming a logic device therein. Metal layer 302 includes IMD layer 206 and metal lines 208 in both MRAM region 100A and logic region 100B. IMD layer 206 may be an oxide such as silicon dioxide, a low-k dielectric material such as a carbon-doped oxide, or a very low-k dielectric material such as porous carbon-doped silicon dioxide. The metal lines 208 may be made of a metal such as aluminum, copper, or a combination thereof. IMD layer 206 may be formed by a deposition process such as Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD) including Plasma Enhanced Chemical Vapor Deposition (PECVD). The metal lines 208 are formed by a deposition process such as PVD, CVD, ALD, or a plating process. In an embodiment, the dielectric layer 210 may include one or more dielectric materials, such as Si₃N₄SiON, SiC, SiCN, or combinations thereof, and may be deposited to a thickness in the range of 12nm to about 20nm using PVD, CVD, ALD, or other suitable process. In an embodiment, the dielectric layer 212 comprises a metal-based dielectric material, such as aluminum oxide, and may be deposited to a thickness in a range of about 2nm to about 6nm using CVD, ALD, or other suitable processes. In an embodiment, the dielectric layer 214 comprises a silicon oxide-based dielectric material, such as Undoped Silicate Glass (USG), and may be deposited to a thickness in a range of about 40nm to about 100nm using CVD, PVD, or other suitable process.

At operation 504, the method 500 (fig. 2A) forms the BEVA 220 and the barrier layer 218 that penetrate the dielectric layers 214, 212, and 210 and are electrically connected to some of the metal lines 208 in the MRAM region 100A, such as shown in fig. 3B. For example, operation 504 may form an etch mask over the dielectric layer 214 using a photolithography and etch process, wherein the etch mask provides openings corresponding to the locations of the BEVA 220 and the barrier layer 218 and covers the remainder of the device 200. In an embodiment, each BEVA 220 corresponds to an MRAM cell 249 in MRAM array 250. Then, operation 504 etches the dielectric layers 214, 212, and 210 through the etch mask to reach the metal layer 302, thereby forming openings (or trenches or holes) in the dielectric layers 214, 212, and 210. Subsequently, an operation 504 deposits a barrier layer 218 on the surface of the opening, and deposits BEVA 220 over the barrier layer 218. Thereafter, operation 504 may perform a Chemical Mechanical Planarization (CMP) process on BEVA 220 and barrier layer 218 to remove any excess material on the top surface of dielectric layer 214. In an embodiment, barrier layer 218 may comprise a non-magnetic material such as titanium nitride, tantalum nitride, or other suitable conductive diffusion barrier layer, and may be deposited using ALD, PVD, CVD, or other suitable deposition methods; BEVA 220 may comprise tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, combinations thereof, or other suitable metals or metal compounds and may be deposited using CVD, PVD, ALD, plating, or other suitable deposition methods.

At operation 506, the method 500 (fig. 2A) deposits a Bottom Electrode (BE) layer 222, MTJ (or MTJ stack) 150, and Top Electrode (TE) layer 228 over the dielectric layer 214, barrier layer 218, and BEVA 220, such as shown in fig. 3C. Specifically, the BE layer 222 is electrically connected to the BEVA 220. In embodiments, BE 222 may comprise a metal nitride such as TaN, TiN, Ti/TiN, TaN/TiN, Ta, or combinations thereof, and may BE deposited using CVD, ALD, or other suitable deposition method. In some embodiments, BE 222 can BE formed to have a thickness in the range of about 1nm to about 8 nm. MTJ 150 may be deposited using CVD, PVD, ALD, or other suitable deposition methods, and may have a thickness in the range of about 20nm to about 50nm in some embodiments. In an embodiment, the TE 228 may comprise a metal nitride such as TaN, TiN, Ti/TiN, TaN/TiN, Ta, or combinations thereof, and may be deposited using CVD, ALD, or other suitable deposition methods. In some embodiments, the TE 228 may be formed to have a thickness in the range of about 10nm to about 25 nm.

At operation 508, method 500 (FIG. 2A) patterns BE layer 222, MTJ 150, and TE layer 228 into a single MRAM cell 249. For example, using photolithography and etching processes, operation 508 may form an etch mask 402 that covers regions of TE layer 228 corresponding to individual MRAM cells 249 and exposes remaining portions of TE layer 228, such as shown in fig. 3D. Operation 508 then etches HE layer 228, MTJ 150, HE layer 222, and dielectric layer 214 through etch mask 402 to form a single MRAM cell 249, such as shown in fig. 3E. The etching process may be a wet etch, a dry etch, a reactive ion etch, or other suitable etching method. Thereafter, the etch mask 402 is removed using etching, stripping, ashing, or other suitable methods.

At operation 510, the method 500 (fig. 2A) forms spacers 224 over sidewalls of the MRAM cells 249, such as shown in fig. 3F. In some embodiments, spacers 224 are considered part of MRAM cells 249. For example, operation 510 may deposit a blanket dielectric layer over device 200 in both MRAM region 100A and logic region 100B using CVD, ALD, or other suitable methods, and then anisotropically etch the blanket dielectric layer to remove it from the top surface of dielectric layer 214 and the top surface of TE 228. Portions of the dielectric layer remain on the sidewalls of MRAM cell 249 as spacers 224. Spacers 224 may comprise one or more dielectric materials, such as silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Silicon oxynitride (Si)_xO_yN_z) And the like. In various embodiments, spacers 224 may comprise one or more layers of dielectric material.

At operation 512, the method 500 (fig. 2A) forms a dielectric layer (also referred to as a capping layer) 226 over the spacers 224 and the dielectric layer 214, and forms a dielectric layer 216 over the dielectric layer 226 in the MRAM region 100A, such as shown in fig. 3G. For example, operation 512 may deposit dielectric layer 226 and dielectric layer 216 in both MRAM region 100A and logic region 100B; forming an etch mask using photolithography and etching processes, wherein the etch mask covers the MRAM region 100A and exposes the logic region 100B; etching the dielectric layer 226 and the dielectric layers 216, 214, and 212 through the etch mask until the dielectric layer 210 is exposed in the logic region 100B; and the etch mask is removed. The dielectric layer 226 may be deposited using CVD, ALD, or other suitable methods. Dielectric layer 216 may be deposited using CVD, PVD, or other suitable methods. The dielectric layer 226 and dielectric layers 216, 214, and 212 may be etched using wet etching, dry etching, reactive ion etching, or other suitable methods.

After etching dielectric layer 226 and dielectric layers 216, 214, and 212, operation 512 further forms dielectric layer 215 in logic area 100B, such as shown in fig. 3H. The dielectric layer 215 may be an oxide such as silicon dioxide, a low-k dielectric material such as a carbon-doped oxide, or a very low-k dielectric material such as porous carbon-doped silicon dioxide. Dielectric layer 215 may be deposited using CVD, PVD, or other suitable methods. Operation 512 also performs a CMP process to planarize the top surfaces of dielectric layers 215 and 216, dielectric layer 226, and TE 228.

At operation 514, the method 500 (fig. 2A) forms the metal vias 213 and the metal lines 217 in the logic area 100B, such as shown in fig. 3I. The metal vias 213 and metal lines 217 may be formed using a dual damascene process or other suitable method. For example, operation 514 may etch holes and/or trenches in dielectric layer 215 to expose top surfaces of metal lines 208, deposit one or more metals into the holes and/or trenches, and perform a CMP process on the one or more metals. The portions of the one or more metals remaining in the holes and/or trenches become metal vias 213 and metal lines 217. The metal vias 213 and metal lines 217 may comprise aluminum, copper, or other suitable low resistance metal and may be deposited using PVD, CVD, ALD, plating, or other suitable method. After operation 514 is complete, the top surface of the metal line 217 is substantially coplanar with the top surface of the TE 228. Operations 504 through 514 are used, thus forming metal layer 304 over metal layer 302.

At operation 516, the method 500 (fig. 2B) deposits dielectric layers 230, 232, and 234 over the metal layer 304 in both the MRAM region 100A and the logic region 100B, such as shown in fig. 3J. In an embodiment, the dielectric layer 230 may comprise one or more dielectric materials, such as nitride (e.g., silicon nitride) or silicon carbide, and may be formed using ALD, CVD, PVD, or other suitable methodsAnd (6) depositing. In some embodiments, the dielectric layer 230 may have a thickness in a range of about 10nm to about 15 nm. In an embodiment, the dielectric layer 232 may comprise a metal-based dielectric material, such as aluminum oxide (i.e., AlO)_xSuch as Al₂O₃) And may be deposited using ALD, CVD, PVD, or other suitable methods. In some embodiments, the dielectric layer 232 may have a thickness in a range of about 4nm to about 10 nm. In an embodiment, the dielectric layer 234 may comprise Undoped Silicate Glass (USG) or doped silicon oxide, such as borophosphosilicate glass (BPSG), Fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials, and may be deposited using CVD, PVD, or other suitable methods. In some embodiments, the dielectric layer 234 may have a thickness in the range of about 40nm to about 100 nm.

At operation 518, the method 500 (fig. 2B) forms an etch mask 404 over the dielectric layer 234, such as shown in fig. 3J. The etch mask 404 provides an opening 406A over the MRAM region 100A and an opening 406B over the logic region 100B. In an embodiment, etch mask 404 comprises a material that is etch selective with respect to dielectric layers 234, 232, and 230 during the etching process. For example, in an embodiment, etch mask 404 may include a photoresist pattern and may further include a patterned hard mask below the photoresist pattern. For example, in an embodiment, the patterned hard mask may comprise titanium nitride and may have a thickness in a range of about 10nm to about 40 nm. Operation 518 may include: depositing a hard mask layer over the dielectric layer 234; coating photoresist on the hard mask layer; performing photolithography (such as exposure and development) on the photoresist layer to form a photoresist pattern; and etching the hard mask layer through the photoresist pattern to form a patterned hard mask. The patterned hard mask and photoresist pattern together form etch mask 404. In the present embodiment, each of the openings 406A corresponds to a column of MRAM cells 249 in the MRAM array 250. In some embodiments, each of the openings 406A corresponds to a subset of a column of MRAM cells 249 in the MRAM array 250. Thus, each of the openings 406A is generally longer (along the "x" direction) than the opening 406B corresponding to a single via.

At operation 520, method 500 (fig. 2B) etches dielectric layers 234, 232, and 230 through etch mask 404 to expose MRAM cells 249 in MRAM region 100A and metal lines 217 in logic region 100B. Fig. 3K and 3K-1 illustrate the resulting device 200 according to an embodiment. Fig. 3K shows device 200 along line B-B in fig. 1B (i.e., along the "x" direction), and fig. 3K-1 shows device 200 along line a-a in fig. 1B (i.e., along the "y" direction, which is perpendicular to the "x" direction). In an embodiment, operation 520 may perform a plurality of etch processes designed to etch each of dielectric layers 234, 232, and 230, respectively. For example, operation 520 may perform a first etch process designed to etch dielectric layer 234 with minimal or no etching of etch mask 404, perform a second etch process designed to etch dielectric layer 232 with minimal or no etching of etch mask 404, and perform a third etch process designed to etch dielectric layer 230 with minimal or no etching of etch mask 404. The plurality of etching processes may include wet etching, dry etching, or a combination of wet and dry etching. In some embodiments, the etching process in operation 520 may etch a plurality of dielectric layers. When dielectric layer 230 is etched, a slight over-etch is performed to ensure that the top surfaces of MRAM cells 249 and the top surfaces of metal lines 217 are exposed.

Because the opening 406A is typically much larger than the opening 406B, the etching of the dielectric layers 234, 232, and/or 230 may occur at different etch rates between the MRAM region 100A and the logic region 100B (referred to as an etch loading effect). For example, the dielectric layer 234 (or 232 or 230) may be etched faster in the MRAM region 100A than in the logic region 100B. Specifically, the dielectric layer 230 is etched faster in the MRAM region 100A than in the logic region 100B due to the etch loading effect. As a result, dielectric layer 216 may also be etched, resulting in recesses 160 in dielectric layer 216 between adjacent MRAM cells 249. In some embodiments, prior to etching, the recess 160 may have a depth d4 of less than 50nm, such as about 5nm to about 50nm, from the top surface of the dielectric layer 216. If depth d4 is too large (such as greater than 50nm), the loss of dielectric layer 216 may be too large and the coupling capacitance between adjacent MRAM cells 249 may be too high. In some embodiments, the recess 160 may be substantially equal to 0nm by controlling various etch parameters. In some embodiments, the recess 160 can extend below the top surface of the MTJ 150. In some embodiments, the TE 228 is partially removed by an etching process. In some alternative embodiments, the TE 228 is completely removed and the top surface of the MTJ 150 is exposed. As shown in fig. 3K and 3K-1, operation 520 extends openings 406A and 406B into dielectric layer 234/232/230. Specifically, the opening (or trench) 406A extends continuously from a first one of the MRAM cells 249 to a last one of the MRAM cells 249 in the same column of the MRAM array (which may have hundreds or thousands of MRAM cells 249 in some embodiments). After exposing MRAM cell 249 and metal line 217, etch mask 404 can be removed.

At operation 522, the method 500 (fig. 2B) forms vias in the openings 406A and 406B. For example, operation 522 may deposit one or more metallic materials 260 into the openings 406A and 406B and over the top surface of the dielectric layer 234, such as shown in fig. 3L. One or more metallic materials 260 are also filled in the recess 160. In embodiments where TE 228 is partially or completely removed by operation 518, such as shown in fig. 7 and 8, metal material(s) 260 also fill the space directly above MTJ 150 and between dielectric layers 226 on two opposing sidewalls of MRAM cell 249. The one or more metallic materials 260 may include a barrier or seed layer of Ta, TaN, Ti, TiN, or other suitable conductive material and a low resistance fill metal (such as copper, aluminum, or other suitable metal).

Subsequently, an operation 522 performs a CMP process on the one or more metal materials 260 to remove them from the top surface of the dielectric layer 234. The resulting structure of device 200 according to an embodiment is shown in fig. 3M and 3M-1. Fig. 3M shows device 200 along line B-B in fig. 1B (i.e., along the "x" direction), and fig. 3M-1 shows device 200 along line a-a in fig. 1B (i.e., along the "y" direction, which is perpendicular to the "x" direction). The remaining portion of the one or more metallic materials 260 in the opening (or trench) 406A becomes the slot via 260A. The remaining portion of the one or more metallic materials 260 in the opening (or trench) 406B becomes the via 260B. As shown in fig. 3M, the pocket via 260A has a length L1 along the "x" direction. As shown in FIG. 3M-1, the pocket via 260A has a width W1 along the "y" direction. In some embodiments, the length L1 is in the range of 100nm to about 10,000nm, the width W1 is in the range of 20nm to about 100nm, and the length L2 of the via 260B along the "x" direction is about 20nm to about 60 nm. In some embodiments, the ratio of length L1 to length L2 is about 5 to 500. Thus, trench vias 260A provide much lower series resistance than vias 260B. In some embodiments, the length of the MTJ 150 along the "x" direction is in the range of 20nm to about 100 nm. In the present embodiment, the length L1 is approximately equal to or greater than the number of MTJs 150 in the same column multiplied by the sum of the length of the MTJs 150 and the spacing of the MTJs 150. Further, the slot via 260A has a thickness d2 directly above MTJ 150 and a thickness d3 directly above the space between two adjacent MTJs 150, and via 260B has a thickness d 1. In an embodiment, thickness d2 is equal to or greater than thickness d1, and thickness d3 is greater than thickness d 1. In some embodiments, thickness d3 is equal to or greater than thickness d 2. For example, in some embodiments, the thickness d3 is about 5nm to about 50nm greater than the thickness d 2. In some examples, the thickness d2 is in a range of 40nm to 80nm, and the thickness d3 is in a range of 45nm to 130 nm.

At operation 524, the method 500 (fig. 2B) deposits a dielectric layer 236 over the vias 260A and 260B and over the dielectric layer 234 in the MRAM region 100A and the logic region 100B, such as shown in fig. 3N. In an embodiment, dielectric layer 236 comprises one or more oxide-based dielectric materials, such as an oxide formed from Tetraethylorthosilicate (TEOS), an undoped silicate glass, or a doped silicon oxide such as borophosphosilicate glass (BPSG), fluoride-doped quartz glass (FSG), phosphosilicate glass (PSG), fused silica glass (BSG), and/or other suitable dielectric materials, and may be deposited using CVD, PVD, or other suitable methods. An operation 524 then forms an etch mask 408 over the dielectric layer 236, such as shown in fig. 3N. The etch mask 408 provides an opening 410A over the trench via 260A and an opening 410B over the via 260B. In an embodiment, the etch mask 408 comprises a material that has an etch selectivity with respect to the dielectric layer 236 during the etching process. Etch mask 408 may be formed using deposition, photolithography, and etching processes, as discussed above with reference to etch mask 404.

At operation 526, the method 500 (fig. 2B) etches the dielectric layer 236 through the etch mask 408 to expose the trench vias 260A in the MRAM region 100A and the vias 260B in the logic region 100B, such as shown in fig. 3O. The etching process may use wet etching, dry etching, or a combination of wet and dry etching. The etching process extends openings 410A and 410B through dielectric layer 236 until the top surfaces of trench vias 260A and 260B are exposed. Openings 410A and 410B are wider along the "x" direction than slotted vias 260A and 260B, respectively. Subsequently, the etching mask 408 is removed.

At operation 528, the method 500 (fig. 2B) forms metal lines in the openings 410A and 410B. For example, operation 528 may deposit one or more metallic materials 262 into the openings 410A and 410B and over the top surface of the dielectric layer 236, such as shown in fig. 3P. The one or more metallic materials 262 may include a barrier layer or seed layer having Ta, TaN, Ti, TiN, or other suitable conductive material and a low resistance fill metal, such as copper, aluminum, or other suitable metal.

Subsequently, an operation 528 performs a CMP process on the one or more metal materials 262 to remove them from the top surface of the dielectric layer 236. The resulting structure of device 200 according to an embodiment is shown in fig. 3Q. The remaining portion of the one or more metallic materials 262 in the opening (or trench) 410A becomes the metal line 262A. The remaining portion of the one or more metallic materials 262 in the opening (or trench) 410B becomes the metal line 262B. The metal line 262A is slightly longer than the slot via 260A along the "x" direction. The metal line 262B is slightly longer than the via 260B along the "x" direction. Operations 516 through 528 are used, thus forming metal layer 306 over metal layer 304.

At operation 530, the method 500 (fig. 2B) performs further fabrication of the device 200, such as forming one or more metal layers over the metal layer 306, forming a passivation layer, and performing further process back ends.

Fig. 2A and 2C illustrate a method 500 in an alternative embodiment, which is briefly described below. Referring to fig. 2C, after completion of operation 514 as described above, method 500 proceeds to operation 540 to deposit dielectric layers 230, 232, 234, and 236, such as shown in fig. 4A. Then, at operation 542, the method 500 (fig. 2C) etches the dielectric layer 236 to form openings (or trenches) 410A and 410B, such as shown in fig. 4B. For example, operation 542 may form an etch mask, such as etch mask 408 shown in fig. 3N, and then etch dielectric layer 236 through the etch mask until dielectric layer 234 is exposed. The etch mask is subsequently removed. At operation 544, the method 500 (fig. 2C) etches the dielectric layers 234, 232, and 230 to form openings (or trenches) 406A and 406B, such as shown in fig. 4C. For example, operation 544 may form an etch mask, such as etch mask 404 shown in fig. 3J, and then etch dielectric layers 234, 232, and 230 through the etch mask until MTJ 150 and metal line 217 are exposed. The etch mask is subsequently removed. This operation is similar to operation 520. Then, at operation 546, the method 500 (fig. 2C) forms vias 260A and 260B and metal lines 262A and 262B. For example, operation 546 may deposit one or more metallic materials 264 into the openings 406A, 406B, 410A, and 410B and over the top surface of the dielectric layer 236, such as shown in fig. 4E. One or more metallic materials 264 are also filled in the recess 160. Operation 546 then performs a CMP process on the one or more metal materials 264 to remove them from the top surface of the dielectric layer 236. The resulting structure of device 200 is shown in fig. 4E. The remaining portions of the one or more metallic materials 264 in the openings (or trenches) 406A, 406B, 410A, and 410B become the trench vias 260A, 260B, 262A, and 262B, respectively. The method 500 (fig. 2C) then proceeds to additional manufacturing at operation 530.

In another embodiment, operation 544 may be performed before operation 542. For example, after the dielectric layers 230, 232, 234, and 236 have been deposited at operation 540, the method 500 may proceed to operation 544 to etch the dielectric layers 230, 232, 234, and 236 to form openings (or trenches) 406A and 406B, such as shown in fig. 5A. This operation is similar to operation 520. The method 500 may then proceed to operation 542 to etch the dielectric layer 236 to form openings (or trenches) 410A and 410B, such as shown in fig. 5B. Thereafter, the method 500 may proceed to operation 546 to form vias 260A and 260B and metal lines 262A and 262B as described above.

Fig. 6 illustrates an embodiment of the device 200 in which the etching process in operation 520 (or operation 544) overetches the dielectric layer 216 between adjacent MTJs 150 such that the top surfaces 150 'of the MTJs 150 are higher in the space between adjacent MTJs 150 than the bottom surface 260' of the trench via 260A. This advantageously increases the overall volume of the trench vias 260A to reduce series resistance.

Fig. 7 illustrates an embodiment of device 200 in which the etch process in operation 520 (or operation 544) partially removes TE 288 such that a portion of slot via 260A is laterally disposed between the protective layers on the two opposing sidewalls of MTJ 150. This advantageously increases the overall volume of the trench vias 260A to reduce series resistance.

Fig. 8 illustrates an embodiment of device 200 in which the etch process in operation 520 (or operation 544) completely removes TE 288 such that a portion of slot via 260A is disposed laterally between the protective layers on two opposing sidewalls of MTJ 150 and directly above the top of MTJ 150. This advantageously increases the overall volume of the trench vias 260A to reduce series resistance.

Fig. 9 illustrates an embodiment of a device 200 in which a plurality of trench vias 260A are connected by a common metal line 262A to serve as a bit line or a portion of a bit line. Due to the presence of the trench via 260A, the series resistance of the bit line is greatly reduced. In various embodiments, a bitline in device 200 may include one trench via 260A or multiple trench vias 260A (e.g., two, three, four, etc.), depending on design considerations such as mask fabrication complexity and etch balance between regions in device 200. In the embodiment depicted in fig. 9, the tilt in the dielectric layer 216 between adjacent MRAM cells 249 is negligible (about 0 nm). In other words, the bottom surface of the trench via 260A and the top surface of the dielectric layer 216 are substantially planar. In alternative embodiments, the slope in the dielectric layer 216 between adjacent MRAM cells 249 may range from about 5nm to about 50nm, such as the embodiment depicted in fig. 7 and 8 (in other words, the bottom surface of the trench via 260A extends below the top surface of the dielectric layer 216). Further, in the embodiment depicted in fig. 9, the TE 228 has a top surface that is substantially coplanar with the bottom surface of the trench via 260A and the top surface of the dielectric layer 216. In an alternative embodiment, the TE 228 may be partially or completely removed and the space therein filled with the slotted via 260A, such as the embodiment depicted in fig. 7 and 8.

Although not intended to be limiting, one or more embodiments of the present invention provide many benefits to semiconductor devices and the formation thereof. For example, embodiments of the present invention provide a semiconductor device having an MRAM array in an MRAM region. The MRAM array is provided with a slot via that extends continuously over a column of MRAM cells in the MRAM array and has a thickness equal to or greater than a via in the same metal layer in the logic region. The trench vias advantageously reduce the series resistance of the bit lines for the columns of MRAM cells. In addition, the formation of the semiconductor device can be easily integrated into existing semiconductor manufacturing processes.

In one example aspect, the present invention relates to a semiconductor structure comprising: a first metal layer; a second metal layer disposed above the first metal layer, and a third metal layer disposed directly above the second metal layer. The second metal layer includes a plurality of Magnetic Tunnel Junction (MTJ) devices in a memory device region and a first conductive feature in a logic device region. Each of the MTJ devices includes a bottom electrode and an MTJ stack disposed above the bottom electrode. The third metal layer includes a first via disposed directly above the first conductive component and electrically connected to the first conductive component and a slot via disposed above the MTJ devices and electrically connected to the MTJ stack of each of the MTJ devices. The slot via occupies a space that extends continuously laterally from a first one of the MTJ devices to a last one of the MTJ devices. A first thickness of the first via is equal to or less than a second thickness of the trench via directly above the MTJ stack of one of the MTJ devices. The third metal layer also includes a second conductive feature disposed over and electrically connected to the first via and a third conductive feature disposed over and electrically connected to the slotted via.

In an embodiment of the semiconductor structure, the trench via and the first via each comprise copper. In another embodiment, the second conductive component and the third conductive component each comprise copper.

In an embodiment of the semiconductor structure, the second metal layer includes a dielectric feature disposed laterally between two adjacent ones of the MTJ devices, and a third thickness of the slot via directly above the dielectric feature is greater than the second thickness. In another embodiment, the third thickness is about 5nm to about 50nm greater than the second thickness.

In an embodiment of the semiconductor structure, one of the MTJ devices further comprises a top electrode vertically between the trench via and the MTJ stack of the one of the MTJ devices. In another embodiment, a portion of the slot via extends to a level below a top surface of the MTJ stack of one of the MTJ devices.

In another embodiment, each of the MTJ devices further includes a spacer on a sidewall of the MTJ stack of the respective MTJ device and a protective layer on a sidewall of the spacer, wherein a portion of the slot via is disposed in a space laterally between the protective layers of two adjacent ones of the MTJ devices. In another embodiment, a bottom surface of the portion of the slot through hole is substantially flat.

In another example aspect, the disclosure is directed to a method comprising providing a structure having a first metal layer and a second metal layer disposed above the first metal layer, wherein the second metal layer includes a plurality of Magnetic Tunnel Junction (MTJ) devices in a memory device region and a first conductive feature in a logic device region, wherein each of the MTJ devices includes a bottom electrode, an MTJ stack disposed above the bottom electrode, and a top electrode disposed above the MTJ stack. The method further comprises the following steps: forming one or more dielectric layers over the second metal layer; forming a first etch mask over the one or more dielectric layers, wherein the first etch mask defines a first aperture over the first conductive feature and a second aperture over the MTJ devices and extends continuously from a first one of the MTJ devices to a last one of the MTJ devices; and etching the one or more dielectric layers through the first and second holes to form first and second trenches, respectively, in the one or more dielectric layers, wherein the first trench exposes the first conductive component and the second trench exposes a portion of each of the MTJ devices. The method further comprises the following steps: depositing a first metallic material into the first and second trenches and over the one or more dielectric layers; and performing a chemical mechanical planarization process on the first metal material such that a first portion of the first metal material remains in the first trench, a second portion of the first metal material remains in the second trench, and the first metal material is removed from a top surface of the one or more dielectric layers.

In an embodiment, the method further comprises: forming a second dielectric layer over the one or more dielectric layers and over the first and second portions of the first metallic material; forming a second etch mask over the second dielectric layer, wherein the second etch mask defines a third aperture over the first portion of the first metallic material and a fourth aperture over the second portion of the first metallic material; etching the second dielectric layer through the third and fourth holes to form third and fourth trenches, respectively, in the second dielectric layer, wherein the third and fourth trenches expose the first and second portions of the first metallic material; and depositing a second metallic material into the third and fourth trenches and over the second dielectric layer. In another embodiment, the method further comprises: performing another chemical mechanical planarization process on the second metal material such that a first portion of the second metal material remains in the third trench, a second portion of the second metal material remains in the fourth trench, and the second metal material is removed from a top surface of the second dielectric layer.

In an embodiment of the method, the second metal layer further includes a dielectric feature located laterally between adjacent ones of the MTJ devices, and the etching the one or more dielectric layers partially removes the dielectric feature. In another embodiment of the method, the etching the one or more dielectric layers partially removes the top electrode of at least one of the MTJ devices. In yet another embodiment of the method, the etching of the one or more dielectric layers completely removes the top electrode of at least one of the MTJ devices.

In yet another example aspect, the present disclosure is directed to a method comprising: providing a structure having a first metal layer and a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of Magnetic Tunnel Junction (MTJ) devices in a memory device region and a first conductive feature in a logic device region, wherein each of the MTJ devices includes a bottom electrode, an MTJ stack disposed over the bottom electrode, and a top electrode disposed over the MTJ stack. The method further comprises the following steps: forming a first dielectric layer over the second metal layer and a second dielectric layer over the first dielectric layer; forming a first trench and a second trench in the first dielectric layer, wherein the first trench exposes the first conductive component and the second trench exposes a portion of each of the MTJ devices; forming a third trench and a fourth trench in the second dielectric layer, wherein the third trench is directly over the first conductive component and the fourth trench is directly over the MTJ device; depositing a first metal material into the first, second, third, and fourth trenches and over the second dielectric layer; and performing a chemical mechanical planarization process on the first metal material such that a first portion of the first metal material remains in the first and third trenches, a second portion of the first metal material remains in the second and fourth trenches, and the first metal material is removed from a top surface of the second dielectric layer.

In an embodiment of the method, the second metal layer further includes a dielectric feature laterally between adjacent ones of the MTJ devices, and the forming the first and second trenches partially removes the dielectric feature. In another embodiment of the method, said forming the first trench and the second trench is performed after said forming the third trench and the fourth trench. In another embodiment of the method, the forming the first trench and the second trench partially removes the top electrode of at least one of the MTJ devices. In yet another embodiment of the method, the forming the first trench and the second trench completely removes the top electrode of at least one of the MTJ devices.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.